Memory device and method of performing in-memory processing of memory device

Abstract

A memory device and a method of performing in-memory processing of the memory device are provided. The memory device includes: a memory cell array; and an in-memory processing (PIM) unit including a plurality of multiply and accumulate (MAC) operators configured to perform a multiply-accumulate operation based on the data stored in the memory cell array. The plurality of MAC operators perform a multiply-accumulate operation based on the data in a first stage, and perform a partial sum operation based on a result value of the multiply-accumulate operation in a second stage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0151762 filed in the Korean Intellectual Property Office on November 6, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure described herein relate to a semiconductor memory device, and more particularly, to a memory device configured to perform an in-memory process and a method of performing the in-memory process of the memory device. Background Art

[0004] Semiconductor memory devices can be classified as volatile memory devices or non-volatile memory devices. The read and write speeds of volatile memory devices (e.g., DRAM or SRAM) are generally fast, but when the power is turned off or lost, the data stored in the volatile memory device is lost. In contrast, non-volatile memory devices can retain data even when the power is turned off or lost. Therefore, non-volatile memory devices can be used to store content that must be saved regardless of whether power is supplied.

[0005] A representative example of a volatile memory device is a random access memory (RAM). RAM directly performs some of the operations of a central processing unit (CPU) and is called processing in memory (PIM). Since RAM directly performs some operations, the amount of communication between the CPU and RAM can be reduced, and the bottleneck phenomenon can be solved. However, due to the space limitation of RAM, all operators required for directly performing operations may not be included in the RAM. Summary of the invention

[0006] Example embodiments of the present disclosure provide a memory device configured to perform a MAC operation and a partial sum operation using a plurality of MAC operators included in a PIM unit, and a method of performing an in-memory process of the memory device.

[0007] According to an example embodiment, a memory device includes: a memory cell array; and a processing in memory (PIM) unit including a plurality of multiplication and accumulation (MAC) operators configured to perform multiplication and accumulation operations based on data stored in the memory cell array. The plurality of MAC operators are configured to perform multiplication and accumulation operations based on the data in a first stage, and to perform partial sum operations based on result values ​​of the multiplication and accumulation operations in a second stage.

[0008] According to an example embodiment, a method for performing in-memory processing of a memory device includes: establishing one or more process-in-memory (PIM) instructions; based on the one or more PIM instructions, loading first data for PIM operation from a memory cell array of the memory device; and performing the PIM operation based on the first data. Performing the PIM operation includes: performing a multiplication-accumulation operation on the first data through a plurality of MAC operators in a first stage; and when the multiplication-accumulation operation is completed, performing a partial sum operation based on a result value of the multiplication-accumulation operation in a second stage.

[0009] According to an example embodiment, a memory device includes: a memory cell array; a control logic configured to control data input to the memory cell array and data output from the memory cell array, respectively; and a plurality of MAC operators configured to perform multiplication-accumulation operations based on data stored in the memory cell array in response to a MAC operation start signal received from the control logic. Each of the plurality of MAC operators includes: a multiplier configured to perform a multiplication operation using a first MAC input and a second MAC input as an operation object; a first multiplexer configured to output a first operation result or a first partial sum input of the multiplier based on a phase information signal; a second multiplexer configured to output a second partial sum input or data stored in an accumulation register based on the phase information signal; and an adder configured to perform an addition operation on a first output of the first multiplexer and a second output of the second multiplexer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a memory system according to example embodiments.

[0012] Figure 2 It is shown Figure 1 A block diagram of a memory device.

[0013] Figure 3 It is shown Figure 2 Schematic diagram of a processing-in-memory (PIM) unit.

[0014] Figure 4 It is shown Figure 3 Schematic diagram of an example embodiment of a PIM execution unit.

[0015] Figure 5 is a diagram showing a general PIM operator.

[0016] Figure 6 It is shown Figure 4Schematic diagram of an example embodiment of a PIM operator.

[0017] Figure 7 It is shown Figure 6 An illustration of an example embodiment of a phase manager for .

[0018] Figure 8 is a diagram showing the process during the MAC phase according to an example embodiment. Figure 6 Schematic diagram of the operations of multiple MAC operators in .

[0019] Fig. 9 is a diagram showing a method of performing a Figure 6 Schematic diagram of parts of multiple MAC operators and operations during stages.

[0020] Fig.10 is a diagram showing a method according to an example embodiment Figure 6 Schematic diagram of one of the multiple MAC operators in FIG.

[0021] Fig.11 is a diagram showing a method according to an example embodiment Figure 2 Flowchart of the PIM operation of the PIM unit.

[0022] Fig.12 is a diagram showing the execution of an exemplary embodiment Fig.11 Flowchart of a method of PIM operation.

[0023] Fig.13 It is shown Figure 6 A diagram of an example embodiment of a wiring layout of multiple MAC operators in FIG.

[0024] Fig.14 It is shown Figure 6 A diagram of another example embodiment of a wiring layout of multiple MAC operators in FIG.

[0025] Fig.15 It is shown Figure 6 A diagram of another example embodiment of a wiring layout of multiple MAC operators in FIG. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments of the inventive concept are described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same constituent elements, and repeated descriptions thereof are omitted. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items. It should be noted that, although not specifically described, the aspects described with respect to one embodiment may be incorporated into different embodiments. That is, all embodiments and / or the features of any embodiment may be incorporated in any manner and / or combination.

[0027] Hereinafter, DRAM will be used as an example for illustrating the features and functions of the present disclosure. However, those skilled in the art can easily understand other features and operating performance from the information disclosed herein. The present disclosure can be implemented by other embodiments or applied to other embodiments. In addition, the specific implementation can be modified or changed according to the viewpoint and application without departing from the scope, spirit and other purposes of the present disclosure.

[0028] Figure 1 is a block diagram illustrating a memory system according to an example embodiment. Figure 1 , the memory system 1000 may include a memory controller 1100 and a memory device 1200 .

[0029] According to example embodiments, the memory controller 1100 may perform an access operation of writing data to the memory device 1200 or reading data stored in the memory device 1200. For example, the memory controller 1100 may generate a command CMD and an address ADDR for writing data to the memory device 1200 and / or reading data stored in the memory device 1200. The memory controller 1100 may include a control circuit for controlling the memory device 1200, a system on chip (SoC) such as an application processor (AP), a central processing unit (CPU), a digital signal processor (DSP), and / or a graphic processing unit (GPU).

[0030] According to example embodiments, the memory controller 1100 may provide various signals to the memory device 1200 to control the overall operation of the memory device 1200. For example, the memory controller 1100 may control memory access operations, such as read operations and write operations, of the memory device 1200. The memory controller 1100 may provide a command CMD and an address ADDR to the memory device 1200 to write data DATA into the memory device 1200 or read data DATA from the memory device 1200.

[0031] According to example embodiments, the memory controller 1100 may generate various types of commands CMD to control the memory device 1200. For example, the memory controller 1100 may generate a memory bank request corresponding to a memory bank operation of changing the state of a memory bank in a plurality of memory banks to read or write data DATA. As an example, the memory bank request may include an activation request for changing the state of a memory bank in a plurality of memory banks to an activated state. The memory device 1200 may activate a row (e.g., a word line) included in the memory bank in response to the activation request. The memory bank request may include a precharge request for changing the memory bank from an activated state to a standby state after completing the reading or writing of the data DATA. In addition, the memory controller 1100 may generate an input / output (I / O) request (e.g., a column address strobe (CAS) request) for the memory device 1200 to perform a read operation or a write operation of the data DATA. As an example, the I / O request may include a read request for reading data DATA from an activated memory bank. The I / O request may include a write request for writing data DATA into an activated memory bank. The memory controller 1100 may generate a refresh command for controlling a refresh operation with respect to a memory bank. However, the types of commands CMD described herein are merely examples, and other types of commands CMD may be used.

[0032] According to example embodiments, the memory device 1200 may output data DATA requested to be read by the memory controller 1100 to the memory controller 1100 or may store data DATA requested to be written by the memory controller 1100 in a memory cell of the memory device 1200. The memory device 1200 may input and output data DATA based on a command CMD and an address ADDR. The memory device 1200 may include a memory bank.

[0033] The memory device 1200 may be a volatile memory device such as a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate (DDR) DRAM, a DDR SDRAM, a low power double data rate (LPDDR) SDRAM, a graphic double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), and a static random access memory (SRAM), etc. In other embodiments, the memory device 1200 may be implemented as a non-volatile memory device such as a resistive RAM (RRAM), a phase change memory (PRAM), a magnetoresistive memory (MRAM), a ferroelectric memory (FRAM), a spin transfer torque RAM (STT-RAM), etc. In this specification, the advantages of the present disclosure have been described with respect to DRAM, but example embodiments are not limited thereto.

[0034] According to example embodiments, the memory bank may include a memory cell array divided in units of banks, a row decoder, a column decoder, a sense amplifier, a write driver, etc. The memory bank may store data DATA requested to be written into the memory device 1200 through the write driver, and may read the data DATA requested to be read using the sense amplifier. The memory bank may also include a component for a refresh operation to store and maintain data in the cell array, or an address-based selection circuit.

[0035] According to example embodiments, the memory device 1200 may include a process in memory (PIM) unit 100 (hereinafter referred to as the PIM unit 100). The PIM unit 100 may perform a specified operation on the data DATA stored in the memory device 1200. The memory device 1200 may store the operation result back in the memory bank or transmit the operation result to the memory controller 1100. The PIM unit 100 may perform a specified operation on the data DATA received from the memory controller 1100 and transmit the operation result to the memory bank.

[0036] Figure 2 It is shown Figure 1 A block diagram of a memory device. Figure 2 , the memory device 1200 may include a memory cell array 1210, an address buffer 1220, a row decoder 1221, a column decoder 1222, a bit line sense amplifier 1230, a command decoder 1240, a control logic 1250, and an input / output circuit 1260. In addition, the memory device 1200 may include the PIM unit 100.

[0037] According to example embodiments, the memory cell array 1210 may include a plurality of memory cells arranged in a matrix of rows and columns. For example, the memory cell array 1210 may include a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL may be connected to the rows of the memory cells, and the plurality of bit lines BL may be connected to the columns of the memory cells.

[0038] According to an example embodiment, the address buffer 1220 may be Figure 1 The memory controller 1100 receives the address ADDR. For example, the address ADDR may include a row address RA for addressing a row of the memory cell array 1210 and a column address CA for addressing a column of the memory cell array 1210. The address buffer 1220 may send the row address RA to the row decoder 1211, and may send the column address CA to the column decoder 1212.

[0039] According to example embodiments, the row decoder 1211 may select one of a plurality of word lines WL connected to the memory cell array 1210. The row decoder 1211 may decode a row address RA received from the address buffer 1220 to select a single word line corresponding to the row address RA, and may activate the selected word line.

[0040] According to example embodiments, the column decoder 1212 may select a predetermined bit line from among a plurality of bit lines BL of the memory cell array 1210. The column decoder 1212 may decode a column address CA received from the address buffer 1220 to select a predetermined bit line BL corresponding to the column address CA.

[0041] According to example embodiments, the bit line sense amplifier 1230 may be connected to the bit line BL of the memory cell array 1210. For example, the bit line sense amplifier 1230 may sense a voltage variation of a selected bit line among a plurality of bit lines BL, and may amplify and output the voltage variation.

[0042] According to example embodiments, the command decoder 1240 may decode a write enable signal / WE, a row address strobe signal / RAS, a column address strobe signal / CAS, and a chip select signal / CS received from the memory controller 1100 so that a control signal corresponding to a command CMD is generated in the control logic 1250. The command CMD may include an activation request, a read request, a write request, or a precharge request.

[0043] According to example embodiments, the control logic 1250 may control the overall operation of the bit line sense amplifier 1230 through a control signal corresponding to the command CMD. In addition, the control logic 1250 may control the overall operation of the memory device 1200.

[0044] According to example embodiments, the input / output circuit 1260 may output data DATA to the memory controller 1100 through the data pad based on the voltage sensed and amplified from the bit line sense amplifier 1230. For example, the input / output circuit 1260 may include an input buffer or an output buffer. The input buffer or the output buffer may be electrically connected to the data pad. The input / output circuit 1260 may perform a serialization operation or a deserialization operation of the data DATA.

[0045] According to example embodiments, the PIM unit 100 may perform a designated operation on the data DATA stored in the memory cell array 1210. The operation result may be stored again in the memory cell array 1210 or output through the input / output circuit 1260. The PIM unit 100 may perform a designated operation on the data DATA received from the input / output circuit 1260 and transmit the operation result to the memory cell array 1210.

[0046] According to an example embodiment, the PIM unit 100 may include a plurality of multiplication and accumulation (MAC) operators (hereinafter referred to as MAC operators). For example, the PIM unit 100 may perform a MAC operation through the plurality of MAC operators. In addition, the PIM unit 100 may perform a partial sum operation through an adder included in the plurality of MAC operators. Therefore, an additional space for the adder may be saved, and the memory device 1200 may efficiently perform a MAC operation in the same area.

[0047] Figure 3 It is shown Figure 2 Schematic diagram of a PIM unit. Figure 4 It is shown Figure 3 FIG. 1 is a diagram of an example embodiment of a PIM execution unit. Figures 2 to 4 The PIM unit 100 may include a PIM execution unit 110 and a PIM register 120 . The PIM execution unit 110 may include a PIM control logic 111 , a PIM register file 112 , and a PIM operator 113 .

[0048] According to an example embodiment, the PIM execution unit 110 may be configured to: Figure 2 The PIM execution unit 110 may perform a PIM operation under the control of the control logic 1250. For example, the PIM execution unit 110 may receive first data from the memory cell array 1210. The PIM execution unit 110 may receive second data from the PIM register 120. The PIM execution unit 110 may perform an operation based on the first data and the second data and output result data. As an example, the PIM execution unit 110 may include a single instruction multiple data (SIMD) floating point unit (FPU).

[0049] According to example embodiments, the PIM execution unit 110 may store the result data in the memory cell array 1210 through the bit line sense amplifier 1230. In other embodiments, the PIM execution unit 110 may store the result data in the PIM register 120. The PIM execution unit 110 may repeatedly perform an operation based on the result data stored in the PIM register 120. The result data stored in the PIM register 120 may be transmitted to the memory controller 1100 through the input / output circuit 1260.

[0050] According to an example embodiment, the PIM control logic 111 may be configured to Figure 2 The overall operation of the PIM operator 113 is controlled by the control logic 1250. The PIM register file 112 may include a plurality of registers. The PIM register file 112 may store a plurality of data to be used in the PIM operator 113. The PIM register file 112 may store data received from the memory cell array 1210. The PIM register file 112 may store result data output from the PIM operator 113.

[0051] According to example embodiments, the PIM operator 113 may perform a PIM operation under the control of the PIM control logic 111. For example, the PIM operator 113 may receive first data from the memory cell array 1210. The PIM operator 113 may receive second data from the PIM register file 112. The PIM operator 113 may perform an operation based on the first data and the second data, and the PIM operator 113 may output result data.

[0052] According to an example embodiment, the PIM operator 113 may include a plurality of MAC operators. Each of the plurality of MAC operators may include a multiplier, an adder, and an accumulation register. The PIM operator 113 may perform a MAC operation through the plurality of MAC operators. In addition, the PIM operator 113 may perform a partial sum operation through an adder included in the plurality of MAC operators.

[0053] Figure 5 is a diagram showing a general PIM operator. Figure 5 , the PIM operator 113 may include a plurality of MAC operators 10 and an adder tree 20. The adder tree 20 may include a plurality of adders.

[0054] Each of the plurality of MAC operators 10 may receive two input values. Each of the plurality of MAC operators 10 may perform a MAC operation on the input values ​​and output a result value. The result values ​​of the plurality of MAC operators 10 may be input values ​​of the adder tree 20. The adder tree 20 may perform a partial sum operation of the result values ​​of the plurality of MAC operators 10.

[0055] Each of the multiple adders included in the adder tree 20 can add two input values ​​and output a result value. The adder placed at the top of the adder tree 20 can receive result values ​​from the multiple MAC operators 10 and output the result value. The result value of the adder placed at the top of the adder tree 20 can be the input value of the adder of the next stage in the adder tree 20, and by repeating this process, an adder placed at the bottom of the adder tree 20 can finally output an adder tree result AD_R.

[0056] The adder tree 20 may occupy the same or similar area as the plurality of MAC operators 10. Therefore, in the case where the memory device 1200 has a limited area, the adder tree 20 may be omitted or only partially included. In other embodiments, the partial sum operation of the adder tree 20 may be performed in the host. However, if the PIM operator 113 cannot perform the partial sum operation, the performance of the PIM unit 100 may be limited.

[0057] Figure 6 It is shown Figure 4 Schematic diagram of an example embodiment of a PIM operator. Figure 7 It is shown Figure 6 Schematic diagram of an example embodiment of a phase manager. Figure 6 and Figure 7 The PIM operator 113 may include a phase manager 113a and a plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...). The phase manager 113a may include a phase decoder 113aa and a phase selector 113ab.

[0058] According to an example embodiment, the phase manager 113a may output the phase information signal SI based on the MAC operation completion signal MSD and the partial sum control signal PSUM. For example, the phase decoder 113aa may output the decoding signal DS based on the MAC operation completion signal MSD and the partial sum control signal PSUM. The phase selector 113ab may output the phase information signal SI based on the decoding signal DS.

[0059] According to an example embodiment, a plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may perform MAC operations in a MAC phase based on the phase information signal SI. When the MAC operation completion signal MSD is not received (or a low-level MAC operation completion signal MSD is received), the phase manager 113a may output a phase information signal SI (e.g., a first phase information signal) indicating a MAC phase.

[0060] According to an example embodiment, when a first stage information signal is received, a plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may perform operations in the MAC stage. For example, the first MAC operator 113_1 may perform a MAC operation on the first MAC input Ma1 and Mb1, and output a first MAC result Mr1. ​​The second MAC operator 113_2 may perform a MAC operation on the second MAC input Ma2 and Mb2, and output a second MAC result Mr2. The third MAC operator 113_3 may perform a MAC operation on the third MAC input Ma3 and Mb3, and output a third MAC result Mr3. The fourth MAC operator 113_4 may perform a MAC operation on the fourth MAC input Ma4 and Mb4, and output a fourth MAC result Mr4.

[0061] According to example embodiments, the plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may perform a partial sum operation in a partial sum phase based on the phase information signal SI. When the MAC operation completion signal MSD is received (or the MAC operation completion signal MSD of a high level is received) and the partial sum control signal PSUM is received (or the partial sum control signal PSUM of a high level is received), the phase manager 113a may output a phase information signal SI indicating the partial sum phase (e.g., a second phase information signal).

[0062] According to an example embodiment, when a second stage information signal is received, a plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may perform operations in a partial sum stage. For example, a first MAC operator 113_1 may perform a partial sum operation on a first partial sum input Pa1 and Pb1, and output a first partial sum result Pr1. A second MAC operator 113_2 may perform a partial sum operation on a second partial sum input Pa2 and Pb2, and output a second partial sum result Pr2. A third MAC operator 113_3 may perform a partial sum operation on a third partial sum input Pa3 and Pb3, and output a third partial sum result Pr3. A fourth MAC operator 113_4 may perform a partial sum operation on a fourth partial sum input Pa4 and Pb4, and output a fourth partial sum result Pr4.

[0063] According to an example embodiment, the plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may not perform a partial sum operation after performing a MAC operation based on the phase information signal SI. When the MAC operation completion signal MSD is received (or the MAC operation completion signal MSD of a high level is received) and the partial sum control signal PSUM is not received (or the partial sum control signal PSUM of a low level is received), the phase manager 113a may output a phase information signal SI (e.g., a third phase information signal) indicating the output of a MAC operation result. When the third phase information signal is received, the plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may output a MAC operation result without performing a partial sum operation.

[0064] Figure 8 is a diagram showing the process during the MAC phase according to an example embodiment. Figure 6 Schematic diagram of the operation of multiple MAC operators in . Figure 8 , multiple MAC operators (113_1, 113_2, 113_3, 113_4, ...) can perform MAC operations in the MAC stage based on the first stage information signal SI 1.

[0065] According to an example embodiment, each of the plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may receive two MAC inputs and perform a MAC operation. For example, the first MAC operator 113_1 may perform a MAC operation on the first MAC input Ma1 and Mb1, and output a first MAC result Mr1. ​​The second MAC operator 113_2 may perform a MAC operation on the second MAC input Ma2 and Mb2, and output a second MAC result Mr2. The third MAC operator 113_3 may perform a MAC operation on the third MAC input Ma3 and Mb3, and output a third MAC result Mr3. The fourth MAC operator 113_4 may perform a MAC operation on the fourth MAC input Ma4 and Mb4, and output a fourth MAC result Mr4.

[0066] According to an example embodiment, one of the MAC inputs received in a MAC operator may be from Figure 2 As an example, MAC inputs (Ma1, Ma2, Ma3, Ma4, ...) may be received from the memory cell array 1210.

[0067] According to an example embodiment, another one of the MAC inputs received in one MAC operator may be stored in Figure 4As an example, the MAC inputs (Mb1, Mb2, Mb3, Mb4, ...) can be received from the PIM register file 112.

[0068] According to an example embodiment, each of the plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may repeatedly perform a MAC operation based on the first stage information signal SI 1. As an example, a MAC result (Mr1, Mr2, Mr3, Mr4, ...) is sent as an input to a portion of the plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...), and a MAC operation may be repeatedly performed.

[0069] Fig. 9 is a diagram showing a method of performing a Figure 6 FIG. 1 is a diagram of the operations performed by the multiple MAC operators during the stages. Fig. 9 , the plurality of MAC operators ( 113_1 , 113_2 , 113_3 , 113_4 , . . . ) may perform a partial sum operation in a partial sum stage based on the second stage information signal SI2 .

[0070] According to an example embodiment, a MAC result (Mr1, Mr2, Mr3, Mr4, ...) according to a MAC operation may be sent as an input to a portion of a plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...). As an example, a first MAC result Mr1 generated by a first MAC operator 113_1 may be a partial sum input Pa1 of the first MAC operator 113_1. A second MAC result Mr2 generated by a second MAC operator 113_2 may be another partial sum input Pb1 of the first MAC operator 113_1. In the partial sum stage, the first MAC operator 113_1 may perform a partial sum operation on the first MAC result Mr1 and the second MAC result Mr2, and output a first partial sum result Pr1.

[0071] As an example, the third MAC result Mr3 generated by the third MAC operator 113_3 may be a partial sum input Pa3 of the third MAC operator 113_3. The fourth MAC result Mr4 generated by the fourth MAC operator 113_4 may be another partial sum input Pb3 of the third MAC operator 113_3. In the partial sum stage, the third MAC operator 113_3 may perform a partial sum operation on the third MAC result Mr3 and the fourth MAC result Mr4, and output a third partial sum result Pr3.

[0072] As an example, the first partial sum result Pr1 of the first MAC operator 113_1 may be a partial sum input Pa2 of the second MAC operator 113_2. The third partial sum result Pr3 of the third MAC operator 113_3 may be another partial sum input Pb2 of the second MAC operator 113_2. In the partial sum stage, the second MAC operator 113_2 may perform a partial sum operation on the first partial sum result Pr1 and the third partial sum result Pr3, and output a second partial sum result Pr2.

[0073] According to an example embodiment, in the partial sum stage, a part of the plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may repeatedly perform the partial sum operation. The partial sum result (Pr1, Pr2, Pr3, Pr4, ...) is sent as an input to a part of the plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...), and the partial sum operation may be repeatedly performed. One of the plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may eventually output a partial sum result, and thus, the plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may perform the partial sum operation in the partial sum stage. Figure 5 In the partial and stage, multiple MAC operators (113_1, 113_2, 113_3, 113_4, ...) can generate Figure 5 The adder tree 20 has the same effect or provides the same or similar functions.

[0074] According to an example embodiment, in the partial sum stage, a part of the plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may not be used. For example, since there is no input, the fourth MAC operator 113_4 may not perform an operation in the partial sum stage. Since the partial sum operation is repeated in the partial sum stage, the number of used MAC operators may be reduced. Finally, one MAC operator may output the final partial sum result.

[0075] Fig.10 is a diagram showing a method according to an example embodiment Figure 6 . The other MAC operators in the plurality of MAC operators can be implemented similarly. Fig.10, a MAC operator MACi may include a multiplier CA1, an adder CA2, an accumulator register AR, a first multiplexer MX1, and a second multiplexer MX2. The MAC operator MACi may perform a MAC operation on the i-th MAC input Mai and Mbi, and output the i-th MAC result Mri. The MAC operator MACi may perform a partial sum operation on the i-th partial sum input Pai and Pbi, and output the i-th partial sum result Pri.

[0076] According to an example embodiment, the MAC operator MACi may perform an operation in a MAC stage or a partial sum stage based on the stage information signal SI. For example, the first multiplexer MX1 ​​may output the operation result of the multiplier CA1 or one (Pbi) of the i-th partial sum input Pai and Pbi based on the stage information signal SI. The second multiplexer MX2 may output one (Pai) of the i-th partial sum input Pai and Pbi or data stored in the accumulator register AR based on the stage information signal SI.

[0077] According to an example embodiment, in the MAC stage, the MAC operator MACi may perform a MAC operation on the i-th MAC input Mai and Mbi. For example, the first multiplexer MX1 ​​may output the operation result of the multiplier CA1. The second multiplexer MX2 may output the data stored in the accumulator register AR. The operation result of the adder CA2 may be stored in the accumulator register AR. During the MAC stage, the MAC operator MACi may repeatedly perform a MAC operation through the multiplier CA1, the adder CA2, and the accumulator register AR.

[0078] According to an example embodiment, in the partial sum stage, the MAC operator MACi may perform a partial sum operation on the i-th partial sum input Pai and Pbi. For example, the first multiplexer MX1 ​​may output one (Pbi) of the i-th partial sum input Pai and Pbi. The second multiplexer MX2 may output one (Pai) of the i-th partial sum input Pai and Pbi. The operation result of the adder CA2 may be output as the i-th partial sum result pri.

[0079] Fig.11 It is shown Figure 2 Flowchart of the PIM operation of the PIM unit. Figures 2 to 11 , the memory device 1200 may be based on Figure 1 The memory controller 1100 receives the command CMD or the address ADDR to perform the PIM operation.

[0080] According to an example embodiment, in operation S110, the memory device 1200 may set one or more PIM instructions. For example, when receiving a general command CMD for a PIM operation and a designated address ADDR, the memory device 1200 may perform a PIM operation. In other embodiments, the memory device 1200 may perform a PIM operation when receiving a designated command CMD for a PIM operation.

[0081] According to example embodiments, when receiving an address ADDR or a command CMD for a PIM operation, the control logic 1250 may activate the PIM unit 100. The PIM unit 100 may set a PIM instruction under the control of the control logic 1250. The PIM execution unit 110 may read a PIM instruction from the PIM register 120.

[0082] According to an example embodiment, in operation S120, the memory device 1200 may load data for a PIM operation. For example, the PIM execution unit 110 may load first data from the memory cell array 1210. The PIM execution unit 110 may receive second data from the PIM register 120. The PIM control logic 111 may store the first data and the second data in the PIM register file 112.

[0083] According to example embodiments, in operation S130 , the memory device 1200 may perform a PIM operation. For example, the PIM execution unit 110 may perform a PIM operation based on the first data and the second data. The PIM control logic 111 may perform a PIM operation on the first data and the second data through the PIM operator 113 .

[0084] According to an example embodiment, in operation S140, the memory device 1200 may confirm whether the PIM instruction is completed. For example, the PIM control logic 111 may check whether all set PIM instructions have been completed. When all PIM instructions are completed, the PIM control logic 111 may perform operation S150. When there are at least remaining uncompleted PIM instructions, the PIM control logic 111 may repeatedly perform operations S130 and S140.

[0085] According to example embodiments, in operation S150, the memory device 1200 may store the result data of the PIM operation. For example, the PIM control logic 111 may store the result data of the PIM operation in the PIM register file 112. The PIM execution unit 110 may send the result data of the PIM operation to the memory cell array 1210 or the input / output circuit 1260.

[0086] Fig.12 It shows execution Fig.11Flow chart of the PIM calculation method. Figures 2 to 12 , the PIM unit 100 can perform PIM operations through multiple MAC operators (113_1, 113_2, 113_3, 113_4, ...).

[0087] According to an example embodiment, in operation S131, the PIM unit 100 may perform a MAC operation. For example, the PIM control logic 111 may send a MAC operation start signal to the PIM operator 113. The PIM operator 113 may start a MAC operation based on the MAC operation start signal. As an example, a plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may be set to a MAC stage based on the MAC operation start signal. Each of the plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may perform a MAC operation based on the first data and the second data.

[0088] According to an example embodiment, in operation S132, the PIM unit 100 may confirm whether the MAC operation is completed. For example, the phase manager 113a may check whether a MAC operation completion signal MSD is received. The plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may output a MAC operation completion signal MSD when the MAC operation is completed.

[0089] For example, when the MAC operation completion signal MSD is not received (or when the MAC operation completion signal MSD of a low level is received), the phase manager 113a may output a phase information signal SI indicating a MAC phase (e.g., a first phase information signal). At this time, the PIM unit 100 may repeat operations S131 and S132. When the MAC operation completion signal MSD is received (or the MAC operation completion signal MSD of a high level is received), the phase manager 113a may perform operation S133.

[0090] According to an example embodiment, in operation S133, the PIM unit 100 may confirm whether the partial sum operation is performed. For example, the phase manager 113a may check whether the MAC operation completion signal MSD and the partial sum control signal PSUM are received.

[0091] As an example, upon receiving the MAC operation completion signal MSD (or receiving the high-level MAC operation completion signal MSD) and receiving the partial sum control signal PSUM (or receiving the high-level partial sum control signal PSUM), the phase manager 113a may output a phase information signal SI indicating the partial sum phase (e.g., a second phase information signal). At this time, the PIM unit 100 may perform operation S134.

[0092] As an example, when the MAC operation completion signal MSD is received (or the MAC operation completion signal MSD of a high level is received) and the partial sum control signal PSUM is not received (or the partial sum control signal PSUM of a low level is received), the phase manager 113a may output a phase information signal SI (e.g., a third phase information signal) indicating the output of the MAC operation result. When the third phase information signal is received, the plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may output the MAC operation result without performing the partial sum operation.

[0093] According to an example embodiment, in operation S134, the PIM unit 100 may perform a partial sum operation. For example, when the second stage information signal is received, the plurality of MAC operators (113_1, 113_2, 113_3, 113_4, ...) may perform an operation in the partial sum stage. As an example, the first MAC operator 113_1 may perform a partial sum operation on the first partial sum input Pa1 and Pb1, and output a first partial sum result Pr1. The second MAC operator 113_2 may perform a partial sum operation on the second partial sum input Pa2 and Pb2, and output a second partial sum result Pr2. The third MAC operator 113_3 may perform a partial sum operation on the third partial sum input Pa3 and Pb3, and output a third partial sum result Pr3. The fourth MAC operator 113_4 may perform a partial sum operation on the fourth partial sum input Pa4 and Pb4, and output a fourth partial sum result Pr4.

[0094] Fig.13 It is shown Figure 6 A diagram of an example embodiment of a wiring layout of multiple MAC operators in FIG. Fig.13 An example of using two MAC operators to perform a partial and operation according to an embodiment is shown. Fig.13 , the first MAC operator 113_1 can receive the first MAC input (Ma1, Mb1) and the first partial sum input (Pa1, Pb1), and can output the first MAC result Mr1 and the first partial sum result Pr1. The second MAC operator 113_2 can receive the second MAC input (Ma2, Mb2) and the second partial sum input (Pa2, Pb2), and can output the second MAC result Mr2 and the second partial sum result Pr2.

[0095] According to an example embodiment, in the partial sum stage, the first MAC operator 113_1 may perform a partial sum operation of the first MAC result Mr1 and the second MAC result Mr2. For example, the first accumulator register AR1 may output the first MAC result Mr1. ​​The first MAC result Mr1 may be sent to the first a-part sum input Pa1. The second MAC result Mr2 may be sent to the first b-part sum input Pb1. In the partial sum stage, the first MAC operator 113_1 may perform a partial sum operation, and the second MAC operator 113_2 may be deactivated.

[0096] Fig.14 It is shown Figure 6 A diagram of another example embodiment of a wiring layout of multiple MAC operators in FIG. Fig.14 An example of using three MAC operators to perform partial and operations according to an embodiment is shown. Fig.14 , the first MAC operator 113_1 can receive the first MAC input (Ma1, Mb1) and the first partial sum input (Pa1, Pb1), and can output the first MAC result Mr1 and the first partial sum result Pr1. The second MAC operator 113_2 can receive the second MAC input (Ma2, Mb2) and the second partial sum input (Pa2, Pb2), and can output the second MAC result Mr2 and the second partial sum result Pr2. The third MAC operator 113_3 can receive the third MAC input (Ma3, Mb3) and the third partial sum input (Pa3, Pb3), and can output the third MAC result Mr3 and the third partial sum result Pr3.

[0097] According to an example embodiment, in the partial sum stage, the first MAC operator 113_1 may perform a partial sum operation of a first MAC result Mr1 and a second MAC result Mr2. For example, the first accumulator register AR1 may output the first MAC result Mr1. ​​The first MAC result Mr1 may be sent to the first a-part sum input Pa1. The second MAC result Mr2 may be sent to the first b-part sum input Pb1. The first MAC operator 113_1 may output a first partial sum result Pr1.

[0098] According to an example embodiment, in the partial and stage, the third MAC operator 113_3 may completely output the third MAC result Mr3. For example, the third accumulation register AR3 may output the third MAC result Mr3. The third MAC result Mr3 may be sent to the third a-part and input Pa3. Logic 0 may be input to the third b-part and input Pb3. The third MAC operator 113_3 may output the third MAC result Mr3 as the third partial and result Pr3.

[0099] According to an example embodiment, in the partial sum stage, the second MAC operator 113_2 may perform a partial sum operation of the first partial sum result Pr1 and the third partial sum result Pr3. For example, the first partial sum result Pr1 may be sent to the second a-part sum input Pa2. The third partial sum result Pr3 may be sent to the second b-part sum input Pb2. The second MAC operator 113_2 may output the second partial sum result Pr2.

[0100] Fig.15 It is shown Figure 6 A diagram of another example embodiment of a wiring layout of multiple MAC operators in FIG. Fig.15 An example of using four MAC operators to perform partial and operations according to an embodiment is shown. Fig.15 , the first MAC operator 113_1 can receive the first MAC input (Ma1, Mb1) and the first partial sum input (Pa1, Pb1), and can output the first MAC result Mr1 and the first partial sum result Pr1. The second MAC operator 113_2 can receive the second MAC input (Ma2, Mb2) and the second partial sum input (Pa2, Pb2), and can output the second MAC result Mr2 and the second partial sum result Pr2. The third MAC operator 113_3 can receive the third MAC input (Ma3, Mb3) and the third partial sum input (Pa3, Pb3), and can output the third MAC result Mr3 and the third partial sum result Pr3. The fourth MAC operator 113_4 can receive the fourth MAC input (Ma4, Mb4) and the fourth partial sum input (Pa4, Pb4), and can output the fourth MAC result Mr4 and the fourth partial sum result Pr4.

[0101] According to an example embodiment, in the partial sum stage, the first MAC operator 113_1 may perform a partial sum operation of a first MAC result Mr1 and a second MAC result Mr2. For example, the first accumulator register AR1 may output the first MAC result Mr1. ​​The first MAC result Mr1 may be sent to the first a-part sum input Pa1. The second MAC result Mr2 may be sent to the first b-part sum input Pb1. The first MAC operator 113_1 may output a first partial sum result Pr1.

[0102] According to an example embodiment, in the partial sum stage, the third MAC operator 113_3 may perform a partial sum operation of the third MAC result Mr3 and the fourth MAC result Mr4. For example, the third accumulation register AR3 may output the third MAC result Mr3. The third MAC result Mr3 may be sent to the third a-part sum input Pa3. The fourth accumulation register AR4 may output the fourth MAC result Mr4. The fourth MAC result Mr4 may be sent to the third b-part sum input Pb3. The third MAC operator 113_3 may output the third partial sum result Pr3.

[0103] According to an example embodiment, in the partial sum stage, the second MAC operator 113_2 may perform a partial sum operation of the first partial sum result Pr1 and the third partial sum result Pr3. For example, the first partial sum result Pr1 may be sent to the second a-part sum input Pa2. The third partial sum result Pr3 may be sent to the second b-part sum input Pb2. The second MAC operator 113_2 may output the second partial sum result Pr2.

[0104] According to an embodiment of the present disclosure, since a MAC operation and a partial sum operation are performed by using a plurality of MAC operators included in a PIM unit, an area required for an adder tree may be reduced.

[0105] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A memory device, comprising: a memory cell array; as well as an in-memory processing unit comprising a plurality of multiply and accumulate operators configured to perform multiply and accumulate operations based on data stored in the memory cell array, The plurality of multiplication and accumulation operators are configured to perform the multiplication and accumulation operations based on the data in a first stage, and to perform partial sum operations based on result values ​​of the multiplication and accumulation operations in a second stage.

2. The memory device according to claim 1, wherein: Each of the plurality of multiplication and accumulation operators comprises: a multiplier configured to perform a multiplication operation using the first multiplication and accumulation input and the second multiplication and accumulation input as operands; a first multiplexer configured to output a first operation result or a first partial sum input from the multiplier based on a phase information signal; a second multiplexer configured to output the second portion and the data input or stored in the accumulation register based on the phase information signal; and an adder configured to perform an addition operation on the first output of the first multiplexer and the second output of the second multiplexer, The second operation result output from the adder is stored in the accumulator register.

3. The memory device according to claim 2, wherein: The stage information signal includes a first stage information signal; wherein the first multiplexer is configured to output the first operation result based on the first stage information signal corresponding to the first stage, wherein the second multiplexer is configured to output the data stored in the accumulation register based on the first stage information signal, The adder is configured to store the second operation result in the accumulator register, and The accumulation register is configured to output the second operation result as a multiplication accumulation operation result.

4. The memory device according to claim 2, wherein: The stage information signal includes a second stage information signal; wherein the first multiplexer is configured to output the first portion and input based on the second stage information signal corresponding to the second stage, wherein the second multiplexer is configured to output the second portion and input based on the second stage information signal, and The adder is configured to output the second operation result as a partial sum operation result.

5. The memory device according to claim 1, wherein: The plurality of multiplication and accumulation operators include a first multiplication and accumulation operator and a second multiplication and accumulation operator, wherein the first multiplication and accumulation operator is configured to perform a multiplication and accumulation operation in the first stage using the first multiplication and accumulation input and the second multiplication and accumulation input as operation objects to output a first multiplication and accumulation result, and The second multiplication and accumulation operator is configured to perform a multiplication and accumulation operation using the third multiplication and accumulation input and the fourth multiplication and accumulation input as operation objects in the first stage to output a second multiplication and accumulation result.

6. The memory device according to claim 5, wherein: The first multiplication and accumulation operator is configured to perform a partial sum operation of the first multiplication and accumulation result and the second multiplication and accumulation result in the second stage.

7. The memory device according to claim 1, wherein: The plurality of multiplication and accumulation operators include a first multiplication and accumulation operator, a second multiplication and accumulation operator and a third multiplication and accumulation operator, wherein the first multiplication and accumulation operator is configured to perform a multiplication and accumulation operation in the first stage using the first multiplication and accumulation input and the second multiplication and accumulation input as first operation objects to output a first multiplication and accumulation result, wherein the second multiplication and accumulation operator is configured to perform a multiplication and accumulation operation in the first stage using the third multiplication and accumulation input and the fourth multiplication and accumulation input as second operands to output a second multiplication and accumulation result, and The third multiplication and accumulation operator is configured to perform a multiplication and accumulation operation using the fifth multiplication and accumulation input and the sixth multiplication and accumulation input as third operation objects in the first stage to output a third multiplication and accumulation result.

8. The memory device according to claim 7, wherein: The first multiplication and accumulation operator is configured to perform a partial sum operation of the first multiplication and accumulation result and the second multiplication and accumulation result in the second stage to output a first partial sum result, wherein the third multiplication and accumulation operator is configured to perform a partial sum operation of the third multiplication and accumulation result and logic 0 in the second stage to output a second partial sum result, and The second multiplication and accumulation operator is configured to perform a partial sum operation of the first partial sum result and the second partial sum result in the second stage.

9. The memory device according to claim 1, wherein: The plurality of multiplication and accumulation operators are configured to include a first multiplication and accumulation operator, a second multiplication and accumulation operator, a third multiplication and accumulation operator, and a fourth multiplication and accumulation operator, wherein the first multiplication and accumulation operator is configured to perform a multiplication and accumulation operation in the first stage using the first multiplication and accumulation input and the second multiplication and accumulation input as first operation objects to output a first multiplication and accumulation result, wherein the second multiplication and accumulation operator is configured to perform a multiplication and accumulation operation in the first stage using the third multiplication and accumulation input and the fourth multiplication and accumulation input as second operation objects to output a second multiplication and accumulation result, wherein the third multiplication and accumulation operator is configured to perform a multiplication and accumulation operation in the first stage using the fifth multiplication and accumulation input and the sixth multiplication and accumulation input as third operands to output a third multiplication and accumulation result, and The fourth multiplication and accumulation operator is configured to perform a multiplication and accumulation operation using the seventh multiplication and accumulation input and the eighth multiplication and accumulation input as fourth operands in the first stage to output a fourth multiplication and accumulation result.

10. The memory device according to claim 9, wherein: The first multiplication and accumulation operator is configured to perform a partial sum operation of the first multiplication and accumulation result and the second multiplication and accumulation result in the second stage to output a first partial sum result, wherein the third multiplication and accumulation operator is configured to perform a partial sum operation of the third multiplication and accumulation result and the fourth multiplication and accumulation result in the second stage to output a second partial sum result, wherein the second multiplication and accumulation operator is configured to perform a partial sum operation of the first partial sum result and the second partial sum result in the second stage, and Wherein, the fourth multiplication and accumulation operator is configured to be deactivated in the second stage.

11. The memory device of claim 1 , further comprising: A phase manager is configured to generate a phase information signal determining the first phase or the second phase.

12. The memory device according to claim 11, wherein: The phase manager is further configured to generate a first phase information signal corresponding to the first phase or a second phase information signal corresponding to the second phase based on multiplication and accumulation operation completion signals received from the plurality of multiplication and accumulation operators and a partial sum control signal received from the in-memory processing unit.

13. A method of performing an in-memory process of a memory device, the method comprising: establishing one or more in-memory processing instructions; loading first data for an in-memory processing operation from a memory cell array of the memory device based on the one or more in-memory processing instructions; as well as performing the in-memory processing operation based on the first data, Wherein, executing the in-memory processing operation includes: performing a multiplication and accumulation operation on the first data by a plurality of multiplication and accumulation operators in a first stage; and When the multiplication-accumulation operation is completed, a partial sum operation is performed in a second stage based on the result value of the multiplication-accumulation operation.

14. The method according to claim 13, wherein: Performing the multiplication and accumulation operation includes performing a multiplication and accumulation operation on two multiplication and accumulation inputs in each of the plurality of multiplication and accumulation operators, respectively, to output a multiplication and accumulation result.

15. The method according to claim 14, wherein: Performing the partial sum operation includes inputting the multiplication and accumulation results from the plurality of multiplication and accumulation operators into a first portion of the plurality of multiplication and accumulation operators to output a partial sum operation result.

16. The method according to claim 15, wherein: Executing the partial sum operation also includes: inputting the partial sum operation result into the second part of the plurality of multiplication and accumulation operators to finally output a partial sum operation result.

17. A memory device comprising: a memory cell array; control logic configured to control data input to and data output from the memory cell array, respectively; as well as a plurality of multiplication and accumulation operators configured to perform multiplication and accumulation operations based on data stored in the memory cell array in response to a multiplication and accumulation operation start signal received from the control logic, Wherein, each of the plurality of multiplication and accumulation operators comprises: a multiplier configured to perform a multiplication operation using the first multiplication and accumulation input and the second multiplication and accumulation input as operands; a first multiplexer configured to output a first operation result or a first partial sum input of the multiplier based on a phase information signal; a second multiplexer configured to output the second portion and the data input or stored in the accumulation register based on the phase information signal; and An adder is configured to perform an addition operation on the first output of the first multiplexer and the second output of the second multiplexer.

18. The memory device of claim 17, wherein: The first multiplexer and the second multiplexer are configured to receive a first phase information signal during a first phase, The first multiplexer is further configured to output the first operation result based on the first stage information signal. The second multiplexer is further configured to output the data stored in the accumulation register based on the first stage information signal, The adder is further configured to store the second operation result in the accumulator register, and The accumulation register is configured to output the second operation result as a multiplication accumulation operation result.

19. The memory device of claim 18, wherein: The first multiplexer and the second multiplexer are configured to receive a second phase information signal during a second phase, wherein the first multiplexer is further configured to output the first portion and input based on the second stage information signal, wherein the second multiplexer is further configured to output the second portion and input based on the second stage information signal, and The adder is further configured to output the second operation result as a partial sum operation result.

20. The memory device of claim 17, wherein: The first multiplexer and the second multiplexer are configured to be deactivated in response to receiving a third phase information signal.

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