Memory device, control logic circuit and operating method thereof

Abstract

A memory device includes a memory array configured to store data and a peripheral circuit coupled to the memory array, the peripheral circuit including a control logic circuit to control an operation of the peripheral circuit. The control logic circuit comprises a main control circuit and at least one first sub-control circuit, and the main control circuit and the first sub-control circuit interact through a first trigger signal and a first indication signal. The main control circuit and the first sub-control circuit interact through asynchronous control logic without a global clock signal.

Description

Technical Field

[0001] The present disclosure relates to memory devices, control logic circuits, and operations thereof. Background Art

[0002] A memory device such as a flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. The peripheral circuits of the memory device usually include various register circuits and corresponding control logic circuits, which interact with the main control digital circuits through global clocks and bus protocols to complete the operation of the memory device. However, the wiring on these global clocks and buses is very long, and power is consumed on the clocks and buses. Summary of the invention

[0003] In one aspect, a memory device is disclosed. The memory device includes a memory array configured to store data and a peripheral circuit coupled to the memory array, the peripheral circuit including a control logic circuit to control the operation of the peripheral circuit. The control logic circuit includes a main control circuit and at least one first sub-control circuit, and the main control circuit and the first sub-control circuit interact through a first trigger signal and a first indication signal.

[0004] In some implementations, the main control circuit and the first sub-control circuit interact with each other through asynchronous control logic without a global clock signal.

[0005] In some embodiments, the first sub-control circuit includes an asynchronous control circuit, which is configured to receive the first trigger signal from the main control circuit and generate a local clock signal; and a state machine circuit, which is configured to receive the local clock signal and generate the first indication signal.

[0006] In some embodiments, the asynchronous control circuit includes a first XOR gate, the first XOR gate includes a first input terminal, a second input terminal and a first output terminal, wherein the first input terminal is configured to receive the first trigger signal and the first output terminal is configured to output the local clock signal; a trigger circuit, the trigger circuit includes an enable terminal coupled to the first output terminal of the first XOR gate, a second output terminal, and a data terminal coupled to the second output terminal; and a first delay element, the first delay element is arranged between the second input terminal of the first XOR gate and the second output terminal of the trigger circuit.

[0007] In some embodiments, the trigger circuit includes a D flip-flop. In some embodiments, the asynchronous control circuit further includes an inverter between the data terminal and the second output terminal of the trigger circuit.

[0008] In some embodiments, the state machine circuit includes at least one state, which is triggered by the local clock signal to switch the state, and the state machine circuit includes a clock input terminal configured to receive the local clock signal, a third output terminal configured to output a next signal when the state is switched, and an indication output terminal.

[0009] In some implementations, the indication output terminal is configured to output the first indication signal when the state in the state machine circuit is switched.

[0010] In some embodiments, the memory device also includes a second XOR gate and a second delay element, the second XOR gate including a third input terminal configured to receive the first trigger signal, a fourth input terminal, and a fourth output terminal coupled to the asynchronous control circuit; the second delay element is arranged between the fourth input terminal of the second XOR gate and the third output terminal of the state machine circuit.

[0011] In some embodiments, the fourth output terminal of the second XOR gate is coupled to the first input terminal of the first XOR gate. In some embodiments, the first delay element includes at least one inverter, and the second delay element includes at least one inverter.

[0012] In some embodiments, the control logic circuit further includes a second sub-control circuit, and the main control circuit and the second sub-control circuit interact through a second trigger signal and a second indication signal. In some embodiments, the first sub-control circuit and the second sub-control circuit operate independently.

[0013] In some embodiments, the main control circuit is configured to output the first trigger signal and the second trigger signal, respectively, and receive the first indication signal and the second indication signal, respectively.

[0014] In another aspect, a control logic circuit for controlling the operation of a peripheral circuit of a memory device is disclosed. The control logic circuit includes a main control circuit and at least one first sub-control circuit, and the main control circuit and the at least one first sub-control circuit interact with each other through a first trigger signal and a first indication signal. The sub-control circuit includes an asynchronous control circuit configured to receive the first trigger signal and generate a local clock signal; and a state machine circuit configured to receive the local clock signal and generate a first indication signal.

[0015] In some embodiments, the asynchronous control circuit includes a first XOR gate, the first XOR gate includes a first input terminal, a second input terminal and a first output terminal, wherein the first input terminal is configured to receive the first trigger signal and the first output terminal is configured to output the local clock signal; a trigger circuit, the trigger circuit includes an enable terminal coupled to the first output terminal of the first XOR gate, a second output terminal, and a data terminal coupled to the second output terminal; and a first delay element, the first delay element is arranged between the second input terminal of the first XOR gate and the second output terminal of the trigger circuit.

[0016] In some embodiments, the trigger circuit includes a D flip-flop. In some embodiments, the asynchronous control circuit further includes an inverter between the data terminal and the second output terminal of the trigger circuit.

[0017] In some embodiments, the state machine circuit includes at least one state, which is triggered by the local clock signal to switch the state, and the state machine circuit includes a clock input terminal configured to receive the local clock signal, a third output terminal configured to output a next signal when the state is switched, and an indication output terminal.

[0018] In some implementations, the indication output terminal is configured to output the first indication signal when the state in the state machine circuit is switched.

[0019] In some embodiments, the memory device also includes a second XOR gate and a second delay element, the second XOR gate including a third input terminal configured to receive the first trigger signal, a fourth input terminal, and a fourth output terminal coupled to the asynchronous control circuit; the second delay element is arranged between the fourth input terminal of the second XOR gate and the third output terminal of the state machine circuit.

[0020] In some embodiments, the fourth output terminal of the second XOR gate is coupled to the first input terminal of the first XOR gate. In some embodiments, the first delay element includes at least one inverter, and the second delay element includes at least one inverter.

[0021] In some embodiments, the control logic circuit further includes a second sub-control circuit, and the main control circuit and the second sub-control circuit interact through a second trigger signal and a second indication signal. In some embodiments, the first sub-control circuit and the second sub-control circuit operate independently.

[0022] In some embodiments, the main control circuit is configured to output the first trigger signal and the second trigger signal, respectively, and receive the first indication signal and the second indication signal, respectively.

[0023] In yet another aspect, a method for operating a peripheral circuit of a memory device is disclosed. A trigger signal is generated by a main control circuit, the trigger signal is received by a sub-control circuit, a local clock signal is generated in the sub-control circuit, a state machine circuit in the sub-control circuit is triggered by the local clock signal, an indication signal is generated by the sub-control circuit, and the indication signal is sent to the main control circuit.

[0024] In some implementations, the trigger signal and the first delay signal are combined to generate a request signal, and the request signal is sent to an asynchronous control circuit.

[0025] In some implementations, the request signal and the second delayed signal are combined to generate the local clock signal.

[0026] In some implementations, a flip-flop circuit is triggered by the local clock signal to generate a flip-flop output signal, and the flip-flop output signal is delayed to generate the second delayed signal. In some implementations, the flip-flop output signal is delayed by a delay element.

[0027] In some implementations, at least one state is defined in the state machine circuit, and the states in the state machine circuit are switched sequentially when the local clock signal is received.

[0028] In some implementations, a next state signal is generated when the state in the state machine circuit is switched, and the next state signal is delayed to generate a first delayed signal.

[0029] In some implementations, the indication signal is generated when the state in the state machine circuit is switched, and the indication signal is sent to the main control circuit to indicate that the interaction between the main control circuit and the sub-control circuit is completed.

[0030] In yet another aspect, a method of operating a control logic circuit is disclosed. The control logic circuit includes a main control circuit and at least one sub-control circuit. A trigger signal from the main control circuit is received by the sub-control circuit. A local clock signal is generated in the sub-control circuit in response to receiving the trigger signal. A state machine circuit in the sub-control circuit is triggered by the local clock signal. An indication signal is generated by the sub-control circuit and the indication signal is sent to the main control circuit.

[0031] In some implementations, the trigger signal and the first delay signal are combined to generate a request signal, and the request signal is sent to an asynchronous control circuit.

[0032] In some implementations, the request signal and the second delayed signal are combined to generate the local clock signal.

[0033] In some implementations, a flip-flop circuit is triggered by the local clock signal to generate a flip-flop output signal, and the flip-flop output signal is delayed to generate the second delayed signal. In some implementations, the flip-flop output signal is delayed by a delay element.

[0034] In some implementations, at least one state is defined in the state machine circuit, and the states in the state machine circuit are switched sequentially when the local clock signal is received.

[0035] In some implementations, a next state signal is generated when the state in the state machine circuit is switched, and the next state signal is delayed to generate a first delayed signal.

[0036] In some implementations, the indication signal is generated when the state in the state machine circuit is switched, and the indication signal is sent to the main control circuit to indicate that the interaction between the main control circuit and the sub-control circuit is completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the disclosure and together with the description serve to further explain the disclosure and enable one skilled in the relevant art to make and use the disclosure.

[0038] Figure 1A A block diagram of an exemplary memory device including a memory cell array and peripheral circuits according to some aspects of the present disclosure is shown.

[0039] Figure 1B A schematic circuit diagram of a memory device including peripheral circuits according to some aspects of the present disclosure is shown.

[0040] Figure 2 A block diagram of an exemplary control logic circuit including a main control circuit and several register circuits according to some aspects of the present disclosure is shown.

[0041] Figure 3 A block diagram of an exemplary click element of an asynchronous control circuit according to some aspects of the present disclosure is shown.

[0042] Figure 4 A block diagram of an exemplary control logic circuit including a main control circuit and several sub-control circuits according to some aspects of the present disclosure is shown.

[0043] Figure 5 A block diagram of an exemplary sub-control circuit according to some aspects of the present disclosure is shown.

[0044] Figure 6 A block diagram of an exemplary asynchronous control circuit according to some aspects of the present disclosure is shown.

[0045] Figure 7 A timing diagram of an exemplary control logic circuit according to some aspects of the present disclosure is shown.

[0046] Figure 8 A flow chart illustrating an exemplary method of operating peripheral circuits of a memory device according to some aspects of the present disclosure is shown.

[0047] Fig. 9 A block diagram of an exemplary system having a memory device according to some aspects of the present disclosure is shown.

[0048] Fig. 10A A diagram of an exemplary memory card having a memory device according to some aspects of the present disclosure is shown.

[0049] Fig. 10B A diagram of an exemplary solid-state drive (SSD) having a memory device according to some aspects of the present disclosure is shown.

[0050] Various aspects of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0051] Although specific configurations and arrangements have been discussed, it should be understood that this is done for exemplary purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. Moreover, the present disclosure may also be employed in a variety of other applications. The functions and structural features described in the present disclosure may be combined, adjusted, and modified with each other in a manner not specifically shown in the accompanying drawings, so that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0052] Generally, terms should be understood, at least in part, by the context in which they are used. For example, depending, at least in part, on the context, the term "one or more" as used herein may be used to describe a feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending, at least in part, on the context, terms such as "a," "an," or "the" may be understood to convey singular use or to convey plural use. In addition, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, but rather may allow for the presence of additional factors that may not be explicitly described, again depending, at least in part, on the context.

[0053] Figure 1A A block diagram of an exemplary memory device 100 including a memory cell array 102 and peripheral circuits according to some aspects of the present disclosure is shown. In some embodiments, the peripheral circuits include page buffers / sense amplifiers 104, column decoders / bit line drivers 106, row decoders / word line drivers 108, voltage generators 110, control logic 112, registers 114, interfaces 116, and data buses 118. It should be understood that other peripheral circuits not shown in FIG. 1 may also be included.

[0054] The page buffer / sense amplifier 104 can be configured to read data from the memory cell array 102 and program (write) data to the memory cell array 102 according to a control signal from the control logic 112. In one embodiment, the page buffer / sense amplifier 104 can store a page of programming data (write data) to be programmed into a page of the memory cell array 102. In another example, the page buffer / sense amplifier 104 can perform a programming verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another embodiment, the page buffer / sense amplifier 104 can also sense a low-power signal representing a data bit stored in the memory cell from the bit line in a read operation and amplify the small voltage swing to a recognizable logic level. The column decoder / bit line driver 106 can be configured to be controlled by the control logic 112 according to a control signal from the control logic 112, and select one or more NAND memory strings by applying a bit line voltage generated by the voltage generator 110.

[0055] The row decoder / word line driver 108 may be configured to be controlled by the control logic 112 according to a control signal from the control logic 112, and select / deselect a block of the memory cell array 102 and select / deselect a word line. The row decoder / word line driver 108 may be further configured to drive a word line using a word line voltage generated by the voltage generator 110. The voltage generator 110 may be configured to be controlled by the control logic 112 according to a control signal from the control logic 112, and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be provided to the memory cell array 102.

[0056] The control logic 112 may be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits by generating and sending various control signals. As described in detail below, the control logic 112 may include a main control unit or main control circuit to communicate or interact with several sub-control units or sub-control circuits.

[0057] The interface 116 may be coupled to the control logic 112 and function as an instruction fetcher / buffer and an instruction decoder, thereby decoding instructions received from the memory controller and forwarding the decoded instructions to the control logic 112. The interface 116 may also buffer status information received from the control logic 112 and forward it to the memory controller. The interface 116 may be coupled to the column decoder / bit line driver 106 via a data bus 118 and further function as a data input / output (I / O) interface and a data buffer, thereby buffering and forwarding data to and from the memory cell array 102.

[0058] Figure 1B A schematic circuit diagram of a memory device 150 including a peripheral circuit according to some aspects of the present disclosure is shown. The memory device 150 may include a memory cell array 151 and a peripheral circuit 152 coupled to the memory cell array 151. The memory device 100 may be an example of a memory device 150, wherein the memory cell array 151 and at least the peripheral circuit 152 may be included in the peripheral circuit 104.

[0059] The memory cell array 151 may be a NAND flash memory cell array, wherein the memory cells 156 are provided in an array of NAND memory strings 138. In some embodiments, each NAND memory string 158 includes a plurality of memory cells 156 coupled in series. Each memory cell 156 is capable of holding a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped within the region of the memory cell 156. Each memory cell 156 may be a "floating gate" type memory cell including a floating gate transistor, or may be a "charge trap" type memory cell including a charge trap transistor.

[0060] In some embodiments, each memory cell 156 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, the first memory state "0" may correspond to a first range of voltages, and the second memory state "1" may correspond to a second range of voltages. In some embodiments, each memory cell 156 is a multi-level cell (MLC) capable of storing more than one bit of data in four or more memory states. For example, an MLC is capable of storing two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to present a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erased state to present one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used as an erased state.

[0061] like Figure 1B As shown in , each NAND memory string 158 may include a source select gate (SSG) transistor 160 at its source end and a drain select gate (DSG) transistor 162 at its drain end. The SSG transistor 160 and the DSG transistor 162 may be configured to activate a selected NAND memory string 158 (column of the array) during read and program operations. In some embodiments, each SSG transistor 160 of each NAND memory string 158 within the same memory block 154 is coupled to (e.g.,) ground via a common source line (SL) 164 (e.g., a common SL). According to some embodiments, the DSG transistor 162 of each NAND memory string 158 is coupled to a corresponding bit line 166, and data can be read from or programmed to the bit line 166 via an output bus (not shown). In some embodiments, each NAND memory string 158 is configured to be selected or deselected by applying a selection voltage (e.g., exceeding the threshold voltage of the DSG transistor 162) or a deselection voltage (e.g., 0 V) ​​to a corresponding DSG transistor 162 via one or more DSG lines 163 and / or by applying a selection voltage (e.g., exceeding the threshold voltage of the SSG transistor 160) or a deselection voltage (e.g., 0 V) ​​to a corresponding SSG transistor 160 via one or more SSG lines 165.

[0062] like Figure 1B As shown in , the NAND memory strings 158 can be organized into multiple blocks 154, each of which can have a common source line 164. In some embodiments, each block 154 is a basic data unit for erase operations, for example, all memory cells 156 on the same block 154 are erased at the same time. The memory cells 156 of adjacent NAND memory strings 158 can be coupled by word lines 168, which select which row of memory cells 166 is affected by read and program operations.

[0063] The peripheral circuit 152 may be coupled to the memory cell array 151 through the bit line 166, the word line 168, the source line 164, the SSG line 165, and the DSG line 163. As described above, the peripheral circuit 152 may include any suitable circuits for facilitating the operation of the memory cell array 151 by applying a voltage signal and / or a current signal to each target memory cell 156 via the bit line 166 through the word line 168, the source line 164, the SSG line 165, and the DSG line 163, and sensing a voltage signal and / or a current signal from each target memory cell 206, thereby facilitating the operation. The peripheral circuit 152 may include various types of peripheral circuits formed using CMOS technology.

[0064] Figure 2 A block diagram of an exemplary control logic circuit 200 including a main control circuit 202 and several logic circuits 204 according to some aspects of the present disclosure is shown. In some embodiments of the memory device design, the main control circuit 202 can be placed in the center of the chip, and many other circuits, such as the logic circuit 204 and its corresponding control circuits, are spread out in various areas of the chip. In some embodiments, the logic circuit 204 can include register circuits and related control logic circuits. In some embodiments, the main control circuit 202 and the logic circuit 204 can be placed Figure 1A In some embodiments, the main control circuit 202 and logic circuit 204 can be placed in the control logic 112 to communicate with or control the register 114, the column decoder / bit line driver 106, and the row decoder / word line driver 108. In some embodiments, these circuits interact with the main control circuit 202 that relies on the global clock and bus protocol 206. Since the area of ​​the memory device is large, the wiring on the global clock and bus is long, and in some embodiments, the power consumption on the global clock and bus is almost equal to the power consumption of the main digital circuit itself.

[0065] The present disclosure provides a simplified asynchronous circuit handshake protocol to generate a local clock signal, which replaces the original digital global clock and bus in a memory device, thereby completely saving power consumption on the global clock and bus.

[0066] Figure 3 A block diagram of an exemplary click element 300 of an asynchronous circuit according to some aspects of the present disclosure is shown. Asynchronous circuits (clockless or self-timed circuits) are sequential digital logic circuits that do not require a global clock circuit or signal generator to synchronize their components. Instead, the components are driven by handshake circuits, which indicate the completion of a set of instructions. Asynchronous circuits are a method of designing clockless digital systems. In a process called handshaking between circuit parts that send and receive data, local signaling replaces global synchronization by exchanging request (req) and acknowledgment (ack) signals. In addition to eliminating clock skew, other potential advantages of asynchronous systems include average-case performance, lower energy consumption, and robustness. The handshake is accomplished by a simple data transfer protocol. In some embodiments, the handshake circuit or handshake protocol can be accomplished by the click element 300, which uses request signals (Ri, Ro) and acknowledgment signals (Ai, Ao) to complete the communication between the main control circuit and the registers, such as Figure 3 shown.

[0067] Figure 4FIG. 4 is a block diagram of an exemplary control logic circuit 400 including a main control circuit 402 and several sub-control circuits 404 according to some aspects of the present disclosure. In some embodiments, the main control circuit 402 and the sub-control circuits 404 may be placed in Figure 1A In some embodiments, the main control circuit 402 and the sub-control circuit 404 can be placed in the control logic 112 to communicate with or control the register 114, the column decoder / bit line driver 106, and the row decoder / word line driver 108. Figure 4 As shown, without the need for a global clock signal, the main control circuit 402 and the sub-control circuit 404 interact or communicate through a trigger signal (request signal) "go" and an indication signal (confirmation signal) "done". In some embodiments, the main control circuit 402 can send a "go" signal to the sub-control circuit 404 to indicate the start of data transmission, and the sub-control circuit 404 can send a "done" signal back to the main control circuit 402 to indicate the completion of data transmission.

[0068] In some embodiments, the control logic circuit 400 may include a main control circuit 402 and several different sub-control circuits 404. The trigger signal "go" and the indication signal "done" between the main control circuit 402 and the different sub-control circuits 404 may be independently operated. In other words, the main control circuit 402 outputs trigger signals to different sub-control circuits 404, and receives indication signals from different sub-control circuits 404, respectively.

[0069] By using this handshake protocol, a local clock signal is generated in the sub-control circuit 404 to replace the global clock and bus in the memory device, so that the power consumption of the global clock and bus can be completely saved.

[0070] Figure 5 A block diagram of an exemplary sub-control circuit 404 according to some aspects of the present disclosure is shown. In some embodiments, the sub-control circuit 404 can include an asynchronous control circuit 506 and a state machine circuit 508. In some embodiments, the asynchronous control circuit 506 can be a click element that receives a trigger signal 502 "go" generated by the main control circuit 402. In some embodiments, the asynchronous control circuit 506 can generate a local clock signal "fire" and provide the local clock signal "fire" to the state machine circuit 508.

[0071] In some embodiments, the state machine circuit 508 may include at least one state triggered by a local clock signal "fire" to switch states. In some embodiments, the state machine circuit 508 may have a local clock input terminal "clk" that receives the local clock signal "fire" from the asynchronous control circuit 506. In some embodiments, the number of states in the state machine circuit 508 may be predefined based on actual applications, and the number of states is not limited. In some embodiments, each time a state in the state machine circuit 508 is switched to the next state, the state machine circuit 508 may output a signal "next" at the output terminal to indicate the switching of the state. In some embodiments, when all states defined in the state machine circuit 508 are completely switched, the state machine circuit 508 may output an indication signal 504 "done" at another output terminal to indicate that the data transmission is completed, and send the indication signal "done" back to the main control circuit 402.

[0072] In some embodiments, the sub-control circuit 404 may further include a delay element 510 and an XOR gate 512. In some embodiments, the XOR gate 512 may include an input terminal for receiving a trigger signal 502 "go" generated by the main control circuit 402 and another input terminal for receiving a signal "next_dly" delayed by the delay element 510. The delay element 510 is disposed between the input terminal of the XOR gate 512 and the output terminal of the output signal "next" of the state machine circuit 508. In some embodiments, the delay element 510 may be an inverter to delay the signal "next" by a predefined time. In some embodiments, the predefined time of the delay element 510 may be used to define a low level time of the local clock signal "fire".

[0073] In some implementations, the XOR gate 512 can combine the delayed signal “next_dly” delayed by the delay element 510 with the trigger signal 502 “go” to generate a request signal, and the request signal is provided to the asynchronous control circuit 506 as the trigger signal “in_req”.

[0074] Figure 6 2 shows a block diagram of an asynchronous control circuit 506 according to some aspects of the present disclosure. Figure 6As shown, the asynchronous control circuit 506 may include an XOR gate 602, a flip-flop circuit 604, and a delay element 606. The XOR gate 602 may include an input terminal that receives a trigger signal “in_req” from the trigger signal 502 “go”. The XOR gate 602 may include another input terminal that receives a signal “pul_gen” from the delay element 606, and the XOR gate 602 combines the trigger signal “in_req” and the signal “pul_gen” to generate a local clock signal “fire” at the output terminal of the XOR gate 602. In some embodiments, the flip-flop circuit 604 may include an enable terminal coupled to the output terminal of the XOR gate 602, and the local clock signal “fire” may also be provided to enable the flip-flop circuit 604.

[0075] In some embodiments, the flip-flop circuit 604 may be a D flip-flop. In some embodiments, the flip-flop circuit 604 may include an output terminal coupled to a data terminal of the flip-flop circuit 604 through an inverter 608. In some embodiments, the delay element 606 is disposed between the input terminal of the XOR gate 602 and the output terminal of the flip-flop circuit 604 to delay the output signal of the flip-flop circuit 604 by a predefined time. In some embodiments, the delay element 606 may be an inverter to delay the output signal of the flip-flop circuit 604 by a predefined time. In some embodiments, the predefined time of the delay element 606 may be used to define the high level time of the local clock signal "fire".

[0076] Figure 7 A timing diagram 700 of an exemplary control logic circuit according to some aspects of the present disclosure is shown, and Figure 8 FIG. 8 is a flowchart showing an exemplary method 800 of operating a peripheral circuit of a memory device according to some aspects of the present disclosure. Figure 7 The timing diagram in Figure 8 It is to be understood that the operations shown in method 800 are not exhaustive, and other operations may be performed before, after, or between any of the operations illustrated. In addition, some of the operations may be performed simultaneously or in different order. Figure 7 and Figure 8 Executed in the order shown.

[0077] like Figure 7 as well as Figure 8As shown in operations 802 and 804 of the asynchronous control circuit 506, at time "t0", a trigger signal "go" is generated by the main control circuit 402, and the trigger signal "go" is received by the sub-control circuit 404. In some embodiments, the trigger signal "go" and the delay signal "next_dly" are combined to generate a request signal "in req", and the request signal "in req" is input to the input terminal of the asynchronous control circuit 506.

[0078] like Figure 7 and Figure 8 As shown in operation 806 of , at time “t1”, a local clock signal “fire” is generated in the sub-control circuit 404. In some embodiments, the local clock signal “fire” is generated in the asynchronous control circuit 506. In some embodiments, the request signal “in req” is combined with the delay signal “pul_gen” to generate the local clock signal “fire”. In some embodiments, the flip-flop circuit 604 is triggered by the local clock signal “fire” to generate a flip-flop output signal, and the flip-flop output signal is provided to the delay element 606 to generate the delay signal “pul_gen” that is fed back to the XOR gate 602.

[0079] like Figure 7 As shown, at time "t2", when the delay signal "pul_gen" is at a high level, the XOR gate 602 can combine the delay signal "pul_gen" with the request signal "in req" to pull down the local clock signal "fire". In other words, the predefined time of the delay element 606 can be used to define the high level time of the local clock signal "fire".

[0080] After the local clock signal "fire" is generated, the local clock signal "fire" is provided to the state machine circuit 508 as a clock signal to switch the state in the state machine circuit 508. Figure 7 and Figure 8 As shown in operation 808, at time "t1", the state machine circuit 508 in the sub-control circuit 404 is triggered by the local clock signal "fire". In some embodiments, the state machine circuit 508 may include one or more states predefined based on different applications. When the local clock signal is received, the state machine circuit 508 is switched sequentially.

[0081] In some embodiments, each time the state in the state machine circuit 508 is switched to the next state, the state machine circuit 508 can output a signal "next" at the output terminal to indicate the switching of the state. The signal "next" is provided to the delay element 510 to generate a delayed signal "next_dly" at time "t3". Then, the delayed signal "next_dly" is provided to the XOR gate 512 to be combined with the trigger signal "go" to generate a trigger signal "in_req", and the XOR gate 602 can combine the delayed signal "pul_gen" and the request signal "in req" to pull up the local clock signal "fire". In other words, the predefined time of the delay element 510 can be used to define the low level time of the local clock signal "fire".

[0082] In some embodiments, when all states defined in the state machine circuit 508 are switched sequentially and completely, the state machine circuit 508 may output an indication signal 504 "done" at another output terminal to indicate that the data transmission is completed, and send an indication signal "done" back to the main control circuit 402. Figure 7 as well as Figure 8 As shown in operation 810 , at time “ t4 ”, the indication signal “done” is generated by the sub-control circuit 404 and sent to the main control circuit 402 .

[0083] By using this handshake protocol, a local clock signal is generated in the sub-control circuit 404 to replace the global clock and bus in the memory device, so that the power consumption of the global clock and bus can be completely saved.

[0084] Fig. 9 A block diagram of an exemplary system 900 having a memory device according to some aspects of the present disclosure is shown. The system 900 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other electronic device having a memory located therein. Fig. 9 As shown in , system 900 may include a host 908 and a memory system 902, the memory system 902 having one or more memory devices 904 and a memory controller 906. The host 908 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system on a chip (SoC), such as an application processor (AP). The host 908 may be configured to send or receive data to or from the memory device 904.

[0085] The memory device 904 may be any memory device disclosed in the present disclosure, for example, the memory device 100. As disclosed in detail above, the memory device 904 may have a controlled predefined discharge current in a discharge operation of discharging a bit line. According to some embodiments, a memory controller 906, such as the control logic circuit 400 described above, is coupled to the memory device 904 and a host 908, and is configured to control the memory device 904. The memory controller 906 may manage data stored in the memory device 904 and communicate with the host 908. For example, the memory controller 906 may be coupled to the memory device 904 (e.g., the memory device 100 described above), and the memory controller 906 may be configured to control the operation of the memory unit through a peripheral device.

[0086] In some embodiments, the memory controller 906 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 906 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 906 can be configured to control the operation of the memory device 904, such as read, erase, and program operations. The memory controller 906 can also be configured to manage various functions related to data stored in or to be stored in the memory device 904, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 906 is further configured to process error correction code (ECC) related to data read from or written to the memory device 904. Any other suitable functions may also be performed by the memory controller 906, for example, formatting the memory device 904. The memory controller 906 may communicate with an external device (e.g., the host 908) according to a specific communication protocol. For example, the memory controller 906 may communicate with the external device through at least one of various interface protocols such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced mini disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0087] The memory controller 906 and the one or more memory devices 904 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 902 may be implemented and packaged into different types of terminal electronic products. Fig. 10A In one example shown, the memory controller 906 and the single memory device 904 may be integrated into a memory card 1002. The memory card 1002 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1002 may further include a processor that connects the memory card 1002 to a host (e.g., Fig. 9 The memory card connector 1004 is coupled to the host 908 in FIG. Fig. 10B In another example shown, the memory controller 906 and the plurality of memory devices 904 may be integrated into the SSD 1006. The SSD 1006 may further include a processor that interfaces the SSD 1006 with a host (e.g., Fig. 9 In some implementations, the storage capacity and / or operating speed of the SSD 1006 is higher than the storage capacity and / or operating speed of the memory card 1002.

[0088] The description of the above specific embodiments can be easily modified and / or adapted for various applications. Therefore, based on the teaching and guidance provided herein, it is intended that such adjustments and modifications fall within the meaning and equivalents of the disclosed embodiments.

[0089] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A memory device, comprising: a memory array configured to store data; as well as a peripheral circuit coupled to the memory array and including a control logic circuit to control the operation of the peripheral circuit, The control logic circuit includes a main control circuit and at least one first sub-control circuit, and the main control circuit and the first sub-control circuit interact with each other through a first trigger signal and a first indication signal.

2. The memory device according to claim 1, wherein: The main control circuit and the first sub-control circuit interact with each other through asynchronous control logic without requiring a global clock signal.

3. The memory device according to claim 1, wherein: The first sub-control circuit comprises: an asynchronous control circuit configured to receive the first trigger signal from the main control circuit and generate a local clock signal; and A state machine circuit is configured to receive the local clock signal and generate the first indication signal.

4. The memory device according to claim 3, wherein: The asynchronous control circuit comprises: a first XOR gate, the first XOR gate comprising a first input terminal, a second input terminal and a first output terminal, wherein the first input terminal is configured to receive the first trigger signal, and the first output terminal is configured to output the local clock signal; a trigger circuit, the trigger circuit comprising an enable terminal coupled to the first output terminal of the first XOR gate, a second output terminal, and a data terminal coupled to the second output terminal; and A first delay element is arranged between the second input terminal of the first XOR gate and the second output terminal of the trigger circuit.

5. The memory device according to claim 4, wherein: The trigger circuit includes a D trigger.

6. The memory device according to claim 4, wherein: The asynchronous control circuit further includes an inverter between the data terminal and the second output terminal of the flip-flop circuit.

7. The memory device according to claim 4, wherein: The state machine circuit includes at least one state, which is triggered by the local clock signal to switch the state, and the state machine circuit includes a clock input terminal configured to receive the local clock signal, a third output terminal configured to output a next signal when the state is switched, and an indication output terminal.

8. The memory device according to claim 7, wherein: The indication output terminal is configured to output the first indication signal when the state in the state machine circuit is switched.

9. The memory device of claim 7, further comprising: a second XOR gate, the second XOR gate comprising a third input terminal configured to receive the first trigger signal, a fourth input terminal, and a fourth output terminal coupled to the asynchronous control circuit; as well as A second delay element is provided between the fourth input terminal of the second XOR gate and the third output terminal of the state machine circuit.

10. The memory device according to claim 9, wherein: The fourth output terminal of the second XOR gate is coupled to the first input terminal of the first XOR gate.

11. The memory device according to claim 9, wherein: The first delay element includes at least one inverter, and the second delay element includes at least one inverter.

12. The memory device according to claim 1, wherein: The control logic circuit also includes a second sub-control circuit, and the main control circuit and the second sub-control circuit interact with each other through a second trigger signal and a second indication signal.

13. The memory device according to claim 12, wherein: The first sub-control circuit and the second sub-control circuit are independently operated.

14. The memory device according to claim 13, wherein: The main control circuit is configured to output the first trigger signal and the second trigger signal, respectively, and receive the first indication signal and the second indication signal, respectively.

15. A control logic circuit for controlling the operation of a peripheral circuit of a memory device, comprising: a main control circuit and at least one first sub-control circuit, wherein the main control circuit and the at least one sub-control circuit interact with each other through a first trigger signal and a first indication signal, Wherein, the sub-control circuit includes: an asynchronous control circuit configured to receive the first trigger signal and generate a local clock signal; and A state machine circuit is configured to receive the local clock signal and generate the first indication signal.

16. The control logic circuit according to claim 15, wherein: The asynchronous control circuit comprises: a first XOR gate, the first XOR gate comprising a first input terminal, a second input terminal and a first output terminal, wherein the first input terminal is configured to receive the first trigger signal, and the first output terminal is configured to output the local clock signal; a trigger circuit, the trigger circuit comprising an enable terminal coupled to the first output terminal of the first XOR gate, a second output terminal, and a data terminal coupled to the second output terminal; and A first delay element is arranged between the second input terminal of the first XOR gate and the second output terminal of the trigger circuit.

17. The control logic circuit according to claim 16, wherein: The trigger circuit includes a D trigger.

18. The control logic circuit according to claim 16, wherein: The asynchronous control circuit further includes an inverter between the data terminal and the second output terminal of the flip-flop circuit.

19. The control logic circuit according to claim 16, wherein: The state machine circuit includes at least one state, which is triggered by the local clock signal to switch the state, and the state machine circuit includes a clock input terminal configured to receive the local clock signal, a third output terminal configured to output a next signal when the state is switched, and an indication output terminal.

20. The control logic circuit according to claim 19, wherein: The indication output terminal is configured to output the first indication signal when the state in the state machine circuit is switched.

21. The control logic circuit of claim 19, further comprising: a second XOR gate, the second XOR gate comprising a third input terminal configured to receive the first trigger signal, a fourth input terminal, and a fourth output terminal coupled to the asynchronous control circuit; as well as A second delay element is provided between the fourth input terminal of the second XOR gate and the third output terminal of the state machine circuit.

22. The control logic circuit according to claim 21, wherein: The fourth output terminal of the second XOR gate is coupled to the first input terminal of the first XOR gate.

23. The control logic circuit according to claim 21, wherein: The first delay element includes at least one inverter, and the second delay element includes at least one inverter.

24. The control logic circuit according to claim 15, further comprising a second sub-control circuit, wherein: The main control circuit and the second sub-control circuit interact with each other through a second trigger signal and a second indication signal.

25. The control logic circuit of claim 24, wherein: The first sub-control circuit and the second sub-control circuit are independently operated.

26. The control logic circuit according to claim 25, wherein: The main control circuit is configured to output the first trigger signal and the second trigger signal, respectively, and receive the first indication signal and the second indication signal, respectively.

27. A method of operating a peripheral circuit of a memory device, comprising: A trigger signal is generated by the main control circuit; The sub-control circuit receives the trigger signal; generating a local clock signal in the sub-control circuit; triggering a state machine circuit in the sub-control circuit by the local clock signal; as well as An indication signal is generated by the sub-control circuit and sent to the main control circuit.

28. The method according to claim 27, wherein: Receiving the trigger signal by the sub-control circuit includes: combining the trigger signal and the first delay signal to generate a request signal; and The request signal is sent to an asynchronous control circuit.

29. The method according to claim 28, wherein: Generating the local clock signal in the sub-control circuit includes: The request signal and the second delayed signal are combined to generate the local clock signal.

30. The method of claim 29, further comprising: triggering a trigger circuit by the local clock signal to generate a trigger output signal; as well as The flip-flop output signal is delayed to generate the second delayed signal.

31. The method according to claim 30, wherein: Delaying the trigger output signal to generate the second delayed signal comprises: The flip-flop output signal is delayed by a delay element.

32. The method of claim 28, wherein: Triggering the state machine circuit in the sub-control circuit by the local clock signal includes: defining at least one state in the state machine circuit; and The states in the state machine circuit are switched sequentially when the local clock signal is received.

33. The method of claim 32, further comprising: generating a next state signal when the state in the state machine circuit is switched; as well as The next state signal is delayed to generate the first delayed signal.

34. The method of claim 33, wherein: Generating the indication signal by the sub-control circuit and sending the indication signal to the main control circuit comprises: generating the indication signal when the state in the state machine circuit is switched; and The indication signal is sent to the main control circuit to indicate completion of the interaction between the main control circuit and the sub-control circuit.

35. A method of operating a control logic circuit, wherein: The control logic circuit includes a main control circuit and at least one sub-control circuit, including: The sub-control circuit receives a trigger signal from the main control circuit; generating a local clock signal in the sub-control circuit in response to receiving the trigger signal; triggering a state machine circuit in the sub-control circuit by the local clock signal; and An indication signal is generated by the sub-control circuit and sent to the main control circuit.

36. The method of claim 35, wherein: Receiving the trigger signal from the main control circuit by the sub-control circuit includes: combining the trigger signal and the first delay signal to generate a request signal; and The request signal is sent to an asynchronous control circuit.

37. The method of claim 36, wherein: Generating the local clock signal in the sub-control circuit in response to receiving the trigger signal comprises: The request signal and the second delayed signal are combined to generate the local clock signal.

38. The method of claim 37, further comprising: triggering a trigger circuit by the local clock signal to generate a trigger output signal; as well as The flip-flop output signal is delayed to generate the second delayed signal.

39. The method of claim 38, wherein: Delaying the trigger output signal to generate the second delayed signal comprises: The flip-flop output signal is delayed by a delay element.

40. The method of claim 36, wherein: Triggering the state machine circuit in the sub-control circuit by the local clock signal includes: defining at least one state in the state machine circuit; and The states in the state machine circuit are switched sequentially when the local clock signal is received.

41. The method of claim 40, further comprising: generating a next state signal when the state in the state machine circuit is switched; as well as The next state signal is delayed to generate the first delayed signal.

42. The method according to claim 41, wherein: Generating the indication signal by the sub-control circuit and sending the indication signal to the main control circuit comprises: generating the indication signal when the state in the state machine circuit is switched; and The indication signal is sent to the main control circuit to indicate completion of the interaction between the main control circuit and the sub-control circuit.

43. A memory system comprising: Memory controller; as well as A memory device coupled to the memory controller and comprising: a memory array configured to store data; and a peripheral circuit coupled to the memory array and including a control logic circuit to control the operation of the peripheral circuit, The control logic circuit includes a main control circuit and at least one first sub-control circuit, and the main control circuit and the first sub-control circuit interact with each other through a first trigger signal and a first indication signal.

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