Operation method of memory, memory and memory system

Abstract

The invention provides an operation method of a memory, the memory and a memory system, and relates to the technical field of semiconductor chips. The operation method comprises the following steps: in response to a first reading instruction, applying a reading voltage to a word line, reading data of a plurality of storage units to obtain a first reading result, and in response to a second reading instruction, applying the reading voltage to the word line, reading the data of the plurality of storage units to obtain a second reading result, and determining a target memory cell according to the first reading result and the second reading result, applying a reading voltage to a word line coupled to the target memory cell, and performing a reading operation on the target memory cell to obtain a true random binary sequence. When data are encrypted in a 3D NAND product, the generated true random binary sequence can be used for encryption, so that the problem of relatively low data security caused by data encryption by using a pseudo-random number can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a memory operation method, a memory, and a storage system. Background Art

[0002] At present, data security has received widespread attention, and in this context, the data encryption issue of 3D NAND products has become particularly important. Data encryption aims to protect sensitive information from unauthorized access and theft. Therefore, for the data stored in 3D NAND chips, its security is of vital importance. Data encryption of 3D NAND products often relies on the generation of random numbers, and existing 3D NAND products use pseudo-random numbers generated by a pseudo-randomized numbers generator (PRNG) for data encryption. Summary of the invention

[0003] The embodiments of the present disclosure provide a memory operation method, a memory, and a storage system, aiming to improve the problem that using pseudo-random numbers to perform data encryption in 3D NAND products will lead to reduced data security.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In a first aspect, a method for operating a memory is provided, the method comprising: in response to a first read instruction, applying a read voltage to a word line, reading data of a plurality of memory cells, and obtaining a first read result, wherein the plurality of memory cells are coupled to the word line; in response to a second read instruction, applying a read voltage to the word line, reading data of the plurality of memory cells, and obtaining a second read result; if a difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than a threshold value, determining a memory cell in the plurality of memory cells whose first read result is different from the second read result as a target memory cell, applying a read voltage to the word line coupled to the target memory cell, performing a read operation on the target memory cell, and obtaining a truly random binary sequence.

[0006] The memory operation method provided by the present disclosure screens out the target memory cells that are easily affected by random noise by comparing the results of multiple reads. And by reading the storage state of the target memory cell again, the logic value corresponding to its storage state is used as a true random number. By using the physical characteristics of the memory cell to generate a true random number, and based on the unpredictable true random number to encrypt data, the security requirements of data encryption are met. And because no additional circuit is added, there is no increase in production cost and increase in product volume.

[0007] In some embodiments, the memory includes a page buffer, the memory includes a page buffer circuit, the page buffer circuit includes a first latch, a first data latch and a second data latch, and in response to a first read instruction, a read voltage is applied to a word line to read data of multiple storage cells, and obtain a first read result including: reading data of multiple storage cells and storing the read data in the first latch, and ANDing the data stored in the first latch with mask data of a preset storage state pre-stored in the first data latch to obtain a first read result, and storing the first read result in the second data latch.

[0008] In some embodiments, the page buffer circuit also includes a second latch and a VFC (voltage to frequency converter, VFC) circuit. In response to a first read instruction, a read voltage is applied to the word line to read data of multiple storage cells. Obtaining the first read result also includes: transferring the data stored in the second data latch to the second latch, and counting the number of first logic values ​​stored in the second latch through the VFC circuit.

[0009] In some embodiments, in response to a second read instruction, a read voltage is applied to the word line, data of multiple storage cells are read, and a second read result is obtained, including: reading data of multiple storage cells and storing the read data in a first latch, and ANDing the data stored in the first latch with mask data of a preset storage state pre-stored in the first data latch to obtain a second read result, and storing the second read result in the first latch.

[0010] In some embodiments, in response to a second read instruction, a read voltage is applied to the word line, data of multiple storage cells are read, and a second read result is obtained, including: reading data of multiple storage cells and storing the read data in a first latch, and ANDing the data stored in the first latch with mask data of a preset storage state pre-stored in the first data latch to obtain a second read result, and storing the second read result in the first latch.

[0011] In some embodiments, the page buffer circuit further includes a second latch and a VFC circuit, and in response to a second read instruction, applies a read voltage to the word line, reads data of a plurality of memory cells, and obtains a second read result, further comprising:

[0012] The data stored in the first latch is transferred to the second latch, and the number of the first logic values ​​stored in the second latch is counted by the VFC circuit.

[0013] In some embodiments, before reading the data of the plurality of memory cells, the method further includes: storing mask data of a preset storage state into a first data latch.

[0014] In some embodiments, determining a storage unit having a first read result and a second read result different from each other among a plurality of storage units as a target storage unit comprises: performing an XOR operation on the data stored in the second data latch and the data stored in the first latch, and storing the XOR result in the first latch;

[0015] The memory cell corresponding to the first latch storing a logic value of 1 is determined as the target memory cell.

[0016] In some embodiments, the method also includes: if the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is greater than or equal to a threshold, repeatedly executing the first read instruction and the second read instruction to read data of multiple storage cells and obtain the first read result and the second read result respectively, until the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than the threshold.

[0017] In a second aspect, a memory is provided, comprising: a memory cell array and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to: in response to a first read instruction, apply a read voltage to a word line, read data of a plurality of memory cells, and obtain a first read result, wherein the plurality of memory cells are coupled to the word line, and in response to a second read instruction, apply a read voltage to the word line, read data of the plurality of memory cells, and obtain a second read result, and if the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than a threshold value, determine a memory cell among the plurality of memory cells whose first read result is different from the second read result as a target memory cell, apply a read voltage to the word line coupled to the target memory cell, perform a read operation on the target memory cell, and obtain a truly random binary sequence.

[0018] In some embodiments, the peripheral circuit also includes a page buffer circuit, the peripheral circuit includes a page buffer circuit, the page buffer circuit includes a first latch, a first data latch and a second data latch, the page buffer circuit is specifically configured to: read data of multiple storage cells, and store the read data in the first latch, and perform ANDing on the data stored in the first latch with the mask data of a preset storage state pre-stored in the first data latch to obtain a first reading result, and store the first reading result in the second data latch.

[0019] In some embodiments, the page buffer circuit further includes a second latch and a VFC circuit, and the page buffer circuit is specifically configured to: transfer the data stored in the second data latch to the second latch, and count the number of first logic values ​​stored in the second latch through the VFC circuit.

[0020] In some embodiments, the peripheral circuit further includes a page buffer circuit, the page buffer circuit includes a first latch and a first data latch, and the page buffer circuit is specifically configured to: read data of a plurality of storage cells and store the read data in the first latch,

[0021] The data stored in the first latch is ANDed with the mask data of the preset storage state pre-stored in the first data latch to obtain a first reading result, and the first reading result is stored in the first latch.

[0022] In some embodiments, the page buffer circuit further includes a second latch and a VFC circuit, and the page buffer circuit is specifically configured to: transfer the data stored in the first latch to the second latch, and count the number of first logic values ​​stored in the second latch through the VFC circuit.

[0023] In some embodiments, the page buffer circuit is further configured to store the mask data of a preset storage state into the first data latch.

[0024] In some embodiments, the page buffer circuit is specifically configured to: XOR the data stored in the second data latch with the data stored in the first latch, store the XOR result in the first latch, and determine the storage cell corresponding to the first latch storing the logic value of 1 as the target storage cell.

[0025] In some embodiments, the page buffer circuit is further configured to: if the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is greater than or equal to a threshold, then repeatedly execute in response to the first read instruction, read data of multiple storage cells and the second read operation, and obtain the first read result and the second read result respectively, until the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than the threshold.

[0026] In a third aspect, a storage system is provided, comprising: a memory, and a storage controller, wherein the storage controller is connected to the memory via a flash memory interface circuit; the storage controller is the memory provided by any embodiment of the second aspect.

[0027] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, any one of the methods in the first aspect above can be implemented.

[0028] In a fifth aspect, an electronic device is provided, including a host such as the storage system provided in the third aspect, wherein the host is connected to the storage system to write data to the storage system or read data stored in the storage system.

[0029] It can be understood that the technical effects of the second to fifth aspects refer to the technical effects of the first aspect and any embodiment thereof, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A block diagram of an electronic device provided for an embodiment of the present disclosure;

[0031] Figure 2 A block diagram of a storage system provided in an embodiment of the present disclosure;

[0032] Figure 3 A block diagram of another storage system provided in an embodiment of the present disclosure;

[0033] Figure 4 A schematic diagram of the distribution of the threshold voltage of a memory cell provided in an embodiment of the present disclosure;

[0034] Figure 5 A schematic diagram of the structure of a memory and peripheral circuits provided in an embodiment of the present disclosure;

[0035] Figure 6 A schematic diagram of a flow chart of a method for operating a memory provided by an embodiment of the present disclosure;

[0036] Figure 7 A schematic diagram of another distribution of memory cell threshold voltages provided by an embodiment of the present disclosure;

[0037] Figure 8 A schematic diagram of another distribution of memory cell threshold voltages provided by an embodiment of the present disclosure;

[0038] Fig. 9 A schematic diagram of another distribution of memory cell threshold voltages provided by an embodiment of the present disclosure;

[0039] Fig.10 A schematic diagram of another distribution of memory cell threshold voltages provided by an embodiment of the present disclosure;

[0040] Fig.11 A schematic diagram of another distribution of memory cell threshold voltages provided by an embodiment of the present disclosure;

[0041] Fig.12 A schematic diagram of another distribution of memory cell threshold voltages provided by an embodiment of the present disclosure;

[0042] Fig.13 A schematic diagram of the structure of a page buffer circuit provided by an embodiment of the present disclosure;

[0043] Fig.14 A schematic diagram of a flow chart of a method for operating a memory provided by an embodiment of the present disclosure;

[0044] Fig.15A flowchart of a method for operating a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0046] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0047] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0048] When describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. In this case, "coupled" may also be described as "connected". In addition, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0049] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0050] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B. The use of "suitable for" or "configured to" herein is meant to be open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps. In addition, the use of "based on" is meant to be open and inclusive, because a process, step, calculation or other action "based on" one or more conditions or values ​​can be based on additional conditions or beyond values ​​in practice.

[0051] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0052] The embodiments of the present disclosure provide an electronic device, which may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc. Figure 1 , Figure 1 A schematic diagram of an electronic device 10 provided by an embodiment of the present disclosure is shown, including a host 100 and a storage system 110. The host 100 is coupled to the storage system 110 to write data to the storage system 110 or read data stored in the storage system 110. The host is also called a master device, and the storage system is also called a slave device. In an electronic device, a slave device can be accessed by different master devices. For example, taking the electronic device as a mobile phone as an example, the central processing unit (CPU) and digital signal processor (DSP) of the mobile phone can all access the storage system as a host.

[0053] For example, see Figure 2 , Figure 2 A schematic diagram of a storage system 110 provided in an embodiment of the present disclosure is shown, the storage system 110 includes a storage controller 111 and a memory 112, the storage controller 111 is coupled to the memory 112 to control the memory 112 to store data. The memory 112 may be a two-dimensional (2-dimension, 2D) memory or a three-dimensional (3-dimension, 3D) memory.

[0054] The storage system 110 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package). That is, the storage system 110 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0055] In some embodiments, the storage system 110 includes a storage controller 111 and a memory 112, and the storage system 110 can be integrated into a memory card. The memory card includes any one of a personal computer memory card international association (PCMCIA) card (abbreviated as PC card), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD) card, and a UFS.

[0056] In other embodiments, see Figure 3 The storage system 110 includes a storage controller 111 and a plurality of memories 112 , and the storage system 110 is integrated into solid state drives (SSDs).

[0057] In the storage system 110, in some embodiments, the storage controller 111 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0058] In other embodiments, the storage controller 111 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0059] In some embodiments, the storage controller 111 may be configured to manage data stored in the memory 112 and communicate with an external device (e.g., the host 100). In some embodiments, the storage controller 111 may also be configured to control operations of the memory 112, such as read, erase, and program operations. In some embodiments, the storage controller 111 may also be configured to manage various functions regarding data stored or to be stored in the memory 112, including at least one of bad block management, garbage collection (GC), logical to physical address conversion, and wear leveling. In some embodiments, the storage controller 111 is also configured to process error correction codes regarding data read from or written to the memory 112.

[0060] In addition, the storage controller 111 can communicate with an external device (e.g., the host 100) through at least one of various interface protocols. It should be noted that the interface protocol includes at least one of a universal serial bus (USB) protocol, a Microsoft Management Console (MMC) protocol, a peripheral component interconnect (Peripheral Component Interconnect), a PCI protocol, a PCI Express (Peripheral Component Interconnect Express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronic (IDE) protocol, and a FireWire protocol.

[0061] For 3D NAND products, using pseudo-random numbers generated by a pseudo-random number generator for data encryption will bring some security and predictability issues:

[0062] Predictability: A pseudo-random number generator generates a seemingly random sequence of numbers through an algorithm, but in fact it generates a random sequence of numbers based on an initial seed value. If an attacker can obtain or guess the seed value, the pseudo-random number sequence can be reproduced, thereby breaking the encryption.

[0063] Reduced security: The algorithm of the pseudo-random number generator is known, so attackers can analyze the algorithm to find patterns or weaknesses that can lead to password cracking or attack.

[0064] Reuse risk: If the pseudo-random number generator uses the same initial seed value to generate sequences, then the sequences generated with the same seed value will also be the same.

[0065] In summary, if pseudo-random numbers generated by a pseudo-random number generator are used for data encryption in 3D NAND products, the security of encryption may be reduced and the ability to resist attacks may be weakened. In order to avoid the above risks, a true random number generator (TRNG) can be used to generate true random numbers that meet the randomness requirements. A true random number generator uses the unpredictability in a physical process or device to generate truly random numbers. Unlike a pseudo-random number generator, a true random number generator does not rely on a deterministic algorithm or seed value, but uses the randomness of a physical process to generate random numbers. Therefore, a true random number generator relies on unpredictable physical processes, making it difficult for attackers to predict the generated random numbers and crack encryption.

[0066] As for 3D NAND products, adding a true random number generator to existing products will lead to problems such as increased costs and larger product size.

[0067] On the one hand, adding a true random number generator will lead to a significant increase in costs. Designing, manufacturing, and integrating such a circuit usually requires additional R&D resources and technical investment. This may increase the production cost of the product.

[0068] On the other hand, adding a true random number generator will lead to an increase in product size. 3D NAND products usually adopt a compact design to achieve greater storage capacity within a relatively small physical size. In this case, the introduction of additional circuits may limit the flexibility of product design, making it difficult for the product to accommodate more components within the existing volume framework.

[0069] In the above context, how to realize the application of true random number generator while keeping the cost and product volume reasonable is a key issue in the field of 3D NAND products.

[0070] Based on this, an embodiment of the present disclosure provides a solution: using the electronic devices in the 3D NAND product itself to build a true random number generator, that is, making full use of the physical properties of the electronic devices in the 3D NAND itself to generate true random numbers without introducing additional circuits or components.

[0071] For the memory cell, there is random read noise. Under the influence of random read noise, the threshold voltage of the memory cell will be disturbed or changed unpredictably and irregularly. Random read noise exists naturally and is not affected by external factors. Therefore, it has a truly random nature. Due to the influence of random read noise, the threshold voltage of the memory cell will change.

[0072] For example, see Figure 4 , the inherent threshold voltage of the memory cell is near the read voltage Vrd. If at time T1, the threshold voltage of the memory cell is affected by random read noise and reduced (shifted to the left), then at time T1, if the read voltage Vrd is continued to be used for reading, the state stored in the memory cell will be read as the first logic value "1". If at time T2, the threshold voltage of the memory cell is affected by random read noise and increased (shifted to the right), then at time T2, if the read voltage Vrdd is continued to be used for reading, the state stored in the memory cell will be read as the second logic value "0". Therefore, if the inherent threshold voltage of the memory cell is near the read voltage, due to the influence of random read noise, its threshold voltage will also change randomly, causing the state of the read memory cell to fluctuate between the second logic value "0" and the first logic value "1".

[0073] Figure 5 A schematic diagram of the structure of a memory cell array and peripheral circuits is shown. Figure 5 In the embodiment, the peripheral circuit 400 includes an I / O interface 410, a control logic circuit 420, a row decoder 430, a voltage generator 440, a column decoder 450, a page buffer circuit 460, a data bus 470, and a register 480. It should be understood that in some examples, the peripheral circuit 400 may also include Figure 5 Additional circuitry not shown.

[0074] I / O interface 410 may be coupled to control logic circuit 420 and act as a control buffer to buffer data from a storage controller (eg, Figure 2 The I / O interface 410 may also be coupled to the page buffer circuit 460 via the data bus 470 to buffer data and relay it to or from the memory cell array 300.

[0075] The control logic circuit 420 may be coupled to the voltage generator 440, the page buffer circuit 460, the column decoder 450, the row decoder 430, the I / O interface 410, etc., and is configured to control the operation of each peripheral circuit. The control logic circuit 420 may generate an operation signal to control the operation of the row decoder 430, the column decoder 450, the page buffer circuit 460, and the voltage generator 440 in response to a command (CMD) or a control signal from the memory controller 111; wherein the command may be a program command, a read command, etc.

[0076] The row decoder 430 may supply the word line voltage generated from the voltage generator 440 to the selected word lines and the unselected word lines of the memory cell array 300 in response to the control of the control logic circuit 420. As described in detail below, the row decoder 430 is configured to perform a program operation on the memory cells coupled to one or more selected word lines in the memory cell array 300.

[0077] The voltage generator 440 may generate various voltages for performing operations such as erasing, programming, reading, and verifying on the memory cell array 300 using an external power supply voltage or an internal power supply voltage.

[0078] The column decoder 450 may be controlled in response to the control logic circuit 420 , and select one or more memory cell strings in the memory cell array 300 by applying a bit line voltage generated from the voltage generator 440 .

[0079] The page buffer circuit 460 can read data from the memory cell array 300 and program (write) data to the memory cell array 300 according to the control signal from the control logic circuit 420. In one example, the page buffer circuit 460 can store the programming data (write data) to be programmed into the memory cell array 300. In another example, the page buffer circuit 460 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer circuit 460 can also detect a low-power signal from a bit line representing a data bit stored in the memory cell, and amplify the small voltage swing to a recognizable logic level in a read operation.

[0080] The register 480 may be coupled to the control logic circuit 420 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit.

[0081] Specifically, when the peripheral circuit 400 works, the following steps are performed: Figure 6The operation method shown includes steps S10-S40, and the peripheral circuit 400 can execute the steps from S10 to S40.

[0082] In some embodiments, in the process of constructing a true random number generator, it is necessary to screen out target storage units with random characteristics as entropy sources, and the number of target storage units to be deployed needs to be determined based on actual application requirements. However, it should be noted that the number of target storage units as entropy sources needs to be much larger than the maximum number of binary random numbers required for data encryption.

[0083] For example, if data encryption in a 3D NAND product requires a binary sequence of up to 8 bits in length, the number of target storage units can be 12, which not only meets the needs of data encryption, but also provides additional spare target storage units. The advantage of this redundant design is that even if some target storage units are damaged during use, true random numbers can still be generated from the spare target storage units.

[0084] Secondly, after determining the number of target memory cells to be laid out, the number of target memory cells to be laid out is compared with the maximum number threshold of target memory cells that can be screened out on a word line, and the maximum number threshold is a pre-calibrated value. If the number of target memory cells to be laid out is less than or equal to the maximum number threshold of target memory cells that can be screened out on a word line, a word line is randomly selected, and the operations of steps S10-S20 are performed on the memory cells coupled thereto, thereby screening out the target memory cells. If the number of target memory cells to be laid out is greater than the number threshold of target memory cells that can be screened out on a word line, multiple word lines that meet the number of laying out are randomly selected, and the operations of steps S10-S20 are performed on the memory cells coupled thereto, thereby screening out the target memory cells.

[0085] Before executing step S10 , an erase voltage is applied to the selected word line to erase the data of the memory cell coupled to the selected word line.

[0086] Exemplarily, in the erasing phase, the control logic circuit 420 controls the row decoder 430 to apply the erasing voltage Vss generated by the voltage generator 440 to the word line, and the control logic circuit 420 controls the row decoder 430 to apply the erasing voltage Vers generated by the voltage generator 440 to the bit line. It should be noted that the erasing voltage Vers is a high potential, and the erasing voltage Vss is a low potential (0V), so that a large potential difference is formed between the channel potential and the gate potential of the memory block to be erased, so as to achieve erasing of the memory cells in the memory block.

[0087] After the erasing operation on the memory cells coupled to the selected word line is completed, the memory cells need to be programmed to different storage states.

[0088] Exemplarily, in the programming stage, the control logic circuit 420 controls the row decoder 430 to apply the programming voltage generated by the voltage generator 440 to the selected word line, so as to form a larger potential difference with the channel potential, so that electrons are injected into the charge trapping layer through tunneling. At the same time, the row decoder 430 is also controlled to apply the pass voltage generated by the voltage generator 440 to the non-selected word line, so as to turn on the memory cells that are not selected for programming, so that the memory cells coupled to the selected word line are programmed to N different programming states.

[0089] After the above operations are completed on the selected storage cells, the target storage cells are screened out by executing the operations of S10 to S30.

[0090] S10: In response to a first read instruction, applying a read voltage to a word line, reading data of a plurality of memory cells, and obtaining a first read result.

[0091] In order to screen out as many and most stable target memory cells as possible, the read voltage needs to be adaptively adjusted when applying the read voltage.

[0092] For example, in the SLC mode, when the threshold voltage of the memory cell is within the threshold voltage range corresponding to the erased state, its logic value is a first logic value "1", and when the threshold voltage is within the threshold voltage range corresponding to the programmed state, its logic value is a second logic value "0". Figure 7 According to the threshold voltage distribution in the SLC mode, the number of storage cells with inherent threshold voltages near the initial read voltage Vrd is almost 0. Therefore, in order to screen out as many target storage cells as possible, it is necessary to adjust the size of the read voltage Vrd and move it to the position where the number of storage cells in the P0 erased state or the P1 storage state is the largest, thereby obtaining a corrected Vrd. That is, the read voltage Vrd is set at the position corresponding to the peak of the P0 erased state or the P1 storage state. Then, a read operation is performed on the storage cell according to the corrected read voltage Vrd, thereby obtaining a first read result.

[0093] Further, in order to screen out storage cells with stability, see Figure 8 , the modified read voltage Vrd can be set at the position corresponding to the peak of the P1 storage state, thereby obtaining VrdP1. Fig. 9 , the threshold voltage at the position corresponding to the P1 storage state peak is about 0V, and the storage cell with a threshold voltage of 0V has the highest stability.

[0094] For example, if each memory cell stores multiple bits of data, only one or more bits of data may be read during reading. The reading process of the UP logic page in the TLC mode is used to illustrate that the highest bit of data in each memory cell is read. If the threshold voltage of the memory cell is within the threshold voltage range corresponding to the erased state, its logic value is "1", and if the threshold voltage is within the threshold voltage range corresponding to the programmed state, its logic value is "0". Fig.10 According to the threshold voltage distribution in the TLC mode, the number of storage cells with inherent threshold voltages near the initial read voltage Vrd1 is almost 0. Therefore, in order to screen out as many target storage cells as possible, it is necessary to move the position of the read voltage Vrd1 to the position where the number of storage cells is the largest, that is, to set the read voltage Vrd1 to the position corresponding to the peak of any storage state among the P0 erased state, P1 storage state, P2 storage state, P3 storage state, P4 storage state, P5 storage state, P6 storage state, or P7 storage state, and move Vrd2 to the right side of the P7 storage state. Then, the storage cell is read according to the adjusted read voltages Vrd1 and Vrd2, thereby obtaining the first read result.

[0095] Further, in order to screen out storage cells with stability, see Fig.11 , the read voltage Vrd1 can be set at the position corresponding to the peak of the P3 storage state to obtain VrdP3, and the read voltage Vrd2 can be set at the right position of the P7 storage state to obtain VrdP7, see Fig.12 , the threshold voltage at the position corresponding to the P3 storage state peak is about 0V, and the storage cell with a threshold voltage of 0V has the highest stability.

[0096] Exemplarily, in the first read cycle, the control logic circuit 420 controls the row decoder 430 to apply the read voltage generated by the voltage generator 440 to the word line coupled to the memory cell selected as the screening target, and to apply the pass voltage to the word line coupled to the unselected memory cell, and then determine the logic state of each memory cell according to the detection of the current on the bit line. If the current can be detected on the bit line, it means that the selected memory cell is turned on, and the state of the selected memory cell is the first logic value "1"; if the current is not detected on the bit line, it means that the selected memory cell is not turned on, and the state of the selected memory cell is the second logic value "0". Then the logic state of each memory cell is integrated to obtain the first read result.

[0097] S20: In response to a second read instruction, applying a read voltage to the word line, reading data of a plurality of memory cells, and obtaining a second read result.

[0098] After obtaining the first read result, after a preset time, a second read instruction is triggered, and in response to the second read instruction, a second read operation is performed to obtain a second read result of the storage unit. It should be noted that in the first read cycle and the second read cycle, the read voltage applied to the word line coupled to the storage unit selected as the screening target is the same.

[0099] Exemplarily, in the second read cycle, the control logic circuit 420 controls the row decoder 430 to apply the read voltage generated by the voltage generator 440 to the word line coupled to the memory cell selected as the screening target, and to apply the pass voltage to the word line coupled to the unselected memory cell, and then determine the logic state of each memory cell according to the detection of the current on the bit line. If the current can be detected on the bit line, it means that the selected memory cell is turned on, and the state of the selected memory cell is the first logic value "1"; if the current is not detected on the bit line, it means that the selected memory cell is not turned on, and the state of the selected memory cell is the second logic value "0". Then the logic state of each memory cell is integrated to obtain the second read result.

[0100] The first read cycle refers to the process of obtaining the first read result, and the second read cycle refers to the process of obtaining the second read result. After obtaining the first read result and the second read result, the first read result includes the logic value corresponding to each storage unit in the first read cycle, and the second read result includes the logic value corresponding to each storage unit in the second read cycle. Then, according to the change of the logic value corresponding to the read result of each storage unit in the first read cycle and the second read cycle, the target storage unit is screened out.

[0101] S30: If the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than a threshold, determine a memory cell having different first read results and second read results among the plurality of memory cells as a target memory cell.

[0102] After obtaining the read result of the storage unit in the first read cycle and the read result of the second read cycle, the target storage unit can be screened out by comparing whether the logic value of the storage unit changes in the two read operations and the change situation.

[0103] Exemplarily, for example, the number of storage cells used to screen the target storage cells is 50, and the preset number threshold is 4. In the first read cycle, the number of storage cells whose read results are the first logic value "1" is 26, and the number of storage cells whose read results are the second logic value "0" is 24. In the second read cycle, the number of storage cells whose read results are the first logic value "1" is 25, and the number of storage cells whose read results are the second logic value "0" is 25. Then the difference between the number of the first logic value in the first read result and the number of the first logic value in the second read result is 1, which is less than the preset threshold of 4, and the screening condition is met. Then the storage cells whose read results in the first read cycle are the first logic value "1" and the read results in the second read cycle are the second logic value "0", or the storage cells whose read results in the first read cycle are the second logic value "0" and the read results in the second read cycle are the first logic value "1" are all determined as target storage cells. This is because these storage cells show sufficient randomness in the multiple reading processes, which meets the requirements for building a true random number generator.

[0104] S40: In response to the random number generation instruction, applying a read voltage to a word line coupled to the target memory cell, performing a read operation on the target memory cell, and obtaining a truly random binary sequence.

[0105] After the target memory cell is screened, the target memory cell can be used as an entropy source to construct a true random number generator, and a true random number is generated according to the constructed true random number generator. When there is a need for data encryption, the random number generation instruction is triggered, and then a read operation is performed to obtain the read result of the target memory cell. It should be noted that in the true random number generation stage, the read voltage applied to the word line coupled to the target memory cell is the same as the read voltage applied in the first read cycle and the read voltage applied in the second read cycle.

[0106] Exemplarily, if the random number generation instruction indicates that a true random binary sequence of a preset number of bits is required, and the preset number of bits is less than the number of target memory cells, the control logic circuit 420 controls the row decoder 430 to apply the read voltage generated by the voltage generator 440 to the word line coupled to the target memory cell, applies a pass voltage to the word line coupled to the non-target memory cell, and then determines the logical state of each target memory cell based on the detection of the current on the bit line, and uses the logical value representing the state of the logical target memory cell as the true random binary sequence.

[0107] The memory operation method provided by the present disclosure compares multiple reading results to screen out target memory cells that are easily affected by random noise. The storage state of the target memory cell is read again, and the logic value corresponding to the storage state is used as a true random number. The true random number is generated by using the physical characteristics of the memory cell, so it has true randomness, thereby meeting the requirements of data encryption.

[0108] See also Fig.13 The page buffer circuit 460 includes a first latch 501, a second latch 504, a first data latch 502, and a second data latch 503. The latch is connected to the data line and can be used to store input data transmitted by the data line during the programming operation, or to store output data output by the read operation device. The page buffer circuit 460 is coupled to a corresponding bit line in the bit line. That is, the page buffer circuit 460 can be coupled to the memory cell of the corresponding column through the corresponding bit line.

[0109] The data latch can store input data during the programming operation. The number of data latches can be adjusted according to the type of flash memory. For example, each memory cell of TLC flash memory can store 3 bits of data, so 3 data latches are required. Each memory cell of QLC flash memory can store 4 bits of data, so 4 data latches are required. The memory cell can be configured to work in SLC mode, or it can also be configured to work in MLC mode, TLC mode, QLC mode, or PLC mode.

[0110] When performing a read operation on a storage unit, not only the read results of the storage unit in the target storage state are obtained, but also the read results of the storage unit in the non-target storage state are obtained, and the read results of the storage unit in the non-target storage state are non-essential data. In order to keep only the read results of the storage unit in the target storage state, the interference of the non-essential data needs to be eliminated.

[0111] In some embodiments, before reading the data of the plurality of memory cells, the method further includes: storing mask data of a preset storage state into a first data latch.

[0112] Mask data refers to data used to shield or limit other data, so the mask data of the target storage state can be used to eliminate data in non-target storage states, thereby leaving only the read results of the storage cells in the target storage state.

[0113] As an example, before performing a read operation on the storage unit, the mask data of the preset storage state can be assigned to the first data latch. When the storage mode adopted by the memory is the SLC mode, the preset storage state can be P1, and when the storage mode adopted by the memory is the TLC mode, the preset storage state can be P3. It should be noted that in the TLC mode, the preset storage state can be any one of P1 to P7.

[0114] See also Fig.14 In a possible implementation, when the first reading result is obtained, S10 includes the following sub-steps:

[0115] S101: Read data of a plurality of memory cells and store the read data in a first latch.

[0116] During the first reading operation, data of data pages of the plurality of storage units need to be read, and then the data are temporarily stored in the first latch for subsequent processing operations.

[0117] S102: performing AND operation on the data stored in the first latch and the mask data of the preset storage state pre-stored in the first data latch to obtain a first reading result, and storing the first reading result in the second data latch.

[0118] The mask data of the preset storage state is a set of specific bit values, which are used to perform an AND operation with the data stored in the first latch to obtain a reading result. The data after the AND operation is then stored in the second data latch.

[0119] When the storage mode adopted by the memory is SLC mode, the target storage state is P1, and the read voltage is set to the peak of the P1 storage state, the read results of the storage cells whose threshold voltage is less than the read voltage VrdP1 are all the first logic value "1", but this part of the storage cells not only includes the storage cells in the P1 storage state, but also includes the storage cells in the P0 erased state, and the screening target is the storage cells whose threshold voltage is near the read voltage VrdP1, so it is necessary to screen the storage cells whose read results are the first logic value "1" and eliminate the read data of the storage cells in the P0 erased state.

[0120] For example, there are eight storage cells numbered A1 to A8, wherein A1 to A2 are storage cells with threshold voltages in the P0 erase state, and A3 to A8 are storage cells with threshold voltages in the P1 storage state. Then, the mask in the first data latch (D1 latch) can be 0 / 0 / 1 / 1 / 1 / 1 / 1 / 1, and the data stored in the first latch (C latch) is 1 / 1 / 0 / 1 / 0 / 1 / 0 / 1, which means that each storage cell corresponds to one bit, and the result after the bitwise AND operation is: 0 / 0 / 0 / 1 / 0 / 1 / 0 / 1. Then, the read result 0 / 0 / 0 / 1 / 0 / 1 / 0 / 1 is stored in the second data latch (D2 latch). It should be noted that when storing data, since a latch can only store one bit of data, the number of latches needs to be determined according to the amount of data in the read result. For example, when there are 8 storage cells, the number of latches required is 8. It can be seen that even if the read logic value of the storage cells A1 and A2 is the first logic value "1", after being eliminated by the mask, the read logic value is also set to the second logic value "0".

[0121] When the storage mode adopted by the memory is TLC mode, the target storage state is P3, and the read voltage is set to the peak of the P3 storage state, the read results of the storage cells whose threshold voltage is less than the read voltage VrdP3 are all the first logic value "1", but this part of the storage cells not only includes the storage cells in the P3 storage state, but also includes the storage cells whose threshold voltage is in the P0, P1 and P2 storage states, and the screening target is the storage cells whose threshold voltage is near the read voltage Vread3, so it is necessary to screen the storage cells whose read results are the first logic value "1" and eliminate the read data of the storage cells in the P0, P1 and P2 storage states.

[0122] For example, there are eight memory cells numbered A1 to A8, wherein A1 to A8 are memory cells with threshold voltages in the storage states of P0, P1, P2, P3, P4, P5, P6, and P7. The mask in the first data latch (D1 latch) may be 0 / 0 / 0 / 1 / 0 / 0 / 0 / 0, and the data stored in the first latch (C latch) is 1 / 1 / 1 / 1 / 1 / 1 / 1 / 1. The result after the bitwise AND operation is: 0 / 0 / 0 / 1 / 0 / 0 / 0 / 0, and then the read result 0 / 0 / 0 / 0 / 0 / 1 / 0 / 1 is stored in the second data latch (D2 latch). It can be seen that even if the read logic value of all memory cells is "1", after the mask is eliminated, except for the memory cell numbered A3, the read logic values ​​of the remaining memory cells are all set to the second logic value "0".

[0123] After the masked read result is stored in the second data latch, it is necessary to count the number of the first logic value “1” contained in the read result stored in the second data latch.

[0124] The page buffer circuit 460 further includes a VFC circuit, and the VFC circuit can be used to count the number of first logic values ​​“1”.

[0125] See also Fig.14 In a possible implementation, after S102, the following steps are further included:

[0126] S103: The data stored in the second data latch is transferred to the second latch, and the VFC circuit counts the number of the first logic values ​​stored in the second latch.

[0127] The VFC circuit can convert the input level signal into a corresponding frequency signal, and then count the number of the first logic value "1" according to the level of the frequency signal.

[0128] Exemplarily, the first read result stored in the second data latch (D2 latch) is first transferred to the second latch (L latch), and the VFC circuit uses the logic value stored in the second latch as input. These input level values ​​are then converted into corresponding frequency signals. The frequency of the signal output by the VFC circuit is proportional to the number of logic 1s in the input level. For the first read result 0 / 0 / 0 / 1 / 0 / 1 / 0 / 1, the number of its first logic values ​​is 3.

[0129] In a possible implementation, when the second reading result is obtained, S20 includes the following sub-steps:

[0130] S201: Read data of a plurality of memory cells, and store the read data in a first latch.

[0131] During the second reading operation, it is necessary to read data of data pages from a plurality of storage units, and then temporarily store the data in the first latch for subsequent processing operations.

[0132] S202: performing AND operation on the data stored in the first latch and the mask data of the preset storage state pre-stored in the first data latch to obtain a second reading result, and storing the second reading result in the first latch.

[0133] Continuing to explain the implementation process in step S102, for example, there are eight memory cells numbered A1 to A8, where A1 to A2 are memory cells with threshold voltages in the P0 erased state, and A3 to A8 are memory cells with threshold voltages in the P1 storage state. The mask in the first data latch (D1 latch) can be 0 / 0 / 1 / 1 / 1 / 1 / 1 / 1, and the data stored in the first latch (C latch) is 1 / 1 / 1 / 0 / 1 / 0 / 1 / 0, which means that each memory cell corresponds to a bit, and the result after the bitwise AND operation is: 0 / 0 / 1 / 0 / 1 / 0 / 1 / 0. Then the read result 0 / 0 / 1 / 0 / 1 / 0 / 1 / 0 is stored in the first latch (C latch).

[0134] S203: The data stored in the first latch is transferred to the second latch, and the VFC circuit counts the number of the first logic values ​​stored in the second latch.

[0135] Exemplarily, the second read result stored in the first latch (C latch) is first transferred to the second latch (L latch), and the VFC circuit uses the logic value stored in the second latch as input. These input level values ​​are then converted into corresponding frequency signals. For the second read result 0 / 0 / 1 / 0 / 1 / 0 / 1 / 0, the number of its first logic values ​​is 3.

[0136] After obtaining the first read result and the second read result, it is necessary to determine whether the result of this operation meets the requirement of a preset threshold value based on the comparison between the first read result and the second read result, and select the target storage unit if the requirement of the preset threshold value is met.

[0137] See also Fig.15 In a possible implementation, when screening the target storage unit, S30 includes the following sub-steps:

[0138] S301: XOR the data stored in the second data latch with the data stored in the first latch, and store the XOR result in the first latch.

[0139] S302: Determine a memory cell corresponding to a first latch storing a logic value of 1 as a target memory cell.

[0140] The second data latch is used to store the first read result, and the first latch is used to store the second read result. The target storage unit is screened out by comparing the first read result and the second read result.

[0141] Exemplarily, the first read result is 0 / 0 / 0 / 1 / 0 / 1 / 0 / 1, and the second read result is 0 / 0 / 1 / 0 / 1 / 0 / 1 / 0. After the bitwise XOR operation, the result is 0 / 0 / 1 / 1 / 1 / 1 / 1 / 1 / 1. It can be seen that the logical values ​​of the storage cells numbered A3-A8 have changed in the two read operations, so the storage cells numbered A3-A8 can be used as target storage cells. Then the address information of the storage cells numbered A3-A8 is stored in the first latch. The address information of the storage cells represents the index position of the true random bit generator, that is, the target storage cell can be found according to the address information, and a true random number sequence is generated by reading the state of the target storage cell.

[0142] If the difference between the number of first logic values ​​"1" in the first read result and the number of first logic values ​​"1" in the second read result is greater than a preset threshold, it means that the read result does not meet the randomness requirement. Because under normal conditions, under the action of random read noise, the probability that the state of the storage unit is flipped between two read operations is equal. This means that in the two read operations, the probability that the first logic value changes to the second logic value and the second logic value changes to the first logic value is the same. Therefore, if the difference between the two read results exceeds the preset threshold, it may indicate that the state change of the storage unit is not caused by randomness, but may be affected by some non-random factors. Therefore, if the read result does not meet the randomness requirement, it is necessary to repeat steps S10-S30 until the target storage unit is screened out.

[0143] In some embodiments, if the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is greater than or equal to a threshold, the data of multiple storage cells and the second read operation are read in response to the first read instruction and the first read result and the second read result are obtained respectively, until the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than the threshold.

[0144] Exemplarily, for example, the number of storage cells used to screen the target storage cells is 50, and the threshold is 4. In the first read cycle, the number of storage cells whose read results are the first logic value "1" is 26, and the number of storage cells whose read results are the second logic value "0" is 24. In the second read cycle, the number of storage cells whose read results are the first logic value "1" is 15, and the number of storage cells whose read results are the second logic value "0" is 35. The difference between the number of the first logic value in the first read result and the number of the first logic value in the second read result is 9, which is greater than the preset threshold of 4, and does not meet the screening condition. It is necessary to execute steps S10 to S30 again until the target storage cell is screened out.

[0145] The memory operation method provided by the present disclosure compares the reading results of multiple read operations, thereby screening out the target storage unit that is easily changed by random noise. And by reading the storage state of the target storage unit again, the logical value corresponding to its storage state is used as a true random number. By using the physical characteristics of the storage unit to generate random numbers, the generated binary sequence has true randomness, thereby meeting the requirements of data encryption.

[0146] The embodiment of the present disclosure further provides a memory, for example, the memory may be the aforementioned Figure 5 The memory shown includes a memory cell array 300 and a peripheral circuit 400 coupled to the memory cell array, and the peripheral circuit 400 is configured as follows:

[0147] In response to a first read instruction, a read voltage is applied to a word line, and data of a plurality of memory cells are read to obtain a first read result. In response to a second read instruction, a read voltage is applied to a word line, and data of a plurality of memory cells are read to obtain a second read result. If the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than a threshold value, a memory cell among the plurality of memory cells whose first read result is different from the second read result is determined as a target memory cell, a read voltage is applied to a word line coupled to the target memory cell, and a read operation is performed on the target memory cell to obtain a truly random binary sequence.

[0148] In a possible implementation of the present disclosure, the peripheral circuit 400 also includes a page buffer circuit 460, which includes a first latch, a first data latch and a second data latch. The page buffer circuit 460 is specifically configured to: read data of multiple storage cells, and store the read data in the first latch, and perform ANDing on the data stored in the first latch with mask data of a preset storage state pre-stored in the first data latch to obtain a first reading result, and store the first reading result in the second data latch.

[0149] In a possible implementation of the present disclosure, the page buffer further includes a second latch, and the page buffer circuit 460 is specifically configured to: transfer the data stored in the second data latch to the second latch, and the VFC circuit counts the number of first logic values ​​stored in the second latch.

[0150] In a possible implementation of the present disclosure, the peripheral circuit further includes a page buffer circuit, the page buffer circuit includes a first latch and a first data latch, and the page buffer circuit 460 is specifically configured to: read data of a plurality of storage cells and store the read data in the first latch,

[0151] The data stored in the first latch is ANDed with the mask data of the preset storage state pre-stored in the first data latch to obtain a first reading result, and the first reading result is stored in the first latch.

[0152] In a possible implementation of the present disclosure, the page buffer further includes a second latch, and the page buffer circuit 460 is further specifically configured to: transfer the data stored in the first latch to the second latch, and the VFC circuit counts the number of first logic values ​​stored in the second latch.

[0153] In a possible implementation of the present disclosure, the page buffer circuit 460 is further configured to store the mask data of the preset storage state into the first data latch.

[0154] In a possible implementation of the present disclosure, the page buffer circuit 460 is specifically configured to: perform XOR operation on the data stored in the second data latch and the data stored in the first latch, and store the XOR result in the first latch; and determine the storage cell corresponding to the first latch storing a logic value of 1 as the target storage cell.

[0155] In a possible embodiment of the present disclosure, the page buffer circuit 460 is also configured to: if the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is greater than or equal to a threshold, then repeatedly execute in response to the first read instruction, read data of multiple storage cells and the second read operation, and obtain the first read result and the second read result respectively, until the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than the threshold.

[0156] The present disclosure also provides a storage system. For example, the storage system includes a memory and a storage controller as described in the above embodiment. The memory is coupled to the storage controller. Figure 2 or Figure 3 The storage system shown.

[0157] The present disclosure also provides an electronic device, which includes a host and the aforementioned storage system, wherein the host is connected to the storage system and is used to store data in the storage system or read data read by the storage system. Figure 1 The electronic device shown.

[0158] Those skilled in the art can clearly understand that, for the convenience and brevity of description, in the above embodiments, the description of each embodiment has different emphases, and the parts that are not described in detail in a certain embodiment can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0159] In the several embodiments provided in the present disclosure, it should be understood that the provided programming method and memory can be implemented in other ways. For example, the division of a module is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0160] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.

[0161] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for operating a memory, characterized in that: The method comprises: In response to a first read instruction, applying a read voltage to a word line to read data of a plurality of memory cells to obtain a first read result, wherein the plurality of memory cells are coupled to the word line; In response to a second read instruction, applying the read voltage to the word line, reading data of the plurality of memory cells, and obtaining a second read result; If the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than a threshold, determining a storage unit among the plurality of storage units in which the first read result and the second read result are different as a target storage unit; The read voltage is applied to the word line coupled to the target memory cell, and a read operation is performed on the target memory cell to obtain a true random binary sequence.

2. The method according to claim 1, characterized in that The memory includes a page buffer circuit, the page buffer circuit includes a first latch, a first data latch, and a second data latch, and in response to a first read instruction, applying a read voltage to a word line, reading data of a plurality of storage cells, and obtaining a first read result includes: Reading data of the plurality of storage cells, and storing the read data in the first latch; The data stored in the first latch is ANDed with the mask data of the preset storage state pre-stored in the first data latch to obtain the first reading result, and the first reading result is stored in the second data latch.

3. The method according to claim 2, characterized in that The page buffer circuit further includes a second latch and a voltage-frequency conversion (VFC) circuit. In response to the first read instruction, a read voltage is applied to the word line to read data of a plurality of storage cells, and obtaining a first read result further includes: The data stored in the second data latch is transferred to the second latch, and the number of first logic values ​​stored in the second latch is counted by the VFC circuit.

4. The method according to claim 2, characterized in that: The step of applying a read voltage to the word line in response to the second read instruction, reading the data of the plurality of storage cells, and obtaining a second read result comprises: Reading data of the plurality of storage cells, and storing the read data in the first latch; The data stored in the first latch is ANDed with the mask data of the preset storage state pre-stored in the first data latch to obtain the second reading result, and the second reading result is stored in the first latch.

5. The method according to claim 4, characterized in that The page buffer circuit further includes a second latch and a VFC circuit, and in response to the second read instruction, applying a read voltage to the word line to read the data of the plurality of storage cells, and obtaining a second read result further includes: The data stored in the first latch is transferred to the second latch, and the number of first logic values ​​stored in the second latch is counted by the VFC circuit.

6. The method according to claim 2 or 4, characterized in that: Before reading the data of the plurality of storage cells, the method further includes: The mask data of the preset storage state is stored in the first data latch.

7. The method according to claim 5, characterized in that The step of determining, as a target storage unit, a storage unit in the plurality of storage units where the first reading result and the second reading result are different, comprises: XORing the data stored in the second data latch with the data stored in the first latch, and storing the XOR result in the first latch; The storage cell corresponding to the first latch storing a logic value of 1 is determined as the target storage cell.

8. The method according to claim 1, characterized in that The method further comprises: If the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is greater than or equal to the threshold, the responding to the first read instruction and the responding to the second read instruction to read the data of the multiple storage units and the second read operation are repeatedly executed to obtain the first read result and the second read result, respectively, until the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than the threshold.

9. A memory, characterized in that: include: A memory cell array and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured as follows: In response to a first read instruction, applying a read voltage to a word line to read data of a plurality of memory cells to obtain a first read result, wherein the plurality of memory cells are coupled to the word line; In response to a second read instruction, applying the read voltage to the word line, reading data of the plurality of memory cells, and obtaining a second read result; If the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than a threshold, determining a storage unit among the plurality of storage units in which the first read result and the second read result are different as a target storage unit; The read voltage is applied to the word line coupled to the target memory cell, and a read operation is performed on the target memory cell to obtain a true random binary sequence.

10. The memory according to claim 9, characterized in that: The peripheral circuit includes a page buffer circuit, the page buffer circuit includes a first latch, a first data latch and a second data latch, and the page buffer circuit is specifically configured as follows: Reading data of the plurality of storage cells, and storing the read data in the first latch; The data stored in the first latch is ANDed with the mask data of the preset storage state pre-stored in the first data latch to obtain the first reading result, and the first reading result is stored in the second data latch.

11. The memory according to claim 10, characterized in that: The page buffer circuit further includes a second latch and a VFC circuit, and the page buffer circuit is specifically configured as follows: The data stored in the second data latch is transferred to the second latch, and the number of first logic values ​​stored in the second latch is counted by the VFC circuit.

12. The memory according to claim 10, characterized in that: The peripheral circuit further includes a page buffer circuit, the page buffer circuit includes a first latch and a first data latch, and the page buffer circuit is specifically configured as follows: Reading data of the plurality of storage cells, and storing the read data in the first latch; The data stored in the first latch is ANDed with the mask data of the preset storage state pre-stored in the first data latch to obtain the first reading result, and the first reading result is stored in the first latch.

13. The memory according to claim 12, characterized in that: The page buffer circuit further includes a second latch and a VFC circuit, and the page buffer circuit is specifically configured as follows: The data stored in the first latch is transferred to the second latch, and the number of first logic values ​​stored in the second latch is counted by the VFC circuit.

14. The memory according to claim 10 or 12, characterized in that: The page buffer circuit is further configured to: The mask data of the preset storage state is stored in the first data latch.

15. The memory according to claim 13, characterized in that: The page buffer circuit is specifically configured as follows: XORing the data stored in the second data latch with the data stored in the first latch, and storing the XOR result in the first latch; The storage cell corresponding to the first latch storing a logic value of 1 is determined as the target storage cell.

16. The memory according to claim 9, characterized in that: The page buffer circuit is further configured to: If the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is greater than or equal to the threshold, the responding to the first read instruction and the responding to the second read instruction to read the data of the multiple storage units and the second read operation are repeatedly executed to obtain the first read result and the second read result, respectively, until the difference between the number of first logic values ​​in the first read result and the number of first logic values ​​in the second read result is less than the threshold.

17. A storage system, characterized in that: The invention comprises a storage controller and the memory according to any one of claims 9 to 16, wherein the storage controller is configured to control the memory to write data or read data stored in the memory.

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