Elimination and verification of non-volatile memory

Abstract

A method for performing elimination and verification of a plurality of non-volatile memory (NVM) cells is described. The method includes performing an operation for setting all of the plurality of NVM cells to a single state. Depending on the NVM architecture, the single state may be one of a conductive or non-conductive state. After the operation for setting the unit to the single state is completed, the verification is performed. In a verification operation, all cells of the plurality of NVM cells are set to the single state by performing a single read operation on the plurality of NVM cells. Detection of one of the conductive or non-conductive paths of the plurality of NVM cells is used to verify whether the content of all cells of the NVM array is eliminated. Notifications are provided in response to all cells not being set to a single known state.

Description

Technical Field

[0001] The present disclosure relates generally to memory, and more particularly to erasure and verification of non-volatile memory (NVM). Background Art

[0002] Sometimes it is necessary to eliminate or clear all data from NVM. Generally speaking, there are two situations where this may be necessary. One situation involves a use case where it is expected to ensure that the NVM is initialized in a known state, such as immediately after manufacturing or before transitioning to a blank life cycle state. In another use case, all NVM contents must be damaged to avoid leaking or exposing secret or sensitive information to an attacker or unauthorized user. However, some implementations of NVM are inexperienced because it is expected that triggering a memory content cleanup or elimination operation means that the memory content will be cleared. An attacker may be able to easily find multiple ways to disrupt the correct execution of the elimination process.

[0003] Therefore, there is a need for a method of ensuring quick and efficient erasure of memory contents and verifying the erasure of memory contents. Summary of the invention

[0004] According to a first aspect of the present invention, there is provided a method for performing erase and verify operations of a plurality of non-volatile memory (NVM) cells, the method comprising:

[0005] performing operations for setting all of the plurality of NVM cells to a single predetermined state;

[0006] verifying that all of the plurality of NVM cells are set to the single predetermined state by performing a single read operation on the plurality of NVM cells, wherein detection of one of the conductive or non-conductive paths through the plurality of NVM cells is used to verify that the contents of all cells of the NVM array are erased; and

[0007] If it is determined that all of the plurality of units are not set to a single known state, a notification of authentication failure is sent to the authenticator device.

[0008] In one or more embodiments, the plurality of NVM cells are part of a NVM array having a parallel architecture, wherein the cells of the plurality of NVM cells are non-conductive when set to the single known state.

[0009] In one or more embodiments, the plurality of NVM cells are part of a NVM array having a serial architecture, and wherein the cells of the plurality of NVM cells are turned on when set to the single known state.

[0010] In one or more embodiments, the operation for setting all cells of the plurality of NVM cells to a predetermined state is a programming operation, and wherein the programming operation sets the plurality of NVM cells to a non-conducting state.

[0011] In one or more embodiments, the operation for setting all cells of the plurality of NVM cells to a predetermined state is an erase operation, and wherein the erase operation sets the plurality of NVM cells to a conductive state.

[0012] In one or more embodiments, the plurality of NVM cells are connected in parallel, and wherein the single read operation follows a logical AND function when more than one of the parallel-connected cells is selected simultaneously.

[0013] In one or more embodiments, the plurality of NVM cells are connected in series, and wherein the single read operation follows a logical OR function when more than one of the serially connected cells are selected simultaneously.

[0014] In one or more embodiments, the plurality of NVM cells are words having a predetermined number of bits, and wherein the memory comprises a plurality of words.

[0015] In one or more embodiments, the verification failure results in a system reset of a system including the plurality of NVM cells.

[0016] According to a second aspect of the present invention, there is provided a method for performing erase and verify operations of a non-volatile memory (NVM) array, the method comprising:

[0017] performing an operation for setting all cells of the NVM array to a single predetermined state;

[0018] selecting a portion of the NVM array for logic state verification, wherein the portion includes a plurality of NVM cells and the NVM array includes a plurality of portions;

[0019] applying a current to the portion of the NVM array;

[0020] determining that all of the plurality of NVM cells in the portion are set to the single predetermined state when the current provides a first voltage, and determining that all of the plurality of NVM cells in the portion are not set to the single predetermined state when the current provides a second voltage;

[0021] repeating the selecting, applying, and determining for all of the plurality of portions when all of the plurality of NVM cells of the portion are not set to the single predetermined state; and

[0022] When all of the cells of the NVM array have not been set to a single known state, a notification of authentication failure is sent to an authenticator device.

[0023] In one or more embodiments, the NVM array has a parallel architecture, and wherein the cells of the NVM array are non-conductive when set to the single predetermined state.

[0024] In one or more embodiments, the NVM array has a serial architecture, and wherein the cells of the NVM array are in a conducting state when set to the single predetermined state.

[0025] In one or more embodiments, the operation for setting all cells of the NVM array to a known state is a programming operation, and wherein the programming operation sets all the cells of the NVM array to a non-conducting state.

[0026] In one or more embodiments, the operation for setting all cells of the NVM array to a known state is an erase operation, and wherein the erase operation sets all the cells of the NVM array to a conductive state.

[0027] In one or more embodiments, the cells of the portion of the NVM array are connected in parallel, and wherein a single read operation follows a logical AND function when more than one of the parallel-connected cells is selected simultaneously.

[0028] In one or more embodiments, the cells of the portion of the NVM array are connected in series, and wherein the single read operation follows a logical OR function when more than one of the serially connected cells are selected simultaneously.

[0029] In one or more embodiments, the portion of the NVM array is a word having a predetermined number of bits, and wherein the NVM array includes a plurality of words.

[0030] According to a third aspect of the present invention, there is provided a non-volatile memory (NVM), comprising:

[0031] a plurality of NVM cells; and

[0032] A control circuit for controlling an operation for setting all of the plurality of NVM cells to a single predetermined state, the control circuit controlling a verification operation for verifying that all of the plurality of cells are set to the single predetermined state by performing a single read operation on the plurality of NVM cells, wherein detection of one of the conductive or non-conductive paths of the plurality of NVM cells is used to verify whether contents of all cells of the NVM array are eliminated by the operation for setting all of the plurality of NVM cells to the single predetermined state.

[0033] In one or more embodiments, the NVM is embedded in a data processing system.

[0034] In one or more embodiments, the plurality of NVM cells have one of a parallel architecture or a serial architecture.

[0035] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The present invention is illustrated by way of example and not limitation in the accompanying figures, in which like reference numerals indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0037] Figure 1A A parallel read access NVM according to an embodiment is shown in block diagram form.

[0038] Figure 1B A serial read access NVM according to an embodiment is shown in block diagram form.

[0039] Figure 2 Shown in more detail Figure 1A The parallel architecture circuit portion of the NVM.

[0040] Figure 3 Shown in more detail Figure 1A The serial architecture circuit portion of the NVM.

[0041] Figure 4A A verify read operation of a parallel architecture circuit portion of an NVM cell of an NVM array is shown with all bits turned off according to an embodiment.

[0042] Figure 4B A verify read operation of a serial architecture circuit portion of an NVM array is shown with all bits turned on according to an embodiment.

[0043] Figure 5 A flow chart showing a method for NVM erasure and verification.

[0044] Figure 6 A data processing system according to an embodiment is shown. DETAILED DESCRIPTION

[0045] Generally, a method for safely erasing the contents of a non-volatile memory (NVM) array is provided. In the array, one or more cells can store information "bits", i.e., '1' or '0'. The erasure method includes selecting all bits of the NVM array at the same time, and using a high-voltage programming or erasing operation to change the logic state of all bits to a logic '1' or logic '0' state. The selection of the logic state is arbitrary and can be determined by the NVM architecture, application or other criteria. From the perspective of content damage / initialization, both the programming operation and the erasing operation correspond to so-called "bulk", "large-scale" or "all" erasing and programming operations. In the context of security, it is crucial that no user can access the complete memory or at least those words with sensitive data. The term "erasure" will be used throughout the text to indicate that the memory contents are eliminated, damaged, erased, cleared or cleaned. The term "cell" refers to a circuit that stores a bit, i.e., "1" or "0".

[0046] After the elimination operation, a verification is performed that the elimination operation changes the logic state of all cells as expected. The array can have an architecture in a parallel architecture or a serial architecture. For an array with a parallel architecture that associates all bits of different words in parallel, the cell content is eliminated as non-conductive, which allows the cell groups of the array to be read simultaneously. For example, for a single read operation of a group of cells connected in parallel, if a single cell in the group is conductive, the read operation will show a conductive result and therefore fail. Similarly, for a serial architecture that connects cells of different words in series, the cells are first set to be conductive, thereby allowing all cells to be read simultaneously. If a single cell will not be conductive, the read operation will show a non-conductive result and therefore fail.

[0047] Performing NVM erasure and verification in this manner potentially reduces verification time, thereby shortening the window of opportunity for an attacker to subvert the NVM erasure operation. Furthermore, NVM erasure using a program or erase operation is non-destructive, thereby allowing product reusability or product analysis.

[0048] According to an embodiment, a method for performing an erase and verify operation of a plurality of non-volatile memory (NVM) cells is provided, the method comprising: performing an operation for setting all of the plurality of NVM cells to a single predetermined state; verifying that all of the plurality of NVM cells are set to a single predetermined state by performing a single read operation on the plurality of NVM cells, wherein detection of one of the conductive or non-conductive paths of the plurality of NVM cells is used to verify whether the contents of all of the cells of the NVM array are erased; and if it is determined that all of the plurality of cells are not set to a single known state, sending a notification of verification failure to a verifier device. The plurality of NVM cells may be part of an NVM array having a parallel architecture, wherein the cells in the plurality of NVM cells are non-conductive when set to a single known state. The plurality of NVM cells may be part of an NVM array having a serial architecture, wherein the cells in the plurality of NVM cells are conductive when set to a single known state. The operation for setting all of the plurality of NVM cells to a predetermined state may be a programming operation, and wherein the programming operation may set the plurality of NVM cells to a non-conductive state. The operation for setting all cells of the plurality of NVM cells to a predetermined state may be an erase operation, and wherein the erase operation may set the plurality of NVM cells to a conductive state. The plurality of NVM cells may be connected in parallel, and wherein when more than one of the cells connected in parallel is selected at the same time, a single read operation may follow a logical AND function. The plurality of NVM cells may be connected in series, and wherein when more than one of the cells connected in series is selected at the same time, a single read operation may follow a logical OR function. The plurality of NVM cells may be words having a predetermined number of bits, and wherein the memory may include a plurality of words. A verification failure may result in a system reset of a system including the plurality of NVM cells.

[0049] In another embodiment, a method for performing an erase and verify operation of a non-volatile memory (NVM) array is provided, the method comprising: performing an operation for setting all cells of the NVM array to a single predetermined state; selecting a portion of the NVM array for logic state verification, wherein the portion includes a plurality of NVM cells and the NVM array includes a plurality of portions; applying a current to the portion of the NVM array; determining that all the plurality of NVM cells of the portion are set to a single predetermined state when the current provides a first voltage, and determining that all the plurality of NVM cells of the portion are not set to a single predetermined state when the current provides a second voltage; repeating the selecting, applying, and determining for all portions of the plurality of portions when all the plurality of NVM cells of the portion are not set to a single predetermined state; and sending a notification of verification failure to a verifier device when all cells of the NVM array have not been set to a single known state. The NVM array may have a parallel architecture, and wherein the cells of the NVM array may be non-conductive when set to a single predetermined state. The NVM array may have a serial architecture, and wherein the cells of the NVM array may be in a conductive state when set to a single predetermined state. The operation for setting all cells of the NVM array to a known state may be a programming operation, and wherein the programming operation may set all cells of the NVM array to a non-conducting state. The operation for setting all cells of the NVM array to a known state may be an erase operation, and wherein the erase operation sets all cells of the NVM array to a conducting state. The cells of a portion of the NVM array may be connected in parallel, and wherein when more than one of the cells connected in parallel is selected at the same time, a single read operation may follow a logical AND function. The cells of a portion of the NVM array may be connected in series, and wherein when more than one of the cells connected in series is selected at the same time, a single read operation may follow a logical OR function. The portion of the NVM array may be a word having a predetermined number of bits, and wherein the NVM array may include multiple words.

[0050] In yet another embodiment, a non-volatile memory (NVM) is provided, comprising: a plurality of NVM cells; and a control circuit for controlling an operation for setting all cells of the plurality of NVM cells to a single predetermined state, the control circuit controlling a verification operation for verifying that all cells of the plurality of cells are set to a single predetermined state by performing a single read operation on the plurality of NVM cells, wherein detection of one of the conductive or non-conductive paths of the plurality of NVM cells is used to verify whether the contents of all cells of the NVM array are eliminated by the operation for setting all cells of the plurality of NVM cells to a single predetermined state. The NVM may be embedded in a data processing system. The plurality of NVM cells may have one of a parallel architecture or a serial architecture.

[0051] Figure 1A A NVM 10 with parallel read access operations according to an embodiment is shown in block diagram form. The NVM 10 may include a plurality of non-volatile cells organized in words, including, for example, any type of non-volatile memory cell, such as multi-time programmable (MTP), electrically erasable read-only memory (EEPROM), flash memory, magnetic random access memory (MRAM), resistive random access memory (RRAM), and other programmable and erasable non-volatile memory cells not listed here. In the same manner, the cell may be a "1T cell" (single transistor access and content) or a "2T cell" (content transistor and access transistor), or other more complex cells. For example, a 3T cell includes a first transistor for storing a bit, a second transistor for word selection, and a third transistor for sector selection.

[0052] In one embodiment, any number of memory cells may be used to store a single bit. For example, common cell types include differential cells, parallel cells, and serial cells. A differential cell is a logical '1' when two cells are provided and a single cell is conductive. A differential cell provides an exclusive-or (XOR) logic operation. A parallel cell includes two cells and provides a logical '1' when both cells are non-conductive. A parallel cell provides an AND logic function. A serial cell is a logical '1' when one of the cells is non-conductive and provides a logical OR function.

[0053] For example, NVM 10 may include multiple words, where word 12 includes a predetermined number B of bits 14. Multiple NVM arrays 10 may be included in a memory device. NVM 10 may be organized in a hierarchical manner of cell groups. For example, multiple words 12 may be used to form sectors of words. Multiple sectors may be used to form, for example, quadrants or sector banks. It should be noted that the naming convention for the groups may be arbitrarily selected. In different embodiments, different names may be used for the same cell group. Commonly used different names are references to different hierarchical groups of words, sectors, pages, blocks, segments, quadrants, banks, etc.

[0054] Serial read access memory reads a single bit selected within a selected word (and sector). Parallel read access memory reads all bits within a selected word simultaneously. In a memory with parallel access operation, all bits of each word have independent paths into and out of the memory array. For example, in a read operation of word 12 of NVM array 10, a word select signal labeled "WORD SELECT" is used to select the word to be read out. All B bits 14 of word 12 are read out of NVM array 10 in parallel via their own separate paths to form a data structure labeled "DATA OUT <b:0>” data output word.

[0055] Whether an erase or program operation for a bit generates a logic '0' or a logic '1' is arbitrary to NVM and may depend on the process, type of NVM cell, application, etc. Typically, one operation makes the cell more or less "conductive" and the other operation makes the cell more or less "non-conductive." The read peripheral circuitry including logic, sense amplifiers, current comparators, output buffers, etc. determines whether the data is shown as a '0' or a '1'.

[0056] In a normal read operation of the NVM 10 that makes all words parallel, the read operation selects all words one by one. Therefore, the read operation of the NVM 10 to check the memory content results in the number of read operations equal to the number of words.

[0057] In one embodiment, in a read verification operation of the NVM 10 after a memory erase programming or erase operation, if the array has an architecture that connects all cells of different words in parallel and the cells are non-conductive when programmed, all cells can be read simultaneously in a single read operation. The read operation for verifying the erase operation can be performed on all cells of the NVM 10 in a single step operation. If the parallel-connected cells are successfully programmed to be non-conductive by the erase operation, the read operation will show a non-conductive result, such as a logic '1'. However, if one single cell fails to program and is conductive, indicating, for example, a logic '0', the read operation will show a conductive result, and thus the verification operation has failed,

[0058] The amount of benefit provided is based on whether the memory content erase operation produces conductive cells or non-conductive cells, and how the memory cell array or matrix defines its architecture. In one embodiment, all cells may be read simultaneously without cycling through all cells.

[0059] Due to potential electrical limitations imposed by memory size, such as the amount of current consumption required to program or erase a large array at one time, multiple memory erase operations to smaller partitions of the memory array may be used.

[0060] Figure 1B An NVM 20 with serial read access operation according to an embodiment is shown in block diagram form. In serial read access memory, a single bit is selected within a selected word (and sector) to be accessed. If a word is to be accessed, the word is accessed one bit at a time. The NVM 20 is similar to Figure 1A 1, except that in NVM 20, access to a word 22 of bits is performed serially. NVM 20 may include multiple words, where word 22 includes a predetermined number B of bits 24. A word may have any number of bits. Multiple NVM arrays 20 may be included in a memory device. In a memory having serially connected bits, each bit is accessed serially for operation. When accessing a word (e.g., word 22), a bit selection circuit 26 serially selects each bit 24 of word 22 using a bit selection signal BITSELECT to output to the bit selection circuit system 26 as an output signal DATA OUT. It should be noted that a memory module for a data processing system may include any combination of serial and parallel architectures and serial and parallel read access operations.

[0061] In an NVM 20 having an architecture where all bits are connected in series and the cell contents are conductive when erased, all cells can be read simultaneously in one read operation and the read operation will output a logic '0'. If one single cell of the serial connection of bits is not conductive, the read operation will output a non-conductive logic state '1'. In a verify operation of a memory erase program or erase operation, this will indicate that not all bits were erased and therefore the verify failed.

[0062] Figure 2 Shown in more detail Figure 1A A parallel architecture circuit portion 30 of the NVM 10 is shown. The parallel circuit portion 30 includes a parallel-connected cell 31 and a parallel-connected cell 32. The parallel-connected cell 31 includes NVM cells 33-36 connected in parallel between a sensing terminal SENSE and ground. A current source 37 is connected between a supply voltage SUPPLY and the sensing terminal to provide a current labeled "I". A sense amplifier 38 has an input connected to the sensing terminal and an output for providing an output signal labeled "DATA OUT B". The parallel read access has as many sense amplifiers as there are bits in a word. In this case, bits of different words can be associated in a parallel or serial architecture. The parallel-connected cell 32 includes NVM cells 39-42 connected in parallel between a sensing terminal SENSE and ground. A current source 43 is connected between a supply voltage SUPPLY and the sensing terminal to provide a current labeled "I". A sense amplifier 44 has an input connected to the sensing terminal and an output for providing an output signal labeled "DATA OUT 0". Using a WORD <0> to WORD <w>The word select signal accesses each word stored in the NVM, where there are W words in the array.

[0063] As an example of a normal read operation, the word select signal WORD of the word having representative cells 35 and 41 indicated by dashed boxes is used. <w-1>Accessing a word. The operation of the NVM cells is based on current injection (source or sink) into the cell acting as an impedance. Cell 35 is programmed to read logic '1' and is non-conductive. For illustration purposes, non-conductive cells are light colored and conductive cells are dark colored. The word select signal couples the cells of the selected word to their corresponding source lines (ground). Unselected cells are shown with dashed lines between the cell and the ground line. Because cell 35 is non-conductive, when connected to ground, no current flows to ground and sense amplifier 38 outputs a logic '1' DATA OUT B. On the other hand, cell 41 is programmed to be conductive. When the word select signal WORD is asserted <w-1>When coupled to ground, cell 41 will cause the sensing terminal to be pulled low and sense amplifier 44 will output a logic '0' data output 0. In this way, the selected word WORD <w-1>All cells of the NVM are read out simultaneously.

[0064] As can be seen, Figure 2 The parallel memory structure shown in requires separate read paths and one sense amplifier per bit, which requires more area on the integrated circuit. However, parallel memory is faster because all B bits of a word can be read simultaneously. Parallel memory consumes more peak current than serial memory. Parallel memory does not need to switch B times to read a complete word, which saves current and time. Parallel memory requires a lower voltage supply to operate because each bit has less load, which provides faster switching that can compensate for the higher peak current.

[0065] Figure 3 Shown in more detail Figure 1A A serial architecture circuit portion 50 of the NVM 20 of the embodiment. The serial circuit portion 50 includes cells 51 and 52 connected in series. The serially connected cell 51 includes NVM cells 53-56 connected in series between ground and a sensing terminal SENSE. A current source 57 is connected between a supply voltage SUPPLY and the sensing terminal to provide a current I. A sense amplifier 58 has an input connected to the sensing terminal and an output for providing an output signal DATA OUT B. The serially connected cell 52 includes NVM cells 59-62 connected in series between ground and a sensing terminal SENSE. A current source 63 is connected between a supply voltage SUPPLY and the sensing terminal to provide a current I. A sense amplifier 64 has an input connected to the sensing terminal and an output for providing an output signal DATAOUT 0. It should be noted that in another embodiment, there is only one sense amplifier, and each of the serially connected cell groups is connected to the sense amplifier through a bit selection circuit, such as Figure 1B As shown in . The bit selection circuit can be, for example, a multiplexer.

[0066] As an example normal read operation of NVM portion 50, word select signal WORD is used to select a word having representative cells 55 and 61 indicated by dashed boxes. <w-1>Access word. The operation of the NVM cell is based on current injection (source or sink) into the cell acting as an impedance. For illustration purposes, non-conductive cells are light-colored and conductive cells are dark-colored. Word select signal WORD <w-1>The cells that select the word to be read include cells 55 and 61. In one embodiment, the bit selection logic (see Figure 1B ) allows each cell of a word to be read one at a time through a single sense amplifier. Figure 3 The time points of reading the cell 61 are shown. The cell 55 is read at different times. The cell 61 is non-conductive and stores a logic '1'. During the read operation of the selected cell 61, the other cells 59, 60 and 62 of the serially connected cells 52 are shorted by the read path between the sense terminal SENSE and the ground so that the logic state of the selected cell 61 can be read. Because the selected cell 61 is non-conductive, the selected cell disconnects the read path from the ground and causes a logic high at the sense terminal, which is sensed and amplified by the sense amplifier 64 as DATAOUT 0. Each of the other cells of the selected word is read in the same manner until all the cells of the selected word are read. In this way, the selected word WORD <w-1>All cells are read out from the NVM in sequence.

[0067] Compared to parallel read access, serial read access provides less peak current because serial read access does not require simultaneous operation of many sense amplifiers. However, the read operation requires more time and higher operating voltage because each bit load is higher.

[0068] Figure 4A FIG. 2 shows a verify read operation of a parallel portion 61 of NVM cells of an NVM array with all bits non-conductive in accordance with an embodiment. Figure 2 The parallel section 30 in the array includes memory cells 62-65 connected in parallel between the sensing terminal SENSE and ground. The current source 66 provides a current I from the power supply voltage SUPPLY to the sensing terminal SENSE. In the array, if all bits of different words are connected in parallel, when the word selection signal WORD is used at the same time <0> to WORD <w>When several words are selected, the data output follows a logical AND function. During a programming operation for setting the logic state of all cells of the NVM to one logic state to erase the memory contents, a high programming voltage is applied to the array to set all cells to non-conductive. If all cells are successfully set to non-conductive by the programming operation, the output of the read verification operation in which all cells 62-65 are selected and connected to the ground line will be pulled high toward the power supply voltage SUPPLY, and the sense amplifier 67 will provide a logic '1', indicating that all cells are successfully programmed. However, if a single bit of the selected word fails to program and conducts, the data output is a logic '0', indicating that at least one of the cells 62-65 failed to be properly programmed.

[0069] Thus, by selecting all words and sectors of words (if applicable), a single read operation is sufficient to check that all bits are not conducting and the programming operation has been verified. This results in much faster memory erasure and verification. However, if not all bits have been successfully programmed, multiple read operations are required to check which bits are conducting. The number of operations can be as many as the number of words multiplied by the number of sectors.

[0070] Figure 4B FIG. 2 shows a verify read operation of the serial portion 71 of the NVM array with all bits turned on according to an embodiment. Figure 3 The serial portion 51 in the array includes memory cells 72-75 connected in series between a sensing terminal SENSE and ground. A current source 76 provides a current I from a power supply voltage SUPPLY to a sensing terminal SENSE. In the array, if all bits of different words are connected in series, the output data follows a logic or function when several words are selected at the same time. During an erase operation for setting the logic states of all cells in the serially connected cells of the NVM to one logic state to erase the memory contents, a high erase voltage is applied to the array to set all cells to be conductive. If all cells 72-75 are successfully set to be conductive by the erase operation, the output of the read verification operation in which all cells 72-75 are selected will be pulled down toward ground, and the sense amplifier 77 will provide a logic '0', indicating that all cells are successfully erased. However, if a single bit of all selected words fails to erase and is not conductive, the output data will be a logic '1', indicating that at least one of the cells 72-75 has failed to be correctly erased.

[0071] As mentioned above, if all cell contents are successfully erased, this can result in much faster memory erase and verification. If any cell fails to program or erase, more time is required, which is appropriate for the memory architecture.

[0072] Figure 5 A flow chart of a method 80 for NVM erasure and verification using a programming operation is shown. For purposes of discussion, the programming operation is arbitrarily selected to provide a non-conducting state associated with a logic '1' output. Also for purposes of discussion, the NVM array includes S sectors, where S can be any number, and each sector includes W words. A word includes any number of bits. The cells for storing bits are connected in parallel, such as Figure 2 and Figure 4A As shown in . As mentioned above, when several words are selected for a read operation at the same time, the cells connected in parallel form a logical AND function, and provide a logic '1' output when all cells are programmed to be non-conductive. The predetermined number of bits can be any number, such as 16, 32, 64, etc. Method 80 begins with a programming operation for all bits of the array. In one embodiment, the programming operation can be a programming operation for memory erasure, in which a higher than normal programming voltage is used. For the memory erasure operation, the target high voltage is higher than the normal programming voltage. Therefore, the high voltage flag is ignored. A higher than normal programming voltage requires more time to program the cell than a normal programming voltage. A higher than normal programming voltage results in a deeper conductive or non-conductive state than required for a normal memory life cycle. This deeper state provides a safer and more reliable state. At box 81, all words of all sectors are selected for programming operations. At box 83, a programming voltage is applied to the array. At box 82, if the write sensor indicates that the programming operation failed, the method fails at box 96. If a higher than normal programming voltage is used, the high voltage (HV) alarm flag is ignored.

[0073] The data verification operation follows the programming operation. At decision block 84, all words of all sectors of the NVM array that are being erased are selected for a single read verification operation of parallel connected cells, as described above in Figure 2 8. If the read operation indicates that all cells are programmed, that is, the output indicates '1', the method proceeds to box 85 and the memory erase operation passes and the operation is allowed to continue. Because only one read operation is required, the erase can be performed and verified very quickly when all cells are correctly programmed. However, if the output of the read operation is '0', indicating that not all cells are '1' after the programming operation, the method proceeds to box 86. At box 86, all words of the first sector (e.g., sector 0) are selected for a single read operation. At decision box 87, it is checked that the current sector is not the last sector, and the method proceeds to box 88, where the selected sector is read using a single read operation. If the sector read indicates '1', the method proceeds to box 89, where the sector is incremented and the method returns to box 87. If at box 88, '0' is the output, the method continues to box 90 and the words of the selected sector are read at box 92. If at box 92, the output is '1', the word is incremented at box 93 and the steps are repeated until all words of all sectors are checked. When the output of the read at box 92 is not '1', as indicated by 'XYZ' at box 97, all words of all sectors are selected for another programming operation. If the write OK sensor indicates that the programming operation failed, then at step 96, verification fails. If verification indicates that the erase operation failed, a notification of the failure can be provided to the user, who can be a verifier device, such as a host processor or other entity. In one embodiment, since the method failed to erase the NVM, a system reset can be performed. It should be noted that any HV alarm flags are ignored during the programming operation. At box 98, the word and sector previously selected at box 90 are selected for another read operation at box 99. If the programming operation is successful, that is, the output is '1', the next word of the selected sector is selected and the method repeats until box 99 is reached. However, if at box 99, the read indicates that the programming operation was unsuccessful, then attack 100 may be the cause of the programming and verification failure and method 80 fails at box 96.

[0074] Using method 80 for parallel connected NVM cells, if there are no faults, the memory erase and verify operations can be performed very quickly because only one read operation of the entire array is required. It should be noted that very large arrays may require multiple steps, but the method 80 can still be performed quickly. Moreover, if a fault occurs, the method can be performed quickly because only the segment where the fault is detected needs to be reprogrammed.

[0075] It should be noted that, as discussed above, the use of a program operation or an erase operation is arbitrarily selected depending on whether a conductive or non-conductive state of the NVM is desired. Moreover, the output logic state can be arbitrarily selected to provide a logic '1' or a logic '0'. Therefore, those skilled in the art will appreciate that the Figure 5 The method replaces the "PROGRAM ALL" operation of all bits in the NMV array with the "ERASE ALL" operation of all bits in the NVM array to logic '0'. Similarly, Figure 5 The data verify portion of the method will then replace the program operation of block 97 with an erase operation.

[0076] Figure 6 A data processing system 140 according to an embodiment is shown. The data processing system 140 may be implemented on one or more integrated circuits and may be used in the implementation of the described embodiments of memory elimination and verification. The data processing system 140 includes a bus or switching network 142. Various modules or circuits may be connected to the bus 142. For example, one or more processor cores 144, NVM 146, input / output (I / O) circuits 148, memory management circuits 150, instruction memory 152, and network interfaces 154 are connected to the bus 142. The one or more processor cores 144 may include any hardware device capable of executing instructions stored in the NVM 146 or instructions in some embodiments, and the instructions and / or data may have to be copied from the NVM 146 to a random access memory (RAM) before being provided to the processor core 144. The processor core 144 may be, for example, a microprocessor, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a similar device. The processor core 144 may be implemented in a secure hardware element and may be tamper-resistant.

[0077] NVM 146 may include an array of any kind of NVM cells, such as MTP, EEPROM, flash memory, MRAM, RRAM, and other non-volatile memory cells not listed here. As described herein, NVM 146 may have cells coupled together serially or in parallel. Moreover, NVM 146 may be connected to I / O circuits 148 for accessing the memory cells of NVM 146, including word line selection, column selection, decoders, sense amplifiers, and other peripheral circuits required to access NVM 146. Memory management circuits 150 are coupled to I / O circuits 148 and bus 142 and control programming, erasing, and reading operations of NVM 146. Memory management circuits 150 have control circuit systems that include hardware, logic, and / or software to control erasure and verification operations according to the described embodiments. Memory management circuits 150 include high voltage management for programming and erasure erasure operations. In one embodiment, NVM 146 is embedded in data processing system 140. In another embodiment, NVM 146 may be separate from data processing system 140 .

[0078] Instruction memory 152 may include one or more machine-readable non-transitory storage media for storing instructions for execution by processor core 144. In other embodiments, both memories 146 and 152 may store data that may be operated on by processor core 144. Memories 152 and 154 may be implemented in secure hardware elements and may be tamper-resistant.

[0079] The network interface 154 may include one or more circuits for implementing communication with other hardware devices. For example, the network interface 154 may include or be coupled to a network interface card (NIC) configured to communicate according to the Ethernet protocol. Moreover, the network interface 154 may implement a TCP / IP stack for communicating according to the TCP / IP protocol. Communication between the authentication device and the verifier device may be via the network interface 154 or a similar interface. Various other hardware or configurations for communication are available.

[0080] Various embodiments or portions of embodiments may be implemented in hardware or as instructions on a non-transitory machine-readable storage medium, which includes any mechanism for storing information in a form readable by a machine, such as a personal computer, a laptop computer, a file server, a smart phone, or other computing device. Non-transitory machine-readable storage media may include volatile and non-volatile memory, such as read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory, etc. Non-transitory machine-readable storage media do not include transitory signals.

[0081] Although the present invention is described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the present invention as set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive, and all such modifications are intended to be included within the scope of the present invention. It is not intended that any benefit, advantage, or solution to a problem described herein with respect to a specific embodiment be construed as a key, essential, or requisite feature or element of any or all claims.

[0082] In addition, as used herein, the terms "a" and "an" are defined as one or more than one. Moreover, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be interpreted as implying that another claim element introduced by the indefinite article "a" limits any particular claim containing the introduced claim element to an invention containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a". The same applies to the use of definite articles. The terms "circuit" and "circuitry" may refer to hardware, software, or a combination of hardware and software.

[0083] Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements these terms describe. Therefore, these terms are not necessarily intended to indicate a temporal or other prioritization of such elements. As used herein, the term "coupled" is not intended to be limited to a direct coupling or a mechanical coupling.< / w> < / w>

Claims

1. A method for performing erase and verify operations of a plurality of non-volatile memory NVM cells, characterized in that, The method comprises: performing operations for setting all of the plurality of NVM cells to a single predetermined state; verifying that all of the plurality of NVM cells are set to the single predetermined state by performing a single read operation on the plurality of NVM cells, wherein detection of one of the conductive or non-conductive paths through the plurality of NVM cells is used to verify that the contents of all cells of the NVM array are erased; and If it is determined that all of the plurality of units are not set to a single known state, a notification of authentication failure is sent to the authenticator device.

2. The method according to claim 1, characterized in that The plurality of NVM cells are part of a NVM array having a parallel architecture, wherein the cells of the plurality of NVM cells are non-conductive when set to the single known state.

3. The method according to claim 1, characterized in that The plurality of NVM cells are part of a NVM array having a serial architecture, and wherein the cells of the plurality of NVM cells are conductive when set to the single known state.

4. The method according to claim 1, characterized in that: The operation for setting all cells of the plurality of NVM cells to a predetermined state is a programming operation, and wherein the programming operation sets the plurality of NVM cells to a non-conductive state.

5. The method according to claim 1, characterized in that The operation for setting all of the plurality of NVM cells to a predetermined state is an erase operation, and wherein the erase operation sets the plurality of NVM cells to a conductive state.

6. The method according to claim 1, characterized in that The plurality of NVM cells are connected in parallel, and wherein the single read operation follows a logical AND function when more than one of the parallel-connected cells is selected simultaneously.

7. The method according to claim 1, characterized in that The plurality of NVM cells are connected in series, and wherein the single read operation follows a logical OR function when more than one of the serially connected cells is selected simultaneously.

8. The method according to claim 1, characterized in that The verification failure results in a system reset of a system including the plurality of NVM cells.

9. A method for performing erase and verify operations of a non-volatile memory (NVM) array, characterized in that: The method comprises: performing an operation for setting all cells of the NVM array to a single predetermined state; selecting a portion of the NVM array for logic state verification, wherein the portion includes a plurality of NVM cells and the NVM array includes a plurality of portions; applying a current to the portion of the NVM array; determining that all of the plurality of NVM cells in the portion are set to the single predetermined state when the current provides a first voltage, and determining that all of the plurality of NVM cells in the portion are not set to the single predetermined state when the current provides a second voltage; repeating the selecting, applying, and determining for all of the plurality of portions when all of the plurality of NVM cells of the portion are not set to the single predetermined state; and When all of the cells of the NVM array have not been set to a single known state, a notification of authentication failure is sent to an authenticator device.

10. A non-volatile memory NVM, characterized in that: include: Multiple NVM cells; as well as A control circuit for controlling an operation for setting all of the plurality of NVM cells to a single predetermined state, the control circuit controlling a verification operation for verifying that all of the plurality of cells are set to the single predetermined state by performing a single read operation on the plurality of NVM cells, wherein detection of one of the conductive or non-conductive paths of the plurality of NVM cells is used to verify whether contents of all cells of the NVM array are eliminated by the operation for setting all of the plurality of NVM cells to the single predetermined state.

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