Electronic device, detection method thereof and adapter plate

Abstract

The embodiment of the invention provides an electronic device, a detection method thereof and an adapter plate. The electronic device includes: a plurality of parallel connected branches coupled between a first terminal and a second terminal, each branch including a fusible element and a capacitor connected in series, the fusible element coupled between the first terminal and a third terminal, and the capacitor coupled between the second terminal and the third terminal; wherein the state of the fusible element comprises a non-fusing state and a fusing state, when the fusible element is in the non-fusing state, the first terminal and the third terminal are electrically connected, and when the fusible element is in the fusing state, the first terminal and the third terminal are not electrically connected; the fusible element in the at least one branch is in an unfused state, and / or the fusible element in the at least one branch is in a fused state.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the technical field of electronic devices, including but not limited to an electronic device and a detection method thereof, and an adapter board. Background Art

[0002] With the development of advanced packaging technology, the demand for high-performance capacitor chips is becoming more and more urgent. As a high-end alternative to multilayer ceramic capacitors (MLLC), silicon capacitors are widely used in power decoupling, high-frequency and high-speed transmission, and other fields. Capacitor chips play an important role in the power integrity and signal integrity of products in advanced packaging.

[0003] As the demand for the capacitance of capacitor chips continues to increase, the capacitance of a single capacitor can be increased through process or design. In terms of process, a multilayer capacitor can be used to replace a single-layer capacitor, and a high dielectric constant material with a larger dielectric constant can be selected as the dielectric layer between the first electrode and the second electrode of the capacitor. In terms of design, the area of ​​the first electrode and the second electrode of a single capacitor can be increased. However, the above methods of increasing the capacitance of a single capacitor may result in a yield loss of the capacitor chip. Summary of the invention

[0004] In view of this, the embodiments of the present disclosure provide an electronic device, a detection method thereof, and an adapter board.

[0005] In a first aspect, an embodiment of the present disclosure provides an electronic device, comprising: a plurality of parallel-connected branches coupled between a first terminal and a second terminal, each branch comprising a fusible element and a capacitor connected in series, the fusible element being coupled between the first terminal and a third terminal, and the capacitor being coupled between the second terminal and the third terminal; wherein the state of the fusible element comprises an un-fused state and a fused state, when the fusible element is in the un-fused state, the first terminal and the third terminal are electrically connected, and when the fusible element is in the fused state, the first terminal and the third terminal are not electrically connected; the fusible element in at least one of the branches is in the un-fused state, and / or the fusible element in at least one of the branches is in the fused state.

[0006] In some embodiments, the fusible element includes: a plurality of first conductive lines coupled to the first terminal and the third terminal and connected in parallel, a first node and a second node being provided on the first conductive line, the first conductive line including a first sub-conductive line provided between the first terminal and the first node, a second sub-conductive line provided between the first node and the second node, and a third sub-conductive line provided between the second node and the third terminal; wherein, when the fusible element is in an un-fused state, the first sub-conductive line and the third sub-conductive line are electrically connected through the second sub-conductive line; when the fusible element is in a fused state, the second sub-conductive line has a gap, and the first sub-conductive line and the third sub-conductive line are not electrically connected.

[0007] In some embodiments, the fusible element further includes: a barrier layer disposed on the side wall of the first conductive line, the resistivity of the barrier layer being greater than the resistivity of the first conductive line; wherein, when the fusible element is in an un-fused state or a fused state, a portion of the barrier layer disposed on the side wall of the first sub-conductive line and a portion of the barrier layer disposed on the side wall of the third sub-conductive line are connected via a portion of the barrier layer disposed on the side wall of the second sub-conductive line.

[0008] In some embodiments, the first sub-conductive wire, the second sub-conductive wire and the third sub-conductive wire are made of the same material; the cross-sectional area of ​​the first sub-conductive wire is greater than the cross-sectional area of ​​the second sub-conductive wire, and the cross-sectional area of ​​the third sub-conductive wire is greater than the cross-sectional area of ​​the second sub-conductive wire.

[0009] In some embodiments, the fusible element includes N first conductive wires, the first sub-conductive wire, the second sub-conductive wire and the third sub-conductive wire have the same thickness, the width of the first sub-conductive wire is N times the width of the second sub-conductive wire, and the width of the third sub-conductive wire is N times the width of the second sub-conductive wire; wherein N is an integer greater than 1.

[0010] In some embodiments, the material of the first sub-conductive wire and the third sub-conductive wire is the same and different from the material of the second sub-conductive wire; the electrical mobility of the second sub-conductive wire is greater than the electrical mobility of the first sub-conductive wire, and the electrical mobility of the second sub-conductive wire is greater than the electrical mobility of the third sub-conductive wire.

[0011] In some embodiments, the fusible element includes: a second conductive wire and a variable resistor coupled between the first terminal and the third terminal and connected in series, the second conductive wire and the variable resistor being made of different materials; wherein, when the fusible element is in an un-fused state, the resistance of the variable resistor is less than the resistance of the variable resistor when the fusible element is in a fused state.

[0012] In a second aspect, an embodiment of the present disclosure provides an adapter board, which includes: an electronic device as described in the above technical solution.

[0013] In a third aspect, an embodiment of the present disclosure provides a method for detecting an electronic device, the method comprising: providing an electronic device to be detected, comprising: a plurality of branches connected in parallel coupled between a first terminal and a second terminal, each branch comprising a fusible element and a capacitor connected in series, and the fusible element in each branch being in an un-blown state; detecting the electronic device to be detected, and determining whether the electronic device to be detected is qualified based on a leakage current in the electronic device to be detected and an actual capacitance of the electronic device to be detected; detecting each capacitor in an unqualified electronic device, and determining whether the capacitor is qualified based on a leakage current in the capacitor and an actual capacitance of the capacitor; and performing a melting process on the fusible element coupled to the unqualified capacitor, so that the fusible element is changed from an un-blown state to a blown state.

[0014] In some embodiments, the fusible element is coupled between the first terminal and the third terminal; the fusible element includes a plurality of first conductive lines connected in parallel and coupled between the first terminal and the third terminal, a first node and a second node are provided on the first conductive line, the first conductive line includes a first sub-conductive line provided between the first terminal and the first node, a second sub-conductive line provided between the first node and the second node, and a third sub-conductive line provided between the second node and the third terminal; the fusing process of the fusible element coupled to the unqualified capacitor includes: fusing the second sub-conductive line coupled to the unqualified capacitor, the second sub-conductive line undergoing electromigration to form a gap in the second sub-conductive line, so that the first sub-conductive line and the third sub-conductive line are not electrically connected.

[0015] In some embodiments, the first sub-conductive wire, the second sub-conductive wire and the third sub-conductive wire are made of the same material; the cross-sectional area of ​​the first sub-conductive wire is greater than the cross-sectional area of ​​the second sub-conductive wire, and the cross-sectional area of ​​the third sub-conductive wire is greater than the cross-sectional area of ​​the second sub-conductive wire.

[0016] In some embodiments, the material of the first sub-conductive wire and the third sub-conductive wire is the same and different from the material of the second sub-conductive wire; the electrical mobility of the second sub-conductive wire is greater than the electrical mobility of the first sub-conductive wire, and the electrical mobility of the second sub-conductive wire is greater than the electrical mobility of the third sub-conductive wire.

[0017] In some embodiments, the fusible element is coupled between the first terminal and the third terminal; the fusible element includes a second conductive wire and a variable resistor coupled between the first terminal and the third terminal and connected in series, and the second conductive wire and the variable resistor are made of different materials; the fusing process of the fusible element coupled to the unqualified capacitor includes: fusing the variable resistor coupled to the unqualified capacitor so that there is no electrical connection between the first terminal and the third terminal; wherein, when the fusible element is in an unfused state, the resistance value of the variable resistor is less than the resistance value of the variable resistor when the fusible element is in a fused state.

[0018] In some embodiments, determining whether the electronic device to be detected is qualified includes: when the leakage current in the electronic device to be detected is less than a first preset value, and the absolute value of the difference between the actual capacitance of the electronic device to be detected and the sum of the theoretical capacitance of all the capacitors is less than a second preset value, determining that the electronic device to be detected is a qualified electronic device; when the leakage current in the electronic device to be detected is greater than or equal to the first preset value, and / or the absolute value of the difference between the actual capacitance of the electronic device to be detected and the sum of the theoretical capacitance of all the capacitors is greater than or equal to the second preset value, determining that the electronic device to be detected is an unqualified electronic device.

[0019] In some embodiments, determining whether the capacitor is qualified includes: when the leakage current in the capacitor is less than a third preset value, and the absolute value of the difference between the actual capacitance of the capacitor and the theoretical capacitance of the capacitor is less than a fourth preset value, determining that the capacitor is a qualified capacitor; when the leakage current in the capacitor is greater than or equal to the third preset value, and / or the absolute value of the difference between the actual capacitance of the capacitor and the theoretical capacitance of the capacitor is greater than or equal to the fourth preset value, determining that the capacitor is an unqualified capacitor.

[0020] In some embodiments, after the fusible element coupled to the unqualified capacitor is blown, the method further includes: classifying the qualified electronic devices and the unqualified electronic devices that have been blown according to the target theoretical capacitance of the electronic device to be tested.

[0021] The disclosed embodiment provides an electronic device and a detection method thereof, and an adapter board. The electronic device includes: a plurality of parallel-connected branches coupled between a first terminal and a second terminal, each branch including a fusible element and a capacitor connected in series, the fusible element coupled between the first terminal and the third terminal, and the capacitor coupled between the second terminal and the third terminal; wherein the fusible element state includes an unfused state and a fused state, when the fusible element is in the unfused state, the first terminal and the third terminal are electrically connected, and when the fusible element is in the fused state, the first terminal and the third terminal are not electrically connected; the fusible element in at least one branch is in the unfused state, and / or the fusible element in at least one branch is in the fused state. In the disclosed embodiment, unqualified electronic devices are identified among the electronic devices to be tested, and then unqualified capacitors are identified among the unqualified electronic devices. Fusible elements coupled to the unqualified capacitors are fused so that the fusible elements are changed from an unfused state to a fused state, thereby avoiding yield loss of electronic devices caused by unqualified capacitors, thereby improving the yield of electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of capacitor chips provided for some examples Figure 1 ;

[0023] Figure 2 Schematic diagram of capacitor chips provided for some examples Figure 2 ;

[0024] Figure 3 Schematic diagram of capacitor chips provided for some examples Figure 3 ;

[0025] Figure 4 A schematic diagram of B capacitors connected in parallel provided in an embodiment of the present disclosure;

[0026] Figure 5 A schematic diagram of a flow chart of a method for detecting an electronic device provided in an embodiment of the present disclosure;

[0027] Figure 6 A schematic diagram of an electronic device to be detected provided in an embodiment of the present disclosure;

[0028] Figure 7 Schematic diagram of a fusible element provided in an embodiment of the present disclosure Figure 1 ;

[0029] Figure 8 Schematic diagram of a fusible element provided in an embodiment of the present disclosure Figure 2 ;

[0030] Fig. 9 Schematic diagram of a fusible element provided in an embodiment of the present disclosure Figure 3 ;

[0031] Fig.10 A schematic diagram of an electronic device provided by an embodiment of the present disclosure;

[0032] Fig.11 A block diagram of an adapter board provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] The following will be combined with the embodiments of the present disclosure and the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0034] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0035] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0036] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0037] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0038] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0039] In order to thoroughly understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below, but in addition to these detailed descriptions, the present disclosure may also have other implementations.

[0040] refer to Figure 1 , Figure 1 Schematic diagram of capacitor chips provided for some examples Figure 1 .like Figure 1 As shown, the capacitor chip may include three capacitors connected in parallel, and the capacitance of the three capacitors is C1, C2 and C3 respectively. If the three capacitors are all good, then the three capacitors can be in normal working state. At this time, the capacitance of the capacitor chip is the sum of the capacitance of the three capacitors, that is, the equivalent capacitance = C1 + C2 + C3.

[0041] Considering the defect density (or yield level) of manufacturing capacitor chips, some capacitors in the capacitor chip may have defects and fail to work properly. Figure 2 , Figure 2 Schematic diagram of capacitor chips provided for some examples Figure 2 .like Figure 2As shown, the capacitor chip may include three capacitors connected in parallel, the capacitors with capacitance values ​​of C1 and C2 are both good products, and the capacitor with capacitance value of C3 is defective, then the capacitors with capacitance values ​​of C1 and C2 can be in normal working state, and the capacitor with capacitance value of C3 is in a state that cannot work properly (for example, short circuit state). At this time, the capacitance of the capacitor chip is 0, that is, the equivalent capacitance = 0. In other words, in the capacitor chip, as long as one capacitor is in a short circuit state, the equivalent capacitance of the capacitor chip is 0, which will cause other capacitors that can be in normal working state to be unable to be used normally, resulting in a waste of capacitors, thereby causing a loss of yield of the capacitor chip.

[0042] refer to Figure 3 , Figure 3 Schematic diagram of capacitor chips provided for some examples Figure 3 .like Figure 3 As shown, the capacitor chip may include three capacitors connected in parallel. When the capacitor with a capacitance value of C3 is defective and in a short-circuit state, the branch where the capacitor with a capacitance value of C3 is located may be disconnected. At this time, the capacitor chip includes two capacitors connected in parallel, and the capacitance of the capacitor chip is the sum of the capacitance values ​​of the two capacitors, that is, the equivalent capacitance = C1 + C2. In other words, if the branch where the defective capacitor is located can be disconnected, then although the capacitance of the capacitor chip is reduced, other capacitors that can be in a normal working state can still be used normally, avoiding the waste of capacitors, thereby improving the yield of the capacitor chip.

[0043] Based on this, when designing capacitor chips, it is necessary to consider the yield level of the capacitor chips during the manufacturing process and the target capacitance of the capacitor chips. For example, some redundant capacitors can be designed in the capacitor chip. If a capacitor in the capacitor chip is defective and cannot be used normally, the redundant capacitors can be used to replace these capacitors that cannot be used normally, ensuring that the capacitance of the capacitor chip is greater than or equal to the target capacitance. In this way, even if some capacitors in the capacitor chip are defective, the capacitor chip can still meet the usage requirements.

[0044] In the process of designing capacitor chips, the capacitor chip with the target capacitance can be divided into multiple capacitors with the same capacitance, and a certain proportion of redundant capacitors can be added to the capacitor chip. Figure 4 , Figure 4 Schematic diagram of B capacitors connected in parallel provided by an embodiment of the present disclosure. Figure 4 As shown, the capacitor chip may include B capacitors connected in parallel, each capacitor has the same capacitance value and is C, and the B capacitors may be represented as C1, C2, ..., C B. Define X of the B parallel-connected capacitors as redundant capacitors, then the target capacitance of the capacitor chip is (BX)*C, and ultimately it is only necessary to ensure that the capacitance of the manufactured capacitor chip is greater than or equal to (BX)*C. In other words, even if X of the capacitors in the capacitor chip are defective and cannot be used normally, they can be repaired using redundant capacitors to improve the yield of the capacitor chip.

[0045] For example, if the target capacitance of the capacitor chip is 10*C, then for example 2 redundant capacitors can be added. The capacitor chip designed in this way includes 12 capacitors connected in parallel. It only needs to ensure that the capacitance of the manufactured capacitor chip is greater than or equal to 10*C to meet the usage requirements.

[0046] In view of this, the embodiments of the present disclosure provide an electronic device and a detection method thereof, and an adapter board. In the detection method provided by the embodiments of the present disclosure, unqualified electronic devices are determined in the electronic devices to be detected, and then unqualified capacitors are determined in the unqualified electronic devices, and the fusible elements coupled to the unqualified capacitors are fused, so that the fusible elements are changed from an unfused state to a fused state, thereby avoiding the yield loss of the electronic device caused by the unqualified capacitors, thereby improving the yield of the electronic device.

[0047] refer to Figure 5 , Figure 5 A schematic diagram of a flow chart of a method for detecting an electronic device provided in an embodiment of the present disclosure. An embodiment of the present disclosure provides a method for detecting an electronic device, the method comprising:

[0048] Step S110: providing an electronic device to be tested, comprising: a plurality of branches connected in parallel and coupled between a first terminal and a second terminal, each branch comprising a fusible element and a capacitor connected in series, and the fusible element in each branch is in an unfused state;

[0049] Step S120: testing the electronic device to be tested, and determining whether the electronic device to be tested is qualified according to the leakage current in the electronic device to be tested and the actual capacitance of the electronic device to be tested;

[0050] Step S130: testing each capacitor in the unqualified electronic device, and determining whether the capacitor is qualified according to the leakage current in the capacitor and the actual capacitance value of the capacitor;

[0051] Step S140: performing a fusing process on the fusible element coupled to the unqualified capacitor, so that the fusible element changes from an unfrozen state to a frosted state.

[0052] refer to Figure 6 , Figure 6 Schematic diagram of an electronic device to be tested provided by an embodiment of the present disclosure. Figure 6As shown, in step S110, an electronic device 200 to be tested is provided, including: a plurality of parallel-connected branches 208 (coupled between a first terminal 202 and a second terminal 204) Figure 6 Each branch 208 includes a fusible element 210 and a capacitor 212 connected in series, and the fusible element 210 in each branch 208 is in an unfused state. Here, the first terminal 202 may also be represented as a P1 terminal, and the second terminal 204 may also be represented as a P2 terminal.

[0053] Here, each branch 208 includes a fusible element 210 and a capacitor 212 connected in series, the fusible element 210 is coupled between the first terminal 202 and the third terminal 206, and the capacitor 212 is coupled between the second terminal 204 and the third terminal 206, that is, the third terminal 206 is arranged between the fusible element 210 and the capacitor 212. The number of branches included in the electronic device 200 to be detected is B, that is, the electronic device 200 to be detected includes B fusible elements 210 and B capacitors 212; wherein B is an integer greater than 1. The B capacitors 212 can be represented by C1, C2, ..., C B .

[0054] like Figure 6 As shown, in the first branch 208, the fusible element 210 is disposed between the P1 terminal and the P3 terminal, and the capacitor C1 is disposed between the P3 terminal and the P4 terminal (or the P2 terminal). In the second branch 208, the fusible element 210 is disposed between the P1 terminal and the P5 terminal, and the capacitor C2 is disposed between the P5 terminal and the P6 terminal (or the P2 terminal). Similarly, in the Bth branch 208, the fusible element 210 is disposed between the P1 terminal and the P5 terminal, and the capacitor C2 is disposed between the P5 terminal and the P6 terminal (or the P2 terminal). 2B+1 Between the terminals, the capacitor C B Located in P 2B+1 Terminal and P 2B+2 Terminals (or, P2 terminals). It should be noted that, Figure 6 The P3 terminal, P5 terminal and P 2B+1 The terminals are all third terminals 206 .

[0055] Here, the electronic device 200 to be tested includes a fuse structure and a partition test structure. The fuse structure refers to a fusible element, for example, a fusible element provided between the P1 terminal and the P3 terminal, a fusible element provided between the P1 terminal and the P5 terminal, and a fusible element provided between the P1 terminal and the P5 terminal. 2B+1 The fusible elements between the terminals are all fusible structures. The partition test structure refers to capacitors, for example, capacitor C1 between P3 and P4, capacitor C2 between P5 and P6, and capacitor C3 between P6 and P7. 2B+1Terminal and P 2B+2 Capacitance C between the terminals B The partitioned test structure is beneficial for subsequent testing of a single capacitor 212 disposed between two terminals, so as to determine whether the capacitor 212 is qualified.

[0056] Figure 7 , Figure 8 and Fig. 9 A schematic diagram of a fusible element provided in an embodiment of the present disclosure is shown below in conjunction with Figure 7 , Figure 8 and Fig. 9 , describing in detail the structure of the fusible element.

[0057] The fusible element 210 may be Figure 7 The fusible element 300 is shown schematically. Figure 7 As shown, in some embodiments, the fusible element 300 includes a plurality of first conductive lines 302 coupled to a first terminal P1 and a third terminal P3 and connected in parallel, wherein the first conductive line 302 is provided with a first node 304 and a second node 306, and the first conductive line 302 includes a first sub-conductive line 308 provided between the first terminal P1 and the first node 304, and a second sub-conductive line 310 provided between the first node 304 and the second node 306 (such as Figure 7 The first node 304 includes a first conductive line 306 and a second conductive line 312 disposed between the second node 306 and the third terminal P3. The first conductive line 308, the second conductive line 310 and the third conductive line 312 are sequentially connected in series between the first terminal P1 and the third terminal P3. 1-1 , P 1-2 and P 1-N , the second node 306 includes P 3-1 , P 3-2 and P 3-N .

[0058] Here, the fusible element 300 includes N first conductive lines 302 , that is, the number of the first sub-conductive lines 308 , the second sub-conductive lines 310 , and the third sub-conductive lines 312 are all N; wherein N is an integer greater than 1.

[0059] Each first conductive line 302 is provided with a first node 304 and a second node 306. Figure 7 As shown, in the first first conductive line 302, the second sub-conductive line 310 is set at the first node P 1-1 and the second node P 3-1 In the second first conductive line 302, the second sub-conductive line 310 is provided at the first node P 1-2 and the second node P 3-2By analogy, in the Nth first conductive line 302, the second sub-conductive line 310 is set at the first node P 1-N and the second node P 3-N between.

[0060] In some embodiments, the first sub-conductive wire 308, the second sub-conductive wire 310, and the third sub-conductive wire 312 are made of the same material; the cross-sectional area of ​​the first sub-conductive wire 308 (or the third sub-conductive wire 312) is greater than the cross-sectional area of ​​the second sub-conductive wire 310. Here, the cross-sectional areas of the first sub-conductive wire 308 and the third sub-conductive wire 312 may be the same. The cross-sectional area of ​​a conductive wire refers to the product of the width and thickness of the conductive wire, and the cross-sectional area of ​​the conductive wire determines the current carrying capacity of the conductive wire.

[0061] In some embodiments, the thickness of the first sub-conductive line 308, the second sub-conductive line 310, and the third sub-conductive line 312 are the same, and the width of the first sub-conductive line 308 (or the third sub-conductive line 312) is N times the width of the second sub-conductive line 310. In other words, the cross-sectional area of ​​the first sub-conductive line 308 (or the third sub-conductive line 312) is N times the cross-sectional area of ​​the second sub-conductive line 310. If the widths of the first sub-conductive line 308 and the third sub-conductive line 312 are both a, then the width of the second sub-conductive line 310 is a / N, and the current carrying capacity of the N second sub-conductive lines 310 connected in parallel is equivalent to the current carrying capacity of one first sub-conductive line 308 (or the third sub-conductive line 312).

[0062] Here, the length of the second sub-conductive line 310 may be less than or equal to the distance between the first node 304 and the second node 306. The present disclosure has no special limitation on the length of the second sub-conductive line 310. Figure 7 The length of the second sub-conductive line 310 shown is only an optional embodiment.

[0063] Exemplarily, forming the first conductive line 302 may include: etching the first dielectric layer to form a first groove, the first groove including a first sub-groove, a second sub-groove and a third sub-groove connected in sequence; filling the first conductive material in the first sub-groove, the second sub-groove and the third sub-groove to form a first sub-conductive line in the first sub-groove, a second sub-conductive line in the second sub-groove and a third sub-conductive line in the third sub-groove. Here, the etching depths of the first sub-groove, the second sub-groove and the third sub-groove may be the same, and correspondingly, the thicknesses of the first sub-conductive line, the second sub-conductive line and the third sub-conductive line formed after filling may be the same. The widths of the first sub-groove and the third sub-groove may be the same and greater than the width of the second sub-groove, and correspondingly, the widths of the first sub-conductive line and the third sub-conductive line formed after filling are the same and greater than the width of the second sub-conductive line.

[0064] In some embodiments, the first conductive material may include a metal material, such as copper.

[0065] In some embodiments, before the first sub-groove, the second sub-groove, and the third sub-groove are filled with the first conductive material, the method may further include: forming a first barrier layer covering the sidewalls and bottom of the first sub-groove, the second sub-groove, and the third sub-groove; wherein the resistivity of the first barrier layer is greater than the resistivity of the first conductive line. Here, the first barrier layer may partially surround the first conductive line to prevent the metal material used to make the first conductive line from diffusing into the first dielectric layer.

[0066] Here, the material of the first barrier layer may include but is not limited to titanium nitride or tantalum nitride.

[0067] In this embodiment, since the first sub-conductive wire 308, the second sub-conductive wire 310 and the third sub-conductive wire 312 are made of the same material, the first sub-conductive wire 308, the second sub-conductive wire 310 and the third sub-conductive wire 312 can be formed in the same process, and the process flow is more convenient. By controlling the widths of the first sub-conductive wire 308, the second sub-conductive wire 310 and the third sub-conductive wire 312, the first conductive wire 302 can be used as a fusible element 300. Under appropriate temperature and current conditions, the first conductive wire 302 is fused, and the N second sub-conductive wires 310 can be electromigrated, and gaps are formed in the second sub-conductive wire 310, so that the first sub-conductive wire 308 and the third sub-conductive wire 312 are not electrically connected. In this way, the fusible element 300 can be changed from an unfused state to a fused state.

[0068] The fusible element 210 may be Figure 8 The fusible element 400 is shown schematically. Figure 8 As shown, the fusible element 400 includes a plurality of first conductive lines 402 coupled to a first terminal P1 and a third terminal P3 and connected in parallel, wherein the first conductive line 402 is provided with a first node 404 and a second node 406, and the first conductive line 402 includes a first sub-conductive line 408 provided between the first terminal P1 and the first node 404, and a second sub-conductive line 410 provided between the first node 404 and the second node 406 (as shown in FIG. Figure 8 The first node 404 includes a first conductive line 406 and a second conductive line 412 disposed between the second node 406 and the third terminal P3. The first conductive line 408, the second conductive line 410, and the third conductive line 412 are sequentially connected in series between the first terminal P1 and the third terminal P3. 1-1 , P 1-2 and P 1-M , the second node 406 includes P 3-1 , P 3-2 and P 3-M .

[0069] Here, the fusible element 400 includes M first conductive lines 402 , that is, the number of the first sub-conductive lines 408 , the second sub-conductive lines 410 , and the third sub-conductive lines 412 are all M; wherein M is an integer greater than 1.

[0070] Each first conductive line 402 is provided with a first node 404 and a second node 406. Figure 8 As shown, in the first first conductive line 402, the second sub-conductive line 410 is set at the first node P 1-1 and the second node P 3-1 In the second first conductive line 402, the second sub-conductive line 410 is provided at the first node P 1-2 and the second node P 3-2 By analogy, in the Mth first conductive line 402, the second sub-conductive line 410 is set at the first node P 1-M and the second node P 3-M between.

[0071] In some embodiments, the first sub-conductive wire 408 and the third sub-conductive wire 412 are made of the same material and different from the material of the second sub-conductive wire 410; the electrical mobility of the second sub-conductive wire 410 is greater than the electrical mobility of the first sub-conductive wire 408 (or the third sub-conductive wire 412). Here, the first sub-conductive wire 408 and the third sub-conductive wire 412 can be formed in the same process.

[0072] Exemplarily, forming the first conductive line 402 may include: etching the second dielectric layer to form a fourth sub-groove and a fifth sub-groove arranged at intervals; filling the fourth sub-groove and the fifth sub-groove with a second conductive material to form a first sub-conductive line in the fourth sub-groove and a third sub-conductive line in the fifth sub-groove; etching the second dielectric layer to form a sixth sub-groove between the first sub-conductive line and the third sub-conductive line, wherein the sixth sub-groove may expose the cross-section of the first sub-conductive line and the third sub-conductive line; and filling the sixth sub-groove with a third conductive material to form a second sub-conductive line in the sixth sub-groove. Here, only the example of forming the first sub-conductive line and the third sub-conductive line first and then forming the second sub-conductive line is used for exemplary description. The present disclosure does not specifically limit the process sequence of forming the first sub-conductive line, the second sub-conductive line, and the third sub-conductive line.

[0073] In some embodiments, the ratio between the resistivity of the first sub-conductive line 408 (or the third sub-conductive line 412 ) and the resistivity of the second sub-conductive line 410 is in a range of 0.5 to 5.

[0074] In some embodiments, the second conductive material may include a metal material, such as copper; the third conductive material may be, for example, pure aluminum. Here, the resistivity of the second conductive material and the third conductive material are relatively close, which is conducive to ensuring the conductive performance of the first conductive line 402; the electrical mobility of the third conductive material is greater than that of the second conductive material, and the third conductive material is more likely to undergo electrical migration than the second conductive material, so as to form a gap in the second sub-conductive line 410.

[0075] In this embodiment, the material of the first sub-conductive wire 408 and the third sub-conductive wire 412 is the same, and different from the material of the second sub-conductive wire 410. The electrical mobility of the second sub-conductive wire 410 is greater than that of the first sub-conductive wire 408 (or the third sub-conductive wire 412). The material with greater electrical mobility is selected to make the second sub-conductive wire 410, so that the first conductive wire 402 can be used as the fusible element 400. Under appropriate temperature and current conditions, the first conductive wire 402 is fused, and the N second sub-conductive wires 410 are more likely to undergo electrical migration, and gaps are formed in the second sub-conductive wires 410, so that the first sub-conductive wire 408 and the third sub-conductive wire 412 are not electrically connected. In this way, the fusible element 400 can be changed from an unfused state to a fused state.

[0076] In some embodiments, the cross-sectional areas of the first sub-conductive line 408, the second sub-conductive line 410, and the third sub-conductive line 412 may be the same. The thicknesses of the first sub-conductive line 408, the second sub-conductive line 410, and the third sub-conductive line 412 may be the same, and the widths of the first sub-conductive line 408, the second sub-conductive line 410, and the third sub-conductive line 412 may also be the same.

[0077] In other embodiments, the cross-sectional areas of the first sub-conductive line 408 and the third sub-conductive line 412 may be the same and greater than the cross-sectional area of ​​the second sub-conductive line 410. The thicknesses of the first sub-conductive line 408, the second sub-conductive line 410 and the third sub-conductive line 412 are the same, and the width of the first sub-conductive line 408 (or the third sub-conductive line 412) is M times the width of the second sub-conductive line 410. In other words, the cross-sectional area of ​​the first sub-conductive line 408 (or the third sub-conductive line 412) is M times the cross-sectional area of ​​the second sub-conductive line 410. Based on this, compared with the first sub-conductive line 408 and the third sub-conductive line 412, the width of the second sub-conductive line 410 is smaller and the third conductive material is more likely to undergo electromigration, which is more conducive to forming a gap in the second sub-conductive line 410, so that the first sub-conductive line 408 and the third sub-conductive line 412 are not electrically connected, so that it is more conducive to the fusible element 400 to change from an unfused state to a fused state.

[0078] Here, the length of the second sub-conductive line 410 may be less than or equal to the distance between the first node 404 and the second node 406. The present disclosure has no particular limitation on the length of the second sub-conductive line 410. Figure 8 The illustrated length of the second sub-conductive line 410 is only an optional embodiment.

[0079] In some embodiments, before filling the second conductive material in the fourth and fifth sub-grooves, the method may further include: forming a second barrier layer covering the sidewalls and bottom of the fourth and fifth sub-grooves; before filling the third conductive material in the sixth sub-groove, the method may further include: forming a third barrier layer covering the sidewalls and bottom of the sixth sub-groove. Here, the resistivity of the second barrier layer (or the third barrier layer) is greater than the resistivity of the first conductive line.

[0080] Here, the materials of the second barrier layer and the third barrier layer may include but are not limited to titanium nitride or tantalum nitride.

[0081] The fusible element 210 may be Fig. 9 The fusible element 500 is shown schematically. Fig. 9 As shown, in some embodiments, the fusible element 500 is coupled between the first terminal P1 and the third terminal P3; the fusible element 500 includes a second conductive line 502 and a variable resistor 504 (such as a resistor 504) coupled between the first terminal P1 and the third terminal P3 and connected in series. Fig. 9 The second conductive line 502 and the variable resistor 504 are made of different materials. The present disclosure has no particular limitation on the number of variable resistors 504 connected in series, and the number can be selected according to actual conditions.

[0082] Here, the variable resistor 504 is blown, and the resistance of the variable resistor 504 can be adjusted. By increasing the resistance of the variable resistor 504, the resistance of the series path between the first terminal P1 and the third terminal P3 is increased, and a high-resistance state is achieved. There is no electrical connection between the first terminal P1 and the third terminal P3. In this way, the fusible element 500 can be changed from an unblown state to a blown state.

[0083] Here, the variable resistor 504 may include a positive temperature coefficient (PTC) thermistor material, the resistivity of which changes significantly with temperature near the Curie temperature, and the resistivity increases sharply with increasing temperature. By fusing the variable resistor 504, the temperature of the thermistor material can be increased, and the resistance of the thermistor increases by an order of magnitude after the temperature is increased, and the resistance of the entire series path increases, thereby achieving a high resistance state.

[0084] Compared to Figure 7 and Figure 8 In the schematic diagram of the fusible element, a gap appears in the second sub-conductive line after the fusing process, that is, the second sub-conductive line appears in a physically disconnected state. In this embodiment, the variable resistor 504 does not appear in a physically disconnected state, and a high-resistance state can be achieved by increasing the resistance value of the variable resistor 504, which is more conducive to controlling the fusible element 500 to change from an unfused state to a fused state.

[0085] In the embodiment of the present disclosure, in step S120, the electronic device to be detected is detected, and whether the electronic device to be detected is qualified is determined based on the leakage current in the electronic device to be detected and the actual capacitance of the electronic device to be detected. In some embodiments, step S120 includes: when the leakage current in the electronic device to be detected is less than a first preset value, and the absolute value of the difference between the actual capacitance of the electronic device to be detected and the sum of the theoretical capacitances of all capacitors is less than a second preset value, the electronic device to be detected is determined to be a qualified electronic device; when the leakage current in the electronic device to be detected is greater than or equal to the first preset value, and / or the absolute value of the difference between the actual capacitance of the electronic device to be detected and the sum of the theoretical capacitances of all capacitors is greater than or equal to the second preset value, the electronic device to be detected is determined to be an unqualified electronic device. Here, a qualified electronic device means that each capacitor in the electronic device is a qualified capacitor, and an unqualified electronic device means that at least one capacitor in the electronic device is an unqualified capacitor.

[0086] Here, two aspects need to be considered to determine whether the electronic device to be tested is qualified. On the one hand, it is necessary to consider the size relationship between the leakage current in the electronic device to be tested and the first preset value. If a capacitor in the electronic device to be tested has a defect and causes a short circuit or the leakage defect of a capacitor is serious, then the current in the electronic device to be tested is large, for example, greater than or equal to the first preset value; if all capacitors in the electronic device to be tested are good, then the leakage current in the electronic device to be tested is small, for example, less than the first preset value. Therefore, the size relationship between the leakage current in the electronic device to be tested and the first preset value can be used as one of the conditions for judging whether the electronic device to be tested is qualified.

[0087] Here, the leakage current can be used as a parameter to determine whether the electronic device to be detected is qualified, and the breakdown voltage can be used as a parameter to determine whether the electronic device to be detected is qualified. Usually, the leakage current of the capacitor increases with the increase of the working voltage of the capacitor. When the working voltage reaches the breakdown voltage (Voltage Break Down, VBD) of the capacitor, the rapid increase of the leakage current indicates that the capacitor has broken down. The first preset value can be determined according to the design specifications of the capacitor. The present disclosure has no special limitation on the specific value of the first preset value, and it can be set according to the design specifications of the capacitor.

[0088] Secondly, it is necessary to consider the absolute value of the difference between the actual capacitance of the electronic device to be tested and the sum of the theoretical capacitance of all capacitors and the second preset value. If a capacitor in the electronic device to be tested is defective and causes a short circuit, the actual capacitance of the electronic device to be tested is 0; if all capacitors in the capacitor are good, the actual capacitance of the electronic device to be tested is the sum of the actual capacitance of all capacitors.

[0089] It should be noted that due to the existence of manufacturing process errors, there may be an error between the actual capacitance and theoretical capacitance of a single capacitor. For example, the theoretical capacitance of the designed capacitor is 5F, and the actual capacitance of the capacitor can be 5±0.2F. In other words, the actual capacitance of the capacitor obtained by testing can be considered as a qualified capacitor within the range of 4.8 to 5.2F. Here, the manufacturing process error can be considered, and the sum of the theoretical capacitance of all capacitors and the sum of the actual capacitance of all capacitors of the electronic device to be tested can be determined according to the theoretical capacitance and actual capacitance of a single capacitor; the second preset value is determined according to the absolute value of the difference between the sum of the theoretical capacitance of all capacitors and the sum of the actual capacitance of all capacitors. If the absolute value of the difference between the actual capacitance of the electronic device to be tested and the sum of the theoretical capacitance of all capacitors is less than the second preset value, then the absolute value of the difference between the actual capacitance of the electronic device to be tested and the sum of the theoretical capacitance of all capacitors is within the acceptable manufacturing process error range.

[0090] In the embodiment of the present disclosure, in step S130, each capacitor in the unqualified electronic device is detected, and whether the capacitor is qualified is determined according to the leakage current in the capacitor and the actual capacitance of the capacitor. In some embodiments, step S130 includes: when the leakage current in the capacitor is less than the third preset value, and the absolute value of the difference between the actual capacitance of the capacitor and the theoretical capacitance of the capacitor is less than the fourth preset value, determining that the capacitor is a qualified capacitor; when the leakage current in the capacitor is greater than or equal to the third preset value, and / or the absolute value of the difference between the actual capacitance of the capacitor and the theoretical capacitance of the capacitor is greater than or equal to the fourth preset value, determining that the capacitor is an unqualified capacitor.

[0091] Here, for unqualified electronic devices, each capacitor in the unqualified electronic devices needs to be tested separately. There are two aspects to consider when judging whether the capacitor is qualified. On the one hand, it is necessary to consider the size relationship between the leakage current in the capacitor and the third preset value. If there is a defect in the capacitor that causes a short circuit or the leakage defect of a capacitor is serious, then the current in the capacitor is large, for example, greater than or equal to the third preset value; if the capacitor is a good product, then the leakage current in the capacitor is small, for example, less than the third preset value. Therefore, the size relationship between the leakage current in the capacitor and the third preset value can be used as one of the conditions for judging whether the capacitor is qualified.

[0092] Similarly, the breakdown voltage of the capacitor can also be used as a parameter to determine whether the capacitor is qualified. The third preset value can be determined according to the design specifications of the capacitor. The present disclosure has no special limitation on the specific value of the third preset value, which can be set according to the design specifications of the capacitor.

[0093] In the second aspect, the absolute value of the difference between the actual capacitance of the capacitor and the theoretical capacitance of the capacitor and the fourth preset value. If the capacitor is defective and causes a short circuit, the actual capacitance of the capacitor is 0; if the capacitor is good, the absolute value of the difference between the actual capacitance of the capacitor and the theoretical capacitance is within an acceptable manufacturing process error range.

[0094] In the embodiment of the present disclosure, in step S140, a fusible element coupled to the unqualified capacitor is fused, so that the fusible element is changed from an unfused state to a fused state.

[0095] In some embodiments, step S140 includes: under suitable temperature and current conditions, Figure 7 The second sub-conductive line 310 shown in the diagram is subjected to a fusing process, and the second sub-conductive line 310 undergoes electromigration to form a gap in the second sub-conductive line 310, forming an open circuit state between the first terminal P1 and the third terminal P3, so that there is no electrical connection between the first sub-conductive line 308 and the third sub-conductive line 312, so that the fusible element 300 can be changed from an unfused state to a fused state.

[0096] In some embodiments, the first barrier layer is further disposed on the sidewall of the first conductive line 302. Although the second sub-conductive line 310 undergoes electromigration and a gap is formed in the second sub-conductive line 310, a portion of the first barrier layer disposed on the sidewall of the first sub-conductive line 308 and a portion of the first barrier layer disposed on the sidewall of the third sub-conductive line 312 are still connected through a portion of the first barrier layer disposed on the sidewall of the second sub-conductive line 310. Since the resistivity of the first barrier layer is greater than the resistivity of the second sub-conductive line 310, the second sub-conductive line 310 between the first terminal P1 and the third terminal P3 is disconnected, and the first barrier layer between the first terminal P1 and the third terminal P3 is connected, forming a high resistance state between the first terminal P1 and the third terminal P3. At this time, the first terminal P1 and the third terminal P3 are not electrically connected.

[0097] In some embodiments, step S140 includes: under suitable temperature and current conditions, Fig. 9 The second sub-conductive line 410 shown in the diagram is subjected to a fusing process, and the second sub-conductive line 410 undergoes electrical migration to form a gap in the second sub-conductive line 410, forming an open circuit state between the first terminal P1 and the third terminal P3, so that there is no electrical connection between the first sub-conductive line 408 and the third sub-conductive line 412, so that the fusible element 400 can be changed from an unfused state to a fused state.

[0098] In some embodiments, a second barrier layer is further disposed on the sidewall of the first conductive line 402. After the second sub-conductive line 410 undergoes electromigration, a portion of the second barrier layer disposed on the sidewall of the first sub-conductive line 408 and a portion of the second barrier layer disposed on the sidewall of the third sub-conductive line 412 are still connected via a portion of the second barrier layer disposed on the sidewall of the second sub-conductive line 410. Since the resistivity of the second barrier layer is greater than the resistivity of the second sub-conductive line 410, the second sub-conductive line 410 between the first terminal P1 and the third terminal P3 is disconnected, and the second barrier layer between the first terminal P1 and the third terminal P3 is connected, forming a high resistance state between the first terminal P1 and the third terminal P3. At this time, the first terminal P1 and the third terminal P3 are not electrically connected.

[0099] In some embodiments, step S140 includes: Fig. 9 The variable resistor 504 in the illustrated fusible element 500 is blown, the resistance of the variable resistor 504 increases, and a high-resistance state is formed between the first terminal P1 and the third terminal P3, so that there is no electrical connection between the first terminal P1 and the third terminal P3. In this way, the fusible element 500 can be changed from an unblown state to a blown state.

[0100] In some embodiments, the theoretical capacitance of the capacitor in each branch may be the same or different. For ease of description, the following description is based on an example in which the theoretical capacitance of the capacitor in each branch is the same.

[0101] In some embodiments, the method further includes: classifying qualified electronic devices and unqualified electronic devices that have undergone fuse processing according to target theoretical capacitance values ​​of the electronic devices to be tested.

[0102] Here, the B capacitors in the qualified electronic device are all good products, and the theoretical capacitance of each capacitor is C, where B is an integer greater than 1. Therefore, the theoretical capacitance of the qualified electronic device is B*C. At this time, the B fusible elements in the qualified electronic device are all in an unfused state.

[0103] Here, among the B capacitors included in the unqualified electronic device, there are D unqualified capacitors, and the number of qualified capacitors is (BD); wherein B is greater than or equal to D, and D is a positive integer. Therefore, the theoretical capacitance of the unqualified electronic device after the fusing process is (BD)*C. At this time, among the unqualified electronic devices after the fusing process, D fusible elements are in the fused state, and (BD) fusible elements are in the unfused state.

[0104] In some embodiments, the target theoretical capacitance of the electronic device to be detected is E*C, where E is less than B and E is a positive integer. Here, considering the manufacturing process error, the electronic device to be detected is usually provided with redundant capacitors, the number of designed redundant capacitors is (BE), and the target theoretical capacitance of the electronic device to be detected is (BE)*C.

[0105] Here, electronic devices can be classified according to different rules, and the following is only an exemplary explanation of classification into three categories. The theoretical capacitance of the first category of electronic devices is greater than or equal to the target theoretical capacitance, that is, the number of capacitors that can be in normal working condition in the first category of electronic devices is greater than or equal to E. In other words, the number of capacitors that cannot be used normally in the first category of electronic devices is less than or equal to (BE). The theoretical capacitance of the second category of electronic devices is greater than 0 and less than the target theoretical capacitance, that is, the number of capacitors that can be in normal working condition in the second category of electronic devices is greater than 0 and less than E. The theoretical capacitance of the third category of electronic devices is 0, that is, the number of capacitors that can be in normal working condition in the third category of electronic devices is 0. In other words, all capacitors in the third category of electronic devices cannot be used normally, or all fusible elements in the third category of electronic devices are in a fused state.

[0106] In some embodiments, when (BD) ≥ E, qualified electronic devices and unqualified electronic devices that have been fused are both classified as first-category electronic devices; when 0 < (BD) < E, qualified electronic devices are classified as first-category electronic devices, and unqualified electronic devices that have been fused are classified as second-category electronic devices; when (BD) = 0, qualified electronic devices are classified as first-category electronic devices, and unqualified electronic devices that have been fused are classified as third-category electronic devices. That is, when (BD) = 0, the theoretical capacitance of the electronic device that has been fused is 0.

[0107] The following will describe the detection method of the electronic device to be detected with reference to a specific example.

[0108] In step S110, the target theoretical capacitance of the designed electronic device is 10*C, the electronic device to be detected may include 12 capacitors, and the theoretical capacitance of the electronic device to be detected is 12*C, of ​​which 2 capacitors are redundant capacitors.

[0109] In step S120, it is determined whether the electronic device to be detected is qualified. When the leakage current in the electronic device to be detected is less than the first preset value, and the absolute value of the difference between the actual capacitance of the electronic device to be detected and 12*C is less than the second preset value, the electronic device to be detected is determined to be a qualified electronic device; when the leakage current in the electronic device to be detected is greater than or equal to the first preset value, and / or the absolute value of the difference between the actual capacitance of the electronic device to be detected and 12*C is greater than or equal to the second preset value, the electronic device to be detected is determined to be an unqualified electronic device.

[0110] In step S130, it is determined whether each capacitor in the unqualified electronic device is qualified. When the leakage current in the capacitor is less than the third preset value, and the absolute value of the difference between the actual capacitance of the capacitor and the theoretical capacitance of the capacitor is less than the fourth preset value, the capacitor is determined to be a qualified capacitor; when the leakage current in the capacitor is greater than or equal to the third preset value, and / or the absolute value of the difference between the actual capacitance of the capacitor and the theoretical capacitance of the capacitor is greater than or equal to the fourth preset value, the capacitor is determined to be an unqualified capacitor.

[0111] In step S140, a fusible element coupled to the unqualified capacitor is fused, so that the fusible element is changed from an unfused state to a fused state.

[0112] The number of unqualified capacitors is illustrated. For example, the number of unqualified capacitors may be 1, and the number of qualified capacitors may be 11. One fusible element in the electronic device is in a blown state, and 11 fusible elements are in an unblown state. The theoretical capacitance of the electronic device is 11*C, which is greater than the target theoretical capacitance of 10*C and can meet the use requirements.

[0113] For example, the number of unqualified capacitors may be 5, and the number of qualified capacitors may be 7. Five fusible components in the electronic device are in a blown state, and seven fusible components are in an unblown state. The theoretical capacitance of the electronic device is 7*C, which is smaller than the target theoretical capacitance of 10*C, and can meet the use scenarios with smaller capacitance requirements.

[0114] For example, the number of unqualified capacitors may be 12. Twelve fusible components in the electronic device are in a blown state. The theoretical capacitance of the electronic device is 0, which cannot meet the use requirements.

[0115] Compared with setting 12 capacitors connected in parallel, as long as one capacitor is in a short-circuit state, the capacitance of the entire capacitor is 0. In the detection method provided by the embodiment of the present disclosure, when an unqualified capacitor is detected, the fusible element coupled to the unqualified capacitor can be fused, and when the number of unqualified capacitors is less than or equal to 2, the unqualified electronic device after the fusion treatment can still be used as a first-class electronic device; when the number of unqualified capacitors is greater than 0 and less than 12, the unqualified electronic device after the fusion treatment can be used as a second-class electronic device. Therefore, the yield of electronic devices can be improved.

[0116] refer to Fig.10 , Fig.10 Schematic diagram of an electronic device provided by an embodiment of the present disclosure. Fig.10 As shown, an embodiment of the present disclosure provides an electronic device, which includes: a plurality of parallel-connected branches 608 coupled between a first terminal 602 and a second terminal 604, each branch 608 including a fusible element 610 and a capacitor 612 connected in series, the fusible element 610 coupled between the first terminal 602 and the third terminal 606, and the capacitor 612 coupled between the second terminal 604 and the third terminal 606; wherein the fusible element state includes an un-fused state and a fused state, when the fusible element 610 is in the un-fused state, the first terminal 602 and the third terminal 606 are electrically connected, and when the fusible element 610 is in the fused state, the first terminal 602 and the third terminal 606 are not electrically connected; the fusible element 610 in at least one branch 608 is in the un-fused state, and / or, the fusible element 610 in at least one branch 608 is in the fused state.

[0117] here, Fig.10 The electronic device 600 is shown to include B branches 608 connected in parallel, each branch 608 includes a fusible element 610 and a capacitor 612 connected in series, that is, the electronic device 600 includes B fusible elements 610 and B capacitors 612. After detection, the electronic device 600 includes D unqualified capacitors 612, and the fusible elements 610 coupled to these unqualified capacitors 612 have been fused. Therefore, among the B fusible elements 610 of the electronic device 600, D fusible elements 610 are in a fused state, and (BD) fusible elements 610 are in an unfused state.

[0118] Here, the theoretical capacitance of the electronic device 600 is the sum of the theoretical capacitances of the (BD) capacitors 612 , and the actual capacitance of the electronic device 600 is the sum of the actual capacitances of the (BD) capacitors 612 .

[0119] Return to reference Figure 7As shown, in some embodiments, the fusible element 300 includes: a plurality of first conductive lines 302 coupled to a first terminal P1 and a third terminal P3 and connected in parallel, a first node 304 and a second node 306 being provided on the first conductive line 302, the first conductive line 302 including a first sub-conductive line 308 provided between the first terminal P1 and the first node 304, a second sub-conductive line 310 provided between the first node 304 and the second node 306, and a third sub-conductive line 312 provided between the second node 306 and the third terminal P3; wherein, when the fusible element 400 is in an un-fused state, the first sub-conductive line 308 and the third sub-conductive line 312 are electrically connected through the second sub-conductive line 310; when the fusible element 400 is in a fused state, a gap is provided in the second sub-conductive line 310, and the first sub-conductive line 308 and the third sub-conductive line 312 are not electrically connected.

[0120] In some embodiments, the fusible element also includes: a barrier layer disposed on the side wall of the first conductive line, the resistivity of the barrier layer being greater than the resistivity of the first conductive line; wherein, when the fusible element is in an unfused state or a fused state, a portion of the barrier layer disposed on the side wall of the first sub-conductive line and a portion of the barrier layer disposed on the side wall of the third sub-conductive line are connected via a portion of the barrier layer disposed on the side wall of the second sub-conductive line.

[0121] In some embodiments, the first sub-conductive line 308 , the second sub-conductive line 310 and the third sub-conductive line 312 are made of the same material; the cross-sectional area of ​​the first sub-conductive line 308 (or the third sub-conductive line 312 ) is greater than the cross-sectional area of ​​the second sub-conductive line 310 .

[0122] In some embodiments, the fusible element 300 includes N first conductive wires 302, the first sub-conductive wire 308, the second sub-conductive wire 310 and the third sub-conductive wire 312 have the same thickness, and the width of the first sub-conductive wire 308 (or, the third sub-conductive wire 312) is N times the width of the second sub-conductive wire 310; wherein N is an integer greater than 1.

[0123] Return to reference Figure 8 As shown, in some embodiments, the material of the first sub-conductive line 408 and the third sub-conductive line 412 is the same and different from the material of the second sub-conductive line 410; the electrical mobility of the second sub-conductive line 410 is greater than the electrical mobility of the first sub-conductive line 408 (or, the third sub-conductive line 412).

[0124] Return to reference Fig. 9As shown, in some embodiments, the fusible element 500 includes: a second conductive line 502 and a variable resistor 504 coupled between the first terminal P1 and the third terminal P3 and connected in series, and the second conductive line 502 and the variable resistor 504 are made of different materials; wherein, when the fusible element 500 is in an un-fused state, the resistance of the variable resistor 504 is less than the resistance of the variable resistor 504 when the fusible element 500 is in a fused state.

[0125] refer to Fig.11 , Fig.11 The block diagram of the adapter board provided in the embodiment of the present disclosure is shown in FIG. Fig.11 As shown, the embodiment of the present disclosure provides a transfer board, and the transfer board 700 includes: an electronic device 702 as in the above technical solution. Here, the electronic device 702 is a qualified electronic device that has been tested, or an unqualified electronic device that has been blown. The structure of the fusible element in the qualified electronic device and the unqualified electronic device that has been blown can be referred to Figures 7 to 9 shown.

[0126] Compared with active devices on active chips, such as transistors, amplifiers or integrated circuits, they can actively generate, amplify or adjust signals and play a leading role in the behavior of the circuit. These components can control the current and voltage in the circuit, and have the characteristics of energy amplification and complexity. Therefore, different circuit function selections can be realized through programming or control logic. However, 2.5D silicon adapters or high-density capacitor process platforms only have passive devices, such as resistors, capacitors or inductors. Passive devices cannot actively generate or amplify signals, but can only limit, adjust or transmit input signals, and cannot provide additional energy output. Since passive devices do not involve energy conversion, their structure and operation are relatively simple. Therefore, passive devices cannot dynamically respond to external signals or make complex circuit function selections like active devices. The response of passive devices depends only on parameters such as resistance, capacitance, inductance, etc. in the circuit. They do not have the ability to control other components, nor can they produce self-oscillation phenomena or signal amplification and transmission capabilities. Therefore, the embodiments of the present disclosure can repair the yield loss of electronic devices caused by short circuit and leakage problems through the structural design of electronic devices, and solve the problem of improving the yield of capacitor products when functional selection cannot be achieved due to the lack of energy conversion and control capabilities in passive devices.

[0127] The disclosed embodiments provide an electronic device and a detection method thereof, and an adapter board. The electronic device includes: a plurality of parallel-connected branches coupled between a first terminal and a second terminal, each branch including a fusible element and a capacitor connected in series, the fusible element coupled between the first terminal and the third terminal, and the capacitor coupled between the second terminal and the third terminal; wherein the fusible element state includes an unfused state and a fused state, when the fusible element is in the unfused state, the first terminal and the third terminal are electrically connected, and when the fusible element is in the fused state, the first terminal and the third terminal are not electrically connected; the fusible element in at least one branch is in the unfused state, and / or the fusible element in at least one branch is in the fused state. In the disclosed embodiment, unqualified electronic devices are identified among the electronic devices to be tested, and then unqualified capacitors are identified among the unqualified electronic devices. Fusible elements coupled to the unqualified capacitors are fused so that the fusible elements are changed from an unfused state to a fused state, thereby avoiding yield loss of electronic devices caused by unqualified capacitors, thereby improving the yield of electronic devices.

[0128] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0129] The above description is only a preferred embodiment of the present disclosure, and does not limit the patent scope of the present disclosure. All equivalent structural changes made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. An electronic device, characterized in that: The electronic device comprises: A plurality of parallel-connected branches coupled between the first terminal and the second terminal, each of the branches comprising a fusible element and a capacitor connected in series, the fusible element coupled between the first terminal and the third terminal, and the capacitor coupled between the second terminal and the third terminal; Among them, the state of the fusible element includes an un-fused state and a fused state. When the fusible element is in the un-fused state, the first terminal and the third terminal are electrically connected, and when the fusible element is in the fused state, the first terminal and the third terminal are not electrically connected; the fusible element in at least one of the branches is in the un-fused state, and / or the fusible element in at least one of the branches is in the fused state.

2. The electronic device according to claim 1, characterized in that The fusible element comprises: A plurality of first conductive lines coupled to the first terminal and the third terminal, wherein the first conductive lines are provided with a first node and a second node, and the first conductive lines include a first sub-conductive line provided between the first terminal and the first node, a second sub-conductive line provided between the first node and the second node, and a third sub-conductive line provided between the second node and the third terminal; Among them, when the fusible element is in an un-blown state, the first sub-conductive wire and the third sub-conductive wire are electrically connected through the second sub-conductive wire; when the fusible element is in a blown state, there is a gap in the second sub-conductive wire, and the first sub-conductive wire and the third sub-conductive wire are not electrically connected.

3. The electronic device according to claim 2, characterized in that: The fusible element further comprises: a barrier layer disposed on a side wall of the first conductive line, wherein the resistivity of the barrier layer is greater than the resistivity of the first conductive line; Wherein, when the fusible element is in an unfused state or a fused state, part of the barrier layer arranged on the side wall of the first sub-conductive line and part of the barrier layer arranged on the side wall of the third sub-conductive line are connected through part of the barrier layer arranged on the side wall of the second sub-conductive line.

4. The electronic device according to claim 2 or 3, characterized in that: The first sub-conductive wire, the second sub-conductive wire and the third sub-conductive wire are made of the same material; the cross-sectional area of ​​the first sub-conductive wire is greater than that of the second sub-conductive wire, and the cross-sectional area of ​​the third sub-conductive wire is greater than that of the second sub-conductive wire.

5. The electronic device according to claim 4, characterized in that: The fusible element includes N first conductive wires, the first sub-conductive wire, the second sub-conductive wire and the third sub-conductive wire have the same thickness, the width of the first sub-conductive wire is N times the width of the second sub-conductive wire, and the width of the third sub-conductive wire is N times the width of the second sub-conductive wire; wherein N is an integer greater than 1.

6. The electronic device according to claim 2 or 3, characterized in that: The material of the first sub-conductive wire and the third sub-conductive wire is the same and different from the material of the second sub-conductive wire; the electrical mobility of the second sub-conductive wire is greater than the electrical mobility of the first sub-conductive wire, and the electrical mobility of the second sub-conductive wire is greater than the electrical mobility of the third sub-conductive wire.

7. The electronic device according to claim 1, characterized in that: The fusible element comprises: A second conductive wire and a variable resistor are coupled between the first terminal and the third terminal and connected in series, and the second conductive wire and the variable resistor are made of different materials; wherein when the fusible element is in an un-blown state, the resistance of the variable resistor is less than the resistance of the variable resistor when the fusible element is in a blown state.

8. An adapter plate, characterized in that: The adapter board comprises: the electronic device according to any one of claims 1 to 7.

9. A method for detecting an electronic device, characterized in that: The method comprises: An electronic device to be tested is provided, comprising: a plurality of parallel-connected branches coupled between a first terminal and a second terminal, each of the branches comprising a fusible element and a capacitor connected in series, and the fusible element in each of the branches is in an unfused state; Testing the electronic device to be tested, and determining whether the electronic device to be tested is qualified according to the leakage current in the electronic device to be tested and the actual capacitance of the electronic device to be tested; Detecting each of the capacitors in the unqualified electronic device, and determining whether the capacitor is qualified according to the leakage current in the capacitor and the actual capacitance of the capacitor; The fusible element coupled to the unqualified capacitor is subjected to a fusing process, so that the fusible element is changed from an unfused state to a fused state.

10. The detection method according to claim 9, characterized in that: The fusible element is coupled between the first terminal and the third terminal; the fusible element comprises a plurality of first conductive lines connected in parallel and coupled between the first terminal and the third terminal, a first node and a second node are provided on the first conductive line, the first conductive line comprises a first sub-conductive line provided between the first terminal and the first node, a second sub-conductive line provided between the first node and the second node, and a third sub-conductive line provided between the second node and the third terminal; The fusing process of the fusible element coupled to the unqualified capacitor includes: The second sub-conductive line coupled to the unqualified capacitor is subjected to a fusing process, and the second sub-conductive line undergoes electromigration to form a gap in the second sub-conductive line, so that the first sub-conductive line and the third sub-conductive line are not electrically connected.

11. The detection method according to claim 10, characterized in that: The first sub-conductive wire, the second sub-conductive wire and the third sub-conductive wire are made of the same material; the cross-sectional area of ​​the first sub-conductive wire is greater than that of the second sub-conductive wire, and the cross-sectional area of ​​the third sub-conductive wire is greater than that of the second sub-conductive wire.

12. The detection method according to claim 10, characterized in that: The material of the first sub-conductive wire and the third sub-conductive wire is the same and different from the material of the second sub-conductive wire; the electrical mobility of the second sub-conductive wire is greater than the electrical mobility of the first sub-conductive wire, and the electrical mobility of the second sub-conductive wire is greater than the electrical mobility of the third sub-conductive wire.

13. The detection method according to claim 9, characterized in that: The fusible element is coupled between the first terminal and the third terminal; the fusible element comprises a second conductive line and a variable resistor coupled between the first terminal and the third terminal and connected in series, and the second conductive line and the variable resistor are made of different materials; The fusing process of the fusible element coupled to the unqualified capacitor includes: The variable resistor coupled to the unqualified capacitor is fused so that there is no electrical connection between the first terminal and the third terminal; wherein, when the fusible element is in an unfused state, the resistance of the variable resistor is less than the resistance of the variable resistor when the fusible element is in a fused state.

14. The detection method according to claim 9, characterized in that: The step of determining whether the electronic device to be tested is qualified comprises: When the leakage current in the electronic device to be detected is less than a first preset value, and the absolute value of the difference between the actual capacitance of the electronic device to be detected and the sum of the theoretical capacitances of all the capacitors is less than a second preset value, the electronic device to be detected is determined to be a qualified electronic device; When the leakage current in the electronic device to be detected is greater than or equal to the first preset value, and / or the absolute value of the difference between the actual capacitance of the electronic device to be detected and the sum of the theoretical capacitances of all the capacitors is greater than or equal to the second preset value, the electronic device to be detected is determined to be an unqualified electronic device.

15. The detection method according to claim 14, characterized in that: The determining whether the capacitor is qualified includes: When the leakage current in the capacitor is less than a third preset value, and the absolute value of the difference between the actual capacitance of the capacitor and the theoretical capacitance of the capacitor is less than a fourth preset value, determining that the capacitor is a qualified capacitor; When the leakage current in the capacitor is greater than or equal to the third preset value, and / or the absolute value of the difference between the actual capacitance of the capacitor and the theoretical capacitance of the capacitor is greater than or equal to the fourth preset value, the capacitor is determined to be an unqualified capacitor.

16. The detection method according to claim 15, characterized in that: After fusing the fusible element coupled to the unqualified capacitor, the method further includes: According to the target theoretical capacitance of the electronic device to be tested, the qualified electronic devices and the unqualified electronic devices that have been subjected to the fusing process are classified and processed.

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