Semiconductor device and forming method thereof

Abstract

In an embodiment, a method includes forming an active device over a semiconductor substrate; forming an interconnect structure over the semiconductor substrate, the interconnect structure including a contact pad embedded in the dielectric layer; forming a first passivation layer over the interconnect structure; forming a first opening through the first passivation layer to expose the contact pad; depositing a seed layer over the first passivation layer and in the first opening; forming a sacrificial material over the seed layer; patterning the sacrificial material to reform the first opening and to form a second opening; depositing a conductive material to form a first redistribution line in the first opening and a second redistribution line in the second opening; removing the sacrificial material; and attaching an integrated circuit die to the first redistribution line and the second redistribution line. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density comes from the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, the demand for smaller semiconductor dies with more components emerges. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming an active device above a semiconductor substrate; forming an interconnect structure above the semiconductor substrate, the interconnect structure comprising a contact pad embedded in a dielectric layer; forming a first passivation layer above the interconnect structure; forming a first opening through the first passivation layer to expose the contact pad; depositing a seed layer above the first passivation layer and in the first opening; forming a sacrificial material above the seed layer; patterning the sacrificial material to reform the first opening and to form a second opening; depositing a conductive material to form a first redistribution line in the first opening and a second redistribution line in the second opening; removing the sacrificial material; and attaching an integrated circuit die to the first redistribution line and the second redistribution line.

[0004] Other embodiments of the present application provide a semiconductor device, comprising: a first integrated circuit die, comprising: a first interconnect structure located above the device layer, the first interconnect structure including a first contact pad; a first passivation layer located above the first interconnect structure; a second passivation layer located above the first passivation layer; and a first redistribution line extending from the upper surface of the second passivation layer to the first contact pad; and a second integrated circuit die attached to the first integrated circuit die, a conductive component of the second integrated circuit die directly bonded to the first redistribution line, and a dielectric layer of the second integrated circuit die directly bonded to the second passivation layer.

[0005] Some other embodiments of the present application provide a semiconductor device, including: a first integrated circuit, including a first device layer and a first interconnect structure; a second integrated circuit, electrically connected to the first integrated circuit, the second integrated circuit including a second device layer and a second interconnect structure; and a bonding area, between the first interconnect structure and the second interconnect structure, the bonding area including: a first passivation layer, adjacent to the first interconnect structure; a first redistribution line, embedded in the first passivation layer; a second passivation layer, adjacent to the second interconnect structure, the second passivation layer bonded to the first passivation layer; and a second redistribution line, embedded in the second passivation layer, the second redistribution line bonded to the first redistribution line. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figures 1 to 10 is a cross-sectional view of an intermediate stage in the fabrication of an integrated circuit die in accordance with some embodiments.

[0008] Figures 11 to 14 is a cross-sectional view of an intermediate stage in the fabrication of an integrated circuit die in accordance with some embodiments.

[0009] Figure 15 to Figure 16 is a cross-sectional view of an intermediate stage in the fabrication of a die structure according to some embodiments.

[0010] Figures 17 to 18D is a plan view of a bonding surface of a die structure according to some embodiments.

[0011] Figure 19 to Figure 20 is a cross-sectional view of an intermediate stage in the fabrication of a die structure according to some embodiments.

[0012] Figures 21 to 22D is a plan view of a bonding surface of a die structure according to some embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] Embodiments of the present disclosure provide various embodiments of an integrated circuit die and a die structure including an integrated circuit die, and methods for forming them. According to various embodiments of the first integrated circuit die, an interconnect structure is formed above the active device layer. Redistribution lines embedded in a passivation layer are formed above the interconnect structure. Then, the redistribution lines and the passivation layer are processed to be configured for direct bonding with the conductive components and dielectric layers of the second integrated circuit die. For example, a planarization process is used to remove the upper portions of the redistribution lines and the passivation layer, resulting in substantially flush upper surfaces of the redistribution lines and the passivation layer. The conductive components of the second integrated circuit die may be die connectors (e.g., bonding pads) or redistribution lines. The dielectric layer of the second integrated circuit die may be a passivation layer or a dielectric bonding layer. The first integrated circuit die and the second integrated circuit die may be directly bonded to each other without forming die connectors and dielectric bonding layers above the first integrated circuit die, and optionally, without forming die connectors and dielectric bonding layers above the second integrated circuit die. The integrated circuit die can be manufactured with fewer steps and higher yield, which can further make the integrated circuit die thinner, have greater bonding density (e.g., smaller bonding pitch), and have improved performance. Therefore, similar advantages are also achieved for the die structure incorporating the integrated circuit die.

[0016] Figures 1 to 10 is an integrated circuit die 100 (see Fig.10) is a cross-sectional view of an intermediate stage in the manufacture of an integrated circuit die 100. The integrated circuit die 100 may be a logic device (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a memory device (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management device (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a microelectromechanical system (MEMS) device, a signal processing device (e.g., a digital signal processing (DSP) die), a front-end device (e.g., an analog front-end (AFE) die), etc., or a combination thereof (e.g., a system on chip (SoC) die). The integrated circuit die 100 may be formed in a wafer, which may include different device regions that are segmented in subsequent steps to form a plurality of integrated circuit dies 100.

[0017] exist Figure 1 In the process, a semiconductor substrate 102 is formed or provided. The semiconductor substrate 102 may be a doped or undoped silicon substrate, or an active layer of a semiconductor on insulator (SOI) substrate. The semiconductor substrate 102 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The semiconductor substrate 102 has an active surface (e.g., a front side) sometimes referred to as a front side. Figure 1 the surface facing upward) and the inactive surface sometimes called the backside (e.g. Figure 1 The semiconductor substrate 102 may be a semiconductor substrate 104 that is ...

[0018] An interconnect structure 104 is formed over the active surface of the semiconductor substrate 102. The interconnect structure 104 interconnects the devices of the semiconductor substrate 102 to form an integrated circuit. The interconnect structure 104 may be formed in a suitable back-end-of-line (BEOL) process. The interconnect structure 104 may include one or more dielectric layers and corresponding metallization patterns in the dielectric layers. Acceptable dielectric materials for the dielectric layers include: oxides, such as silicon oxide, aluminum oxide, etc.; nitrides, such as silicon nitride, silicon oxynitride; combinations thereof; etc. The dielectric layer may be formed of a low-k (LK) dielectric material such as carbon-doped silicon oxide, an extremely low-k (LK) dielectric material such as porous carbon-doped silicon oxide, etc. Other acceptable dielectric materials may be utilized. The metallization pattern may include conductive vias and / or wires to interconnect the devices of the semiconductor substrate 102. The metallization pattern may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, etc. The metallization pattern may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc.

[0019] Contact pads 106 are formed at the front side of the integrated circuit die 100. The contact pads 106 may be pads, conductive pillars, etc. that make external connections. The contact pads 106 may be located in and / or on the interconnect structure 104. For example, the contact pads 106 may be part of an upper metallization pattern of the interconnect structure 104. The contact pads 106 may be formed of a metal, such as copper, aluminum, copper alloys, combinations thereof, etc., which may be formed, for example, by plating, etc. In some embodiments, the contact pads 106 are part of an upper metallization layer of the interconnect structure 104 and are formed similarly as described with respect to other metallization layers of the interconnect structure 104.

[0020] The dielectric layer 108 is located at the front side of the integrated circuit die 100. The dielectric layer 108 can be located in and / or on the interconnect structure 104. For example, the dielectric layer 108 can be an upper dielectric layer of the interconnect structure 104. The dielectric layer 108 laterally surrounds the contact pad 106. The dielectric layer 108 can be an oxide, a nitride, a polymer, etc. or a combination thereof. The dielectric layer 108 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc.

[0021] In some embodiments (not separately shown), the integrated circuit die 100 is a stacked device including a plurality of semiconductor substrates 102. For example, the integrated circuit die 100 may be a memory device including a plurality of memory dies, such as a hybrid memory multidimensional cube (HMC) module, a high bandwidth memory (HBM) module, etc. In such embodiments, the integrated circuit die 100 includes a plurality of semiconductor substrates 102 interconnected by through substrate vias (TSVs) such as through silicon vias. Each of the semiconductor substrates 102 may (or may not) have an interconnect structure 104.

[0022] exist Figure 2 In the embodiment of the present invention, a passivation layer 114 is formed over the interconnect structure 104 (e.g., over the dielectric layer 108 and the contact pad 106). The passivation layer 114 can be formed of one or more acceptable dielectric materials, such as silicon nitride, silicon oxide, combinations thereof, etc. Other acceptable dielectric materials include polymers, such as polyimide, solder resist, polybenzoxazole (PBO), benzocyclobutene (BCB) based polymers, molding compounds, etc. The passivation layer 114 can be formed by deposition (e.g., CVD), spin coating, lamination, combinations thereof, etc. The passivation layer 114 can be formed to a maximum thickness, such as at to Furthermore, the passivation layer 114 may be planarized, such as by a chemical mechanical polishing (CMP) process.

[0023] An etch stop layer 112 is formed between the passivation layer 114 and the interconnect structure 104. The etch stop layer 112 may be formed of a dielectric material having a high etch selectivity relative to the etching of the passivation layer 114, such as silicon nitride, silicon carbonitride, silicon oxynitride, etc., which may be formed by any suitable deposition process, such as CVD, atomic layer deposition (ALD), etc. According to some embodiments, the etch stop layer 112 includes silicon carbonitride, and the passivation layer 114 includes silicon nitride.

[0024] exist Figure 3 , passive devices 116 are optionally formed on the passivation layer 114. The passive devices 116 may include capacitors, inductors, resistors, etc. The passive devices 116 are embedded passive devices and may be electrically coupled to the semiconductor substrate 102. In some embodiments, one or more of the passive devices 116 may have a metal-insulator-metal (MIM) structure including one or more metal layers and one or more insulating layers (not separately labeled). The integrated circuit die 100 may include any desired combination and number of the passive devices 116 shown.

[0025] exist Figure 4 , a passivation layer 118 is formed over the passive devices 116 (if present) and the passivation layer 114. The passivation layer 118 may be formed of one or more acceptable dielectric materials, such as silicon nitride, silicon oxide, combinations thereof, and the like. Other acceptable dielectric materials include polymers, such as polyimide, solder resist, PBO, BCB-based polymers, molding compounds, and the like. The passivation layer 118 may be formed by deposition (e.g., CVD), spin coating, lamination, combinations thereof, and the like. The passivation layer 118 may be formed to a maximum thickness and then planarized, such as by a CMP process. According to some embodiments, the passivation layer 118 includes the same or similar material as the passivation layer 114, such as silicon nitride.

[0026] exist Figure 5 , an opening 122 is patterned through the passivation layer 118, the passivation layer 114, and the etch stop layer 112, thereby exposing the contact pad 106. The opening 122 can be formed using acceptable photolithography and etching techniques. For example, a photoresist 120 can be formed and patterned above the passivation layer 118 to include an upper opening 122. The photoresist 120 can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist 120 corresponds to the contact pad 106. The patterning forms an opening 122 directly above the contact pad 106. The opening 122 can then extend through the various layers (e.g., the passivation layer 118, the passivation layer 114, and the etch stop layer 112) by one or more etching processes with appropriate etching selectivity to expose the contact pad 106. For example, a first dry etching process can be used to etch through the passivation layer 118, and a second dry etching process can be used to etch through the passivation layer 114. In embodiments where passive devices 116 are formed, openings 122 may be patterned around the passive devices 116 such that the openings 122 are disposed between adjacent passive devices 116 .

[0027] Figures 6 to 8 The formation of redistribution lines 124 (see Figure 8 ) steps. The redistribution line 124 may be formed as described below or using any suitable method. Figure 6 In the embodiment of the present invention, a seed layer 127 may be formed over the upper surface of the passivation layer 118 and in the opening 122 (e.g., over the contact pad 106). Optionally, before forming the seed layer 127, a liner layer 126 may be formed over the passivation layer 118. The liner layer 126 may be a diffusion barrier layer, an adhesion layer, or the like. For example, the liner layer 126 may be formed along the upper surface of the passivation layer 118 and formed in the opening 122 along the sidewalls of the passivation layer 118 and the passivation layer 114, the exposed surface of the etch stop layer 112, and the exposed upper surface of the contact pad 106. The liner layer 126 may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. In some embodiments, the seed layer 127 is a metal layer, which may be a single layer or a composite layer including a plurality of sublayers formed of different materials. For example, the seed layer 127 may include a copper layer (e.g., a titanium layer) over the liner layer 126. The seed layer 127 may be formed using, for example, physical vapor deposition (PVD) or the like.

[0028] exist Figure 7 In the embodiment, a photoresist 128 is formed and patterned on the liner layer 126 and the seed layer 127, similarly as described above in conjunction with the photoresist 120. The photoresist 128 may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist 128 corresponds to the redistribution line 124 (see FIG. 1 ) to be formed later. Figure 8). Patterning forms openings 129 through the photoresist 128 to expose the seed layer 127. As shown, some of the openings 129A can expose portions of the seed layer 127 that are located above the contact pads 106, and some of the openings 129B can expose portions of the seed layer 126 that extend parallel to the upper surface of the passivation layer 118. The openings 129B can be locations for redistribution lines 124 that connect to contact pads outside the cross-section shown, or the openings 129B can be locations for dummy redistribution lines 124B. For example, the dummy redistribution lines 124B help achieve benefits related to pattern density (e.g., consistency of pattern density) and / or subsequent bonding of the integrated circuit die 100 to another component.

[0029] exist Figure 8 127. Then, a conductive material 130 is formed in the opening 129 of the photoresist 128 and on the exposed portion of the seed layer 127. The conductive material 130 may be formed by plating, such as by electroplating, chemical plating, etc. The conductive material 130 may include a metal, such as copper, silver, cobalt, titanium, tungsten, aluminum, a combination thereof, etc. For example, the conductive material 130 may be copper, a copper-silver alloy, or a copper-cobalt alloy plated using the seed layer 127. Then, the photoresist 128 and the portions of the seed layer 127 and the pad layer 126 (if present) on which the conductive material 130 is not formed are removed. The photoresist 128 may be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist 128 is removed, one or more acceptable etching processes are used to remove the exposed portion of the seed layer 127, followed by removal of portions of the pad layer 126. An annealing process may be optionally implemented. The remaining portions of the seed layer 127 and the conductive material 130 (and the liner layer 126 , if present) form the redistribution lines 124 .

[0030] The redistribution line 124 has a trace portion 124T located on the top surface of the passivation layer 118 and extending along the top surface of the passivation layer 118. For example, the trace portion 124T is a conductive line extending longitudinally parallel to the main surface of the semiconductor substrate 102. Therefore, the redistribution line 124 extends along the semiconductor substrate 102 in a corresponding longitudinal direction. The trace portion 124T of the redistribution line 124 has a length (in its longitudinal direction) and a width (in a direction perpendicular to the longitudinal direction), wherein the length is greater than the width. The redistribution line 124 may also have one or more through-hole portions 124V physically and electrically coupled to the contact pad 106 in the corresponding opening 122 (through the passivation layer 118, the passivation layer 114, and the etch stop layer 112). The redistribution line 124 (e.g., the redistribution line 124A) may physically contact the contact pad 106. Some of the through-hole portions 124V may be used to electrically couple the passive device 116 to the device of the semiconductor substrate 102.

[0031] The redistribution line 124 can have any type of top surface, considering the application of the integrated circuit die to be formed. In the illustrated embodiment, the redistribution line 124 has a convex top surface, which can be formed when the tool used during the deposition of the conductive material 130 is lifted. In another embodiment, the redistribution line 124 can have a flat top surface, a concave top surface, a polygonal top surface, etc. In addition, the trace portion 124T can have any type of sidewalls, considering the application of the integrated circuit die 100 to be formed. In the illustrated embodiment, the trace portion 124T has sidewalls spaced apart with a tapered width that decreases in a direction extending away from the semiconductor substrate 102. In another embodiment, the trace portion 124T has substantially vertical sidewalls spaced apart with a constant width.

[0032] Furthermore, in some cross-sectional views, the redistribution line 124 includes a redistribution line 124A including a trace portion 124T and a via portion 124V, and a redistribution line 124B including only a trace portion 124T disposed above the upper surface of the passivation layer 118. In some embodiments, the trace portion 124T of the redistribution line 124B may have a greater height above the upper surface of the passivation layer 118 than the height of the trace portion 124T of the redistribution line 124A above the upper surface of the passivation layer 118. In other embodiments, the trace portions 124T of the redistribution lines 124A / 124B may have substantially similar heights. Furthermore, the trace portion 124T of the redistribution line 124B may be longer and wider than similar dimensions of the trace portion 124T of the redistribution line 124A.

[0033] exist Fig. 9 , a passivation layer 132 is formed over the redistribution line 124 and the passivation layer 118. The passivation layer 132 may be formed of one or more acceptable dielectric materials, such as silicon nitride, silicon oxide, combinations thereof, and the like. According to some embodiments, the passivation layer 132 includes a nitride layer 132A, an oxide layer 132B, and a bulk oxide layer 132C. Other acceptable dielectric materials include polymers, such as polyimide, solder resist, polybenzoxazole (PBO), benzocyclobutene (BCB)-based polymers, molding compounds, and the like. Each of the layers of the passivation layer 132 may be formed by deposition (e.g., CVD), spin coating, lamination, combinations thereof, and the like.

[0034] For example, the nitride layer 132A may include silicon nitride and be formed by a CVD process. In addition, the oxide layer 132B may include silicon oxide, such as undoped silicate glass (USG), and may be formed by a CVD process. In some embodiments, each of the nitride layer 132A and the oxide layer 132B is conformally deposited so that they substantially follow the curvature of the upper surface of the redistribution line 124 and the passivation layer 118. In addition, the bulk oxide layer 132C may be formed by a spin coating process, and optionally, followed by another USG deposition.

[0035] The passivation layer 132 may be formed to an initial thickness large enough to cover the trace portions 124T of the redistribution lines 124. In addition, an upper surface of the passivation layer 132 may have a low degree of planarity over the passivation layer 118 and the redistribution lines 124.

[0036] exist Fig.10 In the embodiment, after the passivation layer 132 is deposited, the passivation layer 132 is planarized, such as by a CMP process. During the planarization process, the upper surface of the passivation layer 132 (e.g., the bulk oxide layer 132C) is reduced to expose the oxide layer 132B, then the nitride layer 132A, then the trace portion 124T of the redistribution line 124B, and then the trace portion 124T of the redistribution line 124A (e.g., in embodiments where the trace portion 124T of the redistribution line 124B has a greater height).

[0037] As shown, the planarization process can continue to remove the upper portion of the redistribution line 124. As discussed above, the upper portion of the redistribution line 124 can have a low flatness (e.g., a curved upper surface), and the planarization process can continue until the trace portion 124T of the redistribution line 124 is flush with its corresponding sidewall. Therefore, the redistribution line 124 can be flush with the passivation layer 132 (e.g., the bulk oxide layer 132C and the sidewall portions of the nitride layer 132A and the oxide layer 132B). In addition, the remaining portion of the passivation layer 132 remains disposed between the trace portions 124T of adjacent redistribution lines 124.

[0038] According to various embodiments, the integrated circuit die 100 may be attached in a die structure (and subsequently incorporated into a semiconductor package). Prior to attachment, the integrated circuit die 100 may be singulated or remain in wafer form. The integrated circuit die 100 may be used as a bottom die or a top die within a die structure. As discussed in more detail below, the trace portions 124T of the redistribution lines 124 may be used for direct bonding.

[0039] Figures 11 to 14 is an integrated circuit die 200 (see Fig.14) is a cross-sectional view of an intermediate stage in the manufacture of an integrated circuit die 200. The integrated circuit die 200 may be a logic device (e.g., a CPU, a GPU, a microcontroller, etc.), a memory device (e.g., a DRAM die, an SRAM die, etc.), a power management device (e.g., a PMIC die), an RF device, a sensor device, a MEMS device, a signal processing device (e.g., a DSP die), a front-end device (e.g., an AFE die), etc., or a combination thereof (e.g., a SoC die). The integrated circuit die 200 may be formed in a wafer, which may include different device regions that are segmented in subsequent steps to form a plurality of integrated circuit dies 200.

[0040] As discussed in more detail below, the integrated circuit die 200 may then be bonded to the integrated circuit die 100 (see Fig.10 and Figures 15 to 18D ). The integrated circuit die 200 is similarly combined with the integrated circuit die 100 as above (see Figures 1 to 10 ) is formed as described below, unless otherwise specified below. It should be noted that the same reference numerals denote the same components between the integrated circuit dies 100 / 200. According to various embodiments, the following forms a passivation layer 132 (see Fig. 9 ) thereafter, the processing of the integrated circuit die 200 may be different from the processing of the integrated circuit die 100.

[0041] exist Fig.11 In the formation Fig. 9 After the structure of the passivation layer 132, the passivation layer 132 may be planarized, such as by a CMP process, similarly as above combined Fig.10 For example, the planarization process is performed on the bulk oxide layer 132C and is completed before reaching the oxide layer 132B, the nitride layer 132A, or the redistribution line 124. Due to the planarization, the upper surface of the passivation layer 132 can have a high degree of planarity.

[0042] Although the thickness of the passivation layer 132 is reduced during the planarization process, after the planarization process is completed, the remaining portion of the passivation layer 132 covers the redistribution line 124. Therefore, after planarization, the passivation layer 132 of the integrated circuit die 200 may have a thickness greater than that of the passivation layer 132 of the integrated circuit die 100 (see FIG. Fig.10 ) has a large thickness. The flat upper surface of the passivation layer 132 extends continuously in the region above the redistribution lines 124 and between the redistribution lines 124. The entirety of each corresponding region between the trace portions 124T of the redistribution lines 124 may be filled with the passivation layer 132. The redistribution lines 124 are spaced apart from subsequently formed passive devices by the portions of the passivation layer 132 located above the redistribution lines 124.

[0043] After the planarization process, an etch stop layer 134 may be formed on the passivation layer 132. The etch stop layer 134 will be located between the passivation layer 132 and the subsequently formed upper passivation layer. The etch stop layer 134 may be formed of a dielectric material having a high etch selectivity relative to the etching of the upper passivation layer, such as silicon nitride, silicon oxynitride, etc., which may be formed by any suitable deposition process, such as CVD, ALD, etc.

[0044] Optionally, passive devices (not specifically shown) are formed on the etch stop layer 134. Passive devices may include capacitors, inductors, resistors, etc. Passive devices are embedded passive devices and devices that can be electrically coupled to the semiconductor substrate 102. Passive devices can be similarly formed as described above in conjunction with passive devices 116. In some embodiments, one or more of the passive devices may have a metal-insulator-metal (MIM) structure including one or more metal layers and one or more insulating layers. The integrated circuit die 200 may include any desired combination and quantity of these passive devices.

[0045] exist Fig.12 In the embodiment of the present invention, a dielectric layer 152 is formed over the etch stop layer 134 (and over the passive devices, if present). The dielectric layer 152 may be formed of: an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), an oxide based on tetraethyl orthosilicate (TEOS) (e.g., low-temperature TEOS), etc.; a nitride such as silicon nitride, etc.; a combination thereof; etc. The dielectric layer 152 may be formed, for example, by CVD, ALD, etc. For example, the dielectric layer 152 may be formed of silicon oxide deposited using TEOS. The dielectric material of the dielectric layer 152 may be different from the dielectric material of the passivation layer 132. For example, the dielectric layer 152 may be formed of silicon oxide, while the passivation layer 132 may be formed of silicon nitride. Similar to the passivation layer 132, the dielectric layer 152 may be thick and flat, which may provide a large space on which the passive devices may be formed in subsequent processing.

[0046] An etch stop layer 154 may be formed on the dielectric layer 152. The etch stop layer 154 will be located between the dielectric layer 152 and the subsequently formed upper dielectric layer. The etch stop layer 154 may be formed of a dielectric material having a high etch selectivity relative to the etching of the upper passivation layer, such as silicon nitride (e.g., low temperature silicon nitride), silicon oxynitride, etc., which may be formed by any suitable deposition process, such as CVD, ALD, etc.

[0047] Optionally, passive devices (not specifically shown) are formed on the etch stop layer 154, similarly as described above. Passive devices 156 may include capacitors, inductors, resistors, etc. Passive devices 156 are embedded passive devices and can be electrically coupled to devices of the semiconductor substrate 102. The passive devices can be any of those previously described. The integrated circuit die 200 can include any desired combination and quantity of these passive devices. As previously described in more detail, one or more of the passive devices can have a MIM structure including one or more metal layers and an insulating layer.

[0048] In addition, a dielectric layer 158 may be formed over the etch stop layer 154 (and over the passive devices, if present). The dielectric layer 158 may be formed of: an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), an oxide based on tetraethyl orthosilicate (TEOS) (e.g., low-temperature TEOS), etc.; a nitride, such as silicon nitride, etc.; a combination thereof; etc. The dielectric layer 158 may be formed, for example, by CVD, ALD, etc. For example, the dielectric layer 158 may be formed of silicon oxide deposited using TEOS. The dielectric layer 158 may also be referred to as a dielectric bonding layer. In some embodiments (not specifically shown), the dielectric layer 158 may include, for example, a capping layer of undoped silicate glass (USG).

[0049] exist Fig.13 In the embodiment of the present invention, die connection openings (including via openings 160 and bond pad openings 162) are patterned in dielectric layer 158, etch stop layer 154, dielectric layer 152, etch stop layer 134, and passivation layer 132 to expose redistribution line 124. The die connection openings may be formed by acceptable photolithography and etching techniques.

[0050] The die connector openings may be formed by a damascene process. In this embodiment, the die connector openings are formed by a single damascene process. In the single damascene process, the bond pad openings 162 are formed through the dielectric layer 158 and the etch stop layer 154, while the via openings 160 are formed through the dielectric layer 152, the etch stop layer 134, and the passivation layer 132. The via openings 160 expose the redistribution lines 124. In another embodiment, the etch stop layer 154 and the dielectric layer 158 are omitted, and the die connector openings are formed by a dual damascene process. In the dual damascene process, the bond pad openings 162 are formed through the upper portion of the dielectric layer 152, while the via openings 160 are formed through the lower portion of the dielectric layer 152, the etch stop layer 134, and the passivation layer 132.

[0051] exist Fig.14In the embodiment of the present invention, a die connector 164 (including a through hole 166 and a bonding pad 168) is formed in the die connector opening (including a through hole opening 160 and a bonding pad opening 162, respectively). The die connector 164 can be formed of a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, a combination thereof, etc., which can be formed by, for example, plating, etc. Then, an excess portion of the conductive material is removed, which is located above the top surface of the dielectric layer 158. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. can be utilized. After the planarization process, the top surface of the die connector 164 can be coplanar with the top surface of the dielectric layer 158 (within process variations). The die connector 164 is physically and electrically coupled to the redistribution line 124. The die connector 164 can physically contact the trace portion 124T of the redistribution line 124. Some of the die connections 164 (eg, vias 166 ) may be used to electrically couple the passive devices 136 , 156 to devices of the semiconductor substrate 102 .

[0052] The bond pads 168 of the die connect 164 are disposed in the dielectric layer 158, while the vias 166 of the die connect 164 are disposed in the dielectric layer 152 and the passivation layer 132. The vias 166 extend through the portion of the passivation layer 132 that is located above the redistribution line 124.

[0053] As discussed above, the integrated circuit die 200 can be bonded to the integrated circuit die 100 to form a die structure (and subsequently incorporated into a semiconductor package). Similarly as described above in conjunction with the integrated circuit die 100, the integrated circuit die 200 can be singulated or remain in wafer form. The integrated circuit die 200 can be used as a bottom die or a top die. As discussed in more detail below, the bond pads 168 of the integrated circuit die 200 can be directly bonded to the redistribution lines 124 of the integrated circuit die 100.

[0054] Fig.153 is a cross-sectional view of a die structure 300 according to some embodiments. The die structure 300 is a stack of integrated circuit dies (including a first integrated circuit die 100 and a second integrated circuit die 200). The die structure 300 is formed by bonding the integrated circuit dies 100 / 200. Some of the redistribution lines 124 of the first integrated circuit die 100 (e.g., trace portions 124T) can be coupled (e.g., directly bonded) to some of the die connectors 164 of the second integrated circuit die 200 (e.g., bonding pads 168). In some embodiments, the first integrated circuit die 100 is in wafer form, and the second integrated circuit die 200 can be separated from its wafer before being attached to the first integrated circuit die 100, or vice versa. In additional embodiments, two of the integrated circuit dies 100 / 200 can remain in wafer form during attachment. In further embodiments, one or both of the integrated circuit dies 100 / 200 can be separated before attachment and included in the reconstructed wafer.

[0055] As an example of a bonding process, the second integrated circuit die 200 can be bonded to the first integrated circuit die 100 by direct bonding. For example, the bonding interface between the integrated circuit die 100 / 200 may include metal-to-metal bonding and dielectric-to-dielectric bonding. In addition, some portions of the bonding interface may be metal-to-dielectric. According to various embodiments, the dielectric layer 158 of the second integrated circuit die 200 is directly bonded to the passivation layer 132 of the first integrated circuit die 100 by dielectric-to-dielectric bonding without using any adhesive material (e.g., a die attach film). The die connector 164 of the second integrated circuit die 200 is directly bonded to the redistribution line 124 of the first integrated circuit die 100 by metal-to-metal bonding without using any eutectic material (e.g., solder).

[0056] The bonding may include pre-bonding and annealing. During pre-bonding, a small pressure is applied to press the second integrated circuit die 200 against the first integrated circuit die 100. The pre-bonding is performed at a low temperature (such as about room temperature), and after the pre-bonding, the dielectric layer 158 of the second integrated circuit die 200 is bonded to the passivation layer 132 of the first integrated circuit die 100. The bond strength is then improved in a subsequent annealing step, wherein the passivation layer 132 and the redistribution line 124 of the first integrated circuit die 100 and the dielectric layer 158 and the die connector 164 of the second integrated circuit die 200 are annealed.

[0057] After annealing, a direct bond, such as a fusion bond, is formed, bonding the passivation layer 132 of the first integrated circuit die 100 to the dielectric layer 158 of the second integrated circuit die 200. For example, the bond may be a covalent bond between the material of the passivation layer 132 of the first integrated circuit die 100 and the material of the dielectric layer 158 of the second integrated circuit die 200.

[0058] In addition, the redistribution lines 124 of the first integrated circuit die 100 can be connected to the die connectors 164 of the second integrated circuit die 200 in a one-to-one correspondence or any suitable ratio. The redistribution lines 124 of the first integrated circuit die 100 and the die connectors 164 of the second integrated circuit die 200 can be in physical contact after pre-bonding, or can expand during annealing to make physical contact. In addition, during annealing, the material of the redistribution lines 124 of the first integrated circuit die 100 (e.g., copper or an alloy as described above) and the material of the die connectors 164 of the second integrated circuit die 200 (e.g., copper) mix so that metal-to-metal bonding is also formed.

[0059] Thus, the bonding interface includes dielectric-to-dielectric bonding and metal-to-metal bonding. Dielectric-to-dielectric bonding can include oxide-to-oxide bonding (e.g., O-Si-O), nitride-to-nitride bonding (e.g., N-Si-N), and oxide-to-nitride bonding (e.g., O-Si-N). The multiple bonding is due to the dielectric layer 158 (e.g., including oxide and / or nitride) bonding to portions of the bulk oxide layer 132C and (in some cases) portions of the nitride layer 132A and oxide layer 132B. In general, the redistribution lines 124, the passivation layer 132, the die connector 164, and the dielectric layer 158 can be referred to as a bonding area.

[0060] The metal-to-dielectric region of the bonding interface may include portions of the redistribution lines 124 of the first integrated circuit die 100 that are in physical contact with the dielectric layer 158 of the second integrated circuit die 200. The number and proportion of these interface regions may be prevalent, as the redistribution lines 124 constitute a larger proportion than the die connectors 164 of the bonding interface. In some embodiments, the metal-to-dielectric interface region may include, for example, chemical bonding between metal atoms of the redistribution lines 124 and oxygen and / or nitrogen atoms of the dielectric layer 158. Similarly, some of the die connectors 164 may overlap with the passivation layer 132, thereby forming similar metal-to-dielectric interface regions.

[0061] Fig.16The die structure 300 is shown as further processing that the die structure 300 may undergo in preparation for incorporating the die structure 300 into a semiconductor package. For example, one of the semiconductor substrates 102 may be thinned or removed, and a via 170 may be formed or exposed (if already present). As shown, the via 170 may be electrically connected to the device layer and / or the interconnect structure 104. In some embodiments, a dielectric layer 172 and a redistribution line 174 are formed over the via 170. The redistribution line 174 may include a metal pad 176, and one or more passivation layers 178 may be formed over the metal pad 176.

[0062] As shown, a conductive connector is formed over the metal pad 176. For example, an opening may be formed through the passivation layer 178 to expose the metal pad 176, and a dielectric material 180 may be formed over the passivation layer 178 and the metal pad 176. The dielectric material 180 may include a nitride or a polymer, such as a polyimide, a solder resist, a polybenzoxazole (PBO), a benzocyclobutene (BCB)-based polymer, a molding compound, and the like. An opening is then formed through the dielectric material 180 to re-expose the metal pad 176, and then a conductive connector is formed over the exposed metal pad 176. In some embodiments, the conductive connector includes an under-bump metal (UBM) 182 on which a solder bump 184 is formed. The die structure 300 may then be singulated from the wafer and attached to a carrier substrate or otherwise incorporated into a semiconductor package.

[0063] Fig.17A plan view (e.g., a top view layout) of a first integrated circuit die 100 and a second integrated circuit die 200 of a die structure 300 according to some embodiments is shown. In particular, a bonding surface of the integrated circuit die 100 / 200 is shown. The bonding surface of the first integrated circuit die 100 includes a redistribution line 124 (e.g., a trace portion 124T), which is embedded in the passivation layer 132 (e.g., the nitride layer 132A, the oxide layer 132B, and the bulk oxide layer 132C). The bonding surface of the second integrated circuit die 200 includes a die connector 164 (e.g., a bonding pad 168), which is embedded in the dielectric layer 158. Although the redistribution line 124 is shown as having a rectangular shape, the redistribution line 124 can have any suitable shape, such as an elliptical or rounded rectangle. Because the redistribution lines 124 include electrically connected redistribution lines 124A, some of the trace portions 124T will have the shape and pattern of traces in the circuit, and the dummy redistribution lines 124B may also have the shape or trace pattern described above. Similarly, although the die connector 164 is shown as having a square shape, the die connector 164 may have any suitable shape, such as a circle or a rounded square. In some embodiments, the width of the redistribution line 124 is substantially the same as the width (e.g., side length or diameter) of the die connector 164. However, the length of the redistribution line 124 may be greater than these other dimensions.

[0064] In some embodiments, the bonding surface of the first integrated circuit die 100 can have a redistribution line 124 pattern density ranging from 50% to 80%. As discussed above, the redistribution lines 124 and the die connectors 164 can have a one-to-one correspondence. In some embodiments, more than one die connector 164 can correspond to some or all of the redistribution lines 124. For example, one or more of the redistribution lines 124 can be bonded to two or more die connectors 164.

[0065] 18A to 18D An exemplary bonding interface layout is shown after attaching the integrated circuit die 100 / 200 to each other. The embodiments described above may be applicable to these exemplary layouts. Furthermore, the embodiment die structure 300 may include one or more of the provided layouts in any suitable combination.

[0066] Fig.18A An exemplary layout is provided in which the die connector 164 has a width (or diameter) substantially the same as the width of the redistribution line 124. Thus, substantially all of the surface of the die connector 164 may be in physical contact with the surface of the corresponding redistribution line 124. Furthermore, the remaining portion of the surface of the redistribution line 124 may be in physical contact with the dielectric layer 158.

[0067] Fig.18BAn exemplary layout is provided in which the die connector 164 has a width that is greater than the width of the redistribution line 124. Thus, the die connector 164 can overextend one or more edges of the corresponding redistribution line 124 and be in physical contact with any number of the passivation layers 132. Additionally, the remainder of the surface of the redistribution line 124 can be in physical contact with the dielectric layer 158, similarly as described above.

[0068] Fig. 18C An exemplary layout is provided in which the die connector 164 has a width that is less than the width of the redistribution line 124. Thus, the redistribution line 124 may overextend all edges of the corresponding die connector 164. In addition, the remaining portion of the surface of the redistribution line 124 that is in physical contact with the dielectric layer 158 may be greater than the bonding Fig.18A Similar to the rest of the description.

[0069] Fig.18D An exemplary layout is provided in which the die connector 164 is not aligned with the redistribution line 124. The die connector 164 and the redistribution line 124 may have the above combination. 18A to 18C Thus, the die connector 164 and the corresponding redistribution line 124 may over-extend each other, similarly as described above in conjunction with Fig. 18C Thus, the die connector 164 may be in physical contact with any number of the passivation layers 132 , and the redistribution line 124 may be in physical contact with the dielectric layer 158 .

[0070] Fig.19 4 is a cross-sectional view of a die structure 400 according to some embodiments. The die structure 400 is a stack of integrated circuit dies (including a first integrated circuit die 100A and a second integrated circuit die 100B). The die structure 400 is formed by bonding the integrated circuit dies 100 to each other. Some of the redistribution lines 124 of the first integrated circuit die 100A (e.g., trace portions 124T) can be coupled (e.g., directly bonded) to some of the redistribution lines 124 of the second integrated circuit die 100B (e.g., trace portions 124T). In some embodiments, the first integrated circuit die 100A is in wafer form, and the second integrated circuit die 100B can be separated from its wafer before being attached to the first integrated circuit die 100A, or vice versa. In additional embodiments, two of the integrated circuit dies 100 can remain in wafer form during attachment. In further embodiments, one or both of the integrated circuit dies 100 can be separated before attachment and included in the reconstructed wafer.

[0071] As an example of a bonding process, the second integrated circuit die 100B can be bonded to the first integrated circuit die 100A by direct bonding. For example, the bonding interface between the integrated circuit dies 100 may include metal-to-metal bonding and dielectric-to-dielectric bonding. In addition, some portions of the bonding interface may be metal-to-dielectric. According to various embodiments, the passivation layer 132 of the second integrated circuit die 100B is directly bonded to the passivation layer 132 of the first integrated circuit die 100A by dielectric-to-dielectric bonding without using any adhesive material (e.g., a die attach film). The redistribution line 124 of the second integrated circuit die 100B is directly bonded to the redistribution line 124 of the first integrated circuit die 100A by metal-to-metal bonding without using any eutectic material (e.g., solder).

[0072] The bonding may include pre-bonding and annealing. During pre-bonding, a small pressure is applied to press the second integrated circuit die 100B against the first integrated circuit die 100A. The pre-bonding is performed at a low temperature (such as about room temperature), and after the pre-bonding, the passivation layer 132 of the second integrated circuit die 100B is bonded to the passivation layer 132 of the first integrated circuit die 100A. The bonding strength is then improved in a subsequent annealing step, wherein the passivation layer 132 and the redistribution line 124 of the first integrated circuit die 100A and the passivation layer 132 and the redistribution line 124 of the second integrated circuit die 100B are annealed.

[0073] After annealing, a direct bond, such as a fusion bond, is formed, bonding the passivation layer 132 of the first integrated circuit die 100A to the passivation layer 132 of the second integrated circuit die 100B. For example, the bond may be a covalent bond between materials of the respective passivation layers 132, which may include the same, similar, or different layers.

[0074] In addition, the redistribution lines 124 of the first integrated circuit die 100A can be connected to the redistribution lines 124 of the second integrated circuit die 100B in a one-to-one correspondence or any suitable ratio. The corresponding redistribution lines 124 of the integrated circuit die 100 can be in physical contact after pre-bonding, or can expand during annealing to make physical contact. In addition, during annealing, the materials of the corresponding redistribution lines 124 (e.g., copper or alloys as described above) mix so that metal-to-metal bonding is also formed. It should be noted that the corresponding redistribution lines 124 can include the same, similar or different materials.

[0075] Therefore, the bonding interface includes dielectric to dielectric bonding and metal to metal bonding. Dielectric to dielectric bonding can include oxide to oxide bonding (e.g., O-Si-O), nitride to nitride bonding (e.g., N-Si-N), and oxide to nitride bonding (e.g., O-Si-N). This multiple bonding is due to the corresponding passivation layers 132 including oxide and nitride layers being bonded to each other. This multiple bonding is also due to the corresponding redistribution lines 124 having different sizes and shapes and / or being misaligned with each other. In general, the redistribution lines 124, the passivation layer 132, the die connector 164, and the dielectric layer 158 can be referred to as bonding areas.

[0076] The metal-to-dielectric regions of the bonding interface may include portions of the redistribution lines 124 of the first integrated circuit die 100A that are in physical contact with the passivation layer 132 of the second integrated circuit die 100B and portions of the redistribution lines 124 of the second integrated circuit die 100B that are in physical contact with the passivation layer 132 of the first integrated circuit die 100A. The number and proportion of these interface regions depends on the degree to which the corresponding redistribution lines 124 differ in size, shape, and / or alignment. In some embodiments, the metal-to-dielectric interface regions may include, for example, chemical bonding between metal atoms of the redistribution lines 124 of one of the integrated circuit dies 100 and oxygen and / or nitrogen atoms of the corresponding passivation layer 132 of another of the integrated circuit dies 100.

[0077] Fig. 20 The die structure 400 is shown as further processing that the die structure 400 may undergo in preparation for incorporating the die structure 400 into a semiconductor package. For example, one of the semiconductor substrates 102 may be thinned or removed, and a via 170 may be formed or exposed (if already present). As shown, the via 170 may be electrically connected to the device layer and / or the interconnect structure 104. In some embodiments, a dielectric layer 172 and a redistribution line 174 are formed over the via 170. The redistribution line 174 may include a metal pad 176, and one or more passivation layers 178 may be formed over the metal pad 176.

[0078] As shown, a conductive connector is formed over metal pad 178. For example, an opening may be formed through passivation layer 178 to expose metal pad 176, and dielectric material 180 may be formed over passivation layer 178 and metal pad 176. Dielectric material 180 may include a nitride or a polymer, such as polyimide, solder resist, polybenzoxazole (PBO), a benzocyclobutene (BCB)-based polymer, a molding compound, etc. An opening is then formed through dielectric material 180 to re-expose metal pad 176, and then a conductive connector is formed over the exposed metal pad 176. In some embodiments, the conductive connector includes an under-bump metal (UBM) 182 on which solder bumps 184 are formed. The die structure 400 may then be singulated from the wafer and attached to a carrier substrate or otherwise incorporated into a semiconductor package.

[0079] Fig.21 A plan view (e.g., a top view layout) of a first integrated circuit die 100A and a second integrated circuit die 100B of a die structure 400 according to some embodiments is shown. In particular, the bonding surfaces of the integrated circuit die 100 are shown. Both bonding surfaces of the integrated circuit die 100 include redistribution lines 124 (e.g., trace portions 124T) embedded in a passivation layer 132 (e.g., nitride layer 132A, oxide layer 132B, and bulk oxide layer 132C). Although the plan view shows the redistribution lines 124 as having a rectangular shape, these features can have any suitable shape, such as those discussed above in conjunction with the die structure 300.

[0080] In some embodiments, the bonding surface of each of the integrated circuit dies 100 may have a redistribution line 124 pattern density ranging from 50% to 80%. In particular, the bonding surface of the first integrated circuit die 100A may have a greater pattern density than the second integrated circuit die 100B, or vice versa. The integrated circuit dies 100 may have substantially the same pattern density, or may be different within the limits of the range described above. As discussed above, the corresponding redistribution lines 124 of the integrated circuit dies 100 may have a one-to-one correspondence. In some embodiments, any particular redistribution line 124 of the integrated circuit die 100 may be bonded to more than one redistribution line 124 of another integrated circuit die 100. Therefore, the bonding interface may include any variety of the above-mentioned interfaces, and the integrated circuit dies 100 have a substantially one-to-one correspondence or other relationship.

[0081] FIG. 22A to FIG. 22D Exemplary bonding interface layouts are shown after attaching the integrated circuit dies 100 to each other. The described embodiments may be applicable to these exemplary layouts. Furthermore, the embodiment die structure 400 may include one or more of the provided layouts in any suitable combination.

[0082] Fig.22A An exemplary layout is provided in which the corresponding redistribution lines 124 have substantially the same shape, size, and pattern. Therefore, substantially all surfaces of the corresponding redistribution lines 124 may be in physical contact with each other. Similarly, substantially all surfaces of the corresponding passivation layers 132 may be in physical contact with each other.

[0083] Fig. 22B Exemplary layouts are provided with corresponding redistribution lines 124 having different shapes, sizes, and / or patterns (eg, orientations). Thus, the redistribution lines 124 may overextend each other and physically contact any number of passivation layers 132 of other integrated circuit dies 100 .

[0084] Fig. 22C An exemplary layout is provided in which some of the redistribution lines 124 of any integrated circuit die 100 are directly bonded to more than one corresponding redistribution line 124 of another integrated circuit die 100. Thus, these redistribution lines 124 will overextend each other and physically contact some or all of the passivation layer 132 of another integrated circuit die 100, similarly as in the case of bonding Fig. 22B described.

[0085] Fig.22D An exemplary layout is provided in which corresponding redistribution lines 124 are not aligned with each other. The redistribution lines 124 may have the above combination FIG. 22A to FIG. 22C Thus, corresponding redistribution lines 124 may over-extend with respect to each other, similarly as described above in conjunction with Fig. 22B and Fig. 22C Thus, the redistribution line 124 can be in physical contact with any number of passivation layers 132 of another integrated circuit die 100 .

[0086] Embodiments can achieve advantages. In particular, the disclosed embodiments provide an integrated circuit die 100 that can be manufactured with fewer steps and with a smaller thickness due to the use of redistribution lines 124 for direct bonding. In addition, a die structure 300 / 400 including one or more integrated circuit dies 100 can also be assembled to have a smaller thickness. In addition, the pattern density of the redistribution lines 124 can be greater than the pattern density of the die connectors 164 (e.g., bonding pads 168).

[0087] In an embodiment, a method includes: forming an active device above a semiconductor substrate; forming an interconnect structure above the semiconductor substrate, the interconnect structure including a contact pad embedded in a dielectric layer; forming a first passivation layer above the interconnect structure; forming a first opening through the first passivation layer to expose the contact pad; depositing a seed layer above the first passivation layer and in the first opening; forming a sacrificial material above the seed layer; patterning the sacrificial material to reform the first opening and to form a second opening; depositing a conductive material to form a first redistribution line in the first opening and a second redistribution line in the second opening; removing the sacrificial material; and attaching an integrated circuit die to the first redistribution line and the second redistribution line. In another embodiment, the method further includes: forming a second passivation layer above the first redistribution line and the second redistribution line after removing the sacrificial material; and planarizing the second passivation layer to be flush with the first redistribution line and the second redistribution line. In another embodiment, planarizing the second passivation layer includes removing upper portions of the first redistribution line and the second redistribution line. In another embodiment, the second passivation layer includes: a nitride layer along the first passivation layer, the first redistribution line, and the second redistribution line; an oxide layer located above the nitride layer; and a bulk oxide layer located above the oxide layer. In another embodiment, after planarizing the second passivation layer, it includes: making the upper surface of the first redistribution line and the second redistribution line flush with the upper surface of the nitride layer, the oxide layer, and the bulk oxide layer. In another embodiment, attaching the integrated circuit die includes: directly bonding the first die connector of the integrated circuit die to the first redistribution line; and directly bonding the second die connector of the integrated circuit die to the second redistribution line. In another embodiment, attaching the integrated circuit die includes directly bonding the third redistribution line of the integrated circuit die to the first redistribution line and the second redistribution line. In another embodiment, the second redistribution line is a dummy redistribution line. In another embodiment, the method further includes: depositing a barrier layer along the first passivation layer and the contact pad before depositing the seed layer.

[0088] In an embodiment, a semiconductor device comprises: a first integrated circuit die, comprising: a first interconnect structure located above the device layer, the first interconnect structure comprising a first contact pad; a first passivation layer located above the first interconnect structure; a second passivation layer located above the first passivation layer; and a first redistribution line extending from an upper surface of the second passivation layer to the first contact pad; and a second integrated circuit die attached to the first integrated circuit die, a conductive component of the second integrated circuit die directly bonded to the first redistribution line, and a dielectric layer of the second integrated circuit die directly bonded to the second passivation layer. In another embodiment, the first integrated circuit die also includes a second redistribution line extending from an upper surface of the second passivation layer to an upper surface of the first passivation layer. In another embodiment, the conductive component is a third redistribution line. In another embodiment, the second integrated circuit die also includes a second interconnect structure located above the third redistribution line and electrically connected to the third redistribution line, and wherein the second interconnect structure includes a second contact pad in physical contact with the third redistribution line. In another embodiment, the conductive feature is a die connector including a bonding pad and a via, and wherein the second integrated circuit die further comprises: a third redistribution line located above and electrically connected to the via, a second interconnect structure located above and electrically connected to the third redistribution line, and a second device layer located above and electrically connected to the second interconnect structure. In another embodiment, the first passivation layer comprises a lower passivation layer and an upper passivation layer, and wherein the first integrated circuit die further comprises a passive device disposed along an interface between the lower passivation layer and the upper passivation layer.

[0089] In an embodiment, a semiconductor device includes: a first integrated circuit including a first device layer and a first interconnect structure; a second integrated circuit electrically connected to the first integrated circuit, the second integrated circuit including a second device layer and a second interconnect structure; and a bonding area between the first interconnect structure and the second interconnect structure, the bonding area including: a first passivation layer adjacent to the first interconnect structure; a first redistribution line embedded in the first passivation layer; a second passivation layer adjacent to the second interconnect structure, the second passivation layer bonded to the first passivation layer; and a second redistribution line embedded in the second passivation layer, the second redistribution line bonded to the first redistribution line. In another embodiment, the first redistribution line includes a first active redistribution line and a first dummy redistribution line, wherein the second redistribution line includes a second active redistribution line and a second dummy redistribution line, and wherein the first dummy redistribution line and the second dummy redistribution line are electrically isolated from the first integrated circuit and the second integrated circuit. In another embodiment, the first active redistribution line is directly bonded to the second active redistribution line, and wherein the first dummy redistribution line is directly bonded to the second dummy redistribution line. In another embodiment, the first redistribution lines further include third active redistribution lines, and wherein the third active redistribution lines are directly bonded to the second active redistribution lines. In another embodiment, some of the first redistribution lines are in physical contact with the second passivation layer, and wherein some of the second redistribution lines are in physical contact with the first passivation layer.

[0090] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming active devices over the semiconductor substrate; forming an interconnect structure over the semiconductor substrate, the interconnect structure comprising a contact pad embedded in a dielectric layer; forming a first passivation layer over the interconnect structure; forming a first opening through the first passivation layer to expose the contact pad; depositing a seed layer over the first passivation layer and in the first opening; forming a sacrificial material over the seed layer; patterning the sacrificial material to reform the first opening and to form a second opening; depositing a conductive material to form a first redistribution line in the first opening and a second redistribution line in the second opening; removing the sacrificial material; as well as An integrated circuit die is attached to the first redistribution line and the second redistribution line.

2. The method according to claim 1, further comprising: forming a second passivation layer over the first redistribution line and the second redistribution line after removing the sacrificial material; as well as The second passivation layer is planarized to be flush with the first and second redistribution lines.

3. The method according to claim 2, wherein: Planarizing the second passivation layer includes removing upper portions of the first and second redistribution lines.

4. The method according to claim 3, wherein: The second passivation layer comprises: a nitride layer along the first passivation layer, the first redistribution line, and the second redistribution line; an oxide layer located above the nitride layer; and A bulk oxide layer is located above the oxide layer.

5. The method according to claim 4, wherein: After planarizing the second passivation layer, the method includes making upper surfaces of the first redistribution line and the second redistribution line flush with upper surfaces of the nitride layer, the oxide layer, and the bulk oxide layer.

6. The method according to claim 1, wherein: Attaching the integrated circuit die comprises: directly bonding a first die connect of the integrated circuit die to the first redistribution line; and A second die connector of the integrated circuit die is directly bonded to the second redistribution line.

7. The method according to claim 1, wherein: Attaching the integrated circuit die includes directly bonding third redistribution lines of the integrated circuit die to the first and second redistribution lines.

8. The method according to claim 1, wherein: The second redistribution line is a dummy redistribution line.

9. A semiconductor device comprising: A first integrated circuit die comprising: a first interconnect structure located above the device layer, the first interconnect structure comprising a first contact pad; a first passivation layer, located above the first interconnect structure; a second passivation layer located above the first passivation layer; and a first redistribution line extending from an upper surface of the second passivation layer to the first contact pad; and A second integrated circuit die is attached to the first integrated circuit die, a conductive feature of the second integrated circuit die is directly bonded to the first redistribution line, and a dielectric layer of the second integrated circuit die is directly bonded to the second passivation layer.

10. A semiconductor device comprising: A first integrated circuit comprising a first device layer and a first interconnect structure; a second integrated circuit electrically connected to the first integrated circuit, the second integrated circuit comprising a second device layer and a second interconnect structure; as well as a bonding region, between the first interconnect structure and the second interconnect structure, the bonding region comprising: a first passivation layer, adjacent to the first interconnect structure; a first redistribution line embedded in the first passivation layer; a second passivation layer adjacent to the second interconnect structure, the second passivation layer being bonded to the first passivation layer; and A second redistribution line is embedded in the second passivation layer, and the second redistribution line is bonded to the first redistribution line.

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