A multifunctional BGA packaging structure and method

Abstract

This invention relates to the field of chip packaging technology, specifically a multifunctional BGA packaging structure and method. It includes a substrate with a wafer on its front side, a first electrical connection structure on its back side, and several side pads on the sides of the substrate. Compared to existing technologies, designing the memory and controller with side pads and bonding them from these pads not only reduces the overall area but also allows for direct interconnection between the memory and controller components, improving the read / write speed and power integrity of the solid-state drive.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, specifically a multifunctional BGA packaging structure and method. Background Technology

[0002] The current memory packaging type is mainly the ordinary BGA package. This product has the characteristics of a standard part. The final packaged product has a uniform package size and number of balls. However, all the solder balls are located on the back of the substrate. This limits the signal transmission ports and cannot fully guarantee the high-speed read and write capability and power stability of the stored data.

[0003] And, as Figure 10 As shown, in solid-state drive (SSD) products, the distance between storage packaging chips and between the controller chip and storage packaging chips is relatively large, resulting in a relatively large overall SSD layout area. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, this invention provides a multifunctional BGA packaging structure and method.

[0005] To achieve the above objectives, a multifunctional BGA packaging structure is designed, including a substrate. The front side of the substrate has a wafer, the back side of the substrate has a first electrical connection structure, and several side pads are located on the side of the substrate.

[0006] The side pads are provided with a second electrical connection structure.

[0007] The outer side of the second electrical connection structure is provided with an electroplated tin layer.

[0008] The wafer has a molding compound on its outer side, with the exposed portion of the molding compound containing a second electrical connection structure.

[0009] The wafer in question is a memory wafer or a controller wafer.

[0010] To achieve the above objectives, a multifunctional BGA packaging method is designed, comprising the following steps:

[0011] S1, several side pads are evenly arranged on the side of the substrate, and then the gold fingers on the surface of the substrate are electrically connected to the side pads.

[0012] S2, a second electrical connection structure is formed on the side pad;

[0013] S3, the wafer is mounted on the front side of the substrate and the wafer is electrically connected to the gold fingers via bonding wires;

[0014] S4, plastic sealant;

[0015] S5, A first electrical connection structure is formed on the back side of the substrate;

[0016] S6 is cut into individual chips, and the second electrical connection structure is exposed on the side of the individual chip after cutting.

[0017] It also includes step S7, forming a tin plating layer on the outside of the second electrical connection structure.

[0018] It also includes step S8, in which several chips are bonded together through a second electrical connection structure on the side of the chip.

[0019] Compared with the prior art, the present invention makes the memory and controller designed with pads on the side, and then completes the bonding of the memory and controller from the side pads. This not only reduces the overall area, but also allows the memory and controller to be directly interconnected, and improves the read and write speed and power integrity of the solid-state drive. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of the present invention.

[0021] Figure 2 This is a schematic diagram of step S1 of the present invention.

[0022] Figure 3 This is a schematic diagram of step S2 of the present invention.

[0023] Figure 4 This is a schematic diagram of step S3 of the present invention.

[0024] Figure 5 This is a schematic diagram of steps S4 to S6 of the present invention.

[0025] Figure 6 This is a schematic diagram of step S7 of the present invention.

[0026] Figure 7 This is a top view of the side pads obtained by the present invention.

[0027] Figure 8 for Figure 7 Side view at point A in the middle.

[0028] Figure 9 This is a schematic diagram illustrating the use of the present invention.

[0029] Figure 10 This is a schematic diagram of the prior art before the improvement of this invention. Detailed Implementation

[0030] The present invention will now be further described with reference to the accompanying drawings. Example

[0031] like Figure 1As shown, a wafer 2 is provided on the front side of the substrate 1, a first electrical connection structure 3 is provided on the back side of the substrate 1, and several side pads 4 are provided on the side of the substrate 1 for bonding between the chips. A second electrical connection structure 5 is provided on the side pads 4.

[0032] The outer side of the second electrical connection structure 5 is provided with an electroplated tin layer 6.

[0033] The outer side of the wafer 2 is provided with a molding compound 7, which serves as a protection. The molding compound 7 exposes part of the second electrical connection structure 5 to ensure that adjacent chips can be bonded. At the same time, part of the second electrical connection structure 5 is wrapped inside the molding compound 7, which serves as a protection.

[0034] Wafer 2 is a memory wafer or a controller wafer.

[0035] In practical use, the first electrical connection structure 3 and the second electrical connection structure 5 are selected from one or more of solder balls and bumps to complete the electrical connection.

[0036] like Figures 2 to 9 As shown, the multifunctional BGA packaging method in this embodiment includes the following steps:

[0037] S1, several side pads 4 are evenly arranged on the side of the substrate 1, and then the gold fingers 8 on the surface of the substrate 1 are electrically connected to the side pads 4.

[0038] S2, a second electrical connection structure 5 is formed on the side pad 4;

[0039] S3, mount wafer 2 on the front side of substrate 1, and electrically connect wafer 2 to gold finger 8 via bonding wire 9;

[0040] S4, plastic sealant;

[0041] S5, a first electrical connection structure 3 is formed on the back side of the substrate 1;

[0042] S6, cut into individual chips, the side of the cut individual chip exposes the second electrical connection structure 5.

[0043] S7, a tin plating layer 6 is formed on the outside of the second electrical connection structure 5.

[0044] S8 consists of several chips bonded together via a second electrical connection structure 5 on the side of the chip, and then attached to the solid-state drive PCB board via a thermo-press bonding process.

[0045] In practical applications, the number of side pads can be set according to functional requirements. The chips are then bonded side-by-side using thermoforming, maximizing the use of the PCB area. Alternatively, when achieving a fixed hard drive capacity, the PCB area can be reduced, while simultaneously improving memory read / write speed and power integrity.

[0046] In practical applications, the controller used in solid-state drives can be made with side metal pads in the same way, and then the same thermo-bonding technology can be used to bond the controller to the side of the memory. This allows the controller to perform signal control and power supply to the memory device with the shortest distance, thereby improving electrical performance and the read / write capability of the memory.

Claims

1. A multifunctional BGA packaging method, characterized in that: Includes the following steps: S1, several side pads (4) are evenly arranged on the side of the front side of the substrate (1), and then the gold fingers (8) on the front side of the substrate (1) are electrically connected to the side pads (4). S2, a second electrical connection structure (5) is formed on the side pad (4); S3, mount the wafer (2) on the front side of the substrate (1) and electrically connect the wafer (2) to the gold fingers (8) through bonding wires (9); S4, plastic sealant; S5, a first electrical connection structure (3) is formed on the back side of the substrate (1); S6, cut into individual chips, and the side of the cut individual chip exposes part of the second electrical connection structure (5). S7, a tin plating layer (6) is formed on the outside of the second electrical connection structure (5); S8, several chips are bonded together by a second electrical connection structure (5) on the side of the chip.

2. The multifunctional BGA package structure obtained by the multifunctional BGA packaging method according to claim 1, comprising a substrate, characterized in that: The substrate (1) has a wafer (2) on the front side and a first electrical connection structure (3) on the back side. Several side pads (4) are provided on the side of the substrate (1) on the front side.

3. The multifunctional BGA packaging structure according to claim 2, characterized in that: The side pad (4) is provided with a second electrical connection structure (5).

4. The multifunctional BGA packaging structure according to claim 3, characterized in that: The second electrical connection structure (5) has an electroplated tin layer (6) on its outer side.

5. The multifunctional BGA packaging structure according to claim 2, characterized in that: The wafer (2) has a molding compound (7) on its outer side, and the molding compound (7) exposes a portion of the second electrical connection structure (5).

6. The multifunctional BGA packaging structure according to claim 2, characterized in that: The wafer (2) is a memory wafer or a controller wafer.

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