Integrated circuit packaging assembly, packaging method thereof, device and electronic equipment

Abstract

The embodiment of the invention discloses an integrated circuit packaging assembly, a packaging method thereof, a device and electronic equipment, relates to the technical field of integrated circuits, and aims to save more winding resources for a signal line to use by at least one crystal grain in the integrated circuit packaging assembly. The packaging assembly comprises a first crystal grain and a second crystal grain stacked and connected on the first crystal grain; the first crystal grain comprises a device layer and a first interconnection layer which are sequentially stacked on the first side of the substrate, and a second interconnection layer connected with the second crystal grain is arranged on the second side of the substrate; the first power via hole penetrates through the substrate, the first end of the first power via hole extends to the first interconnection layer, is connected with the first interconnection layer and is connected with a power supply circuit on the substrate through the first interconnection layer, and the second end of the first power via hole is connected with the second interconnection layer; the second power via hole penetrates through the substrate, the first end is connected with the active device in the device layer, and the second end is connected with the first power via hole through the second interconnection layer. The method is suitable for power supply and signal network distribution in the overall three-dimensional form of the chip.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an integrated circuit packaging component and a packaging method, device, and electronic device thereof. Background Art

[0002] With the development of advanced packaging technology, the distribution of power and signal networks in the overall three-dimensional form of the chip has also become a focus of attention.

[0003] In the prior art, two types of crystal grains are packaged face-to-back to form a three-dimensional stacked chip. The overall power and signal transmission network is as follows: the substrate provides signals and power to the bottom crystal grain, which is then supplied to the front device layer of the bottom crystal grain through the front metal layer. At the same time, power and signal sources are supplied to the upper crystal grain through three-dimensional silicon vias. When this solution is used, power pins and signal pins need to be arranged on the front side of the bottom crystal grain at the same time, which requires high wiring resources and imposes strong constraints on the design.

[0004] To address the above problems, the traditional solution is to continuously increase the number of metal wire layers on the front of the chip to increase wiring resources. However, as the metal wire size becomes smaller and the routing length increases, the overall resistance will continue to increase. When the chip transmits power and signals, the power and signal resources will squeeze each other. Summary of the invention

[0005] In view of this, the embodiments of the present application provide an integrated circuit package component and a packaging method, device, and electronic device thereof, so as to save more winding resources for signal lines for at least one die in the integrated circuit package component.

[0006] In a first aspect, an embodiment of the present application provides an integrated circuit package assembly, characterized in that it includes: a first die and a second die stacked and connected to the first die; wherein the first die includes: A substrate, wherein a device layer and a first interconnection layer for connecting to the substrate are stacked in sequence on a first side of the substrate, and a second interconnection layer connected to the second crystal grain is provided on a second side of the substrate; a first power via, wherein the first power via passes through the substrate; a first end of the first power via extends to the first interconnection layer and is connected to the first interconnection layer to be connected to a power supply line on the substrate through the first interconnection layer, and a second end of the first power via is connected to the second interconnection layer; a second power via, wherein the second power via passes through the substrate; a first end of the second power via is connected to an active device in the device layer, and a second end of the second power via is connected to the first power via through the second interconnection layer.

[0007] According to a specific implementation method of an embodiment of the present application, the first interconnection layer includes: a first interconnection metal layer, the first interconnection metal layer includes at least two interconnected metal layers; a first dielectric layer, a first power pad for connecting to a power supply line on a substrate is formed on the first dielectric layer; and a first end of the first power via is connected to the first power pad.

[0008] According to a specific implementation of an embodiment of the present application, the second power via includes a source power via and a drain power via; the first end of the source power via is connected to the source of the active device, and the first end of the drain power via is connected to the drain of the active device.

[0009] According to a specific implementation manner of the embodiment of the present application, the second end of the first power via is connected to the first power via in the second die through the second interconnect layer.

[0010] According to a specific implementation manner of the embodiment of the present application, the second end of the second power via is connected to the second power via in the second die through the second interconnect layer.

[0011] According to a specific implementation method of the embodiment of the present application, the first grain also includes: a connecting via, a first end of the connecting via extends to the first interconnection layer and is connected to the first interconnection metal layer in the first interconnection layer, and a second end of the connecting via is connected to the signal via in the second grain through the second interconnection layer; wherein the connecting via is formed synchronously with the first power via and the second power via.

[0012] According to a specific implementation method of an embodiment of the present application, the number of the second grains is more than two; the first power via is formed at a position in the first grain corresponding to the gap between two adjacent second grains; the second power via is formed in the first grain at a position overlapping with the second grain.

[0013] In a second aspect, an embodiment of the present application provides a packaging method for an integrated circuit component, characterized in that it includes: forming a first power via and a second power via connected to the first power via on a first crystal grain; the first power via is used to connect to a power supply line on a substrate, and the second power via is connected to an electrode end of an active device on the first crystal grain; and stacking a second crystal grain on the first crystal grain and connecting it to the first crystal grain to form a packaging component.

[0014] According to a specific implementation of the embodiment of the present application, the first crystal grain includes: a substrate, on the first side of which a device layer and a first interconnection layer are stacked in sequence; wherein, forming a first power via and a second power via connected to the first power via on the first crystal grain includes: forming a first blind hole that penetrates the substrate, the device layer and extends into the first interconnection layer, and exposing a pad on the first interconnection layer to the bottom of the first blind hole; forming a second blind hole that penetrates the substrate and extends into the device layer, and exposing an electrode end of an active device in the device layer to the bottom of the second blind hole; filling the first blind hole with a conductive material to form a first power via; filling the second blind hole with a conductive material to form a second power via; and forming a second interconnection layer on the second side of the substrate, so that the first power via is connected to the second power via through a metal interconnection line in the second interconnection layer.

[0015] According to a specific implementation of an embodiment of the present application, in the process of forming a first power via and a second power via connected to the first power via on a first grain, the method further includes: forming a third blind hole that penetrates the substrate, the device layer and extends into the first interconnection layer, and exposing the signal interconnection line in the first interconnection layer to the bottom of the third blind hole; filling the third blind hole with a conductive material to form a connecting via.

[0016] According to a specific implementation method of an embodiment of the present application, a second interconnection layer is formed on the second side of the substrate so that the first power via is connected to the second power via through a metal interconnection line in the second interconnection layer, including: forming a rewiring layer on the second side of the substrate so that the first power via is connected to the second power via through a power interconnection line in the rewiring layer, and connecting the connection via to a signal interconnection line in the rewiring layer.

[0017] According to a specific implementation method of the embodiment of the present application, a second interconnection layer is formed on the second side of the substrate, and also includes: forming a dielectric layer on the rewiring layer; forming power vias connected to the power interconnection lines in the rewiring layer, and signal vias connected to the signal interconnection lines in the rewiring layer in the dielectric layer; forming a pad layer on the dielectric layer; forming a power pad connected to the power via, and a signal pad connected to the signal via in the pad layer.

[0018] According to a specific implementation method of an embodiment of the present application, the second grain stack is set on the first grain and connected to the first grain, including: the second grain stack is set on the first grain, and the power via on the second grain is connected to the power pad in the second interconnection layer, and the signal via on the second grain is connected to the signal pad in the second interconnection layer.

[0019] In a third aspect, an embodiment of the present application provides an integrated circuit packaging device, characterized in that it includes a substrate and an integrated circuit packaging component arranged on the substrate; wherein the integrated circuit packaging component is the integrated circuit packaging component described in any of the aforementioned embodiments, and the first power via is connected to the power supply line on the substrate.

[0020] In a fourth aspect, an embodiment of the present application provides an electronic device, characterized in that it includes: a shell, an integrated circuit packaging device, a circuit board and a power module, wherein the circuit board is placed inside the space enclosed by the shell, and the integrated circuit packaging device is arranged on the circuit board; the power module is used to supply power to the circuit board and the integrated circuit packaging device; the integrated circuit packaging device is the integrated circuit packaging device described in any of the aforementioned embodiments.

[0021] The integrated circuit packaging assembly and packaging method, device, and electronic device of this embodiment include a first die and a second die stacked and connected to the first die, wherein the first die includes: a device layer and a first interconnection layer for connecting to a substrate are stacked in sequence on a first side of a substrate, and a second interconnection layer connected to the second die is provided on a second side of the substrate; a first power via penetrates the substrate, a first end of the first power via extends to the first interconnection layer, and is connected to the first interconnection layer, so as to be connected to a power supply line on the substrate through the first interconnection layer, and a second end of the first power via is connected to the second interconnection layer; a second power via penetrates the substrate; a first end of the second power via is connected to an active device in the device layer, and a second end of the second power via is connected to the first power via through the second interconnection layer. In this way, the power on the substrate can be directly transferred to the device layer through the first power via and the second power via, so as to realize the back power supply of the first die, so that the first interconnection layer (i.e., the front of the first die) can release more layout space for the signal network, saving more winding resources for the signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A schematic diagram of an integrated circuit packaging assembly provided by an embodiment of the present application; Figure 2 A schematic diagram of the planar via distribution of an integrated circuit package assembly provided by an embodiment of the present application; Figure 3 A schematic diagram of a process flow of a packaging method for an integrated circuit packaging assembly provided by an embodiment of the present application; Figure 4-Figure 7 A process for manufacturing an integrated circuit package assembly provided in an embodiment of the present application; Figure 8 A schematic diagram of a first grain structure provided in an embodiment of the present application; Fig. 9 A top view of a metal interconnection line provided in an embodiment of the present application; Fig.10 This is a diagram showing the effect of grain stacking provided by an embodiment of the present application; Fig.11 A schematic diagram of an integrated circuit packaging device provided by an embodiment of the present application; Fig.12 A schematic diagram of an electronic device provided in accordance with an embodiment of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present application are described in detail below in conjunction with the accompanying drawings. It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0025] In order to enable those skilled in the art to better understand the technical concept, implementation plan and beneficial effects of the embodiments of the present application, specific embodiments are described in detail below.

[0026] Embodiment 1 An embodiment of the present application provides an integrated circuit packaging component and its packaging method, device, and electronic device. After using the packaging component to transmit power and signals, at least one die in the integrated circuit packaging component can save more winding resources for use by signal lines.

[0027] Figure 1 A schematic diagram of an integrated circuit packaging assembly provided by an embodiment of the present application, such as Figure 1As shown, the integrated circuit packaging component in this embodiment includes: a first die 1 and a second die 2 stacked and connected on the first die 1; wherein the first die 1 includes: a substrate 11, on the first side of the substrate 11, a device layer 12 and a first interconnection layer 13 for connecting to the substrate are stacked in sequence, and a second interconnection layer 14 connected to the second die 2 is provided on the second side of the substrate 11; a first power via 15, the first power via 15 passes through the substrate 11; a first end of the first power via 15 extends to the first interconnection layer 13 and is connected to the first interconnection layer 13 to be connected to the power supply line on the substrate through the first interconnection layer 13, and a second end of the first power via 15 is connected to the second interconnection layer 14; a second power via 16, the second power via 16 passes through the substrate 11; a first end of the second power via 16 is connected to the active device 12a in the device layer 12, and a second end of the second power via 16 is connected to the first power via 15 through the second interconnection layer 14.

[0028] The integrated circuit packaging assembly and packaging method, device, and electronic device of this embodiment include a first die and a second die stacked and connected to the first die, wherein the first die includes: a device layer and a first interconnection layer for connecting to a substrate are stacked in sequence on a first side of a substrate, and a second interconnection layer connected to the second die is provided on a second side of the substrate; a first power via penetrates the substrate, a first end of the first power via extends to the first interconnection layer, and is connected to the first interconnection layer, so as to be connected to a power supply line on the substrate through the first interconnection layer, and a second end of the first power via is connected to the second interconnection layer; a second power via penetrates the substrate; a first end of the second power via is connected to an active device in the device layer, and a second end of the second power via is connected to the first power via through the second interconnection layer. In this way, the power on the substrate can be directly transferred to the device layer through the first power via and the second power via, so as to realize the back power supply of the first die, so that the first interconnection layer (i.e., the front of the first die) can release more layout space for the signal network, saving more winding resources for the signal line.

[0029] In this embodiment, the integrated circuit package assembly is formed by stacking and connecting the dies. The dies must first complete the front-end and back-end processes to obtain the first die and the second die. Generally, the first die has more requirements for calculation and function, and the second die has relatively low requirements for power consumption. For example, in some examples, the first die is a CPU die, and the second die is a storage die. The first die and the second die are connected together to form an integrated circuit package assembly.

[0030] The first die includes a substrate, a first power via and a second power via. A device layer and a first interconnection layer for connecting to the substrate are stacked in sequence on the first side of the substrate, and a second interconnection layer connected to the second die is provided on the second side of the substrate. A device layer is stacked on the first side of the substrate, and then a first interconnection layer is stacked on the device layer, wherein the device layer includes a plurality of active devices. One side of the first interconnection layer is connected to the device layer, and the other side is connected to the substrate through metal bumps. In some examples, the substrate is a printed circuit board (PCB), and the substrate can provide power and signals to the first die and the second die through metal bumps.

[0031] On the second side of the substrate, a rewiring layer metal mask is used to form a rewiring layer through an exposure, development and etching process, and copper material is filled therein to form a metal wire, and the surface of the wire is ground and polished. The rewiring layer is a plurality of straight metal interconnects, which connect the first power via and the second power via together, and the connecting vias are interconnected together; wherein the metal interconnects are horizontal or vertical lines. A dielectric layer film is deposited on the rewiring layer to generate spaced pads, and the pads and the rewiring layer are connected by conductive vias to form a second interconnect layer, which is used to connect the first grain and the second grain, and can transmit the power and signal of the substrate to the second grain.

[0032] In order to protect the front side of the first crystal grain, the first interconnection layer is bonded to a temporary silicon carrier. The back side of the first crystal grain is thinned to a target thickness, which is determined by the product characteristics. For example, in one embodiment of the invention, the target thickness is 5-20 μm. Using a power via mask, the thinned first crystal grain is etched through an exposure, development and etching process to form a first power via that penetrates the substrate to the first interconnection layer. The first end of the first power via is connected to the first interconnection layer, and the power supply line of the substrate is connected to the metal bump, and the second end is connected to the rewiring layer in the second interconnection layer. The first power via is filled with conductive material. In some examples, copper material is filled therein, and then the surface of the first power via is ground and polished to make it more flat.

[0033] The preparation of the second power via is similar to the formation of the first power via. A back power via mask is used to etch the thinned first grain through an exposure, development and etching process to form a second power via that penetrates the substrate to the device layer. The first end of the second power via is connected to the active device in the device layer, and the second end is connected to the first power via through the rewiring layer of the second interconnect layer. The second power via is filled with conductive material. In some examples, copper material is filled therein, and then the surface of the second power via is ground and polished to make it more flat.

[0034] The integrated circuit packaging component of this embodiment includes a first die and a second die stacked and connected to the first die, wherein the first die includes: a device layer and a first interconnection layer for connecting to the substrate are stacked in sequence on the first side of the substrate, and a second interconnection layer connected to the second die is provided on the second side of the substrate; a first power via penetrates the substrate, a first end of the first power via extends to the first interconnection layer and is connected to the first interconnection layer to be connected to the power supply line on the substrate through the first interconnection layer, and a second end of the first power via is connected to the second interconnection layer; a second power via penetrates the substrate; a first end of the second power via is connected to the active device in the device layer, and a second end of the second power via is connected to the first power via through the second interconnection layer. In this way, the power on the substrate can be directly transferred to the device layer through the first power via and the second power via, so as to realize the back power supply of the first die, so that the first interconnection layer (i.e., the front of the first die) can release more layout space for the signal network and save more winding resources for the signal line.

[0035] In some embodiments, the first interconnection layer includes: a first interconnection metal layer, the first interconnection metal layer includes at least two interconnected metal layers; a first dielectric layer, a first power pad for connecting to a power supply line on a substrate is formed on the first dielectric layer; and a first end of the first power via is connected to the first power pad.

[0036] The first interconnection layer is divided into two layers: a first interconnection metal layer and a first dielectric layer, which are used to connect the substrate and the first crystal grain. The first interconnection metal layer includes two or more multi-layer interconnection metal layers, and the first dielectric layer includes a plurality of first power pads distributed at intervals. The first power pads are connected to the power supply line on the substrate through metal bumps, and receive power from the substrate to the first power via. Since the second end of the second power via is connected to the first power via through the rewiring layer of the second interconnection layer, the first power via transmits the received power to the second power via through the rewiring layer.

[0037] In some embodiments, the second power via includes a source power via and a drain power via; a first end of the source power via is connected to the source of the active device, and a first end of the drain power via is connected to the drain of the active device.

[0038] The first end of the second power via is connected to the active device in the device layer. The active device includes two electrodes: a source and a drain. The first end of the second power via is connected to the source, which is a source power via. The first end of the second power via is connected to the drain, which is a drain power via. The second power via directly connects the power supply to the source and drain of the active device from the back of the die through the rewiring layer, releasing more layout space for the signal network on the front of the die, dedicating the front-end routing resources to the signal, and avoiding the problem of mutual squeeze between the power supply network and the signal network resources in the prior art.

[0039] In some embodiments, the second end of the first power via is connected to the first power via in the second die through the second interconnect layer.

[0040] A rewiring layer is formed on one side of the second interconnection layer, and pads are generated at intervals on the other side. The pads and the rewiring layer are connected by conductive vias. The second end of the first power via in the first grain is connected to the rewiring layer in the second interconnection layer. The rewiring layer is connected to the conductive via. The conductive via is connected to the first power via of the second grain through the pad. The first power via can supply power to the second grain through this connection.

[0041] In some embodiments, the second end of the second power via is connected to the second power via in the second die through the second interconnect layer.

[0042] The second end of the second power via in the first die is connected to the rewiring layer in the second interconnect layer, the rewiring layer is connected to the conductive via, and the conductive via is connected to the second power via in the second die through the pad.

[0043] In some embodiments, the first grain further includes: a connecting via, a first end of the connecting via extending to the first interconnect layer and connected to the first interconnect metal layer in the first interconnect layer, and a second end of the connecting via connected to a signal via in the second grain through the second interconnect layer; wherein the connecting via is formed synchronously with the first power via and the second power via.

[0044] The preparation of the connecting via is similar to the formation of the first power via. A three-dimensional through-hole mask is used to form a connecting via that penetrates the substrate to the first interconnection layer through an exposure, development and etching process. The first end of the connecting via extends to the first interconnection layer and is connected to the first interconnection metal layer in the first interconnection layer. Since the first interconnection metal layer includes two or more multi-layer interconnection metal layers, the connecting via can be connected to which interconnection metal layer according to the process selection and the via size. The second end of the connecting via is connected to the rewiring layer in the second interconnection layer, and the rewiring layer is connected to the conductive via. The conductive via is connected to the signal via of the second grain through a pad. The connecting via is filled with a conductive material. In some examples, copper material is filled therein, and then the surface of the connecting via is ground and polished to make it more flat.

[0045] The connecting via is formed synchronously with the first power via and the second power via, but the process of preparing the three types of vias can be implemented in different ways. In some examples, the first power via is prepared first and the filling of the conductive material and the grinding and polishing of the via surface are completed, and then the second power via and the connecting via are repeated. Alternatively, the three types of vias can be prepared first, and the filling of the conductive material and the grinding and polishing of the via surface are completed at one time. The scheme selection can be determined according to the difference in the size of the vias. The size of the second power via and the connecting via can be the same. For example, in some examples, the size of the second power via and the connecting via is 0.7um. The size of the three types of vias can also be different. For example, in some examples, the second power via is 0.7um, the connecting via is 2.5um, and the first power via is 5um or larger.

[0046] In some embodiments, Figure 2 is a schematic diagram of the planar via distribution, such as Figure 2 As shown, the number of the second grains 2 is more than two; the first power via 11 is formed at a position in the first grain 1 corresponding to the gap between two adjacent second grains 2; the second power via 12 is formed at a position in the first grain 1 overlapping with the second grain 2.

[0047] Two or more second dies can be bonded to the first die of the embodiment of the present invention, and the performance of the bonded second dies can be the same or different. The distribution positions of the three types of vias can be determined according to the bonding positions of the dies. The first power via is distributed at the position corresponding to the gap between two adjacent second dies in the first die. No other devices are distributed at the position corresponding to the gap between two adjacent second dies in the first die. The first power via is concentratedly distributed to reduce the impact of large-size first power vias on the reliability of advanced node devices. The second power via and the connection via are distributed at the position overlapping with the second die in the first die.

[0048] Embodiment 2 Figure 3 A schematic diagram of a packaging method for an integrated circuit packaging assembly provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the packaging method of the integrated circuit packaging assembly in this embodiment includes: S11. Form a first power via and a second power via connected to the first power via on a first die; the first power via is used to connect to a power supply line on a substrate, and the second power via is connected to an electrode terminal of an active device on the first die.

[0049] In this embodiment, the integrated circuit packaging component is formed by stacking and connecting two types of grains. The required grains must first be made through the front-end and back-end processes to obtain the first grain and the second grain. The first grain includes a first interconnection layer, a device layer, and a second interconnection layer. A first power via and a second power via are formed on the first grain. One end of the first power via is connected to the first interconnection layer, and the other end is connected to the second interconnection layer. One end of the second power via is connected to the second interconnection layer, and the other end is connected to the electrode end of the active device in the device layer. The first power via can be connected to the second power via through the second interconnection layer. At the same time, the first power via can be connected to the power supply line on the substrate through the first interconnection layer.

[0050] S12, stacking a second die on the first die and connecting the second die to the first die to form a package assembly.

[0051] The second interconnection layer in the first grain includes a rewiring layer and pads distributed at intervals. The second grain can be connected to the first grain through the pads. The first grain can transmit the power supply and signal of the substrate to the pads through the rewiring layer, and the pads transmit the power supply and signal to the second grain. The interconnected first grain and the second grain form a packaging component.

[0052] The packaging method of the integrated circuit packaging component of this embodiment includes forming a first power via and a second power via connected to the first power via on the first crystal grain; the first power via is used to connect to the power supply line on the substrate, and the second power via is connected to the electrode end of the active device on the first crystal grain, and the second crystal grain is stacked and arranged on the first crystal grain and connected to the first crystal grain to form a packaging component. In this way, the first end of the second power via can directly transmit the power signal of the first power via to the device layer, releasing more layout space for the signal network for the first interconnection layer; the second end of the first power via is connected to the second interconnection layer, and the power signal can be directly transmitted to the second crystal grain through the second interconnection layer, so that the power supply path becomes relatively shorter, saving the via resources in the first crystal grain that originally supplied power to the second crystal grain for use by the signal via. This embodiment avoids the power loss and signal attenuation problems caused by the mutual squeeze of power supply network and signal network resources in the prior art, and improves the transmission quality of power and signal.

[0053] In some embodiments, Figure 4-Figure 7 Process for making integrated circuit packaging components, such as Figure 4-Figure 7 As shown, the first crystal grain comprises: a substrate 20, on the first side of which a device layer 21 and a first interconnection layer 22 are sequentially stacked; wherein, forming a first power via 23 and a second power via 24 connected to the first power via 23 on the first crystal grain comprises: forming a first blind hole 25 penetrating the substrate 20, the device layer 21 and extending into the first interconnection layer 22, and exposing a pad 22a on the first interconnection layer 22 to the bottom of the first blind hole 25; forming a second blind hole 26 penetrating the substrate 20 and extending into the device layer 21, and exposing an electrode end of an active device 21a in the device layer 21 to the bottom of the second blind hole 26; filling the first blind hole 25 with a conductive material to form the first power via 23; filling the second blind hole 26 with a conductive material to form the second power via 24; and forming a second interconnection layer 27 on the second side of the substrate 20, so that the first power via 23 is connected to the second power via 24 through a metal interconnection line 27a in the second interconnection layer 27.

[0054] Common substrate materials include single crystal silicon, sapphire with high hardness and transparency, silicon carbide for specific applications, etc., which are used to manufacture integrated circuit devices. In one embodiment of the present invention, the substrate material is single crystal silicon.

[0055] The first side of the substrate in the first crystal grain is stacked with a device layer and a first interconnection layer for connecting to the substrate in sequence, and the second side of the substrate is provided with a second interconnection layer connected to the second crystal grain. The device layer is first stacked on the first side of the substrate, and then a first interconnection layer is stacked on the device layer, wherein the device layer includes a plurality of active devices, and in some examples, the active devices are fin field effect transistors (FINFETs). One side of the first interconnection layer is connected to the device layer, and the other side is connected to the substrate through metal bumps. In some examples, the substrate is a printed circuit board (PCB), and the substrate can provide power and signals to the first crystal grain and the second crystal grain through metal bumps.

[0056] The second side of the substrate in the first crystal grain uses a rewiring layer metal mask, and forms a rewiring layer through an exposure, development and etching process, fills the copper material therein to form a metal wire, and grinds and polishes the wire surface. The rewiring layer is a plurality of straight metal interconnects, which connect the first power via and the second power via together, and the connecting vias are interconnected together; wherein the metal interconnects are horizontal or vertical lines. A dielectric layer film is deposited on the rewiring layer to generate spaced pads, and the pads and the rewiring layer are connected by conductive vias to form a second interconnect layer, which is used to connect the first crystal grain and the second crystal grain, and can transmit the power and signal of the substrate to the second crystal grain.

[0057] A first power via and a second power via connected to the first power via are formed on the first die. The first power via and the second power via are formed by using a mask on the first die through an exposure, development and etching process. Since subsequent processes need to be performed on the back of the die and the front of the die needs to be protected, the first interconnection layer of the first die is bonded to a temporary silicon carrier, and then the die is thinned from the back to a target thickness, which is determined by product characteristics.

[0058] Using a power via mask, the thinned first grain is etched through an exposure, development and etching process to obtain a first blind hole that penetrates the substrate, the device layer and extends into the first interconnection layer. The pad on the first interconnection layer is exposed at the bottom of the first blind hole. The first end of the first blind hole is connected to the pad on the first interconnection layer, and the power supply line of the substrate is connected through a metal bump. The second end is connected to the rewiring layer in the second interconnection layer. The first blind hole is filled with a conductive material. In some examples, copper material is filled therein, and then the surface of the first blind hole is ground and polished to make it more flat to obtain a first power via.

[0059] Using a back-side power supply via mask, the thinned first grain is etched through an exposure, development and etching process to form a second blind hole that penetrates the substrate and extends into the device layer, and the electrode end of the active device in the device layer is exposed to the bottom of the second blind hole. The first end of the second blind hole is connected to the electrode of the active device in the device layer, and the second end is connected to the rewiring layer of the second interconnect layer. The second blind hole is filled with a conductive material. In some examples, copper material is filled therein, and then the surface of the second blind hole is ground and polished to make it more flat, thereby obtaining a second power via. The second power via includes a source power via and a drain power via; the first end of the source power via is connected to the source of the active device, and the first end of the drain power via is connected to the drain of the active device.

[0060] Since the rewiring layer in the second interconnection layer is a plurality of metal interconnection lines, the second end of the first power via is connected to the rewiring layer in the second interconnection layer, and the second end of the second power via is connected to the rewiring layer of the second interconnection layer. The first power via can be connected to the second power via through the metal interconnection line of the rewiring layer in the second interconnection layer.

[0061] In some embodiments, Figure 6 and Figure 7 As shown, in the process of forming a first power via 24 and a second power via 24 connected to the first power via 23 on the first crystal grain, the method further includes: forming a third blind hole 28 penetrating the substrate 20, the device layer 21 and extending into the first interconnection layer 22, and exposing the signal interconnection line 22b in the first interconnection layer 22 to the bottom of the third blind hole 28; filling the third blind hole 28 with a conductive material to form a connecting via 29.

[0062] The preparation of the connecting via is similar to the formation of the first power via. A third blind hole is formed in the first crystal grain through the exposure, development and etching process by using a three-dimensional via mask, which penetrates the substrate, the device layer and extends into the first interconnection layer, and the signal interconnection line in the first interconnection layer is exposed at the bottom of the third blind hole. The first end of the third blind hole is connected to the signal interconnection line in the first interconnection layer. Since the signal interconnection line is a multi-layer interconnection metal line, the third blind hole can be connected to which layer of interconnection metal line according to the process selection and the via size. The second end of the third via is connected to the rewiring layer in the second interconnection layer, and the rewiring layer is connected to the conductive via. The conductive via is connected to the signal via of the second crystal grain through the pad. The third blind hole is filled with conductive material. In some examples, copper material is filled therein, and then the surface of the third blind hole is ground and polished to make it more flat to obtain a connecting via.

[0063] The connecting via connects the first die and the second die in series, and can transmit a signal to the second die through the second interconnection layer. The connecting via is formed synchronously with the first power via and the second power via, but the process of preparing the three types of vias can be implemented in different ways. In some examples, the first power via is prepared first and the filling of the conductive material and the grinding and polishing of the via surface are completed, and then the second power via and the connecting via are repeated. The three types of vias can also be prepared first, and the filling of the conductive material and the grinding and polishing of the via surface are completed at one time. The scheme selection can be determined according to the size difference of the vias. The size of the second power via and the connecting via can be the same. For example, in some examples, the size of the second power via and the connecting via are both 0.7um. The size of the three types of vias can also be different. For example, in some examples, the second power via is 0.7um, the connecting via is 2.5um, and the first power via is 5um or larger.

[0064] In some embodiments, a second interconnection layer is formed on the second side of the substrate so that the first power via is connected to the second power via through a metal interconnection line in the second interconnection layer, including: forming a rewiring layer on the second side of the substrate so that the first power via is connected to the second power via through a power interconnection line in the rewiring layer, and connecting the connection via to a signal interconnection line in the rewiring layer.

[0065] A second interconnection layer is formed on the second side of the substrate, and the second interconnection layer includes a rewiring layer for planar electrical extension and interconnection. The rewiring layer is a plurality of metal interconnection lines, which can transmit power and signals and are divided into power interconnection lines and signal interconnection lines. The first power via can be connected to the second power via through the power interconnection line in the rewiring layer, and the substrate power is transmitted to the second power via; the connecting via can be connected to the signal interconnection line in the rewiring layer, and the first grain and the second grain are connected in series, and the signal can be transmitted to the second grain through the signal interconnection line.

[0066] In some embodiments, Figure 8 is a schematic diagram of the first grain structure, such as Figure 8 As shown, a second interconnection layer 27 is formed on the second side of the substrate 20, and also includes: forming a dielectric layer 27b on the rewiring layer 27a; forming a power via 27c connected to the power interconnection line in the rewiring layer 27a, and a signal via 27d connected to the signal interconnection line in the rewiring layer 27a in the dielectric layer 27b; forming a pad layer 27e on the dielectric layer 27b; forming a power pad 27e1 connected to the power via 27c, and a signal pad 27e2 connected to the signal via 27d in the pad layer 27e.

[0067] A dielectric layer is deposited on the rewiring layer, and vias and pad layers are formed in the dielectric layer. Since the rewiring layer is composed of multiple metal interconnects, Fig. 9 It is a top view of the metal interconnection line. The metal interconnection line can transmit power and signals and is divided into power interconnection lines and signal interconnection lines. Therefore, power vias connected to the power interconnection lines in the rewiring layer and signal vias connected to the signal interconnection lines in the rewiring layer are formed in the dielectric layer. Similarly, power pads connected to the power vias and signal pads connected to the signal vias are formed in the pad layer in the dielectric layer.

[0068] In some embodiments, the step of stacking the second die on the first die and connecting the second die to the first die includes: stacking the second die on the first die, connecting the power via on the second die to the power pad in the second interconnect layer, and connecting the signal via on the second die to the signal pad in the second interconnect layer.

[0069] The second grain stack is arranged on the first grain and connected to the first grain through the second interconnection layer. When connected, the power via of the second grain is connected to the power pad in the second interconnection layer in the first grain, the power pad in the second interconnection layer is connected to the power via in the second interconnection layer, and the power via is connected to the power interconnection line in the rewiring layer; the signal via on the second grain is connected to the signal pad in the second interconnection layer in the first grain, the signal pad in the second interconnection layer is connected to the signal via in the second interconnection layer, and the signal via is connected to the signal interconnection line in the rewiring layer. Fig.10 This is the effect diagram after grain stacking, such as Fig.10 As shown, the power supply networks of the first die and the second die are split: for the first die, power is transferred from the substrate to the first power via, the first power via transfers the power to the rewiring layer, and the second power via directly connects the power to the source and drain of the active device from the back of the die through the rewiring layer, thereby releasing more layout space for the signal network on the front of the first die and dedicating the front-end routing resources to the signal; for the second die, power is transferred from the substrate to the first power via, the first power via transfers the power to the rewiring layer, and the rewiring layer transmits the power to the power via of the second die through the pad. This power path can save the power via that originally needs to supply power to the second die through the connection via of the first die, and give more resources to the signal vias in the second die.

[0070] The packaging method of the integrated circuit packaging component of this embodiment includes a first die and a second die stacked and connected to the first die, wherein the first die includes: a device layer and a first interconnection layer for connecting to the substrate are stacked in sequence on the first side of the substrate, and a second interconnection layer connected to the second die is provided on the second side of the substrate; a first power via penetrates the substrate, a first end of the first power via extends to the first interconnection layer and is connected to the first interconnection layer to be connected to the power supply line on the substrate through the first interconnection layer, and a second end of the first power via is connected to the second interconnection layer; a second power via penetrates the substrate; a first end of the second power via is connected to the active device in the device layer, and a second end of the second power via is connected to the first power via through the second interconnection layer. In this way, the power on the substrate can be directly transferred to the device layer through the first power via and the second power via, so as to realize the back power supply of the first die, so that the first interconnection layer (i.e., the front of the first die) can release more layout space for the signal network and save more winding resources for the signal line.

[0071] Embodiment 3 Fig.11 A schematic diagram of an integrated circuit packaging device provided in an embodiment of the present application, such as Fig.11As shown, an embodiment of the present application provides an integrated circuit packaging device, including a substrate 31 and an integrated circuit packaging component 32 arranged on the substrate 31; wherein the integrated circuit packaging component 32 is the integrated circuit packaging component described in the aforementioned embodiment, and the first power via 32a is connected to the power supply line 31a on the substrate 31.

[0072] The integrated circuit packaging device of this embodiment includes a substrate and an integrated circuit packaging component arranged on the substrate. The integrated circuit packaging component includes a first die and a second die stacked and connected to the first die, wherein the first die includes: a device layer and a first interconnection layer for connecting to the substrate are stacked in sequence on the first side of the substrate, and a second interconnection layer connected to the second die is arranged on the second side of the substrate; a first power via penetrates the substrate, a first end of the first power via extends to the first interconnection layer, and is connected to the first interconnection layer, so as to be connected to the power supply line on the substrate through the first interconnection layer, and a second end of the first power via is connected to the second interconnection layer; a second power via penetrates the substrate; a first end of the second power via is connected to the active device in the device layer, and a second end of the second power via is connected to the first power via through the second interconnection layer. In this way, the power on the substrate can be directly transferred to the device layer through the first power via and the second power via, so as to realize the back power supply of the first die, so that the first interconnection layer (i.e., the front of the first die) can release more layout space for the signal network, saving more winding resources for the signal line.

[0073] Embodiment 4 Fig.12 A schematic diagram of an electronic device provided in an embodiment of the present application, such as Fig.12 As shown, an embodiment of the present application provides an electronic device, including: a shell 41, an integrated circuit packaging device 42, a circuit board 43 and a power module 44, wherein the circuit board 43 is arranged inside the space enclosed by the shell 41, and the integrated circuit packaging device 42 is arranged on the circuit board 43; the power module 44 is used to supply power to the circuit board 43 and the integrated circuit packaging device 42; the integrated circuit packaging device 42 is the integrated circuit packaging device described in the aforementioned embodiment.

[0074] The electronic device of this embodiment includes a housing, an integrated circuit packaging device, a circuit board and a power module. The integrated circuit packaging device includes a first die and a second die stacked and connected to the first die, wherein the first die includes: a device layer and a first interconnection layer for connecting to the substrate are stacked in sequence on the first side of the substrate, and a second interconnection layer connected to the second die is provided on the second side of the substrate; a first power via penetrates the substrate, a first end of the first power via extends to the first interconnection layer, and is connected to the first interconnection layer, so as to be connected to the power supply line on the substrate through the first interconnection layer, and a second end of the first power via is connected to the second interconnection layer; a second power via penetrates the substrate; a first end of the second power via is connected to the active device in the device layer, and a second end of the second power via is connected to the first power via through the second interconnection layer. In this way, the power on the substrate can be directly transferred to the device layer through the first power via and the second power via, so as to realize the back power supply of the first die, so that the first interconnection layer (i.e., the front of the first die) can release more layout space for the signal network, saving more winding resources for the signal line.

[0075] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0076] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0077] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. An integrated circuit package assembly, characterized in that: include: a first die and a second die stacked and connected to the first die; Wherein, the first crystal grain comprises: A substrate, wherein a device layer and a first interconnection layer for connecting to a base plate are sequentially stacked on a first side of the substrate, and a second interconnection layer connected to the second crystal grain is provided on a second side of the substrate; a first power via, wherein the first power via passes through the substrate; a first end of the first power via extends to the first interconnection layer and is connected to the first interconnection layer so as to be connected to a power supply line on the substrate through the first interconnection layer, and a second end of the first power via is connected to the second interconnection layer; A second power via, wherein the second power via passes through the substrate; a first end of the second power via is connected to an active device in the device layer, and a second end of the second power via is connected to the first power via through the second interconnect layer.

2. The integrated circuit package assembly according to claim 1, characterized in that: The first interconnection layer comprises: a first interconnect metal layer, the first interconnect metal layer comprising at least two interconnected metal layers; a first dielectric layer, on which a first power pad for connecting to a power supply line on the substrate is formed; A first end of the first power via is connected to the first power pad.

3. The integrated circuit package assembly according to claim 1, characterized in that: The second power via includes a source power via and a drain power via; a first end of the source power via is connected to the source of the active device, and a first end of the drain power via is connected to the drain of the active device.

4. The integrated circuit package assembly according to claim 1, characterized in that: The second end of the first power via is connected to the first power via in the second die through the second interconnect layer.

5. The integrated circuit package assembly according to claim 4, characterized in that: The second end of the second power via is connected to the second power via in the second die through the second interconnect layer.

6. The integrated circuit package assembly according to claim 1, characterized in that: The first crystal grain further comprises: a connecting via, wherein a first end of the connecting via extends to the first interconnect layer and is connected to the first interconnect metal layer in the first interconnect layer, and a second end of the connecting via is connected to a signal via in the second die through the second interconnect layer; Wherein, the connection via is formed synchronously with the first power via and the second power via.

7. The integrated circuit package assembly according to claim 1, characterized in that: The number of the second grains is two or more; The first power via is formed at a position in the first die corresponding to a gap between two adjacent second die; The second power via is formed at a position in the first die overlapping with the second die.

8. A method for packaging an integrated circuit component, characterized in that: include: forming a first power via and a second power via connected to the first power via on the first die; The first power via is used to connect to a power supply line on the substrate, and the second power via is connected to an electrode terminal of an active device on the first die; The second die is stacked on the first die and connected to the first die to form a package assembly.

9. The packaging method according to claim 8, characterized in that: The first crystal grain comprises: a substrate, on a first side of which a device layer and a first interconnect layer are sequentially stacked; The step of forming a first power via and a second power via connected to the first power via on the first die includes: Forming a first blind hole that penetrates the substrate, the device layer and extends into the first interconnection layer, and exposing the pad on the first interconnection layer to the bottom of the first blind hole; Forming a second blind hole penetrating the substrate and extending into the device layer, and exposing the electrode terminal of the active device in the device layer to the bottom of the second blind hole; Filling the first blind hole with a conductive material to form a first power via; Filling the second blind hole with a conductive material to form a second power via; A second interconnection layer is formed on the second side of the substrate, so that the first power via is connected to the second power via through a metal interconnection line in the second interconnection layer.

10. The packaging method according to claim 9, characterized in that: In the process of forming a first power via and a second power via connected to the first power via on the first die, the method further includes: Forming a third blind hole that penetrates the substrate, the device layer and extends into the first interconnection layer, and exposing the signal interconnection line in the first interconnection layer to the bottom of the third blind hole; A conductive material is filled in the third blind hole to form a connecting via.

11. The packaging method according to claim 9, characterized in that: Forming a second interconnection layer on the second side of the substrate so that the first power via is connected to the second power via through a metal interconnection line in the second interconnection layer, comprising: A rewiring layer is formed on the second side of the substrate so that the first power via is connected to the second power via through a power interconnection line in the rewiring layer, and the connection via is connected to a signal interconnection line in the rewiring layer.

12. The packaging method according to claim 9, characterized in that: A second interconnect layer is formed on the second side of the substrate, further comprising: forming a dielectric layer on the redistribution layer; forming in the dielectric layer a power via connected to the power interconnection line in the rewiring layer, and a signal via connected to the signal interconnection line in the rewiring layer; forming a pad layer on the dielectric layer; A power pad connected to the power via and a signal pad connected to the signal via are formed in the pad layer.

13. The packaging method according to claim 12, characterized in that: The stacking of the second die on the first die and connecting the second die to the first die comprises: A second die stack is disposed on the first die, and the power via on the second die is connected to the power pad in the second interconnection layer, and the signal via on the second die is connected to the signal pad in the second interconnection layer.

14. An integrated circuit packaging device, characterized in that: It comprises a substrate and an integrated circuit package component arranged on the substrate; wherein the integrated circuit package component is the integrated circuit package component as described in any one of the preceding claims 1-7, and the first power via is connected to the power supply line on the substrate.

15. An electronic device, characterized in that: include: A housing, an integrated circuit package device, a circuit board and a power module, wherein the circuit board is placed inside the space enclosed by the housing, and the integrated circuit package device is arranged on the circuit board; A power module is used to supply power to a circuit board and an integrated circuit packaging device; the integrated circuit packaging device is the integrated circuit packaging device according to claim 14.

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