Connection structure of chip and substrate

Abstract

The invention relates to the field of chip packaging, in particular to a connecting structure of a chip and a substrate. Comprising a plurality of first UBM cushion layers and second UBM cushion layers. The first UBM cushion layers are located in the area close to the center of the first connecting layer, and the second UBM cushion layers are located in the area away from the center of the first connecting layer. The difference value between the area of the second UBM cushion layer and the area of the first UBM cushion layer is smaller than or equal to a first preset threshold value. In the invention, the first UBM cushion layer and the second UBM cushion layer which are different in size are arranged in the connecting structure of the chip and the substrate, and when the second UBM cushion layer with a larger size is arranged in a corresponding high-stress area, the salient point density in the area can be improved, so that the differential requirement of a high-computing-power chip on the salient point density in a corner area is met; and therefore, the fracture risk of the ELK isolation dielectric layer in the high-stress area can be reduced, and the operation stability of the chip can be improved.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging, and in particular to a connection structure between a chip and a substrate. Background Art

[0002] With the development of advanced technologies such as AI computing reasoning, big data, and cloud services, the required computing power has also increased exponentially. In order to meet the above computing requirements, more transistors and more layers of metal layers (Metal Layer) can be set on the computing chip through more advanced process technologies (such as 5nm, 7nm). The metal layer plays the role of a circuit, connecting different transistors in different forms to meet the corresponding power supply and logic operation requirements. At the same time, in order to prevent conduction between two adjacent stacked metal layers, an isolation medium is also set between any two adjacent metal circuit layers. In addition, in order to reduce dielectric loss when communicating between different metal circuit layers, the transmission quality and speed of the signal are improved. Therefore, ELK (extremely low-k) materials with a low dielectric constant are used as isolation media between different circuit layers.

[0003] For chips with large computing loads such as AI computing reasoning, big data, and cloud services, they are large in size and require more complex and frequent communication between different metal layers. An isolation medium with a lower K value is required to reduce electrical loss. Because the dielectric constant of a vacuum is the lowest, increasing the proportion of vacuum or air in the dielectric material can reduce the dielectric constant of the entire dielectric material. Therefore, in order to reduce the K value of the dielectric material, there will be more and more holes inside the dielectric material, making the mechanical strength of the dielectric material lower. In addition, the heat generated by such a large computing chip is usually very high, and as the temperature changes, due to the mismatch between the thermal expansion coefficients of the chip and the substrate, the edges and corners of the substrate will produce crying or smiling warping deformations, thereby generating greater extrusion stress on the isolation dielectric layer at the corresponding position, thereby further increasing the risk of fracture of the ELK isolation dielectric layer. Generally, the higher the bump density between the chip and the substrate, the more effective it is in relieving the extrusion stress. Therefore, for the above-mentioned chips with high computing power, it is necessary to have a higher bump density in the area with higher stress to improve the operating stability of the chip.

[0004] In the prior art, bumps of the same size are used for connection, and the bumps in each area of ​​the corresponding chip are of the same size. However, the bump density is usually higher in the corners of the chip, and the existing bump setting method often fails to meet the lower limit of the bump density requirement in the corners. As a result, the risk of ELK isolation dielectric layer fracture is increased, and the operational stability of the chip is reduced. Summary of the invention

[0005] In view of this, the present invention provides a connection structure between a chip and a substrate, which at least partially solves the problems existing in the prior art.

[0006] According to one aspect of the present invention, there is provided a connection structure between a chip and a substrate, comprising:

[0007] The first connection layer is fixedly disposed on a side of the chip close to the substrate.

[0008] A plurality of first UBM pads and a plurality of second UBM pads are fixed on the first connection layer at intervals, the plurality of first UBM pads are located in an area close to the center of the first connection layer, and the plurality of second UBM pads are located in an area far from the center of the first connection layer. The first UBM pad is the UBM pad with the smallest area in the connection structure, and the second UBM pad is the UBM pad with the largest area in the connection structure.

[0009] A difference between an area of ​​the second UBM pad layer and an area of ​​the first UBM pad layer is less than or equal to a first preset threshold.

[0010] Furthermore, it also includes:

[0011] A plurality of first connection bumps are respectively fixed on the first UBM pad layer, and the volume of the first connection bumps is positively correlated with the area of ​​the first UBM pad layer.

[0012] A plurality of second connection bumps are respectively fixed on the second UBM pad layer, and the volume of the second connection bumps is positively correlated with the area of ​​the second UBM pad layer. The difference between the height of the second connection bump and the height of the first connection bump is less than or equal to a second preset threshold. And

[0013] The second connection layer is fixedly arranged on a side of the substrate close to the chip. Each first connection bump and each second connection bump are fixedly connected to the second connection layer.

[0014] Furthermore, the first connection layer includes:

[0015] The passivation layer is fixedly covered on the metal layer on the side of the chip close to the substrate.

[0016] The energy absorbing layer is fixedly covered on the passivation layer. And

[0017] A plurality of first placement through holes penetrate the energy absorption layer and the passivation layer. The placement positions of the plurality of first placement through holes correspond to the placement positions of the first UBM pad layer and the second UBM pad layer respectively. A connection end of the first UBM pad layer and the second UBM pad layer is fixedly disposed in the corresponding first placement through holes respectively.

[0018] Furthermore, the second connection layer includes:

[0019] The protective layer is fixedly covered on the metal layer on the side of the substrate close to the chip. And

[0020] A plurality of second placement through holes are set through the protective layer, and the setting positions of the plurality of second placement through holes correspond to the setting positions of the first placement through holes one by one. The other connection ends of the first connection bump and the second connection bump are fixedly set in the corresponding second placement through holes.

[0021] Furthermore, the first connection layer is rectangular, and the shape of the first connection layer is the same as the shape of the chip.

[0022] The plurality of second UBM pad layers are located at four corner regions of the first connection layer.

[0023] Furthermore, the vertex area is a rectangle or a triangle.

[0024] Furthermore, the first UBM pad layer and the second UBM pad layer are both cylindrical pad layers.

[0025] The diameter of the second UBM pad is determined as follows:

[0026] An initial diameter value range is generated according to the diameter of the first UBM pad layer and a first preset threshold.

[0027] Obtain multiple initial diameter values ​​from the initial diameter value interval.

[0028] According to the first mapping table, the cushion layer spacing value corresponding to each initial diameter value is obtained.

[0029] According to each initial diameter value and the corresponding pad interval value, the number of second UBM pads formed by each initial diameter value in the preset area is determined as A1, A2, ..., A i , …, A z Among them, A i is the number of second UBM pads formed by the i-th initial diameter value in the preset area. z is the total number of initial diameter values, i=1, 2, ..., z.

[0030] like Then confirm is the target diameter to generate multiple target diameters. Wherein, ρ is the lower limit of the bump density in the preset area. S is the total area of ​​the preset area. is the i-th initial diameter value.

[0031] The diameter of the second UBM pad layer is obtained from a plurality of target diameters.

[0032] Further, multiple initial diameter values ​​are obtained from the initial diameter value interval, including:

[0033] According to the preset numerical interval, multiple initial diameter values ​​are obtained from the initial diameter value interval.

[0034] Furthermore, the second preset threshold is 10 um.

[0035] Furthermore, the second preset threshold is positively correlated with the first preset threshold.

[0036] The technical solution of the present invention has at least the following beneficial effects:

[0037] Usually, the chip and the substrate are connected through a more advanced flip-chip technology, specifically, a solder bump is formed on the pad of the I / O port of the wafer through the Bumping (wafer-level bumping process), and then the chip and the substrate are connected through the bump. Correspondingly, the higher the bump density in the connection structure, the greater the ability to offset the stress on the ELK isolation dielectric layer, thereby reducing the risk of fracture of the ELK isolation dielectric layer. At the same time, the size of the bump will be affected by the size of the UBM (underball metal, deposited under-bump metallization layer) layer at the corresponding position. Specifically, the size of the UBM pad is positively correlated with the size of the bump. Therefore, the size of the bump can be controlled by controlling the size of the UBM pad during design.

[0038] In the present invention, a first UBM pad layer and a second UBM pad layer of different sizes are arranged in the chip-substrate connection structure, and the second UBM pad layer of larger size is arranged at the edge and / or top corner area where the stress is greater when the chip is subjected to warping and extrusion. Therefore, when the second UBM pad layer of larger size is arranged in the corresponding high stress area, the bump density in the area can be increased to meet the differentiated requirements of high computing power chips for the bump density in the corner area, thereby reducing the risk of fracture of the ELK isolation dielectric layer in the high stress area and improving the operational stability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 The figure is a schematic cross-sectional view of a connection structure between a chip and a substrate in one embodiment of the present application.

[0041] Figure 2 It is a schematic diagram of the connection structure among the chip, the first connection layer, the UBM pad layer and the bumps in another embodiment of the present application.

[0042] Figure 3This is a schematic structural diagram of the arrangement of bumps in a high stress preset area set in arrangement mode 1 in another embodiment of the present application.

[0043] Figure 4 This is a structural schematic diagram of the arrangement of bumps in a high stress preset area set in arrangement mode 2 in another embodiment of the present application.

[0044] Figure 5 FIG. 1 is a schematic diagram of stress of bumps in various regions when the substrate is warped at high temperature (240° C.) in another embodiment of the present application.

[0045] Reference numerals

[0046] 1. First connection layer; 10. Passivation layer; 11. Energy absorption layer; 12. First placement through hole; 2. UBM pad layer; 3. Bump; 31. First connection bump; 32. Second connection bump; 4. Protection layer. DETAILED DESCRIPTION

[0047] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. Moreover, all other embodiments obtained by ordinary technicians in the field without creative work based on the embodiments in the present disclosure are within the scope of protection of the present disclosure.

[0049] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein may be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein may be implemented independently of any other aspect, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein may be used to implement this device and / or practice this method.

[0050] As an embodiment of the present invention, Figure 1 and Figure 2 As shown, a connection structure between a chip and a substrate is provided, including: a first connection layer 1 and a plurality of first UBM pad layers and a plurality of second UBM pad layers.

[0051] The first connection layer 1 comprises: a passivation layer 10, an energy absorption layer 11 and a plurality of first placement through holes 12. The first connection layer 1 is rectangular, and the shape of the first connection layer 1 is the same as that of the chip.

[0052] Specifically, the passivation layer 10 is fixedly covered on the metal layer on the side of the chip close to the substrate. The passivation layer 10 is mainly used to prevent the metal layer on the side of the chip close to the substrate from being oxidized.

[0053] The energy absorbing layer 11 is fixedly covered on the passivation layer 10. The material of the energy absorbing layer 11 can be polyimide, which has a certain energy absorption effect. Therefore, when the substrate is deformed to squeeze the bump 3, the energy absorbing layer 11 can absorb a certain amount of squeezing force through its own partial deformation. In turn, the magnitude of the pressure value transmitted to the chip can be further reduced, thereby reducing the risk of fracture of the ELK isolation dielectric layer.

[0054] A plurality of first placement through holes 12 penetrate the energy absorption layer 11 and the passivation layer 10, and the arrangement positions of the plurality of first placement through holes 12 correspond to the arrangement positions of the first UBM pad layer and the second UBM pad layer, respectively, and a connection end of the first UBM pad layer and the second UBM pad layer is respectively fixedly arranged in the corresponding first placement through hole 12. Specifically, the first UBM pad layer and the second UBM pad layer are both cylindrical pad layers.

[0055] In the connection structure between the chip and the substrate, the UBM pad 2 is the connection structure between the metal layer on the side of the chip close to the substrate and the bump 3. At the same time, the size of the bump 3 will be affected by the size of the UBM (underball metal, deposited under-bump metallization layer) pad at the corresponding position. Specifically, the size of the UBM pad 2 is positively correlated with the size of the bump 3. Therefore, the size of the bump 3 can be controlled by controlling the size of the UBM pad 2 during design.

[0056] Multiple first UBM pads and second UBM pads are fixed at intervals on the first connection layer 1, multiple first UBM pads are located in an area close to the center of the first connection layer 1, and multiple second UBM pads are located in an area far from the center of the first connection layer 1. The first UBM pad is the UBM pad 2 with the smallest area in the connection structure, and the second UBM pad is the UBM pad 2 with the largest area in the connection structure.

[0057] The difference between the area of ​​the second UBM pad layer and the area of ​​the first UBM pad layer is less than or equal to the first preset threshold. The plurality of second UBM pad layers are located in four corner regions of the first connection layer 1. The corner regions are rectangular or triangular.

[0058] Generally, when the substrate deforms at high temperature, the farther away from the center position, the greater the deformation. The corresponding edge area and top corner area of ​​the chip will become areas with higher stress values. Correspondingly, a higher bump density is required in the high stress area, so multiple second UBM pads are located in the four top corner areas of the first connection layer 1.

[0059] The existing chip structure includes multiple functional modules, and correspondingly there are multiple functional PHY (Port Physical Layer) chips inside the chip. Some of these PHY chips need to be purchased from outside, and usually the size of the UBM pad 2 used in the design of these outsourced PHY chips will have certain differences.

[0060] In this embodiment, in order to ensure that the later chips can be smoothly mounted on the board, it is necessary to control the size difference of all bumps 3 on the entire chip within a reasonable range, such as within 10um. That is, the difference between the height of the second connection bump 32 and the height of the first connection bump 31 is less than or equal to the second preset threshold, and the second preset threshold can be 10um. At the same time, since the second preset threshold is positively correlated with the first preset threshold, the size of the corresponding first preset threshold can be determined.

[0061] In the present invention, a first UBM pad layer and a second UBM pad layer of different sizes are arranged in the chip-substrate connection structure, and the second UBM pad layer of larger size is arranged at the edge and / or top corner area where the stress is greater when the chip is subjected to warping and extrusion. Therefore, when the second UBM pad layer of larger size is arranged in the corresponding high stress area, the bump density in the area can be increased to meet the differentiated requirements of high computing power chips for the bump density in the corner area, thereby reducing the risk of fracture of the ELK isolation dielectric layer in the high stress area and improving the operational stability of the chip.

[0062] Specifically, the effect of improving the bump density in this embodiment is described with the following example:

[0063] The high stress preset area in the whole chip is a rectangular vertex area of ​​900um*900um in the whole chip. The smallest bump 3 (first connection bump 31) is 80um in size, and the second preset threshold is 10um. The interval between bumps 3 is 70um, and the spacing between the outermost second UBM pad and the edge of the preset area is [50um, 200um]. The manufacturer's requirement for the lower limit of bump density in the preset area is 23%, and the requirement for the lower limit of bump density in other ground stress areas is 21%.

[0064] Arrangement method 1: In the existing conventional design, the same bump 3 size of 80um is arranged to cover the entire chip area, such as Figure 3 As shown, 36 bumps 3 are set in the entire high stress preset area, and the corresponding bump density (bump density / preset area) is 22.34%. This bump density cannot meet the requirement of the lower limit of the bump density in the high stress preset area.

[0065] Arrangement method 2: Using the method described in this embodiment, the bumps 3 of 80 um are arranged in the area close to the center of the first connection layer 1, and the bumps 3 of 90 um are arranged in the area far from the center of the first connection layer 1 (900 um*900 um rectangular corner area), such as Figure 4 As shown, 36 bumps 3 are also arranged in the entire high stress preset area, and the corresponding bump density (bump density / preset area) is 28.27%. Compared with the existing arrangement of bumps 3, the arrangement of the present invention has a significant improvement in the bump density of the preset area and can meet the requirement of the lower limit of the bump density.

[0066] In addition, during the chip design process, some sensors are set in areas farther from the center, such as the top corner area and / or the edge area. At the same time, these areas are also the areas where deformation and extrusion are most serious. In order to ensure the stability of the sensor, the bumps 3 cannot be placed in these pressure-sensitive areas. This will further reduce the number of bumps 3 set in the high-stress area, thereby affecting the bump density in the area. The existing bump 3 design of the same size cannot meet the bump density requirements of this area.

[0067] Correspondingly, if there is a pressure-sensitive area in the 900um*900um rectangular vertex area in the above example. Figure 3 and Figure 4 The rectangular area in the upper left corner (shown by the dashed line) is used, so the 4 bumps 3 in this area cannot be set. In this case, both arrangement schemes in the above examples can only place 32 bumps 3. Correspondingly, the bump density in the high stress preset area in arrangement method 1 is 19.86% in this case, which does not meet the use requirements. The bump density in the high stress preset area in arrangement method 2 is 25.13% in this case, which meets the use requirements.

[0068] The bump 3 design method of the present invention can arrange smaller bumps 3 in the area close to the center of the first connection layer 1, thereby increasing the number of bumps 3 arranged and the density of bumps 3 arranged, thereby ensuring the high integration of functions in the chip. At the same time, larger bumps 3 are arranged in the high stress preset area, thereby increasing the coverage area of ​​the bumps 3 in the preset area, increasing the bump density, and improving the operating stability of the chip.

[0069] In addition, by setting a larger sized bump 3 in the high stress preset area, not only can the corresponding bump density requirement in the area be met, but also the volume of the bump 3 will increase accordingly as the size of the bump 3 increases. Figure 5As shown, the instant noodles increase their own energy absorption capacity and absorb more energy of the extrusion stress through their own deformation to reduce the extrusion force transmitted to the ELK insulating dielectric layer. On the other hand, due to the increase in the contact area with the UBM pad 2, the pressure at this position will be reduced, thereby further reducing the pressure of the ELK insulating dielectric layer at the connection of the bump 3 in the high stress area, thereby further reducing the risk of the ELK insulating dielectric layer being fractured.

[0070] like Figure 5 As shown, through finite element simulation analysis, the maximum stress values ​​on the three diameters of the bump 3 in the high stress area (triangular area in the upper right corner) are respectively analyzed under the condition of high temperature (240°C) warping deformation of the substrate. Among them, the maximum stress value is the stress value at the top of the bump 3 at the edge of the upper right corner. And the bumps 3 in other areas of the three experimental groups are set with the same size (80um) and arrangement form. The only difference is that the diameters of the bumps 3 arranged in the high stress area are different, which are 80um, 95um and 90um respectively. Specifically, the maximum stress value results on the bumps 3 in the three experimental groups are shown in Table 1 below:

[0071] Table 1

[0072]

[0073] according to Figure 5 In the graph, the darker the color, the smaller the stress, and the lighter the color, the greater the stress. It can be seen that as the distance between the bump 3 and the center increases, the greater the stress value it bears. The closer the bump 3 is to the chip, the higher the stress value.

[0074] It can be seen from the experimental results in the above table that as the size of the bump 3 increases, the maximum stress on the bump 3 decreases, that is, the extrusion pressure transmitted to the ELK isolation dielectric layer decreases.

[0075] Generally, due to the more common sense, when adding a corresponding bump 3 structure between two plate-like objects, the larger the bump 3 is, the more sensitive the large bump 3 will be than the small bump 3 when the plate on one side is deformed and squeezes the other side, and the squeezing force will be more obviously and directly transmitted to the other side. Even in the case of the same warping deformation, the large bump 3 will squeeze the plate on the other side more greatly due to its large volume, which will make it easier to cause the ELK insulating dielectric layer to break. Due to this technical bias, the general perception of those skilled in the art is to keep the bump 3 size as small as possible when the bump density allows, and in high stress areas, they are more willing to set smaller bumps 3 when allowed.

[0076] The arrangement of the bumps 3 in the present invention overcomes the existing technical bias, arranges the bumps 3 of larger size in the high stress area, and further reduces the maximum stress on the bumps 3.

[0077] Furthermore, a chip-to-substrate connection structure further includes: a plurality of first connection bumps 31 , a plurality of second connection bumps 32 and a second connection layer.

[0078] A plurality of first connection bumps 31 are respectively fixed on the first UBM pad layer, and the volume of the first connection bumps 31 is positively correlated with the area of ​​the first UBM pad layer. A plurality of second connection bumps 32 are respectively fixed on the second UBM pad layer, and the volume of the second connection bumps 32 is positively correlated with the area of ​​the second UBM pad layer. The second connection layer is fixedly arranged on the side of the substrate close to the chip. Each first connection bump 31 and each second connection bump 32 are fixedly connected to the second connection layer. Specifically, the second connection layer includes: a protective layer 4 and a plurality of second placement through holes.

[0079] The protective layer 4 is fixedly covered on the metal layer on the side of the substrate close to the chip. The protective layer 4 can be green oil, which refers to the ink coated on the copper foil on the PCB board. This layer of ink can cover unexpected conductors except for the pads, which can avoid welding short circuits during use and extend the service life of the PCB. A plurality of second placement through holes are arranged through the protective layer 4, and the setting positions of the plurality of second placement through holes correspond to the setting positions of the first placement through holes 12 one by one, and the other connection ends of the first connection bumps 31 and the second connection bumps 32 are respectively fixedly arranged in the corresponding second placement through holes.

[0080] As another embodiment of the present invention, a method for determining the UBM in a chip-substrate connection structure is provided, which is used to determine the diameter of the second UBM pad in the above-mentioned chip-substrate connection structure. Due to the limitations of the actual processing technology, in order to ensure a better stable connection between the chip and the substrate. Usually, there are corresponding restrictions on the spacing between any two bumps 3, the size difference between the largest bump 3 and the smallest bump 3, and the distance between the outer bump 3 and the edge of the high stress area. Therefore, how to determine a more suitable diameter size of the second UBM pad has become the key to ensuring the operational stability of the chip.

[0081] The diameter of the second UBM pad is determined as follows:

[0082] S100: Generate an initial diameter value range according to the diameter of the first UBM pad layer and a first preset threshold.

[0083] Specifically, S100 includes:

[0084] S101: Obtain a first preset threshold value Y1. The first preset threshold value is associated with a bump 3 connection process (wafer level bump process) between a chip and a substrate.

[0085] Usually Y1 is related to the processing capability of the wafer-level bump process used by the corresponding processor, and can be specifically determined according to the corresponding processor. In recent years, with the evolution of chip-on-chip process and bump growth process, it is generally acceptable that the height difference of all bumps 3 on the same chip is within 10um, which makes it possible to grow bumps 3 of different sizes on the same chip. Therefore, in order to maximize the size of bump 3, Y1=10um is preferred.

[0086] S102: Based on the diameter F of the first UBM pad 1 and the first preset threshold value Y1 to generate an initial diameter value interval [F 1 , F 1 +Y1].

[0087] The diameter of the first UBM pad is the diameter of the smallest bump 3 in the entire chip. Taking 80um as an example, the corresponding initial diameter value range is [80um, 90um].

[0088] S200: Acquire multiple initial diameter values ​​from an initial diameter value interval.

[0089] Specifically, S200 includes:

[0090] S201: Acquire multiple initial diameter values ​​from an initial diameter value interval according to a preset numerical interval.

[0091] The preset numerical interval can be determined according to the actual usage scenario. For example, the value can be taken in the initial diameter value range of [80um, 90um] with an interval of 5um, and finally multiple initial diameter values ​​of 80um, 85um and 90um are obtained.

[0092] S300: Obtaining the arrangement interval value corresponding to each initial diameter value according to the first mapping table. Specifically, the arrangement interval value includes the distance between two adjacent second UBM pad layers and the distance between the outermost second UBM pad layer and the edge of the preset area.

[0093] The spacing between two adjacent second UBM pads is to prevent two adjacent bumps 3 from sticking together during the manufacturing process. The spacing between the outermost second UBM pad and the edge of the preset area is to prevent two adjacent bumps 3 inside and outside the preset area from sticking together during the manufacturing process. Usually the spacing is an interval value, and the interval can be [50um, 300um]. The spacing between the above two adjacent second UBM pads is related to the specific size of the bump 3. The larger the size of the bump 3, the larger the corresponding arrangement interval value requirement, and different processing manufacturers have different settings for this correspondence. Thus, a corresponding first mapping table can be generated to determine the correspondence between the size of each bump 3 and the arrangement interval value. At the same time, since the size of the bump 3 also has a corresponding positive correlation with the size of the UBM pad 2, the corresponding relationship is also related to the manufacturer's production and preparation process, so different processors will have different corresponding relationships. Therefore, the first mapping table can also include the correspondence between the initial diameter value of the UBM pad 2 and the arrangement interval value. Through collection and sorting, a more complete first mapping table can be established.

[0094] S400: According to each initial diameter value and the corresponding arrangement interval value, determine the number of second UBM pads formed by each initial diameter value in a preset area A1, A2, ..., A i , …, A z Among them, A i is the number of second UBM pads formed by the i-th initial diameter value in the preset area. z is the total number of initial diameter values, i=1, 2, ..., z.

[0095] like Then confirm is the target diameter to generate multiple target diameters. Wherein, ρ is the lower limit of the bump density in the preset area, which is usually provided by the processing manufacturer. S is the total area of ​​the preset area. is the i-th initial diameter value.

[0096] In the present invention, through the diameter of the first UBM pad and the first preset threshold, a more accurate initial diameter value range can be generated according to the size difference between the maximum bump 3 and the minimum bump 3. After meeting this requirement, the coverage area of ​​the second UBM pad formed by each initial diameter value in the preset area can be determined by the arrangement interval value corresponding to each initial diameter value in the initial diameter value range, thereby determining whether it meets the bump density required for stress offset in the area. After the above processing, the available diameter of the second UBM pad that can meet the minimum bump density requirement of a certain area can be more accurately determined to meet the use requirements of different bump densities in different areas, and further ensure the operational stability of the chip.

[0097] S500: Acquire a diameter of a second UBM pad layer from a plurality of target diameters.

[0098] Furthermore, S500 includes:

[0099] S501: Selecting a minimum value among a plurality of target diameters as the diameter of the second UBM pad layer.

[0100] When there are multiple available target diameters, the smallest diameter that meets the requirements can be selected as the diameter of the second UBM pad, thereby further reducing the size difference between the largest bump 3 and the smallest bump 3 on the same chip to reduce the requirements for the board process.

[0101] S600: generating a plurality of corresponding pad layer arrangement positions in a preset area according to the acquired diameter of the second UBM pad layer and the corresponding arrangement interval value, and generating a second UBM pad layer.

[0102] After the corresponding diameter of the second UBM pad layer is determined, a plurality of corresponding pad layer setting positions in the preset area can be determined, and the second UBM pad layer can be generated at the corresponding positions.

[0103] As another embodiment of the present invention, S500: acquiring the diameter of the second UBM pad layer from a plurality of target diameters includes:

[0104] S501: Based on the minimum value and Max (B1, B2, ..., B n , …, B m ) corresponds to the target diameter and generates a secondary value interval. n is the total coverage area of ​​the second UBM pad formed by the nth target diameter in the preset area. m is the total number of target diameters, n=1, 2, ..., m, m≤z. B n The following conditions must be met:

[0105]

[0106] Among them, E n is the total number of second UBM pad layers formed with the nth target diameter arranged in the preset area. is the size value of the nth target diameter.

[0107] S502: Obtain the diameter of the second UBM pad layer from the secondary value interval.

[0108] Because, in the actual arrangement of bumps 3, a larger bump 3 size will usually correspond to a larger arrangement interval to prevent the bumps 3 from sticking during the growth process. Correspondingly, the spacing between the second UBM pads will also increase, so that as the diameter of the second UBM pad increases, the number of settings of the second UBM pad may be reduced, thereby reducing the coverage area and the bump density. Therefore, after further screening of this embodiment, it can be ensured that the target diameters in the secondary value interval will increase with the increase of the diameter value, and the bump density will also increase further, which is a positive correlation. Therefore, when selecting a larger diameter size, although the requirements for the bump 3 board process are increased, more benefits of increased bump density will be obtained. It can be avoided that the requirements for the bump 3 board process are increased, and the bump density will be reduced at the same time. Then, the risk of fracture of the ELK isolation dielectric layer in the high stress area can be further reduced, and the operational stability of the chip can be improved.

[0109] S512: If there is any standard cushion layer diameter that belongs to the secondary value interval, the standard cushion layer diameter is used as the diameter of the second UBM cushion layer.

[0110] The standard cushion diameter is the standard cushion diameter commonly used by existing processing manufacturers. The selection of the standard cushion diameter can facilitate subsequent processing and production, and can be processed in a more mature and commonly used way to ensure the yield of finished products.

[0111] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip-to-substrate connection structure, characterized in that: include: A first connection layer is fixedly arranged on a side of the chip close to the substrate; as well as A plurality of first UBM pads and a plurality of second UBM pads, wherein the plurality of first UBM pads and the second UBM pads are fixed on the first connection layer at intervals, the plurality of first UBM pads are located in an area close to the center of the first connection layer, and the plurality of second UBM pads are located in an area far from the center of the first connection layer; the first UBM pad is the UBM pad with the smallest area in the connection structure, and the second UBM pad is the UBM pad with the largest area in the connection structure; A difference between an area of ​​the second UBM pad layer and an area of ​​the first UBM pad layer is less than or equal to a first preset threshold.

2. The chip-to-substrate connection structure according to claim 1, characterized in that: Also includes: A plurality of first connection bumps are respectively fixed on the first UBM pad layer, and the volume of the first connection bumps is positively correlated with the area of ​​the first UBM pad layer; A plurality of second connection bumps are respectively fixed on the second UBM pad layer, and the volume of the second connection bumps is positively correlated with the area of ​​the second UBM pad layer; the difference between the height of the second connection bump and the height of the first connection bump is less than or equal to a second preset threshold; as well as The second connection layer is fixedly arranged on a side of the substrate close to the chip; each of the first connection bumps and each of the second connection bumps are fixedly connected to the second connection layer.

3. The chip-to-substrate connection structure according to claim 2, characterized in that: The first connection layer comprises: A passivation layer fixedly covers the metal layer on a side of the chip close to the substrate; an energy absorbing layer fixedly covering the passivation layer; and A plurality of first placement through holes penetrate the energy absorption layer and the passivation layer. The placement positions of the plurality of first placement through holes correspond one-to-one to the placement positions of the first UBM pad layer and the second UBM pad layer. A connection end of the first UBM pad layer and the second UBM pad layer is fixedly disposed in the corresponding first placement through holes.

4. The chip-to-substrate connection structure according to claim 3, characterized in that: The second connection layer comprises: A protective layer fixedly covers the metal layer on a side of the substrate close to the chip; and A plurality of second placement through holes are set through the protective layer, and the setting positions of the plurality of second placement through holes correspond one-to-one to the setting positions of the first placement through holes, and the other connection ends of the first connection bump and the second connection bump are fixedly set in the corresponding second placement through holes.

5. The chip-to-substrate connection structure according to claim 1, characterized in that: The first connection layer is rectangular, and the shape of the first connection layer is the same as the shape of the chip; The plurality of second UBM pad layers are located at four corner regions of the first connection layer.

6. The chip-to-substrate connection structure according to claim 5, characterized in that: The vertex area is a rectangle or a triangle.

7. The chip-to-substrate connection structure according to claim 1, characterized in that: The first UBM pad layer and the second UBM pad layer are both cylindrical pad layers; The diameter of the second UBM pad layer is determined according to the following steps: Generate an initial diameter value range according to the diameter of the first UBM cushion layer and a first preset threshold; Acquire multiple initial diameter values ​​from the initial diameter value interval; According to the first mapping table, obtaining the cushion layer spacing value corresponding to each initial diameter value; According to each initial diameter value and the corresponding pad interval value, the number of second UBM pads formed by each initial diameter value in the preset area is determined as A1, A2, ..., A i , …, A z ; Among them, A i is the number of second UBM pads formed by the i-th initial diameter value in the preset area; z is the total number of initial diameter values, i=1, 2, ..., z; like Then confirm is the target diameter to generate multiple target diameters; wherein ρ is the lower limit of the bump density in the preset area; S is the total area of ​​the preset area; is the i-th initial diameter value; The diameter of the second UBM pad layer is obtained from the multiple target diameters.

8. The chip-to-substrate connection structure according to claim 7, characterized in that: Acquiring multiple initial diameter values ​​from the initial diameter value interval includes: According to a preset numerical interval, a plurality of initial diameter values ​​are obtained from the initial diameter value interval.

9. The chip-to-substrate connection structure according to claim 2, characterized in that: The second preset threshold is 10 μm.

10. The chip-to-substrate connection structure according to claim 2, characterized in that: The second preset threshold is positively correlated with the first preset threshold.

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