Micro-nano column array framework metal composite micro bump interconnection structure and preparation method thereof

Abstract

The invention discloses a micro-nano column array framework metal composite micro bump interconnection structure and a preparation method, and relates to the technical field of electronic packaging, the micro-nano column array framework metal composite micro bump interconnection structure comprises a wafer substrate, an insulating layer and a plurality of interconnection members; in the bonding process, due to the capillary action and the pressure resistance of the micro-nano column array, the problem of solder overflow can be effectively solved, the interconnection pitch is remarkably reduced to 5 microns, and the packaging interconnection density is greatly improved; the advantages of the micro-nano structure composite micro salient points are fully exerted, the diffusion reaction contact area between the high-melting-point micro-nano column and the gap low-melting-point metal is greatly increased, and a continuous intermetallic compound network is induced to be rapidly generated in the whole micro-interconnection structure. And a heterogeneous micro-interconnection structure in which the high-melting-point micro-nano cylindrical array, the low-melting-point micro-nano interconnection filling metal and the IMC network coexist is formed, so that low-temperature high-density bonding and high-temperature service are realized, and meanwhile, the requirements of cost, efficiency, manufacturing process compatibility, high performance and high reliability of the interconnection structure are considered.

Description

Technical Field

[0001] The invention relates to the technical field of electronic packaging, and in particular to a micro-nano column array skeleton metal composite micro-bump interconnection structure and a preparation method thereof. Background Art

[0002] Advanced packaging technology represented by three-dimensional packaging realizes vertical interconnection between multiple chips and between chips and adapter boards based on micro-bump and through silicon via (TSV) technology, with advantages such as high interconnection density, miniaturization, low RC delay, high transmission frequency and high bandwidth. Micro-bump technology is the key to realize the miniaturization and high-density integration of advanced packaging systems. The formed micro-interconnection structure plays the role of electrical interconnection and stress buffering. The mainstream micro-bump interconnection technology currently used is the tin-based solder reflow process, which has the advantages of low connection temperature (~250℃) and low cost. In addition, the self-centering and collapse effects that occur during solder reflow reduce the requirements for equipment centering accuracy and substrate flatness.

[0003] The mainstream micro-bump interconnection technology currently used is the tin-based solder reflow process, which has the advantages of low connection temperature (~250℃) and low cost. The self-centering and collapse effects that occur during solder reflow reduce the requirements for equipment centering accuracy and substrate flatness. However, this process also has many limitations. For example, the overflow problem during solder reflow easily causes the risk of short circuits between adjacent solder joints, limiting the further reduction of the interconnection pitch (the minimum pitch of traditional solder micro-bumps is about 40μm); the large-grained intermetallic compound (IMC) brittle phase generated by the interface reaction easily leads to a decrease in the mechanical reliability of the interconnection structure; the interconnection structure has weak current carrying capacity and is prone to electromigration failure. Therefore, in view of the problems of micro-bump miniaturization, material selection, reliability, etc., it is urgent to improve the existing micro-bump interconnection technology to meet the development requirements of high density and high reliability of advanced packaging interconnection technology. Summary of the invention

[0004] The present invention provides a micro-nano column array skeleton metal composite micro-bump interconnection structure, a preparation method and application thereof. During the bonding process, due to the capillary action and pressure resistance of the micro-nano column array, the problem of solder overflow can be effectively overcome, the interconnection pitch can be significantly reduced to 5μm, and the package interconnection density can be greatly improved; the advantages of the micro-nano structure composite micro-bumps are fully utilized to effectively improve the comprehensive performance of the micro-interconnection structure, thereby achieving low-temperature high-density bonding and high-temperature service while taking into account cost, efficiency, manufacturing process compatibility, interconnection structure performance and reliability requirements.

[0005] To achieve the above-mentioned purpose, the present invention provides a micro-nano column array skeleton metal composite micro-bump interconnection structure, comprising a wafer substrate, an insulating layer and a plurality of interconnection components;

[0006] The interconnection component includes a metal pad and a composite micro-bump;

[0007] The insulating layer is located on the upper surface of the wafer substrate, a plurality of the interconnect components are arranged in an array on the insulating layer on the surface of the wafer substrate, the metal pads in the interconnect components are placed on the insulating layer on the surface of the wafer substrate, the insulating layer between the interconnect components is covered with a dielectric layer, and the composite micro-bumps are located above the metal pads.

[0008] In some embodiments, the metal pad includes a base metal and a bonding pad (UBM), the base metal is consistent with the wiring material inside the chip, including but not limited to Al and Cu; the bonding pad is composed of multiple layers of metal, including but not limited to Ti, Cr, Cu, Ni, and Au; the metal pad is connected to the bottom of the composite micro-bump.

[0009] In some embodiments, the composite micro-bump comprises a micro-nano columnar array skeleton and a micro-nano interconnection filling metal. The micro-nano columnar array skeleton includes a plurality of micro-nano columns. The micro-nano columns are in an array form and are arranged in a direction vertically or at a certain inclination angle close to vertical to the metal pad. The micro-nano columns have uniform size and height, and the micro-nano interconnection filling metal is filled between the micro-nano columns.

[0010] In some embodiments, the micro-nano columnar array skeleton is a high melting point metal, and the micro-nano interconnect filler metal can react with the high melting point metal to generate an IMC or a solid solution of a low melting point metal.

[0011] In some embodiments, the diameter of the micro-nano column is between 100 nm and 5 μm, the height of the micro-nano column is between 5 μm and 50 μm, the diameter 2r of the composite micro-bump satisfies: 5 μm≤2r≤50 μm, and the pitch d between two composite micro-bumps satisfies: r≤d≤8r.

[0012] In some embodiments, the micro-nano pillar may be in the shape of a solid cylinder, a cone, or a hollow tube.

[0013] In some embodiments, the insulating layer is made of silicon oxide.

[0014] In some embodiments, the material of the dielectric layer is oxide.

[0015] The present invention provides a method for preparing a micro-nano column array skeleton metal composite micro-bump interconnection structure, which specifically comprises the following steps:

[0016] The first step: providing a wafer substrate, and arranging a plurality of metal pads on the insulating layer above the wafer substrate;

[0017] Step 2: depositing a dielectric layer on the upper surface of the insulating layer and the upper surface of the metal pad, and then performing a chemical mechanical polishing process to expose the upper surface of the metal pad and make it flush with the dielectric layer;

[0018] Step 3: Laminating a porous film layer on the upper surface of the metal pad, wherein the porous film layer is used as a growth template for the metal micro-nano column, forming the metal micro-nano column on the metal pad by electroplating, and controlling the growth height of the metal micro-nano column to be roughly equal to the height of the porous film layer;

[0019] Step 4: removing the porous membrane layer;

[0020] Step 5: depositing a low melting point metal in the gaps between the metal micro-nano pillars by secondary electroplating, and continuing the deposition until the gaps are completely filled and the height after deposition is consistent with the height of the metal micro-nano pillar array, thereby obtaining a wafer with corresponding composite micro-bumps;

[0021] Step 6: Prepare another wafer body by the same method as the above steps 1 to 2;

[0022] Step 7: Flip-chip welding is performed on the micro-bumps of the wafer obtained in the fifth step and the metal pads of the wafer obtained in the sixth step, so that during flip-chip welding, the metal micro-nano column array with a high melting point reacts with the low melting point metal filled in the gap, and a corresponding IMC is generated at the interface between the two, and a continuous IMC network connecting the upper and lower metal pads is induced in the three-dimensional space of the entire micro-interconnect structure, forming a heterogeneous micro-interconnect structure in which a high melting point micro-nano column array, a low melting point micro-nano interconnect filling metal, and IMC coexist.

[0023] In some embodiments, the porous membrane layer is a material group consisting of a mixture of one or more of a free polycarbonate porous membrane layer, an anodized aluminum porous membrane, or a patterned photoresist.

[0024] Compared with the related art, the micro-nano column array skeleton metal composite micro-bump interconnection structure and preparation method provided by the present invention have the following beneficial effects:

[0025] The present invention provides a micro-nano column array skeleton metal composite micro-bump interconnection structure and a preparation method. The micro-bumps are directly prepared in batches on a metal pad by an electrodeposition method without the need to introduce special equipment and complex process technology. The structure has good preparation process compatibility, is highly efficient and controllable, and is low in cost. The morphology, size, and grain structure of the micro-nano columnar array are controllable.

[0026] The present invention provides a micro-nano column array skeleton metal composite micro-bump interconnection structure and a preparation method thereof. The high-melting-point metal micro-nano column array skeleton embedded in the micro-bumps has a capillary effect and compression resistance, which can effectively limit the flow of low-melting-point liquid metal during hot pressing bonding to solve the problem of solder overflow, while maintaining the advantages of traditional solder reflow soldering and significantly reducing the interconnection pitch to 5μm.

[0027] The present invention provides a micro-nano column array skeleton metal composite micro-bump interconnection structure and a preparation method thereof. During the hot pressing bonding process, the high-melting-point metal micro-nano columnar array skeleton can undergo a solid-liquid diffusion reaction with the interstitial low-melting-point metal, inducing the generation of a continuous IMC network in the three-dimensional space of the entire micro-interconnection structure, forming a heterogeneous micro-interconnection structure in which the micro-nano columnar array and the IMC network coexist, greatly improving the high-temperature stability, mechanical and electrical properties, and long-term service reliability of the micro-bumps.

[0028] The present invention provides a micro-nano column array skeleton metal composite micro-bump interconnection structure and a preparation method, which belongs to the general advanced interconnection technology in the field of electronic device chip packaging, so as to realize the stacking interconnection of multi-layer chips in the vertical direction, and greatly improve the packaging density, performance and reliability of electronic devices. For example, it can be used to realize the stacking interconnection of multi-layer chips of high bandwidth memory (HBM) in high-performance computers. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram of the interconnection structure of metal composite micro-bumps in the micro-nano pillar array skeleton;

[0030] Figure 2 It is a three-dimensional schematic diagram of a composite micro-bump interconnection structure;

[0031] Figure 3 It is a schematic diagram of the structure when the upper and lower wafers are flip-chip welded;

[0032] Figure 4 It is a schematic diagram of the preparation method of the present invention;

[0033] Figure 5 The morphology of the solid pillars, conical pillars and conical hole hollow pillars of the micro-nano pillar array;

[0034] Figure 6 It is the grain organization diagram of the cross section of micro-nano pillars;

[0035] Figure 7 The top view and cross-sectional view of the sample of the micro-nano copper pillar array gap filled with tin by electrodeposition;

[0036] Figure 8 It is the cross-section element distribution diagram.

[0037] Numbers in the figure: 1, wafer substrate; 2, insulating layer; 3, dielectric layer; 4, metal pad; 5, composite micro-bump; 6, micro-nano interconnect filling metal; 1', wafer body. DETAILED DESCRIPTION

[0038] To make the purpose, technical solution and advantages of the present invention clearer, the present invention is further described below in conjunction with specific embodiments. The methods are conventional methods unless otherwise specified, and the raw materials can be obtained from public commercial channels unless otherwise specified.

[0039] like Figure 3 As shown, a method for preparing a micro-nano column array skeleton metal composite micro-bump interconnection structure specifically comprises the following steps:

[0040] S1: providing a wafer substrate, and setting a plurality of metal pads on an insulating layer above the wafer substrate;

[0041] S2: depositing a dielectric layer on the upper surface of the insulating layer and the upper surface of the metal pad, and then performing a chemical mechanical polishing process so that the upper surface of the metal pad is exposed and flush with the dielectric layer;

[0042] S3: a porous film layer is pressed on the upper surface of the metal pad, the porous film layer is used as a growth template for the metal micro-nano column, and the metal micro-nano column is formed on the metal pad by electroplating, and the growth height of the metal micro-nano column is controlled to be roughly equal to the height of the porous film layer;

[0043] S4: removing the porous membrane layer;

[0044] S5: depositing a low melting point metal in the gaps between the metal micro-nano pillars by secondary electroplating, and continuing the deposition until the gaps are completely filled and the deposited metal just covers the top of the metal micro-nano pillar array, thereby obtaining a wafer with corresponding composite micro-bumps;

[0045] S6: preparing another wafer by the same method as the first step to the second step;

[0046] S7: Flip-chip welding is performed on the micro-bumps of the wafer obtained in S5 and the metal pads of the wafer obtained in S6, so that during flip-chip welding, the metal micro-nano column array with a high melting point reacts with the low melting point metal filled in the gap, and a corresponding IMC is generated at the interface between the two, and a continuous IMC network connecting the upper and lower metal pads is induced in the three-dimensional space of the entire micro-interconnection structure, forming a heterogeneous micro-interconnection structure with a high melting point micro-nano column array, a low melting point micro-nano interconnection filling metal, and IMC coexisting. .

[0047] During the hot-press bonding process, the high-melting-point metal micro-nano columnar array skeleton can undergo a solid-liquid diffusion reaction with the interstitial low-melting-point metal, inducing the generation of a continuous IMC network in the three-dimensional space of the entire micro-interconnect structure, forming a heterogeneous micro-interconnect structure in which high-melting-point micro-nano column arrays, low-melting-point micro-nano interconnect filling metals, and IMCs coexist, thereby improving the high-temperature stability and comprehensive performance of the micro-bumps.

[0048] Wherein, the porous membrane layer can be a free polycarbonate porous membrane layer, anodized aluminum porous membrane or a patterned photoresist. It is understood that the material of the porous membrane layer is non-restrictive, and any suitable material can be selected to form the first porous membrane layer, as long as it can be used as a growth template for the metal micro-nano column array and can be removed after the array is formed. In addition, the removal method of the porous membrane layer mentioned above is also non-restrictive, and any suitable method can be used to remove it.

[0049] The IMC particle size at the interface generated by the reaction is uniform and much smaller than the particle size of the intermetallic compound particles prepared by the general process, avoiding the technical difficulties of directly preparing small-sized intermetallic compound nanoparticles. The micro-bumps are prepared in batches directly on the metal pad by electrodeposition, without the need to introduce special equipment and complex process technology, with good preparation process compatibility, high efficiency, controllability and low cost.

[0050] Embodiment 1

[0051] This embodiment provides a micro-nano column array skeleton metal composite micro-bump interconnection structure, such as Figure 1 As shown, the present invention includes a wafer substrate 1, an insulating layer 2 and a plurality of interconnection components;

[0052] The interconnection component includes a metal pad 4 and a composite micro-bump 5;

[0053] The insulating layer 2 is located on the upper surface of the wafer substrate 1, and a plurality of interconnect components are arranged in an array on the insulating layer 2 on the surface of the wafer substrate 1. The metal pads 4 in the interconnect components are placed on the insulating layer 2 on the surface of the wafer substrate 1. The insulating layer 2 between the interconnect components is covered with a dielectric layer 3, and the composite micro-bumps 5 are located above the metal pads 4.

[0054] In this embodiment, the metal pad includes a base metal and a bonding pad (UBM), wherein the base metal is consistent with the wiring material inside the chip, including but not limited to Al and Cu; the bonding pad is composed of multiple layers of metal, including but not limited to Ti, Cr, Cu, Ni, and Au. The metal pad is connected to the bottom of the composite micro-bump. The material of the insulating layer 2 is silicon oxide. The material of the dielectric layer 3 is an oxide, preferably silicon dioxide.

[0055] The composite micro-bump 5 comprises a micro-nano columnar array skeleton and a micro-nano interconnection filling metal 6. The micro-nano columnar array skeleton comprises a plurality of micro-nano columns. The micro-nano columns are in an array form and are arranged vertically or at a certain inclination angle in a direction perpendicular to the metal pad. The micro-nano columns have uniform size and uniform height. The micro-nano interconnection filling metal 6 is filled between the micro-nano columns.

[0056] The micro-nano columnar array skeleton is a high melting point metal, and the micro-nano interconnect filling metal 6 can react with the high melting point metal to generate an IMC or a solid solution of a low melting point metal.

[0057] In this embodiment, the high melting point metal includes but is not limited to pure metals of Au, Ag, Cu, Ni or alloys of Au, Ag, Cu, Ni, and the low melting point metal includes but is not limited to pure metals of Sn, In, Ga or alloys of Sn, In, Ga.

[0058] The diameter of the micro-nano column is between 100nm and 5μm, the height of the micro-nano column is between 5μm and 50μm, the diameter 2r of the composite micro-bump satisfies: 5μm≤2r≤50μm, and the pitch d between two composite micro-bumps satisfies: r≤d≤8r.

[0059] The morphology of the micro-nano column can be solid cylindrical, conical or hollow tubular.

[0060] In this embodiment, the morphology, size and grain structure of the micro-nano columnar array are controllable.

[0061] The high-melting-point metal micro-nano columnar array skeleton embedded in the micro-bumps has a capillary effect and pressure resistance, which can effectively limit the flow of low-melting-point liquid metal during hot-press bonding and solve the problem of solder overflow. It not only maintains the advantages of traditional solder reflow soldering, but also can significantly reduce the interconnection pitch to 5μm.

[0062] Regarding the morphology of the micro-nano copper pillar array, the electroplating process parameters (including but not limited to current density, additives, and electroplating temperature) can be adjusted to prepare the following: Figure 5 The top view and side view of the solid column, tapered column and hollow column with tapered hole are shown in Figure 5 .

[0063] The grain size can also be adjusted by adjusting the process parameters. The cross-sectional grain structure diagram is shown in Figure 6 shown.

[0064] In order to ensure that the low melting point metal evenly fills the gaps of the high melting point metal micro-nano column array, it is often necessary to add a series of additives to the plating solution, including but not limited to:

[0065] 1. Main brightener (mainly responsible for the brightening effect of the coating, capable of forming a bright and smooth coating within a wide current density range), including:

[0066] Alkyl sulfonic acids (such as methanesulfonic acid, ethylsulfonic acid);

[0067] Aromatic compounds (such as benzenesulfonic acid, toluenesulfonic acid).

[0068] 2. Auxiliary brightener (used with the main brightener to further enhance the brightness and leveling of the coating), including:

[0069] Polyethylene glycol (PEG);

[0070] Polyacrylamide (PAM);

[0071] Alcohol compounds (such as glycerol, ethylene glycol).

[0072] 3. Wetting agent (reduces the surface tension of the plating solution and improves the coverage and uniformity of the coating), including:

[0073] Sodium dodecyl sulfate (SDS);

[0074] Polyoxyethylene ethers.

[0075] 4. Leveling agent (to improve the flatness of the coating, reduce defects such as pinholes and roughness), including:

[0076] Sulfur-containing organic compounds (such as thioglycolic acid, mercaptobenzoic acid);

[0077] Benzotriazole (BTA).

[0078] Example: Figure 7 The top view and cross-sectional view of the sample in which tin is electrodeposited in the gap of a micro-nano copper pillar array with a diameter of about 200 nm. As time goes by, the gap is gradually filled with tin. The time and conditions for the gap of the micro-nano pillar array to be filled with low-melting-point metal are preferred, and the situation of 15 minutes in the figure is ideal.

[0079] Figure 8 This is an enlarged cross-sectional element distribution diagram under corresponding conditions. It can be seen that the high-melting-point micro-nano column array is uniformly embedded in the low-melting-point metal, which is similar to the morphology before secondary electroplating.

[0080] The present invention belongs to the general advanced interconnection technology in the field of electronic device chip packaging, which can realize the stacking interconnection of multi-layer chips in the vertical direction, greatly improving the packaging density, performance and reliability of electronic devices. For example, it can be used to realize the stacking interconnection of multi-layer chips of high bandwidth memory (HBM) in high-performance computers.

[0081] Working principle: specially designed micro-nano structure micro-bumps, i.e. metal composite micro-bumps with micro-nano columnar array skeleton structure, each micro-bump contains multiple micro-nano columns (i.e. micro-nano column array) with uniform size and uniform height vertically or nearly vertically to the pad, and the gaps between the micro-nano columns are densely filled with another metal. Among them, the micro-nano columnar array skeleton is a high melting point metal (including but not limited to Au, Ag, Cu, Ni pure metal or Au, Ag, Cu, Ni alloy), and the metal filled in the gap of the micro-nano columnar array skeleton is a low melting point metal (including but not limited to Sn, In, Ga pure metal or Sn, In, Ga alloy) that can react with the above high melting point metal to form IMC or solid solution. The size and morphology of the micro-nano column in the micro-bump can be adjusted, the diameter of the micro-nano column can be adjusted from 100nm to 5μm, and the height can be adjusted from 5μm to 50μm. The morphology of the micro-nano column can be solid cylindrical, conical or hollow tubular, and the grain structure (grain size and orientation) of the micro-nano column can be adjusted. The formed micro-interconnection structure is a heterogeneous micro-interconnection structure in which high-melting-point micro-nano pillar arrays, low-melting-point micro-nano interconnection filling metals, and IMC coexist. The organizational structure can be adjusted by adjusting the original organizational structure of the composite micro-bumps, including the contact area between high and low melting point metals, the composition ratio and spatial distribution, so as to regulate the microstructure of the micro-interconnection structure and improve the high-temperature stability and comprehensive performance of the micro-bumps.

Claims

1. A micro-nano column array skeleton metal composite micro-bump interconnection structure, characterized in that: It includes a wafer substrate, an insulating layer and a plurality of interconnection components; The interconnection component includes a metal pad and a composite micro-bump; The insulating layer is located on the upper surface of the wafer substrate, a plurality of the interconnect components are arranged in an array on the insulating layer on the surface of the wafer substrate, the metal pads in the interconnect components are placed on the insulating layer on the surface of the wafer substrate, the insulating layer between the interconnect components is covered with a dielectric layer, and the composite micro-bumps are located above the metal pads.

2. The micro-nano array skeleton metal composite micro-bump interconnection structure according to claim 1, characterized in that: The metal pad comprises a base metal and a pad, the base metal is consistent with the wiring material inside the chip, the pad is composed of multiple layers of metal, and the metal pad is connected to the bottom of the composite micro-bump.

3. The micro-nano column array skeleton metal composite micro-bump interconnection structure according to claim 1, characterized in that: The composite micro-bump comprises a micro-nano columnar array skeleton and a micro-nano interconnection filling metal. The micro-nano columnar array skeleton comprises a plurality of micro-nano columns. The micro-nano columns are in an array form and are arranged vertically or at a certain inclination angle close to vertical to the metal pad. The micro-nano columns have uniform size and uniform height. The micro-nano interconnection filling metal is filled between the micro-nano columns.

4. The micro-nano column array skeleton metal composite micro-bump interconnection structure according to claim 3, characterized in that: The micro-nano columnar array skeleton is a high melting point metal, and the micro-nano interconnect filling metal is a low melting point metal that can react with the high melting point metal to generate IMC or solid solution.

5. The micro-nano column array skeleton metal composite micro-bump interconnection structure according to claim 3, characterized in that: The diameter of the micro-nano column is between 10 nm and 5 μm, the height of the micro-nano column is between 5 μm and 50 μm, the diameter 2r of the composite micro-bump satisfies: 5 μm≤2r≤50 μm, and the pitch d between two composite micro-bumps satisfies: r≤d≤8r.

6. The micro-nano column array skeleton metal composite micro-bump interconnection structure according to claim 1, characterized in that: The micro-nano column may have a solid cylindrical shape, a cone shape or a hollow tube shape.

7. The micro-nano column array skeleton metal composite micro-bump interconnection structure according to claim 1, characterized in that: The material of the insulating layer is silicon oxide.

8. The micro-nano column array skeleton metal composite micro-bump interconnection structure according to claim 1, characterized in that: The material of the dielectric layer is oxide.

9. A method for preparing a metal composite micro-bump interconnection structure using a micro-nano column array skeleton as claimed in any one of claims 1 to 6, characterized in that: The specific steps include: The first step: providing a wafer substrate, and arranging a plurality of metal pads on the insulating layer above the wafer substrate; Step 2: depositing a dielectric layer on the upper surface of the insulating layer and the upper surface of the metal pad, and then performing a chemical mechanical polishing process to expose the upper surface of the metal pad and make it flush with the dielectric layer; Step 3: Laminating a porous film layer on the upper surface of the metal pad, wherein the porous film layer is used as a growth template for the metal micro-nano column, forming the metal micro-nano column on the metal pad by electroplating, and controlling the growth height of the metal micro-nano column to be roughly equal to the height of the porous film layer; Step 4: removing the porous membrane layer; Step 5: depositing a low melting point metal in the gaps between the metal micro-nano pillars by secondary electroplating, and continuing the deposition until the gaps are completely filled and the height after deposition is consistent with the height of the metal micro-nano pillar array, thereby obtaining a wafer with corresponding composite micro-bumps; Step 6: Prepare another wafer by the same method as Steps 1 to 2 above; Step 7: Flip-chip welding is performed on the micro-bumps of the wafer obtained in the fifth step and the metal pads of the wafer obtained in the sixth step, so that during flip-chip welding, the metal micro-nano column array with a high melting point reacts with the low melting point metal filled in the gap, and a corresponding IMC is generated at the interface between the two, and a continuous IMC network connecting the upper and lower metal pads is induced in the three-dimensional space of the entire micro-interconnect structure, forming a heterogeneous micro-interconnect structure in which a high melting point micro-nano column array, a low melting point micro-nano interconnect filling metal, and IMC coexist.

10. The method for preparing the micro-nano column array skeleton metal composite micro-bump interconnection structure according to claim 1, characterized in that: The porous membrane layer is a free polycarbonate porous membrane layer, an anodized aluminum porous membrane or a patterned photoresist.

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