Semiconductor device and forming method and stress testing method thereof

Abstract

The embodiment of the invention provides a semiconductor device, a forming method thereof and a stress testing method. The semiconductor device includes: an interposer; a metal structure in the interposer; the at least one test structure is located in the intermediate layer, is adjacent to the metal structure and is used for monitoring the stress of the metal structure; each test structure comprises a first electrode parallel to the adjacent surface of the metal structure, and a first dielectric layer and a second electrode which sequentially cover the surface of the first electrode.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor device and a forming method thereof, and a stress testing method thereof. Background Art

[0002] With the development of three-dimensional integrated circuits (3DIC), through silicon via (TSV) technology provides mechanical support, thermal conductivity and electrical connection for vertically stacked chips in 3DIC; however, the multi-layer interface structure of TSV and the difference in coefficient of thermal expansion (CTE) between layers will cause complex thermal stress in the TSV structure under heating conditions, thereby reducing the performance of 3DIC. Therefore, it is urgent to provide an effective test structure and test method to monitor the stress of TSV. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor device, a method for forming the same, and a stress testing method.

[0004] In a first aspect, an embodiment of the present disclosure provides a semiconductor device, including:

[0005] Intermediary layer;

[0006] a metal structure located in the interposer;

[0007] At least one test structure is located in the intermediate layer and is arranged adjacent to the metal structure, for monitoring the stress of the metal structure; each of the test structures includes a first electrode parallel to a surface adjacent to the metal structure, and a first dielectric layer and a second electrode sequentially covering the surface of the first electrode.

[0008] In some embodiments, the semiconductor device further comprises:

[0009] At least one reference structure is located in the interposer and away from the metal structure, and is used to provide a reference for the test structure to monitor the stress; each reference structure has the same structure as the corresponding test structure.

[0010] In some embodiments, the test structure is in the shape of a plate and is parallel to a radial surface of the metal structure, and is used to test the radial stress of the metal structure.

[0011] In some embodiments, the first electrode is a flat plate with an I-shaped cross section, and the first electrode is parallel to a radial surface of the metal structure; the first dielectric layer and the second electrode sequentially cover the surface of at least one side of the first electrode; or,

[0012] The first electrode is a flat plate with a U-shaped cross section, and the bottom surface of the first electrode is parallel to a radial surface of the metal structure; the first dielectric layer and the second electrode sequentially cover the inner wall of the first electrode, and the first dielectric layer and the second electrode are both flat plates with a U-shaped cross section.

[0013] In some embodiments, the test structure is annular and parallel to the axial surface of the metal structure, and is used to test the axial stress of the metal structure.

[0014] In some embodiments, the first electrode is a ring with an I-shaped cross section, and the first electrode is parallel to the axial surface of the metal structure; the first dielectric layer and the second electrode sequentially cover the surface of at least one side of the first electrode; or,

[0015] The first electrode is a ring with a U-shaped cross section, and both sides of the first electrode are parallel to the axial surface of the metal structure; the first dielectric layer and the second electrode sequentially cover the inner wall of the first electrode, and the first dielectric layer and the second electrode are both rings with a U-shaped cross section.

[0016] In some embodiments, each of the test structures further comprises:

[0017] a first connecting wire, the first connecting wire being connected to the first electrode and being used to apply a first voltage to the first electrode;

[0018] A second connecting wire is connected to the second electrode and is used to apply a second voltage to the second electrode.

[0019] In a second aspect, an embodiment of the present disclosure provides a method for forming a semiconductor device, comprising:

[0020] Provide an intermediary layer;

[0021] forming a metal structure, the metal structure being located in the interposer; and,

[0022] At least one test structure is formed, and the at least one test structure is located in the intermediate layer and is arranged adjacent to the metal structure for monitoring the stress of the metal structure; each of the test structures includes a first electrode parallel to a surface adjacent to the metal structure, and a first dielectric layer and a second electrode sequentially covering the surface of the first electrode.

[0023] In some embodiments, while forming the at least one test structure, the method further comprises:

[0024] At least one reference structure is formed, and the at least one reference structure is located in the interposer and is arranged away from the metal structure, and is used to provide a reference benchmark for the test structure when monitoring the stress; each of the reference structures has the same structure as the corresponding test structure.

[0025] In a third aspect, an embodiment of the present disclosure provides a stress testing method, which is used to perform stress testing on a semiconductor device described in any one of the above embodiments, and the stress testing method includes:

[0026] applying a first voltage and a second voltage to a first electrode and a second electrode in the test structure, respectively, to determine a capacitance value of the test structure; and,

[0027] Applying the first voltage and the second voltage to a first electrode and a second electrode in a corresponding reference structure, respectively, to determine a capacitance value of the corresponding reference structure;

[0028] Based on the capacitance value of the test structure and the corresponding capacitance value of the reference structure, the stress of the metal structure is determined.

[0029] The disclosed embodiments provide a semiconductor device and a method for forming the same, as well as a stress testing method; wherein the semiconductor device comprises: an interposer; a metal structure located in the interposer; at least one test structure located in the interposer and disposed adjacent to the metal structure, for monitoring the stress of the metal structure; each test structure comprises a first electrode parallel to a surface adjacent to the metal structure, and a first dielectric layer and a second electrode sequentially covering the surface of the first electrode. Since the test structure comprises a first electrode, and a first dielectric layer and a second electrode covering the surface of the first electrode, and the test structure is disposed parallel to the surface adjacent to the metal structure, after the stress in the metal structure is transferred to the test structure, the spacing between the first electrode and the second electrode in the test structure can be changed, that is, the capacitance value of the test structure can be changed; in this way, the stress change of the metal structure can be monitored according to the capacitance value of the test structure, thereby controlling the stress of the metal structure, which has the advantages of simple operation and easy implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0031] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure Figure 1 ;

[0032] Figure 2 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure Figure 2 ;

[0033] Figure 3 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure Figure 3 ;

[0034] Figure 4 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure Figure 4 ;

[0035] Figure 5 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure Figure 5 ;

[0036] Figure 6 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure Figure 6 ;

[0037] Figure 7 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure Figure 7 ;

[0038] Figure 8 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure Figure 8 ;

[0039] Fig. 9 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure Figure 9 ;

[0040] Fig.10 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure Figure 10 ;

[0041] Fig.11 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure Figure 10 one;

[0042] Fig.12 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure Figure 10 two;

[0043] Fig.13 A schematic diagram of a process for forming a semiconductor device according to an embodiment of the present disclosure;

[0044] Figures 14 to 19 A schematic diagram of a structure in a process of forming a semiconductor device provided by an embodiment of the present disclosure;

[0045] Fig. 20A schematic flow chart of a method for testing a semiconductor device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0047] In the following description, a large number of details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0048] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0049] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0050] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0051] Hereinafter, the semiconductor device and its forming method and stress testing method in the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0052] Before introducing the embodiments of the present disclosure, various directions that may be involved in the embodiments of the present disclosure are first defined: a direction perpendicular to the plane where the semiconductor device is located is defined as a Z direction, and an intersecting X direction and Y direction are defined in the plane where the semiconductor device is located.

[0053] The present disclosure provides a semiconductor device 100. Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure, such as Figure 1 As shown, the semiconductor device 100 includes: an interposer 110; a metal structure 120, which is located in the interposer 110; at least one test structure 130, which is located in the interposer 110 and is arranged adjacent to the metal structure 120, for monitoring the stress of the metal structure 120; each test structure 130 includes a first electrode 131 parallel to a surface adjacent to the metal structure 120, and a first dielectric layer 132 and a second electrode 133 that sequentially cover the surface of the first electrode 131.

[0054] In the embodiment of the present disclosure, the material of the intermediate layer 110 may be silicon (Si), germanium (Ge), or may include other semiconductor elements, such as: silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys, such as: silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or a combination thereof.

[0055] In the embodiment of the present disclosure, the metal structure 120 specifically refers to a structure with stress in the semiconductor device; for example, TSV, rewiring or hybrid bond (HB), etc. The shape of the metal structure can be any suitable shape; for example, a cylindrical shape (such as Figure 1 As shown), prismatic (as Figure 2 As shown), truncated cone, etc. In addition, the material of the metal structure 120 includes tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, silicide (WSix, CoSix, NiSix, AlSix, etc.), metal alloy or any combination thereof.

[0056] In the embodiment of the present disclosure, the number of the test structures 130 can be set according to actual needs. Figure 1 , a test structure 130 may be set to monitor the axial stress of the metal structure 120; for another example, please refer to Figure 2 , a test structure 130 a may be provided to monitor the radial stress of the metal structure 120 , and a test structure 130 b may be provided to monitor the axial stress of the metal structure 120 .

[0057] In this disclosure, please continue to refer to Figure 1 Since the first electrode 131 is parallel to the surface adjacent to the metal structure 120 , and the first dielectric layer 132 and the second electrode 133 sequentially cover the surface of the first electrode 131 , the test structure 130 is parallel to the surface adjacent to the metal structure 120 .

[0058] It should be noted that when the test structure 130 is parallel to one or more surfaces of the metal structure 120, the shape of the test structure 130 is the same as the shape of the one or more surfaces; for example, please refer to Figure 1 Test structure 130 in or Figure 2 The test structure 130b in the embodiment is in the shape of a ring surrounding the side wall of the metal structure 120; for example, please refer to Figure 2 The test structure 130a in the embodiment is in the shape of a flat plate parallel to the top surface of the metal structure 120; thus, the stress of the metal structure 120 can be uniformly transferred to the test structure.

[0059] In this disclosure, please continue to refer to Figure 1 The materials of the first electrode 131 and the second electrode 133 may include metal nitride or metal silicide, for example, titanium nitride. The material of the first dielectric layer 132 may include a high-K dielectric material, for example, lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), hafnium silicate (HfSiO x ) or zirconium oxide (ZrO2) or any combination thereof. In other embodiments, the material of the first electrode 131 and the second electrode 133 may also be polycrystalline silicon.

[0060] In the embodiment of the present disclosure, since the test structure includes a first electrode, and a first dielectric layer and a second electrode covering the surface of the first electrode, and the test structure is arranged in parallel with the surface adjacent to the metal structure, after the stress in the metal structure is transferred to the test structure, the distance between the first electrode and the second electrode in the test structure can be changed, that is, the capacitance value of the test structure can be changed; in this way, the stress change of the metal structure can be monitored according to the capacitance value of the test structure, thereby controlling the stress of the metal structure, which has the advantages of simple operation and easy implementation.

[0061] Next, please refer to Figures 3 to 10 , taking the cylindrical metal structure 120 as an example, the structure of the semiconductor device 100 is described in detail.

[0062] In some embodiments, please refer to Figures 3 to 7 In any one of the embodiments, the test structure 130 may be annular and parallel to the axial surface of the metal structure 120 , and is used to test the axial stress of the metal structure 120 .

[0063] In the embodiment of the present disclosure, since the test structure 130 is arranged axially around the metal structure 120 and the test structure 130 is parallel to the surface of the metal structure 120, on the one hand, the axial stress squeezes the first electrode 131 and the second electrode 133, causing the capacitance value of the test structure 120 to change, thereby monitoring the axial stress inside the metal structure 120; on the other hand, it helps the test structure 130 to receive all axial stress changes in the metal structure 120, reducing errors caused by angle deviation or improper test position.

[0064] In some embodiments, the first electrode 131 is a ring with an I-shaped cross section, and the first electrode 131 is parallel to the axial surface of the metal structure 120 ; the first dielectric layer 132 and the second electrode 133 sequentially cover the surface of at least one side of the first electrode 131 .

[0065] For example, see Figure 3 and Figure 4 The first electrode 131 is a ring with an I-shaped cross-section, and the first electrode 131 is parallel to the axial surface of the metal structure 120; the first dielectric layer 132 and the second electrode 133 sequentially cover the surface of the first electrode 131 away from the metal structure 120 (that is, the first dielectric layer 132 and the second electrode 133 are both rings with an I-shaped cross-section).

[0066] For example, please refer to Figure 5 The first electrode 131 is a ring with an I-shaped cross-section, and the first electrode 131 is parallel to the axial surface in the metal structure 120; the first dielectric layer 132 and the second electrode 133 sequentially cover the surface of the first electrode 131 (that is, the first dielectric layer 132 and the second electrode 133 are both rings with a U-shaped cross-section).

[0067] Please note that, please refer to Figure 3 , the lengths of the test structure 130 and the metal structure 120 in the Z direction can be the same, so that the area of ​​the test structure 130 receiving stress can be larger, making the test structure 130 more sensitive. Figure 4 and Figure 5 The lengths of the test structure 130 and the metal structure 120 in the Z direction may be different, so that the axial stress of a specified area can be tested and the volume of the test structure 130 can be reduced.

[0068] It should also be noted that in the embodiment of the present disclosure, the shape of the first electrode 131 (e.g., I-shaped) refers to the shape of the effective cross-sectional area of ​​the first electrode 131 on the plane where the X and Z directions are located. In fact, in order to facilitate the electrical connection between the first electrode 131 and the second electrode 133 and the external structure, the first electrode 131 and the second electrode 133 also include a laterally extending connecting portion (e.g., Figure 3 and Figure 5 The shapes of the electrodes in the subsequent descriptions can be understood with reference to the above explanations.

[0069] In some embodiments, please refer to Figure 6 and Figure 7 The first electrode 131 is a ring with a U-shaped cross-section, and both sides of the first electrode 131 are parallel to the axial surface of the metal structure 120; the first dielectric layer 132 and the second electrode 133 sequentially cover the inner wall of the first electrode 131, and the first dielectric layer 132 and the second electrode 133 are both rings with a U-shaped cross-section.

[0070] In the embodiments of this disclosure, please refer to Figure 7 In order to reduce the axial support formed by the connecting portion A extending laterally between the first electrode 131 and the second electrode 133, the connecting portion A can be arranged on the outside of the test structure 130, that is, the area B close to the side of the metal structure 120 does not have a connecting portion. In this way, the sensitivity of the test structure 130 can be made higher.

[0071] In some embodiments, please refer to Figures 8 to 10 In any one of the above, the test structure 130 is in the shape of a plate and is parallel to a radial surface of the metal structure 120 , and is used to test the radial stress of the metal structure 120 .

[0072] In the disclosed embodiment, since the flat test structure 130 is parallel to a radial surface of the metal structure 120, the stress transmitted from the surface can squeeze the first electrode 131 and the second electrode 133, causing the capacitance value of the test structure to change, thereby monitoring the radial stress.

[0073] In other embodiments, the flat plate-shaped test structure 130 may also be parallel to an axial surface of the metal structure 120, for example, Figure 2 A side wall of the metal structure 120 is shown, so that the stress in the corresponding direction can be tested as required.

[0074] In some embodiments, the first electrode 131 is a flat plate with an I-shaped cross-section and is parallel to a radial surface of the metal structure 120 ; the first dielectric layer 132 and the second electrode 133 sequentially cover the surface of at least one side of the first electrode 131 .

[0075] For example, see Figure 8 The first electrode 131 is a flat plate with an I-shaped cross-section, and the first electrode 131 is parallel to a radial surface of the metal structure 120; the first dielectric layer 132 and the second electrode 133 sequentially cover the surface of the first electrode 131 away from the metal structure 120.

[0076] For example, please refer to Fig. 9 The first electrode 131 is a flat plate with an I-shaped cross-section, and the first electrode 131 is parallel to a radial surface of the metal structure 120; the first dielectric layer 132 and the second electrode 133 sequentially cover the surface of the first electrode 131 close to the metal structure 120; wherein the first dielectric layer 132 and the second electrode 133 are both flat plates with a U-shaped cross-section.

[0077] In some embodiments, please refer to Fig.10 The first electrode 131 is a flat plate with a U-shaped cross-section, and the bottom surface of the first electrode 131 is parallel to a radial surface of the metal structure 120; the first dielectric layer 132 and the second electrode 133 sequentially cover the inner wall of the first electrode 131, and the first dielectric layer 132 and the second electrode 133 are both flat plates with a U-shaped cross-section.

[0078] It should be noted that Figures 3 to 10 The structures in the figure are only some examples of the test structure 130. The structure of the test structure 130 may also be other suitable structures, which is not limited by the present disclosure. In addition, the number and structure of the test structure 130 in the semiconductor device 100 may be selected according to actual needs.

[0079] It is also necessary to note that please refer to Figures 3 to 7 , Fig.10 , the test structure 130 may also not be in contact with the metal structure 120; or, please refer to Figure 8 and Fig. 9 When the metal structure 120 does not affect the charge amount of the electrode on the test structure 130 , the test structure 130 may also contact the metal structure 120 .

[0080] In the embodiments of this disclosure, please refer to Figures 3 to 10 In any one of the above, the interposer 110 may include a first sub-interposer 111 and a second sub-interposer 112. The materials of the first sub-interposer 111 and the second sub-interposer 112 may be any suitable material; for example, the material of the first sub-interposer 111 may be silicon; and the material of the second sub-interposer may be silicon oxide.

[0081] In this disclosure, please continue to refer to Figures 3 to 10 In order to prevent the test structure 130 from leaking electricity, the semiconductor device 100 further includes an isolation structure 150 located outside the test structure 130; wherein the material of the isolation structure 150 can be any insulating material, such as silicon oxide. It should be noted that the second sub-interposer and the isolation structure 150 are made of the same material, so Figures 3 to 10 The isolation structure 150 between the test structure 130 and the second sub-interposer 112 is not shown.

[0082] In some embodiments, the semiconductor device 100 further includes: at least one reference structure 140 located in the interposer 110 and away from the metal structure 120 , for providing a reference benchmark for the test structure 130 when monitoring stress; each reference structure 140 has the same structure as the corresponding test structure 130 .

[0083] In the disclosed embodiment, the reference structure 140 and the test structure 130 correspond one to one, and the reference structure 140 and the corresponding test structure 130 have the same process and material; it can be understood that the reference structure 140 and the corresponding test structure 130 are formed at the same time.

[0084] For example, please refer to Fig.11 When the test structure 130 is arranged around the metal structure 120, the reference structure 140 has the same shape and size as the test structure 130 and is arranged on the outside of the metal structure 120; in this way, the accuracy of the reference structure 140 in providing a reference benchmark for monitoring axial stress can be guaranteed.

[0085] For example, please refer to Fig.12 When the test structure 130a is arranged on the surface of the radial side of the metal structure 120, the reference structure 140a has the same shape and size as the test structure 130a and is arranged on the outside of the metal structure 120; and when the test structure 130b is arranged around the metal structure 120b, the reference structure 140b has the same shape and size as the test structure 130b and is arranged on the outside of the metal structure 120; in this way, the accuracy of the reference structures 140a and 140b in providing a reference benchmark for monitoring radial stress and axial stress can be guaranteed.

[0086] Please note that, please refer to Fig.12When the semiconductor device 100 includes a plurality of test structures 120 , the position distribution between the plurality of reference structures 140 is the same as the position distribution between the plurality of test structures 120 ; thus, the influence of other factors on the test results can be reduced.

[0087] For further information, please refer to Fig.11 Each reference structure 140 includes a third electrode 141, a second dielectric layer 142 and a fourth electrode 143; wherein, in the reference structure 140 and the corresponding test structure 130, the third electrode 141 and the first electrode 131, the second dielectric layer 142 and the first dielectric layer 132, and the fourth electrode 143 and the second electrode 133 have the same materials and sizes.

[0088] In addition, the difference between the test structure 130 and the corresponding reference structure 140 is that the metal structure 120 is not arranged around the reference structure 140, and the test structure 130 is arranged outside the metal structure 120; since the metal structure 120 is not arranged around the reference structure 140, the stress of the metal structure 120 will not affect the reference structure 140, so that the capacitance value of the reference structure 140 can be used as a reference benchmark for the test structure 130.

[0089] In some embodiments, please refer to Fig.11 Each test structure 130 further includes: a first connecting wire 134 and a second connecting wire 135 , wherein the first connecting wire 134 is connected to the first electrode 131 for applying a first voltage to the first electrode 131 ; and the second connecting wire 135 is connected to the second electrode 133 for applying a second voltage to the second electrode 133 .

[0090] In the embodiment of the present disclosure, since the first connecting wire 134 is connected to the first electrode 131, and the second connecting wire 135 is connected to the second electrode 133, the capacitance value of the test structure 130 can be tested by the voltages (i.e., the first voltage and the second voltage) applied by the first connecting wire 134 and the second connecting wire 135. Here, the first voltage and the second voltage can change over time, thereby changing the amount of charge stored in the test structure 130, and then the capacitance value of the test structure can be determined by the amount of charge stored on the first electrode 131 and the second electrode 133 and the charging voltage of the test structure 130.

[0091] During implementation, the voltage between the first electrode 131 and the second electrode 133 (i.e., the charging voltage) ranges from -3 to 3V, the frequency ranges from 50KHz to 1MHz, and the amplitude voltage is 0.1V, thereby measuring the capacitance value of the test structure 130; specifically, the charging voltage can be 1V (not higher than the breakdown voltage), the frequency can be 100KHz, and the amplitude voltage can be 0.1V.

[0092] In this disclosure, please continue to refer to Fig.11 Each reference structure 140 further includes: a third connecting wire 144 and a fourth connecting wire 145, the third connecting wire 144 is connected to the third electrode 141 for applying a first voltage to the third electrode 141; the fourth connecting wire 145 is connected to the fourth electrode 143 for applying a second voltage to the fourth electrode 143.

[0093] In the embodiment of the present disclosure, the voltage applied to the third electrode 141 and the fourth electrode 143 in the reference structure 140 is the same as the first electrode 131 and the second electrode 133 in the corresponding test structure 130. For example, the charging voltage of the third electrode 141 and the fourth electrode 143 in the reference structure 140 may also be 1V (not higher than the breakdown voltage), the frequency may also be 100KHz, and the amplitude voltage may also be 0.1V.

[0094] In the embodiment of the present disclosure, since the reference structure 140 and the corresponding test structure 130 have the same structure, and the spacing between the third electrode 141 and the fourth electrode 143 in the reference structure will not be affected by the stress in the metal structure 120, that is, the capacitance value of the reference structure 140 will not be affected by the stress in the metal structure 120, when the reference structure 140 is tested using the same test method (that is, test voltage) as the corresponding test structure 130, the capacitance value of the reference structure 140 can be used as a reference benchmark for the capacitance value of the test structure 100.

[0095] In the embodiment of the present disclosure, the materials of the first connecting wire 134, the second connecting wire 135, the third connecting wire 144 and the fourth connecting wire 145 include tungsten, cobalt, copper, titanium, tantalum, aluminum, titanium nitride, tantalum nitride, nickel, silicide, metal alloy or any combination thereof.

[0096] In short, in the embodiment of the present disclosure, the test structure includes a first electrode, a first dielectric layer covering the surface of the first electrode, and a second electrode, and the test structure is arranged in parallel with the surface adjacent to the metal structure; that is, the test structure is a capacitor, and the capacitor is arranged in parallel with the surface adjacent to the metal structure. Further, the capacitance value of the reference structure test is used as a reference to determine the capacitance value change of the test structure, and then determine the stress transmitted from the metal structure to the test structure.

[0097] In the related art, the stress of the metal structure is measured by a resistance strain gauge measurement method; specifically, a resistor is set on the outside of the metal structure. When the metal structure is strained, the shape of the resistor will change with the mechanical deformation of the metal structure, so that the resistance value changes, and the stress of the metal structure is then tested.

[0098] Compared with the related art, the sensitivity of the test structure in the embodiment of the present disclosure is higher. This is because: since the metal structure can change the distance between the first electrode and the second electrode by transmitting a slight stress change, and the distance between the first electrode and the second electrode has a greater impact on the capacitance value, the capacitance value of the test structure changes significantly, and the test structure can accurately measure the stress of the metal structure.

[0099] Furthermore, since the radial stress of the metal structure is relatively complex and may involve strains in multiple directions, the response speed and accuracy of the resistor in the related art make it difficult to measure the radial stress, resulting in low accuracy of the test results. The test structure (i.e., capacitor) in the embodiment of the present disclosure has a faster response speed and is not restricted by direction, so that the test results are more accurate.

[0100] The present disclosure provides a method for forming a semiconductor device to form Fig.12 The semiconductor device 100 shown is used as an example for explanation; Fig.13 A schematic diagram of a process for forming a semiconductor device provided by an embodiment of the present disclosure, such as Fig.13 As shown, the method for forming a semiconductor device includes the following steps:

[0101] Step S110 , providing an intermediate layer 110 .

[0102] Step S120 , forming a metal structure 120 , the metal structure 120 being located in the interposer 110 ; and forming at least one test structure 130 , the at least one test structure 130 being located in the interposer 110 and disposed adjacent to the metal structure 120 .

[0103] Here, the test structures 130 are used to monitor the stress of the metal structure 120 ; each test structure 130 includes a first electrode 131 parallel to a surface adjacent to the metal structure 120 , and a first dielectric layer 132 and a second electrode 133 sequentially covering the surface of the first electrode 131 .

[0104] In some embodiments, while forming at least one test structure 130, the method further includes:

[0105] Step S121 , forming at least one reference structure 140 , wherein the at least one reference structure 140 is located in the interposer 110 and is disposed away from the metal structure 120 .

[0106] Here, the reference structure 140 is used to provide a reference benchmark for the test structure 130 when monitoring stress; each reference structure 140 has the same structure as the corresponding test structure 130 .

[0107] Figures 14 to 19 The schematic diagram of the structure of the semiconductor device during the formation process provided by the embodiment of the present disclosure is as follows: Figures 14 to 19 The formation process of the semiconductor device provided by the embodiment of the present disclosure is described in detail.

[0108] First, execute step S110.

[0109] Please refer to Fig.14 , providing an initial second sub-intermediate layer, etching the second sub-intermediate layer to form a second sub-intermediate layer 112, and two annular first etched grooves 112a located in the second sub-intermediate layer 112. Fig.14 The dashed line shown is used to distinguish between a region where a test structure is subsequently formed (eg, the left side of the dashed line) and a region of a reference structure (eg, the right side of the dashed line).

[0110] Next, step S120 and step S120a are performed.

[0111] Please refer to Fig.15 By any suitable deposition process, the initial isolation structure 150', the initial second electrode 133b', the initial dielectric layer 132b' and the initial first electrode 131b' are sequentially formed on the exposed surface of the second sub-interposer 112. By any suitable etching process, the initial first electrode 131b' and the initial dielectric layer 132b' are sequentially etched to form Fig.16 The first electrode 131b and the first dielectric layer 132b, and the third electrode 141b and the second dielectric layer 142b are shown.

[0112] Please refer to Fig.17 By any suitable etching process, the initial second electrode 133b' and the initial isolation structure 150' are sequentially etched to form the second electrode 133b and the isolation structure 150 located at the bottom of the second electrode 133b, and the fourth electrode 143b and the isolation structure 150 located at the bottom of the fourth electrode 143b.

[0113] Please continue to refer to Fig.17 In order to facilitate the extraction of the first electrode 131b and the second electrode 133b, the second electrode 133b is extended beyond the outside of the first electrode 131b by etching twice; similarly, in order to facilitate the extraction of the third electrode 141b and the fourth electrode 143b, the fourth electrode 143b is extended beyond the outside of the third electrode 141b by etching twice.

[0114] Please refer to Fig.18, a first sub-interlayer 111 is formed on the surface of the second sub-interlayer 112; two third etched grooves (not shown) are formed in the first sub-interlayer, and the first electrode, the first dielectric layer and the second electrode in the test structure 130a are formed in the third etched groove on the left side of the dotted line, and the third electrode, the second dielectric layer and the fourth electrode in the reference structure 140a are formed in the third etched groove on the right side of the dotted line.

[0115] Please continue to refer to Fig.18 In the second sub-interposer, a first connecting wire 134b connected to the first electrode 131b, a second connecting wire 135b connected to the second electrode 133b, a third connecting wire 144b connected to the third electrode 141b, and a fourth connecting wire 145b connected to the fourth electrode 143b are formed. The first connecting wire 134b and the third connecting wire 144b are formed at the same time, and the second connecting wire 135b and the fourth connecting wire 145b are formed at the same time. Similarly, the connecting wires in the test structure 130a and the reference structure 140a are formed.

[0116] Please refer to Fig.19 , flip as Fig.18 The structure shown in FIG. 1 is formed by sequentially etching the second sub-interposer 112 and the first sub-interposer 111 to form a fourth etched groove 120a; the fourth etched groove 120a exposes the test structure 130a, and a metal structure 120 is formed in the fourth etched groove 120a to form a structure as shown in FIG. Fig.12 A semiconductor device 100 is shown.

[0117] It should be noted that semiconductor devices of other structures can be formed by referring to the above-mentioned formation method. In addition, the semiconductor device formed by the formation method of the semiconductor device provided in the embodiment of the present disclosure is similar to the semiconductor device provided in the above-mentioned embodiment. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above-mentioned embodiment for understanding, and no further description will be given here.

[0118] In addition, please refer to Fig. 20 The embodiment of the present disclosure further provides a stress testing method, which is used to perform stress testing on the semiconductor device in the above embodiment. The stress testing method includes:

[0119] In step S210, a first voltage and a second voltage are applied to the first electrode 131 and the second electrode 133 in the test structure 130, respectively, to determine the capacitance value of the test structure 130; and a first voltage and a second voltage are applied to the first electrode 131 and the second electrode 133 in the corresponding reference structure 140, respectively, to determine the capacitance value of the corresponding reference structure 140.

[0120] During implementation, the voltage (i.e., charging voltage) between the first electrode 131 and the second electrode 133 in the test structure 130 has a value range of -3 to 3V, a frequency value range of 50KHz to 1MHz, and an amplitude voltage value of 0.1V, thereby measuring the capacitance value of the test structure 130; specifically, the charging voltage can be 1V (not higher than the breakdown voltage), the frequency can be 100KHz, and the amplitude voltage can be 0.1V.

[0121] Similarly, the voltage applied to the third electrode 141 and the fourth electrode 143 in the reference structure 140 is the same as the first electrode 131 and the second electrode 133 in the corresponding test structure 130. For example, the charging voltage of the third electrode 141 and the fourth electrode 143 in the reference structure 140 may also be 1V (not higher than the breakdown voltage), the frequency may also be 100KHz, and the amplitude voltage may also be 0.1V.

[0122] It should be noted that when the semiconductor device 100 includes multiple test structures 130, the test methods (ie, test voltages) of the multiple test structures 130 may be different. At the same time, the test method of each test structure 130 and the corresponding reference structure 140 are the same. For example, Fig.12 In the semiconductor structure shown, the test structure 130a and the test structure 130b may be tested using different methods, the test structure 130a and the reference structure 140a may be tested using the same method, and the test structure 130b and the reference structure 140b may be tested using the same method.

[0123] Step S220 , determining the stress of the metal structure 120 based on the capacitance value of the test structure 130 and the capacitance value of the corresponding reference structure 140 .

[0124] Specifically, when the test structure 130 is subjected to the tensile stress in the metal structure 120, the distance between the first electrode plate and the second electrode plate will decrease, so that the capacitance value of the test structure 130 increases, that is, the capacitance of the test structure 130 is greater than the capacitance of the corresponding reference structure 140. When the test structure 130 is subjected to the compressive stress in the metal structure 120, the distance between the first electrode plate and the second electrode plate will increase, so that the capacitance value of the test structure 130 decreases, that is, the capacitance of the test structure 130 is less than the capacitance of the corresponding reference structure 140.

[0125] It should be noted that, since the test structure 130 is located on one side of the metal structure 120 and the stress in the metal structure 120 is affected by temperature, there is no situation where the capacitance values ​​of the test structure and the corresponding reference structure are equal.

[0126] In the embodiment of the present disclosure, since the reference structure 140 and the corresponding test structure 130 have the same structure, and the spacing between the third electrode 141 and the fourth electrode 143 in the reference structure will not be affected by the stress in the metal structure 120, that is, the capacitance value of the reference structure 140 will not be affected by the stress in the metal structure 120, when the reference structure 140 is tested using the same test method as the corresponding test structure 130, the capacitance value of the reference structure 140 can be used as a reference benchmark for the capacitance value of the test structure 100.

[0127] In the several embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-targeted manner. The structural embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0128] The features disclosed in several method or structural embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0129] The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: Intermediary layer; a metal structure located in the interposer; At least one test structure is located in the intermediate layer and is arranged adjacent to the metal structure, for monitoring the stress of the metal structure; each of the test structures includes a first electrode parallel to a surface adjacent to the metal structure, and a first dielectric layer and a second electrode sequentially covering the surface of the first electrode.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: At least one reference structure is located in the interposer and away from the metal structure, and is used to provide a reference for the test structure to monitor the stress; each reference structure has the same structure as the corresponding test structure.

3. The semiconductor device according to claim 1, wherein: The test structure is in the shape of a plate and is parallel to a radial surface of the metal structure, and is used to test the radial stress of the metal structure.

4. The semiconductor device according to claim 3, wherein: The first electrode is a flat plate with an I-shaped cross section, and the first electrode is parallel to a radial surface of the metal structure; the first dielectric layer and the second electrode sequentially cover the surface of at least one side of the first electrode; or, The first electrode is a flat plate with a U-shaped cross section, and the bottom surface of the first electrode is parallel to a radial surface of the metal structure; the first dielectric layer and the second electrode sequentially cover the inner wall of the first electrode, and the first dielectric layer and the second electrode are both flat plates with a U-shaped cross section.

5. The semiconductor device according to claim 1, wherein: The test structure is annular and parallel to the axial surface of the metal structure, and is used to test the axial stress of the metal structure.

6. The semiconductor device according to claim 5, wherein: The first electrode is a ring with an I-shaped cross section, and the first electrode is parallel to the axial surface of the metal structure; the first dielectric layer and the second electrode sequentially cover the surface of at least one side of the first electrode; or, The first electrode is a ring with a U-shaped cross section, and both sides of the first electrode are parallel to the axial surface of the metal structure; the first dielectric layer and the second electrode sequentially cover the inner wall of the first electrode, and the first dielectric layer and the second electrode are both rings with a U-shaped cross section.

7. The semiconductor device according to claim 1, wherein: Each of the test structures further comprises: a first connecting wire, the first connecting wire being connected to the first electrode and being used to apply a first voltage to the first electrode; A second connecting wire is connected to the second electrode and is used to apply a second voltage to the second electrode.

8. A method for forming a stress detection structure, characterized in that: The method comprises: Provide an intermediary layer; forming a metal structure, the metal structure being located in the interposer; and, At least one test structure is formed, and the at least one test structure is located in the intermediate layer and is arranged adjacent to the metal structure for monitoring the stress of the metal structure; each of the test structures includes a first electrode parallel to a surface adjacent to the metal structure, and a first dielectric layer and a second electrode sequentially covering the surface of the first electrode.

9. The forming method according to claim 8, characterized in that: While forming the at least one test structure, the method further comprises: At least one reference structure is formed, and the at least one reference structure is located in the interposer and is arranged away from the metal structure, and is used to provide a reference benchmark for the test structure when monitoring the stress; each of the reference structures has the same structure as the corresponding test structure.

10. A stress testing method, the stress testing method being used to perform stress testing on a semiconductor device according to any one of claims 1 to 7, characterized in that: The stress testing method comprises: applying a first voltage and a second voltage to a first electrode and a second electrode in the test structure, respectively, to determine a capacitance value of the test structure; and, Applying the first voltage and the second voltage to a first electrode and a second electrode in a corresponding reference structure, respectively, to determine a capacitance value of the corresponding reference structure; Based on the capacitance value of the test structure and the corresponding capacitance value of the reference structure, the stress of the metal structure is determined.

Images