Package structure, package method, chip stack structure and electronic device

Abstract

The present disclosure relates to a packaging structure, a packaging method, a chip stacking structure and an electronic device, the packaging structure comprising a first chip and a second chip stacked with each other, the first chip being provided with a first element, and the second chip being provided opposite to an active surface of the first chip; wherein an electric connection area and a clearance area are provided between the first chip and the second chip, the first chip and the second chip are electrically connected through the electric connection area, and the clearance area is used to reduce signal interference of the second chip to the first element. The packaging structure of the present disclosure sets the electric connection area and the clearance area between the first chip and the second chip, and the first chip and the second chip are electrically connected through the electric connection area, and the clearance area is used to reduce signal interference of the second chip to the first element, thereby improving signal quality of the first element and improving signal quality of the packaging structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular to a packaging structure, a packaging method, a chip stacking structure and an electronic device. BACKGROUND

[0002] Three-dimensional stacked chips not only can realize high-density vertical interconnection between chips through Hybrid Bonding and other methods, improve the equivalent two-dimensional integration density of the chip, but also can integrate heterogeneous integration under different process nodes, improve the functional density of the system, and meet the growing demand for computing power. However, stacking chips with high integration density results in a small distance between chips, and high-speed signals inside different chips will interfere with each other, affecting the integrity of the high-speed signals. SUMMARY

[0003] In a first aspect, the present disclosure provides a packaging structure to improve the signal quality of the packaging structure.

[0004] The packaging structure of the present disclosure includes a first chip and a second chip stacked with each other, the first chip is provided with a first element, and the second chip is arranged opposite to the active surface of the first chip; wherein an electrical connection area and a clearance area are provided between the first chip and the second chip, the first chip and the second chip are electrically connected through the electrical connection area, and the clearance area is used to reduce the signal interference of the second chip to the first element.

[0005] Optionally, the orthographic projection of the clearance area in the direction towards the first element at least partially covers the first element.

[0006] Optionally, the area of the orthographic projection of the clearance area in the direction towards the first element is greater than the area of the region where the first element is located.

[0007] Optionally, the first chip includes a plurality of wiring layers, the plurality of wiring layers are arranged along the thickness direction of the packaging structure, at least one of the wiring layers is a top layer, the top layer is arranged closer to the second chip than the remaining wiring layers in the thickness direction of the packaging structure, and the first element is at least partially arranged on the top layer.

[0008] Optionally, in the electrical connection area, the first chip and the second chip are connected through hybrid bonding.

[0009] Optionally, the minimum distance between the edge of the orthographic projection of the clearance area in the direction towards the first element and the first element is greater than or equal to 5 μm.

[0010] Optionally, the area of the clearance area is less than or equal to 0.08 mm 2 .

[0011] Optionally, the first element and the number of the clearance area are both plural, and the clearance area is arranged corresponding to at least one of the first elements.

[0012] Optionally, at least one of the clearance areas is arranged corresponding to at least two of the first elements.

[0013] Optionally, the distance between two adjacent clearance areas is greater than or equal to 20 μm.

[0014] Optionally, the shape of the orthographic projection of the first element in the direction towards the clearance area is consistent with the shape of the clearance area.

[0015] Optionally, the orthographic projection of the first element in the direction towards the clearance area is a polygon, and the clearance area is also a polygon.

[0016] Optionally, the first chip comprises a logic chip, the second chip comprises a storage chip, or both the first chip and the second chip are logic chips.

[0017] In a second aspect, the disclosure provides a packaging method.

[0018] The packaging method of the disclosure is used to form the packaging structure described in any of the above, and the packaging method comprises:

[0019] arranging a first element on the first chip;

[0020] stacking the first chip and the second chip, wherein the second chip is arranged opposite to the active surface of the first chip;

[0021] The first chip and the second chip are provided with an electrical connection area and a clearance area, the first chip and the second chip are electrically connected through the electrical connection area, and the clearance area is used to reduce the signal interference of the second chip to the first element.

[0022] Optionally, the first chip is provided with a first element, which comprises:

[0023] forming at least one wiring layer on the active surface of the first chip, the wiring layer is arranged in the thickness direction of the packaging structure, and the first element is formed through the at least one wiring layer.

[0024] Optionally, at least one of the wiring layers is a top layer, the top layer is arranged closer to the second chip than the rest of the wiring layers in the thickness direction of the packaging structure, and the first element is at least partially arranged on the top layer.

[0025] In the present disclosure, forming the first element can be realized by a related process, such as a patterning process. Exemplarily, when the first element is an inductive element, the first element can be realized by etching, photolithography, or the like on the wiring layer, for which the present disclosure does not make a detailed description.

[0026] In a third aspect, the present disclosure provides a chip stack structure.

[0027] The chip stack structure of the present disclosure comprises a substrate and a packaging structure, the packaging structure is arranged on the substrate, and the packaging structure comprises the packaging structure of any one of the above.

[0028] In a fourth aspect, the present disclosure provides an electronic device.

[0029] The electronic device of the present disclosure comprises a printed circuit board and the packaging structure of any one of the above, and the printed circuit board is connected with the packaging structure.

[0030] The packaging structure of the present disclosure, by arranging the electrically connecting region and the clearance region between the first chip and the second chip, and electrically connecting the first chip and the second chip through the electrically connecting region, the clearance region is used to reduce the signal interference of the second chip to the first element, so as to improve the signal quality of the first element and the signal quality of the packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 is a sectional view of the packaging structure of one embodiment of the present disclosure.

[0032] Figure 2 is a sectional view of the chip of another embodiment of the present disclosure.

[0033] Figure 3 is Figure 2 is an enlarged view of A in FIG.

[0034] Figure 4 is a structural schematic view of the clearance region of the chip of another embodiment of the present disclosure.

[0035] Figure 5 is a structural schematic view of the clearance region and the inductive element of the chip of another embodiment of the present disclosure.

[0036] Figure 6 and Figure 7 is a simulation diagram provided by another embodiment of the present disclosure.

[0037] REFERENCE SIGNS:

[0038] 10, packaging structure;

[0039] 1, first chip; 11, first element; 12, electrically connecting region; 13, clearance region; 14, wiring layer; 141, top layer; 101, first electrically connecting member; 102, first through hole;

[0040] 2. second chip; 201, second electrical connection; 202, second via hole;

[0041] 100, packaging structure; 1001, first chip; 1002, second chip; 1003, inductance element; 1004, circuit. DETAILED DESCRIPTION

[0042] Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and cannot be understood as a limitation of the present disclosure.

[0043] Figure 1 A packaging structure 100 is disclosed for an embodiment of the present disclosure. Figure 1 In an example, the inductance element 1003 needs to be provided with a certain size of clearance area to prevent other traces from affecting the Q value and inductance value of the inductance element 1003. Since the active surfaces of the first chip 1001 and the second chip 1002 in the packaging structure 100 are connected by hybrid bonding, the spacing between the first chip 1001 and the second chip 1002 is only a few microns. The inductance element 1003 of the first chip 1001 cannot achieve the required clearance area, and the second chip 1002 will interfere with the inductance element 1003 of the first chip 1001, reducing the signal quality of the inductance element 1003, further affecting the operation of the first chip 1001, especially in high-speed scenarios, such as transmission speed reaching 10BPS or more, the inductance element 1003 is more susceptible to the influence of the second chip 1002. Therefore, how to improve the signal quality of the inductance element 1003 in the first chip 1001 is a technical problem that needs to be solved.

[0044] As shown in Figures 2 to 5 The packaging structure 10 of the embodiment of the present disclosure includes a first chip 1 and a second chip 2 stacked with each other, and the second chip 2 is arranged opposite to the active surface of the first chip 1. An electrical connection area 12 and a clearance area 13 are provided between the first chip 1 and the second chip 2, and the first chip 1 and the second chip 2 are electrically connected through the electrical connection area 12. A first element 11 is provided in the first chip 1, and the clearance area 13 is used to reduce the signal interference of the second chip 2 to the first element 11.

[0045] It should be noted that the chip in the embodiments of the present disclosure can be a die (also referred to as a particle or a bare chip), or a chip wafer. It can be understood that after an epitaxial layer is grown on a wafer, the chip wafer is formed, and the bare chip (die) is obtained after the chip wafer is cut. The die-to-die bonding (D2D bonding) can be used between the dies. The wafer-to-wafer bonding (W2W bonding) can be used for the chip wafer. The die-to-wafer bonding (D2W bonding) can be used for stacking multiple dies to a chip wafer. The package of the present disclosure can also be at least one of chip-to-wafer (C2W) bonding, die-to-wafer (D2C) bonding, and chip-to-chip (C2C) bonding

[0046] The present disclosure does not limit the number of stacked chips in the chip stacking structure, and the number of stacked chips can be set according to application requirements. In addition, the above-mentioned chip can be a storage chip, a logic chip, or a chip with other functions.

[0047] The package structure 10 of the embodiments of the present disclosure reduces or even avoids the signal interference of the second chip 2 on the first element 11 by setting the electrical connection area 12 and the clearance area 13 between the first chip 1 and the second chip 2, and electrically connecting the first chip 1 and the second chip 2 through the electrical connection area 12. The clearance area 13 is used to reduce the signal interference of the second chip 2 on the first element 11, thereby improving the signal quality of the first element 11 and improving the signal quality of the package structure 10.

[0048] Optionally, the first chip 1 includes a logic chip, and the second chip 2 includes a storage chip. Alternatively, the first chip 1 and the second chip 2 are both logic chips.

[0049] The logic chip can be an application chip, and the storage chip can be a dynamic random storage chip.

[0050] In the present disclosure, the first element 11 indicates an element with a specific function. Optionally, the first element 11 includes one of an inductor, a sensor, and a capacitor.

[0051] For example, the first element 11 is an inductor, which is easily affected by signal interference in a high-speed scenario in the package structure.

[0052] By setting the clearance area, the signal quality of the package structure 10 can be improved by reducing or even avoiding the influence of the second chip 2 on the element in the first chip that is easily affected by the second chip.

[0053] In order to make the technical solutions of the present disclosure easier to be understood, the thickness direction of the packaging structure 10 is consistent with the up-down direction as an example, and the technical solutions of the present disclosure are further described below. Wherein, the up-down direction is as shown in Figure 2 and Figure 3 .

[0054] For example, the first chip 1 is arranged on the lower side of the second chip 2, and the clearance area 13 is arranged on the upper side of the first element 11.

[0055] Optionally, as shown in Figure 2 and Figure 3 , the first chip 1 includes a plurality of wiring layers 14, and the plurality of wiring layers 14 are arranged in the thickness direction of the packaging structure 10. At least one wiring layer 14 is a top layer 141, and the top layer 141 is arranged relatively closer to the second chip 2 in the thickness direction of the packaging structure 10 than the remaining wiring layers 14. The first element 11 is at least partially arranged in the top layer 141.

[0056] Among them, the first element 11 is at least partially arranged in the top layer 141, which can be understood as: part of the first element 11 is arranged in the top layer 141, and another part of the first element 11 is arranged in other wiring layers 14 except the top layer 141; or, the first element 11 is arranged in the top layer 141 as a whole.

[0057] For example, the plurality of wiring layers 14 are arranged in the up-down direction. One of the wiring layers 14 is a top layer 141, and the top layer 141 is located at the uppermost side among the plurality of wiring layers 14.

[0058] In the embodiment of the present disclosure, among the plurality of wiring layers 14, the wiring layer 14 closer to the second chip 2 has a greater thickness and a smaller resistance.

[0059] By arranging the first element 11 at least partially in the top layer 141, the parasitic resistance of the first element 11 can be reduced, thereby improving the Q value of the first element 11, further improving the signal quality of the first element 11, and improving the signal quality of the packaging structure 10.

[0060] Optionally, as shown in Figure 2 and Figure 3 , the first chip 1 and the second chip 2 are connected by hybrid bonding.

[0061] For example, as shown in Figure 2 and Figure 3As shown, the first chip 1 is provided with a plurality of first electrical connecting members 101, the second chip 2 is provided with a plurality of second electrical connecting members 201, the first chip 1 is provided with a first through hole 102, and the first electrical connecting members 101 extend to the circuit 1004 of the first chip 1 through the first through hole 102. The second chip 2 is provided with a second through hole 202, and the second electrical connecting members 201 extend to the circuit 1004 of the second chip 2 through the second through hole 202. The second electrical connecting members 201 correspond to the first electrical connecting members 101 one by one and are electrically connected, so that the first chip 1 and the second chip 2 are connected by the hybrid bonding mode. Among them, the first electrical connecting members 101 and the second electrical connecting members 201 are arranged in the electrical connection area 12, and the first electrical connecting members 101 and the second electrical connecting members 201 are not arranged in the clearance area 13.

[0062] The first chip 1 and the second chip 2 are connected by hybrid bonding, which can realize higher density and greater bandwidth of the packaging structure 10.

[0063] Optionally, as shown in Figure 2 , Figure 3 and Figure 5 , the clearance area 13 is at least partially overlapped with the first element 11 in the direction of the normal projection of the clearance area 13.

[0064] Among them, the clearance area 13 is at least partially overlapped with the first element 11 in the direction of the normal projection of the clearance area 13, which can be understood as: the clearance area 13 is entirely overlapped with the first element 11 in the direction of the normal projection of the clearance area 13; or, a part of the clearance area 13 is overlapped with the first element 11 in the direction of the normal projection of the clearance area 13, and another part of the clearance area 13 is not overlapped with the first element 11 in the direction of the normal projection of the clearance area 13.

[0065] It can be understood that the first electrical connecting members 101 and the second electrical connecting members 201 are conductive members, which will interfere with the signal of the first element 11.

[0066] By at least partially overlapping the first element 11 in the direction of the normal projection of the clearance area 13, the clearance area of the first element 11 can be increased, and the signal quality of the first element 11 and the signal quality of the packaging structure 10 can be further improved.

[0067] Optionally, as shown in Figure 2 , Figure 3 and Figure 5 , the area of the normal projection of the clearance area 13 in the direction of the first element 11 is greater than the area of the region where the first element 11 is located. That is, the normal projection of the clearance area 13 in the direction of the first element 11 covers not only the entire first element 11 but also the edge region of the first element 11 to cover more signals generated by the first element 11.

[0068] Optionally, the minimum distance between the edge of the orthographic projection of the clearance area 13 in the direction towards the first element 11 and the first element 11 is greater than or equal to 5 μm.

[0069] In the present disclosure, the minimum distance between the edge of the orthographic projection of the clearance area 13 in the direction towards the first element 11 and the first element 11 indicates the straight line shortest distance of the orthographic projection of both the clearance area 13 and the first element 11 on the plane where the first element 11 is located. As shown in Figure 5 The shortest distance J between the first element 11 and the clearance area 13 is 5 μm.

[0070] Taking the first element as an inductor as an example, the distance between the edge of the orthographic projection of the clearance area 13 in the direction towards the first element 11 and the first element 11 will affect the inductance value (L value) and Q value of the inductor element. As shown in Figure 6 The horizontal coordinate is the minimum distance between the edge of the orthographic projection of the clearance area 13 in the direction towards the first element 11 and the first element 11, and the vertical coordinate is the inductance value (L value) of the inductor element. As shown in Figure 7 The horizontal coordinate is the straight line shortest distance of the orthographic projection of both the clearance area 13 and the first element 11 on the plane where the first element 11 is located in the direction towards the first element 11, and the vertical coordinate is the Q value of the inductor element. It can be seen that when the minimum distance between the edge of the orthographic projection of the clearance area 13 in the direction towards the first element 11 and the first element 11 is greater than 5 μm, the signal of the second chip 2 can be well reduced, and the performance of the first element 11 can be ensured.

[0071] By setting the orthographic projection of the clearance area 13 in the direction towards the first chip 1 to be greater than the area of the region where the first element 11 is located, the clearance area of the first element 11 can be increased, and the signal quality of the first element 11 and the signal quality of the packaging structure 10 can be further improved.

[0072] Optionally, as shown in Figure 5 The number of the first elements 11 and the clearance areas 13 is multiple, and at least one clearance area 13 is provided corresponding to at least one first element 11.

[0073] For example, as shown in Figure 5 The number of the first elements 11 is nine, and the number of the clearance areas 13 is five. Part of the clearance areas 13 are provided corresponding to two first elements 11, and part of the clearance areas 13 are provided corresponding to one first element 11.

[0074] By providing multiple first elements 11 and multiple clearance areas 13, the multiple first elements 11 can be integrated on the same first chip 1, and the integration degree of the packaging structure 10 can be improved.

[0075] Optionally, as shown in Figure 5 At least one clearance area 13 is provided corresponding to at least two first elements 11.

[0076] For example, as shown in FIG. 1, four clearance areas 13 are arranged corresponding to two first elements 11. Figure 5

[0077] It can be understood that the clearance area 13 is not provided with the first electrical connecting member 101 and the second electrical connecting member 201, so that the first chip 1 and the second chip 2 cannot be connected through the first electrical connecting member 101 and the second electrical connecting member 201 at the clearance area 13, which affects the connection stability of the first chip 1 and the second chip 2.

[0078] By arranging at least one clearance area 13 corresponding to at least two first elements 11, the number of clearance areas 13 can be reduced, thereby improving the connection stability of the first chip 1 and the second chip 2 and improving the reliability of the packaging structure 10.

[0079] As described above, the clearance area 13 is not provided with the first electrical connecting member 101 and the second electrical connecting member 201, so that the first chip 1 and the second chip 2 cannot be connected through the first electrical connecting member 101 and the second electrical connecting member 201 at the clearance area 13, which reduces the connection area of the first chip 1 and the second chip 2 and reduces the connection stability of the first chip 1 and the second chip 2.

[0080] Optionally, the distance between the adjacent two clearance areas 13 is greater than or equal to 20 μm. Preferably, the distance between the adjacent two clearance areas 103 is 100 μm, which can avoid that the density between the clearance areas 103 is too large to affect the connection stability between the first chip 1 and the second chip 2 and improve the reliability of the packaging structure 10.

[0081] By setting the distance between the adjacent two clearance areas 13 to be greater than or equal to 20 μm, the distance between the adjacent two unconnected areas between the first chip 1 and the second chip 2 can be reduced, thereby improving the connection stability of the first chip 1 and the second chip 2 and improving the reliability of the packaging structure 10.

[0082] Optionally, the area of the clearance area 13 is less than or equal to 0.08 mm 2 . Preferably, the area of the clearance area 13 is 0.0625 mm 2 . When the clearance area 13 is less than the value described in the embodiments of the present disclosure, the connection stability between the first chip 1 and the second chip 2 can be better guaranteed.

[0083] As described above, the clearance area 13 is not provided with the first electrical connecting member 101 and the second electrical connecting member 201, so that the first chip 1 and the second chip 2 cannot be connected through the first electrical connecting member 101 and the second electrical connecting member 201 at the clearance area 13, which affects the connection stability of the first chip 1 and the second chip 2.

[0084] ​By setting the area of the clearance area 13 to be less than or equal to 0.08mm 2 The area of the unconnected region between the first chip 1 and the second chip 2 can be reduced, the connection stability of the first chip 1 and the second chip 2 can be improved, and the reliability of the packaging structure 10 can be improved.

[0085] Optionally, as shown in Figure 5 , the shape of the orthographic projection of the first element 11 in the direction towards the clearance area 13 is consistent with the shape of the clearance area 13.

[0086] The shape of the orthographic projection of the first element 11 in the direction towards the clearance area 13 is consistent with the shape of the clearance area 13, which can be understood as: the shape of the orthographic projection of the first element 11 in the direction towards the clearance area 13 is the same as the shape of the clearance area 13, or the shape of the orthographic projection of the first element 11 in the direction towards the clearance area 13 is substantially the same as the shape of the clearance area 13.

[0087] For example, as shown in Figure 5 , the shape of the orthographic projection of the first element 11 in the direction towards the clearance area 13 is a rectangle, and the shape of the clearance area 13 is also a rectangle; or the shape of the orthographic projection of the first element 11 in the direction towards the clearance area 13 is an octagon, and the shape of the clearance area 13 is also an octagon.

[0088] By setting the shape of the orthographic projection of the first element 11 in the direction towards the clearance area 13 to be consistent with the shape of the clearance area 13, the corresponding first element 11 can be covered in the case that the area of the clearance area 13 is small. Therefore, the connection stability between the first chip 1 and the second chip 2 can be improved, and the reliability of the packaging structure 10 can be improved.

[0089] Optionally, as shown in Figure 4 and Figure 5 , the orthographic projection of the first element 11 in the direction towards the clearance area 13 is a polygon, and the clearance area 13 is a polygon.

[0090] For example, as shown in Figure 5 , the shape of the orthographic projection of the first element 11 in the direction towards the clearance area 13 is a rectangle, and the shape of the clearance area 13 is also a rectangle; or the shape of the orthographic projection of the first element 11 in the direction towards the clearance area 13 is an octagon, and the shape of the clearance area 13 is also an octagon.

[0091] By setting the orthographic projection of the first element 11 in the direction towards the clearance area 13 and the clearance area 13 to be polygons, the processing and manufacturing of the packaging structure 10 are facilitated.

[0092] The packaging structure 10 of the embodiment of the present disclosure can increase the clearance area of the first element 11, improve the signal quality of the first element 11, and improve the signal quality of the packaging structure 10 by setting the clearance 13 between the first chip 1 and the second chip 2 and corresponding to the first element 11.

[0093] The packaging method of the embodiment of the present disclosure comprises:

[0094] The first element 11 is arranged on the first chip 1.

[0095] The first chip 1 and the second chip 2 are stacked, and the second chip 2 is arranged opposite to the active surface of the first chip 1.

[0096] The first chip 1 and the second chip 2 are provided with an electrical connection area 12 and a clearance 13, the first chip 1 and the second chip 2 are electrically connected through the electrical connection area 12, and the clearance 13 is used to reduce the signal interference of the second chip 2 to the first element 11.

[0097] In some embodiments, the first element 11 arranged on the first chip 1 comprises:

[0098] At least one wiring layer 14 is formed on the active surface of the first chip 1, and the wiring layer 14 is arranged in the thickness direction of the packaging structure 10; the first element 11 is formed through the at least one wiring layer 14.

[0099] In some embodiments, the at least one wiring layer 14 is a top layer 141, the top layer 141 is arranged closer to the second chip 2 than the remaining wiring layers 14 in the thickness direction of the packaging structure 10, and the first element 11 is at least partially arranged on the top layer 141.

[0100] The chip stacking structure in the embodiment of the present disclosure comprises a substrate and a packaging structure 10 arranged on the substrate, and the packaging structure is the packaging structure 10 described in any of the above embodiments.

[0101] The electronic device printed circuit board and the packaging structure 10 of the embodiment of the present disclosure, the packaging structure 10 is the packaging structure 10 described in any of the above embodiments, and the printed circuit board is connected with the packaging structure 10.

[0102] In the description of the present disclosure, it needs to be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present disclosure.

[0103] In addition, the terms "first", "second" are only for descriptive purpose, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly specified and limited.

[0104] In the present disclosure, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood in a broad sense, for example, can be fixedly connected, or can be detachably connected, or can be integrated; can be mechanically connected, or can be electrically connected or can communicate with each other; can be directly connected, or can be indirectly connected through an intermediate medium; can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0105] In the present disclosure, unless otherwise explicitly specified and limited, the first feature "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature "above", "over" and "on" the second feature can be that the first feature is directly above or obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "under" and "under" the second feature can be that the first feature is directly below or obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0106] In this disclosure, the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" mean that the particular feature, structure, material, or characteristic being described is included in at least one embodiment or example of the disclosure. The illustrative appearances of the above-mentioned terms in various places in the specification are not necessarily intended to refer to the same embodiment or example. Moreover, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples. Furthermore, the terms "comprise", "comprising", "include", "including", "contain", "containing", "have", "having", or "hold" are not intended to be limiting and are used in their broadest sense to encompass the stated features, structures, materials, or characteristics, but do not preclude the presence or addition of one or more other features, structures, materials, or characteristics.

[0107] Although the embodiments of the disclosure have been shown and described above, it is understood that the above-described embodiments are exemplary, and are not to be interpreted as limiting the disclosure, and the changes, modifications, replacements, and variations of the above-described embodiments made by those skilled in the art are within the protection scope of the disclosure.

Claims

1. A package structure, characterized by, The package structure comprises a first chip and a second chip stacked with each other, the first chip is internally provided with a first element, The second chip is arranged opposite to the active surface of the first chip; The first chip and the second chip are provided with an electrical connection area and a clearance area, the first chip and the second chip are electrically connected through the electrical connection area, the clearance area is used to reduce the signal interference of the second chip to the first element, the clearance area is arranged on the upper side of the first element, the electrical connection area is provided with a plurality of electrical connectors, and the clearance area is not provided with the electrical connectors. The first chip comprises a plurality of wiring layers, the plurality of wiring layers are arranged in the thickness direction of the package structure, the wiring layers closer to the second chip have greater thickness, at least one of the wiring layers is a top layer, the top layer is arranged closer to the second chip than the remaining wiring layers in the thickness direction of the package structure, and the first element is at least partially arranged in the top layer.

2. The package structure of claim 1, wherein, The clearance area is at least partially overlapped with the first element in the orthographic projection in the direction towards the first element.

3. The package structure of claim 2, wherein, The area of the orthographic projection of the clearance area in the direction towards the first element is greater than the area of the region where the first element is located.

4. The package structure of claim 1, wherein, The minimum distance between the edge of the orthographic projection of the clearance area in the direction towards the first element and the first element is greater than or equal to 5 μm.

5. The package structure of claim 1, wherein, In the electrical connection area, the first chip and the second chip are connected through hybrid bonding.

6. The package structure of any one of claims 1-5, wherein, The area of the clearance zone is less than or equal to 0.08 mm 2 .

7. The package structure of any one of claims 1-5, wherein, The number of the first elements and the number of the clearance areas are both plural, and at least one of the clearance areas is arranged corresponding to at least one of the first elements.

8. The package structure of claim 7, wherein, At least one of the clearance areas is arranged corresponding to at least two of the first elements.

9. The package structure of claim 8, wherein, The distance between two adjacent clearance areas is greater than or equal to 20 μm.

10. The package structure of any one of claims 1-5, wherein, The shape of the orthographic projection of the first element in the direction towards the clearance area is consistent with the shape of the clearance area.

11. The package structure of claim 10, wherein, The orthographic projection of the first element in the direction towards the clearance area is a polygon, and the clearance area is a polygon.

12. The package structure of claim 1, wherein, The first chip comprises a logic chip, and the second chip comprises a storage chip; or, the first chip and the second chip are both logic chips.

13. A packaging method, characterized by, The packaging method is used for forming the package structure of any one of claims 1-12, and the packaging method comprises, arranging a first element on a first chip; stacking the first chip and a second chip, wherein the second chip is arranged opposite to the active surface of the first chip; The first chip and the second chip are provided with an electrical connection area and a clearance area, the first chip and the second chip are electrically connected through the electrical connection area, and the clearance area is used to reduce the signal interference of the second chip to the first element.

14. The packaging method according to claim 13, characterized in that, The first chip is provided with a first element, which comprises: forming at least one wiring layer on the active surface of the first chip, the wiring layer is arranged in the thickness direction of the package structure; and forming the first element through the at least one wiring layer.

15. A chip stack structure, characterized by The package structure comprises a substrate and a package structure arranged on the substrate, and the package structure comprises the package structure of any one of claims 1-12. The package structure comprises a first chip and a second chip stacked with each other, the first chip is internally provided with a first element, The second chip is arranged opposite to the active surface of the first chip; The first chip and the second chip are provided with an electrical connection area and a clearance area, the first chip and the second chip are electrically connected through the electrical connection area, the clearance area is used to reduce the signal interference of the second chip to the first element, the clearance area is arranged on the upper side of the first element, the electrical connection area is provided with a plurality of electrical connectors, and the clearance area is not provided with the electrical connectors. The first chip comprises a plurality of wiring layers, the plurality of wiring layers are arranged in the thickness direction of the package structure, the wiring layers closer to the second chip have greater thickness, at least one of the wiring layers is a top layer, the top layer is arranged closer to the second chip than the remaining wiring layers in the thickness direction of the package structure, and the first element is at least partially arranged in the top layer. The clearance area is at least partially overlapped with the first element in the orthographic projection in the direction towards the first element. The area of the orthographic projection of the clearance area in the direction towards the first element is greater than the area of the region where the first element is located. The minimum distance between the edge of the orthographic projection of the clearance area in the direction towards the first element and the first element is greater than or equal to 5 μm. In the electrical connection area, the first chip and the second chip are connected through hybrid bonding. The number of the first elements and the number of the clearance areas are both plural, and at least one of the clearance areas is arranged corresponding to at least one of the first elements. At least one of the clearance areas is arranged corresponding to at least two of the first elements. The distance between two adjacent clearance areas is greater than or equal to 20 μm. The shape of the orthographic projection of the first element in the direction towards the clearance area is consistent with the shape of the clearance area. The orthographic projection of the first element in the direction towards the clearance area is a polygon, and the clearance area is a polygon. The first chip comprises a logic chip, and the second chip comprises a storage chip; or, the first chip and the second chip are both logic chips. The packaging method is used for forming the package structure of any one of claims 1-12, and the packaging method comprises, arranging a first element on a first chip; stacking the first chip and a second chip, wherein the second chip is arranged opposite to the active surface of the first chip; The first chip and the second chip are provided with an electrical connection area and a clearance area, the first chip and the second chip are electrically connected through the electrical connection area, and the clearance area is used to reduce the signal interference of the second chip to the first element. The first chip is provided with a first element, which comprises: forming at least one wiring layer on the active surface of the first chip, the wiring layer is arranged in the thickness direction of the package structure; and forming the first element through the at least one wiring layer. The package structure comprises a substrate and a package structure arranged on the substrate, and the package structure comprises the package structure of any one of claims 1-12.

16. An electronic device, comprising: A printed circuit board comprising the package structure of any one of claims 1-12, the printed circuit board being connected with the package structure.

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