Package assembly for vertical cavity surface emitting laser on driver IC

Abstract

The invention relates to a package assembly for a vertical cavity surface emitting laser on a driver IC. A package assembly includes a circuit substrate, a top emitting (TE) vertical cavity surface emitting laser (VCSEL) die having a two-dimensional (2D) matrix addressable emitter array, and a driver integrated circuit (IC) having a flip-chip interconnect configuration. The TE-VCSEL die and the driver IC are coupled together to form a die stack mounted to the circuit substrate, wherein the TE-VCSEL die is disposed between the driver IC and the circuit substrate. In one embodiment, the TE-VCSEL die includes a light output portion disposed at a major surface coupled to the driver IC. The light output portion is configured to output light generated by one or more emitters of the emitter array. Thus, the TE-VCSEL die is configured to emit light away from the circuit substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 595,489, filed on November 2, 2023, entitled “PACKAGE ASSEMBLY FOR TOP-EMITTING VERTICAL-CAVITY SURFACE-EMITTING LASER (TE-VCSEL) ON AN INTEGRATEDCIRCUIT (IC) DRIVER”. The disclosure of this prior application is considered a part of this patent application and is incorporated by reference into this patent application. Technical Field

[0003] The present disclosure generally relates to packaging assemblies for TE-VCSEL dies and driver IC dies. Background Art

[0004] A vertical cavity surface emitting laser (VCSEL) is a type of semiconductor laser diode (e.g., laser resonant cavity) whose laser beam emission is perpendicular to the top or bottom surface of the device. A VCSEL typically includes two distributed Bragg reflector (DBR) mirrors arranged parallel to the wafer surface, wherein the active region is arranged between the two DBR mirrors. The active region includes one or more quantum wells for laser generation. VCSELs are widely used in various applications such as data communications, sensing, and optical interconnects because of their advantages over other types of lasers. For example, VCSELs typically have lower power consumption (e.g., VCSELs require much lower power to operate than other types of lasers, which makes them more energy-efficient and cost-effective), are capable of high-speed operation (e.g., this makes VCSELs ideal for data communications and other applications requiring fast signal transmission), have narrow beam divergence (e.g., the narrow beam divergence of VCSELs allows high coupling efficiency with optical fibers and other components, which makes VCSELs easier to integrate into optical systems), and have high reliability (e.g., VCSELs have a longer operating life and are less prone to failure than other types of lasers).

[0005] Different applications such as three-dimensional sensing and data communications can use semiconductor lasers that emit different wavelength bands. For example, short-range communications can use VCSELs that emit about 850 nanometers (nm), while long-range communications can use VCSELs that emit above 1.3 micrometers (μm) or even above 1.5 μm. Three-dimensional sensing applications such as light detection and ranging (LiDAR) can use VCSELs that emit different wavelengths (such as 905nm and 940nm) to achieve various functions.

[0006] A typical VCSEL has a sandwich structure, which mainly includes a top distributed Bragg reflector (DBR), a bottom DBR, and an active region (e.g., an active layer) arranged between the top DBR and the bottom DBR. Each DBR is made of a plurality of alternating high-refractive index layers and low-refractive index layers, and each layer has an optical thickness of an odd multiple (1 / 4, 3 / 4, ...) of 1 / 4λ, where the optical thickness of one λ is the length of a wavelength divided by the refractive index. "High refractive index" refers to a relatively high value of the optical refractive index, while "low refractive index" refers to a relatively low value of the optical refractive index. Optionally, the DBR may include a gradient layer that provides a smoother transition between different energy bands corresponding to high-refractive index and low-refractive index semiconductor materials. The top DBR, the active region, and the bottom DBR form an optical cavity with a gain material. Summary of the invention

[0007] In some implementations, a package assembly includes a circuit substrate, a top-emitting (TE) VCSEL die, and a driver integrated circuit (IC), wherein the circuit substrate includes a first substrate surface and a second substrate surface arranged opposite to the first substrate surface; the TE-VCSEL die is arranged on the first substrate surface of the circuit substrate, wherein the TE-VCSEL die includes an emitter array, the emitter array includes a plurality of VCSEL emitters, the plurality of VCSEL emitters are two-dimensional (2D) matrix addressable, wherein the TE-VCSEL die includes a first main surface and a second main surface, wherein the first main surface is coupled to the first substrate surface and the second main surface is arranged opposite to the first main surface, and wherein the TE-VCSEL die includes a light output portion arranged at the second main surface, the light output portion being configured to output light generated by one or more VCSEL emitters of the plurality of VCSEL emitters; the driver IC is arranged on the first substrate surface of the TE-VCSEL die. The present invention relates to a circuit substrate comprising a first substrate surface and a second substrate surface and coupled to the second main surface, so that the TE-VCSEL die and the driver IC form a die stack on the first substrate surface of the circuit substrate, wherein the driver IC has a flip-chip interconnect configuration, and wherein the driver IC is electrically coupled to the TE-VCSEL die to individually drive each of a plurality of VCSEL emitters according to a 2D matrix address, wherein the driver IC comprises a driver substrate, the driver substrate comprises a third main surface coupled to the second main surface of the TE-VCSEL die, a fourth main surface arranged opposite to the third main surface, and a driver circuit system integrated in the driver substrate, wherein the driver IC comprises a first plurality of conductive interconnect structures coupled to the third main surface, wherein the first plurality of conductive interconnect structures comprises a first subset of conductive interconnect structures electrically coupled to the driver circuit system and the plurality of VCSEL emitters, and a second subset of conductive interconnect structures electrically coupled to the driver circuit system and the circuit substrate.

[0008] In some implementations, a method includes attaching a TE-VCSEL die to a driver integrated circuit (IC) to form a die stack, wherein the TE-VCSEL die includes an emitter array, the emitter array includes a plurality of VCSEL emitters, wherein the TE-VCSEL die includes a first major surface and a second major surface arranged opposite the first major surface, and wherein the TE-VCSEL die includes a light output portion arranged at the second major surface, the light output portion being configured to output light generated by one or more VCSEL emitters of the plurality of VCSEL emitters, wherein the driver IC is coupled to the second major surface of the TE-VCSEL die to form the die stack, wherein the driver IC has a flip-chip interconnect configuration; attaching the TE-VCSEL die to a circuit substrate, the circuit substrate including a first substrate surface and a second substrate surface opposite the first substrate surface A second substrate surface is arranged, wherein the first main surface of the TE-VCSEL die is coupled to the first substrate surface of the circuit substrate, so that the TE-VCSEL die is arranged between the circuit substrate and the driver IC; and the driver IC is electrically coupled to the first substrate surface of the circuit substrate, wherein the driver IC includes a driver substrate, the driver substrate includes a third main surface coupled to the second main surface of the TE-VCSEL die, a fourth main surface arranged opposite to the third main surface, and a driver circuit system integrated in the driver substrate, wherein the driver IC includes a first plurality of conductive interconnect structures coupled to the third main surface, wherein the first plurality of conductive interconnect structures include a first subset of conductive interconnect structures electrically coupled to the driver circuit system and a plurality of VCSEL emitters, and a second subset of conductive interconnect structures electrically coupled to the driver circuit system and the circuit substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A and Figure 1B are diagrams depicting a top view of an example transmitter and a cross-sectional view of the example transmitter along line XX, respectively.

[0010] Figure 2 Package assemblies according to one or more implementations are shown.

[0011] Figure 3 Package assemblies according to one or more implementations are shown.

[0012] Figure 4 is a flow chart of an example process associated with manufacturing a package assembly for a TE-VCSEL device. DETAILED DESCRIPTION

[0013] The following detailed description of example implementations refers to the accompanying drawings.The same reference numbers in different drawings may identify the same or similar elements.

[0014] A package assembly may include a circuit substrate (e.g., a base substrate), one or more electronic components coupled to and / or embedded in the circuit substrate, and a package housing formed on the circuit substrate to protect (e.g., by encapsulating or partially encapsulating) one or more electronic components. One or more electronic components may be interconnected by electrical interconnection to form an electronic system. An electronic component may include one or more die or chips. A die may be manufactured on a substrate (such as a wafer) and may be or include an unpackaged bare chip. An integrated circuit (IC) may also be referred to as a die or chip. For example, an IC may include one or more circuits manufactured (e.g., integrated) on a piece of semiconductor material (e.g., a semiconductor substrate). Therefore, an IC may be integrated on a substrate used as a carrier for the IC. Therefore, the terms die, chip, and IC may be used interchangeably herein.

[0015] A package assembly may be referred to as a die package or chip package that includes one or more dies or chips. A package assembly may provide protection for electronic components and electrical interconnects from damage, and may include mechanisms (such as balls, pins, leads, contact pads, or other electrical interconnect structures) for connecting the electronic components and electrical interconnects to external components (e.g., a carrier substrate).

[0016] A VCSEL die can include multiple emitters (e.g., multiple VCSEL emitters) integrated on a single die. The VCSEL die can be arranged in a package, such as a package for a time-of-flight (ToF) camera. For example, a top-emitting VCSEL (TE-VCSEL) die can be electrically connected to a driver IC via wire bonding. However, wire bonding can only enable row-by-row control of multiple emitters of a TE-VCSEL die. Therefore, each emitter of a corresponding row is enabled or disabled together. Row-by-row control can be referred to as one-dimensional (1D) addressability because multiple emitters can only be addressed in one dimension. 1D addressable package components can have good thermal performance, but the package size of 1D addressable package components is larger.

[0017] When the emitters of the array are addressed in two dimensions (e.g., enabled and disabled), the emitter array is two-dimensionally (2D) addressable. However, the thermal performance of a package assembly with a 2D matrix-addressable emitter array is generally worse than that of a package assembly with a 1D matrix-addressable emitter array. In addition, bottom-emitting (BE)-VCSEL dies are often used to achieve 2D addressing. However, the optical efficiency of BE-VCSEL dies is generally lower than that of TE-VCSELs.

[0018] Some implementations disclosed herein provide a package assembly for a 2D addressable TE-VCSEL die. A 2D addressable TE-VCSEL die may include an emitter that can be addressed (e.g., enabled and disabled) in two dimensions to form a 2D matrix addressable emitter array. Therefore, each emitter can be enabled or disabled individually. A single emitter generally cannot provide enough optical power for most ToF applications. Therefore, a 2D matrix addressable emitter array is more practical than a 1D addressable emitter array because multiple emitters in a desired area can be enabled or disabled (powered on or off) at the same time. The package assembly may include an improved thermal path to dissipate the heat generated by the TE-VCSEL die to improve the thermal performance of the TE-VCSEL die. In addition, by using a TE-VCSEL die within a package assembly, the optical efficiency of the package assembly may be improved over a package assembly using a BE-VCSEL die.

[0019] The package assembly can provide high-quality electrical signals due to the short electrical traces between each VCSEL emitter and the driver circuitry of the driver IC.

[0020] The package assembly can provide high thermal performance. For example, the heat generated by the TE-VCSEL die can be dissipated through the circuit substrate (e.g., base substrate) of the package assembly instead of through the driver IC. At the same time, the driver IC can also have a dedicated thermal path for heat dissipation.

[0021] Compared to, for example, a 1D addressable package component, the package component can provide a smaller package size.

[0022] The package assembly can provide higher light efficiency for etching silicon (Si) cavities because the laser beam does not need to pass through a gallium arsenide (GaAs) substrate as in the case of BE-VCSELs.

[0023] Compared to BE-VCSELs, this package assembly can be more conveniently integrated into optical devices due to the etched Si driver cavity.

[0024] Because the front surface of the VCSEL emitter (eg, the optical surface of the emitter) is bonded to the silicon wafer, the package assembly may provide improved device reliability against moisture penetration.

[0025] For TE-VCSELs with wavelengths of 1150nm or greater, the manufacturing process of the package assembly can include copper-copper (Cu-Cu) thermal compression bonding (TCB) for the electrical bonding pads. In addition, the optical surface of the emitter can be bonded by oxide-to-oxide or atomic layer deposition (ALD). This type of diffusion bonding can be achieved in one process. In the optical path area, the original silicon material of the driver IC can be artificially left without any IC circuitry.

[0026] For TE-VCSELs with wavelengths less than 1150nm (or any wavelength), the manufacturing process of the package assembly may include wet etching a silicon cavity from the back side of a wafer of a driver IC arranged in the optical path of the TE-VCSEL die after manufacturing the IC circuit of the driver IC. Due to the anisotropic behavior of silicon, the opening size of the silicon cavity at the bonding area of ​​the TE-VCSEL die can be easily controlled from the back side of the wafer using a wet etching process. In addition, Cu-Cu diffusion bonding can be used to bond the TE-VCSEL die to the driver IC to provide electrical connection between the TE-VCSEL die and the driver IC.

[0027] In some implementations, a ToF camera based on VCSEL-on-driver technology is provided, which includes bonding electrical pads by Cu-Cu diffusion bonding (or gold-gold (Au-Au) diffusion bonding) and simultaneously bonding the optical surface of the TE-VCSEL die by oxide-oxide bonding (or oxide-nitride bonding) without any bonding interface material at the bonding wire.

[0028] In some implementations, the driver IC has an etched-through window (eg, an etched-away optical window) to provide a light path for the TE-VCSEL die.

[0029] In some implementations, the bottom surface of the TE-VCSEL die is bonded to the substrate.

[0030] In some implementations, the driver IC is electrically connected via copper core solder pillars or copper core solder balls.

[0031] Figure 1A and Figure 1B 1 and 2 are diagrams respectively depicting a top view of an example transmitter 100 and a cross-sectional view 150 of an example transmitter 100 along line XX. Figure 1A As shown, emitter 100 may include a set of emitter layers constructed in an emitter architecture. In some implementations, emitter 100 may correspond to one or more vertical emitting devices described herein.

[0032] like Figure 1A As shown, in this example, the emitter 100 may include a circular implant protection layer 102. In some implementations, the implant protection layer 102 may have another shape, such as an ellipse, a polygon, etc. The implant protection layer 102 is defined based on the space between portions of an implant material (not shown) included in the emitter 100.

[0033] like Figure 1AAs shown in the medium gray and dark gray areas in , the emitter 100 includes an ohmic metal layer 104 (e.g., a P-type ohmic metal layer or an N-type ohmic metal layer) configured in a partial ring shape (e.g., having an inner radius and an outer radius). The medium gray area shows the area of ​​the ohmic metal layer 104 covered by a protective layer (e.g., a dielectric layer or a passivation layer) of the emitter 100, and the dark gray area shows the area of ​​the ohmic metal layer 104 exposed by the via 106. As shown, the ohmic metal layer 104 overlaps the implant protection layer 102. For example, in the case of a P-top / top emitting emitter 100, this configuration can be used. In the case of a bottom emitting emitter 100, this configuration can be adjusted as needed.

[0034] Figure 1A 1 , the transmitter 100 includes a protective layer having a via 106 formed therein (e.g., etched therein). The dark gray area shows the area of ​​the ohmic metal layer 104 exposed by the via 106 (e.g., the shape of the dark gray area may be a result of the shape of the via 106), while the medium gray area shows the area of ​​the ohmic metal layer 104 covered by some portion of the protective layer. The protective layer may cover all portions of the transmitter except the via. As shown, the via 106 is formed as a partial ring (e.g., similar to the ohmic metal layer 104) and is formed above the ohmic metal layer 104 so that the metallization on the protective layer contacts the ohmic metal layer 104. In some implementations, the via 106 and / or the ohmic metal layer 104 may be formed into another shape, such as a full ring shape or an open ring shape.

[0035] As further shown, the emitter 100 includes an optical aperture 108 located in a portion within the inner radius of the partial ring of the ohmic metal layer 104 of the emitter 100. The emitter 100 emits the laser beam via the optical aperture 108. As further shown, the emitter 100 also includes a current limiting aperture 110 (e.g., an oxide aperture formed by an oxide layer (not shown) of the emitter 100). The current limiting aperture 110 is formed below the optical aperture 108.

[0036] like Figure 1A As further shown, the emitter 100 includes a set of trenches 112 (e.g., oxide trenches) that are spaced (e.g., uniformly, non-uniformly) around the circumference of the implant protection layer 102. How closely the trenches 112 can be positioned relative to the optical aperture 108 depends on the application and is generally limited by the implant protection layer 102, the ohmic metal layer 104, the via 106, and manufacturing tolerances.

[0037] Figure 1A The number and arrangement of layers shown are provided as examples only. Figure 1ACompared to that shown, the emitter 100 may include more layers, fewer layers, different layers, or differently arranged layers. For example, although the emitter 100 includes a set of six grooves 112, in practice, other configurations are also possible, such as a compact emitter including five grooves 112, seven grooves 112, or another number of grooves. In some implementations, the grooves 112 can surround the emitter 100 to form a mesa structure dt. As another example, although the emitter 100 is a circular emitter design, in practice, other designs may be used, such as a rectangular emitter, a hexagonal emitter, an elliptical emitter, etc. Additionally or alternatively, a set of layers (e.g., one or more layers) of the emitter 100 can respectively perform one or more functions described as being performed by another set of layers of the emitter 100.

[0038] It is worth noting that while the design of emitter 100 is described as including a VCSEL, other implementations are possible. For example, the design of emitter 100 can be applied in the context of another type of optical device, such as a light emitting diode (LED), or another type of vertical emitting (e.g., top emitting or bottom emitting) optical device. In addition, the design of emitter 100 can be applied to emitters of any wavelength, power level, and / or emission profile. In other words, emitter 100 is not specific to an emitter having given performance characteristics.

[0039] like Figure 1B As shown, the example cross-sectional view may represent a cross-section of the emitter 100 through or between a pair of trenches 112 (eg, as shown in FIG. 1 ). Figure 1A As shown, the emitter 100 may include a back cathode layer 128, a substrate layer 126, a bottom reflector 124, an active region 122, an oxide layer 120, a top reflector 118, an implanted isolation material 116, a protective layer 114 (e.g., a dielectric passivation / reflector layer), and an ohmic metal layer 104. As shown, for example, the total height of the emitter 100 may be approximately 10 μm.

[0040] The back cathode layer 128 may include a layer in electrical contact with the substrate layer 126. For example, the back cathode layer 128 may include an annealed metallization layer, such as an AuGeNi layer, a PdGeAu layer, or the like.

[0041] The substrate layer 126 may include a base substrate layer on which an epitaxial layer is grown. For example, the substrate layer 126 may include a semiconductor layer, such as a GaAs layer, an InP layer, and / or another type of semiconductor layer.

[0042] The bottom reflector 124 may include a bottom reflector layer of the transmitter 100. For example, the bottom reflector 124 may include a distributed Bragg reflector (DBR). A portion of the bottom reflector 124 may include a current blocking DBR including alternating p-doped layers and n-doped layers. In some implementations, the current blocking DBR may include an intrinsic layer (i-layer) between the p-doped layer and the n-doped layer.

[0043] The active region 122 may include a layer that confines electrons and defines the emission wavelength of the emitter 100. For example, the active region 122 may be a quantum well.

[0044] The oxide layer 120 may include an oxide layer that provides optical and electrical confinement of the emitter 100. In some implementations, the oxide layer 120 may be formed as a result of wet oxidation of an epitaxial layer. For example, the oxide layer 120 may be an Al2O3 layer formed as a result of oxidation of an AlAs or AlGaAs layer. The trench 112 may include an opening that allows oxygen (e.g., dry oxygen, wet oxygen) to enter the epitaxial layer forming the oxide layer 120.

[0045] The current limiting aperture 110 may include an optically active aperture defined by the oxide layer 120. The size of the current limiting aperture 110 may be in a range of, for example, about 4 μm to about 20 μm. In some implementations, the size of the current limiting aperture 110 may depend on the distance between the trenches 112 surrounding the emitter 100. For example, the trenches 112 may be etched to expose the epitaxial layer forming the oxide layer 120. Here, before the protective layer 114 is formed (e.g., deposited), the epitaxial layer may be at a specific distance (e.g., such as 100) toward the center of the emitter 100. Figure 1B 1 , the current limiting aperture 110 is formed by oxidation in the cavity 120 and the current limiting aperture 110. In some implementations, the current limiting aperture 110 may include an oxide aperture. Additionally or alternatively, the current limiting aperture 110 may include an aperture associated with another type of current limiting technology, such as an etched mesa, an area not ion implanted, a lithographically defined intracavity mesa, and regrowth, etc.

[0046] The top reflector 118 may include a top reflector layer of the emitter 100. For example, the top reflector 118 may include a DBR.

[0047] The implant isolation material 116 may include a material that provides electrical isolation. For example, the implant isolation material 116 may include an ion implant material, such as a hydrogen / proton implant material or an implant element of the like, to reduce electrical conductivity. In some implementations, the implant isolation material 116 may define the implant protection layer 102.

[0048] The protective layer 114 may include a layer that functions as a protective passivation layer and may function as an additional DBR. For example, the protective layer 114 may include one or more sublayers (e.g., a dielectric passivation layer and / or a reflector layer, a SiO2 layer, a Si3N4 layer, an Al2O3 layer, or other layers) deposited (e.g., by chemical vapor deposition, atomic layer deposition, or other techniques) on one or more other layers of the emitter 100.

[0049] As shown, the protective layer 114 may include one or more vias 106 that provide electrical access to the ohmic metal layer 104. For example, the vias 106 may be formed as an etched portion of the protective layer 114 or a stripped portion of the protective layer 114. The optical aperture 108 may include a portion of the protective layer 114 above the current limiting aperture 110 through which light may be emitted.

[0050] The ohmic metal layer 104 may include a layer that creates an electrical contact, and current may flow through the layer. For example, the ohmic metal layer 104 may include a Ti and Au layer, a Ti and Pt layer, and / or an Au layer, etc., and current may flow through these layers (e.g., through a bonding pad (not shown) that contacts the ohmic metal layer 104 through the via 106). The ohmic metal layer 104 may be a P-type ohmic, an N-type ohmic, or other forms known in the art. The selection of a particular type of ohmic metal layer 104 may depend on the architecture of the emitter and is well within the knowledge of those skilled in the art. The ohmic metal layer 104 may provide an ohmic contact between a metal and a semiconductor, and / or may provide a non-rectifying electrical junction, and / or provide a low resistance contact. In some implementations, the emitter 100 may be manufactured using a series of steps. For example, the bottom reflector 124, the active area 122, the oxide layer 120, and the top reflector 118 may be epitaxially grown on the substrate layer 126, after which the ohmic metal layer 104 may be deposited on the top reflector 118. Next, the trench 112 can be etched to expose the oxide layer 120 for oxidation. The implant isolation material 116 can be produced via ion implantation, after which the protective layer 114 can be deposited. The via 106 can be etched in the protective layer 114 (e.g., to expose the ohmic metal layer 104 for contact). Plating, seeding, and etching can be performed, after which the substrate layer 126 can be thinned and / or ground to a target thickness. Finally, the back cathode layer 128 can be deposited on the bottom surface of the substrate layer 126.

[0051] Figure 1B The number, arrangement, thickness, order, symmetry, etc. of the layers shown are provided as examples only. Figure 1BTransmitter 100 may include more layers, fewer layers, different layers, differently constructed layers, or differently arranged layers than shown. Additionally or alternatively, a set of layers (e.g., one or more layers) of transmitter 100 may perform one or more functions described as being performed by another set of layers of transmitter 100, and any layer may include more than one layer.

[0052] Figure 2 A package assembly 200 is shown according to one or more implementations. The package assembly 200 can be configured for use with an emitter emitting at a wavelength of 1150 nm or greater.

[0053] The package assembly 200 may include a circuit substrate 202 (eg, a base substrate), a TE-VCSEL die 204 , a driver IC 206 (eg, a driver die), and a package case 208 .

[0054] The circuit substrate 202 may include a first substrate surface 202a (e.g., a top substrate surface) and a second substrate surface 202b (e.g., a bottom substrate surface) disposed opposite the first substrate surface 202a. The second substrate surface 202b may include a plurality of conductive interconnect structures 203 (e.g., contact pads) for connecting to one or more external components. The first substrate surface 202a may be used to mount internal components (such as TE-VCSEL die 204 and driver IC 206) and a package housing 208 to the circuit substrate 202.

[0055] The circuit substrate 202 may be a circuit board, such as a printed circuit board (PCB), a ceramic substrate, or any other substrate configured to provide a conductive path between internal components of the package assembly 200 and external components. For example, the circuit substrate 202 may be used to provide power signals (e.g., power supply signals), information signals, and / or control signals from external components to internal components of the package assembly 200. In addition, the circuit substrate 202 may be used to provide feedback signals or information signals from internal components to external components. In some implementations, the circuit substrate 202 may provide a thermal path for dissipating heat from the TE-VCSEL die 204 and for improving the thermal performance of the TE-VCSEL die 204.

[0056] The TE-VCSEL die 204 may be arranged on a first substrate surface 202a of the circuit substrate 202. The TE-VCSEL die 204 may include an emitter array 210 (e.g., a 2D matrix addressable emitter array) having a plurality of VCSEL emitters (which are 2D matrix addressable). Each emitter of the emitter array 210 may be a TE-VCSEL emitter similar to the emitter 100. In addition, the TE-VCSEL die 204 may include a first major surface 204a (e.g., a back surface or bottom surface) and a second major surface 204b (e.g., a front surface or top surface). The first major surface 204a may be coupled or otherwise bonded to the first substrate surface 202a, and the second major surface 204b may be arranged opposite to the first major surface 204a. The first major surface 204a may be bonded to the first substrate surface 202a using a non-conductive medium (such as an adhesive or gel). The TE-VCSEL die 204 may include a light output portion arranged at the second main surface 204b, wherein the light output portion is configured to output light generated by one or more of the plurality of VCSEL emitters. Thus, the optical aperture of each emitter may be arranged at or near the second main surface 204b, and light may exit the TE-VCSEL die 204 from the second main surface 204b.

[0057] The driver IC 206 can be arranged on the second main surface 204b of the TE-VCSEL die 204 and coupled to the second main surface, so that the TE-VCSEL die 204 and the driver IC 206 form a die stack on the first substrate surface 202a of the circuit substrate 202. In addition, the driver IC 206 can have a flip-chip interconnect configuration. As a result, the active area of ​​the driver IC 206 is flipped to face down, rather than face up, and is bonded to the package leads from the outer edge of the die with wires. The flip-chip conductive interconnects (such as bumps, balls, or pads) of the driver IC 206 can be arranged near the active area, at a shorter distance than the wires, which greatly reduces the inductance and provides an improved electrical connection. The driver IC 206 can be electrically coupled (e.g., directly coupled) to the TE-VCSEL die 204 to drive each of the multiple VCSEL emitters individually according to the 2D matrix address. In addition, the flip-chip interconnect configuration can allow the package assembly 200 to be completely free of wire bonding. Thus, shorter electrical connections may be used to transmit higher quality signals within package assembly 200 than would otherwise be possible using wire bonds.

[0058] The driver IC 206 may include a semiconductor substrate (e.g., silicon) or other driver substrate including a third main surface 206a (e.g., front surface or bottom surface) coupled to the second main surface 204b of the TE-VCSEL die 204, a fourth main surface 206b (e.g., back surface or top surface) arranged opposite to the third main surface 206a, and a driver circuit system 212 integrated in the semiconductor substrate. The driver circuit system 212 may be located in one or more active regions of the semiconductor substrate. For example, the driver circuit system 212 may be divided into two or more active regions of the semiconductor substrate to reduce the length of the electrical connection between the driver circuit system 212 and the TE-VCSEL die 204. The driver circuit system 212 may include a digital control circuit configured to generate a drive signal for driving a plurality of VCSEL emitters.

[0059] The driver IC 206 may include a first plurality of conductive interconnect structures 214 coupled to the third major surface 206a. The first plurality of conductive interconnect structures 214 may include a first subset 214a of conductive interconnect structures electrically coupled to the driver circuit system 212 and the plurality of VCSEL emitters of the emitter array 210, and a second subset 214b of conductive interconnect structures electrically coupled to the driver circuit system 212 and the circuit substrate 202. Conductive traces (e.g., a series of conductive layers and vias) integrated in the semiconductor substrate may connect the first subset 214a of the conductive interconnect structures to the driver circuit system 212. Furthermore, additional conductive traces integrated in the semiconductor substrate may connect the second subset 214b of the conductive interconnect structures to the driver circuit system 212. Thus, the first subset 214a of the conductive interconnect structures may be used to provide drive signals from the driver circuit system 212 to the emitter array 210 for 2D addressable control, and the second subset 214b of the conductive interconnect structures may be used to provide signals between the driver circuit system 212 and one or more external elements coupled to the circuit substrate 202. For example, the second subset 214b of the conductive interconnect structure can be configured to receive a power signal and a transmitter control signal from the circuit substrate 202. The package assembly 200 can include a conductive column 216 coupled to the second subset 214b of the conductive interconnect structure and the circuit substrate 202. For example, the conductive column 216 extends between the circuit substrate 202 and the third main surface 206a of the driver IC 206. The conductive column 216 can be a copper (Cu) column or a copper core solder column. Alternatively, a copper ball or a copper core solder ball can be used instead of the conductive column 216. The conductive column 216 can be used to provide an electrical connection and a mechanical connection between the circuit substrate 202 and the driver IC 206. For example, the conductive column 216 can provide structural support for the driver IC 206, which can prevent deformation of the driver IC 206.

[0060] The TE-VCSEL die 204 may include a second plurality of conductive interconnect structures 218 disposed at the second main surface 204b of the TE-VCSEL die 204. The second plurality of conductive interconnect structures 218 may be electrically coupled to the first subset 214a of the conductive interconnect structures. Thus, the second plurality of conductive interconnect structures 218 may be coupled to the first subset 214a of the conductive interconnect structures by metal-to-metal bonding, such as copper-to-copper bonding or gold-to-gold bonding. For example, the second plurality of conductive interconnect structures 218 may be bonded to the first subset 214a of the conductive interconnect structures by TCB bonding or another type of diffusion bonding.

[0061] The package assembly 200 may include one or more bonding layers 220 (e.g., at least one bonding layer) including an inorganic material such as SiO2, Al2O3, and / or Si3N4, wherein the one or more bonding layers 220 are arranged above the emitter array 210, between the TE-VCSEL die 204 and the driver IC 206. Thus, in the light path of the emitted light, the one or more bonding layers 220 may be arranged above the light path region of the TE-VCSEL die 204. The one or more bonding layers 220 are configured to bond the second main surface 204b to the third main surface 206a. In some implementations, two bonding layers 220 may be bonded together. The bonding of the two bonding layers 220 and the metal-to-metal bonding for bonding the second plurality of conductive interconnect structures 218 to the first subset 214a of the conductive interconnect structures may be performed simultaneously in the same processing step (e.g., a manufacturing step). The one or more bonding layers 220 may provide protection for the emitter array 210. For example, package assembly 200 can provide improved device reliability against moisture penetration because the front surface of the VCSEL emitter (e.g., the optical surface of the emitter) is bonded to driver IC 206 via one or more bonding layers 220. Thus, one or more bonding layers 220 can seal emitter array 210 from moisture and other particulate contaminants.

[0062] The TE-VCSEL die 204 may be configured to generate heat during operation. For example, the emitters of the emitter array 210 may generate heat when enabled / activated for light emission. The TE-VCSEL die 204 may be thermally coupled to the circuit substrate 202. Thus, the circuit substrate 202 may be configured to dissipate at least a portion of the heat through one or more thermal paths (e.g., at least one thermal path). Additionally or alternatively, the TE-VCSEL die 204 may be thermally coupled to the semiconductor substrate of the driver IC 206. Thus, the semiconductor substrate of the driver IC 206 may be configured to dissipate at least a portion of the heat through one or more thermal paths. For example, in some implementations, the semiconductor substrate of the driver IC 206 may be configured to dissipate a first portion of the heat, and the circuit substrate 202 may be configured to dissipate a second portion of the heat. The semiconductor substrate of the driver IC 206 may include a blank semiconductor region 222 disposed over the entire area of ​​the emitter array 210. The blank semiconductor region 222 may be a component-free region of the original semiconductor material that is configured to receive the first portion of the heat and distribute the first portion of the heat laterally toward the edge of the semiconductor substrate. In some implementations, the blank semiconductor region 222 is configured to distribute the first portion of the heat away from the driver circuit system 212 so that the first portion of the heat does not degrade the thermal performance of the driver circuit system 212.

[0063] The package housing 208 can be bonded to the first substrate surface 202a and can be disposed above the die stack (extending above the die stack). The package housing 208 can be coupled to the fourth major surface 206b of the driver IC by a bonding material 224 (such as an adhesive or gel). The package housing 208 may include an optical window 226 disposed above the light path region and configured to allow light generated by the emitter array 210 to exit the package assembly 200.

[0064] In some implementations, the semiconductor substrate of the driver IC 206 is optically transparent to light generated by the emitter array 210. For example, the semiconductor substrate can be optically transparent to light having a wavelength of 1150 nm or greater. In other words, for wavelengths of 1150 nm or greater, the light absorption coefficient of the semiconductor substrate can be low enough so that any light absorption is within acceptable limits for light transmission. For example, for wavelengths of 1150 nm or greater, the semiconductor substrate can pass at least 95% of the light received from the emitter array 210. The amount of light transmitted through the semiconductor substrate can depend on the light absorption coefficient of the semiconductor substrate for a particular wavelength and the thickness of the semiconductor substrate.

[0065] The TE-VCSEL die 204 can be configured to transmit light to the optical window 226 through the optical path region of the semiconductor substrate. The optical path region can coincide with the blank semiconductor region 222. For example, the blank semiconductor region 222 can be arranged above the emitter array 210 and located in the optical path region of the semiconductor substrate. The blank semiconductor region 222 is a component-free region of the original semiconductor material and can be configured to receive light from the emitter array 210 and pass the light to the optical window 226.

[0066] In some implementations, the package assembly 200 may include at least one capacitor (cap) die 228, wherein each capacitor die 228 includes a plurality of capacitors (e.g., a cap array). The driver IC 206 may include a third plurality of conductive interconnect structures 230 coupled to the third main surface 206a. The at least one capacitor die 228 may be coupled to the third main surface 206a of the driver IC 206 and may be electrically coupled to the third plurality of conductive interconnect structures 230. In addition, the plurality of capacitors may be electrically coupled to the emitter array 210 via the third plurality of conductive interconnect structures 230. The plurality of capacitors may be used to provide a stable voltage to the driver circuit system 212 and / or the emitter array 210.

[0067] In some implementations, an anti-reflective coating 232 can be disposed on the fourth major surface 206b (e.g., the backside or top surface) of the driver IC 206. The anti-reflective coating 232 can be disposed in an optical path region (e.g., in an optical transmission path). The anti-reflective coating 232 can suppress or attenuate optical substrate modes caused by multiple reflections, which can result in a cleaner spectral output and / or an optical output with lower noise.

[0068] As mentioned above, Figure 2 Other examples can be found in the Figure 2 Different from what is described. Figure 2 The number and arrangement of the devices and elements shown are provided as examples only. Figure 2 There may be more devices or elements, fewer devices or elements, different devices or elements, or differently arranged devices or elements than shown.

[0069] Figure 3 A package assembly 300 is shown according to one or more implementations. The package assembly 300 can be configured for an emitter having an emission wavelength of any wavelength, including wavelengths less than 1150 nm. For example, the light absorption coefficient of the semiconductor substrate can be high enough for wavelengths less than 1150 nm that any light absorption can be out of the acceptable range for light transmission.

[0070] Package assembly 300 can be similar to package assembly 200, except that the semiconductor substrate includes a cavity 302 arranged above the light path region of the emitter array 210 (for example, located in the light path region of the semiconductor substrate of the driver IC 206), and includes a lens 304 arranged above the light path region of the emitter array 210 and above the light path region of the semiconductor substrate.

[0071] The cavity 302 may extend through the semiconductor substrate between the third major surface 206a and the fourth major surface 206b. Thus, the TE-VCSEL die 204 may be configured to transmit light to the optical window 226 through the cavity 302. The cavity 302 may be surrounded by semiconductor material of the semiconductor substrate. Portions of the driver IC 206 at the edges of the cavity 302 may be bonded to the TE-VCSEL die 204 by one or more bonding layers 220.

[0072] The lens 304 may be disposed within the optical window 226 of the package housing 208 and disposed above the cavity 302. In addition, the lens 304 may be coupled to the fourth major surface 206b of the semiconductor substrate of the driver IC 206. For example, the lens 304 may be coupled to the fourth major surface 206b using a bonding material such as an adhesive or a gel.

[0073] The lens 304 can be configured to receive light from the TE-VCSEL die 204 and transmit the light out of the package assembly 300. In some implementations, a diffractive optical element (DOE) 306 can be disposed on the bottom surface of the lens 304 to homogenize and / or focus the laser light. In some implementations, the emitter array 210 can be configured to generate light having a wavelength less than 1150 nm.

[0074] In some implementations, an anti-reflection coating 308 can be disposed on the lens 304. The anti-reflection coating 308 can be disposed in a light path region (e.g., in a light transmission path). The anti-reflection coating 308 can suppress or attenuate optical substrate modes caused by multiple reflections, which can result in a cleaner spectral output and / or a light output with lower noise.

[0075] As mentioned above, Figure 3 Other examples can be found in the Figure 3 Different from what is described.

[0076] Figure 4 is a flow chart of an example process 400 associated with manufacturing a package assembly for a TE-VCSEL device. In some implementations, Figure 4 One or more process blocks of are performed by a package assembly manufacturing system.

[0077] like Figure 4As shown, process 400 may include attaching a TE-VCSEL die to a driver IC (e.g., a driver die) to form a die stack (block 410). Process 400 may include manufacturing the TE-VCSEL die and the driver IC. For example, the TE-VCSEL die may include an emitter array including a plurality of VCSEL emitters, wherein the TE-VCSEL die includes a first major surface and a second major surface arranged opposite to the first major surface, and wherein the TE-VCSEL die includes a light output portion arranged at the second major surface, the light output portion being configured to output light generated by one or more VCSEL emitters of the plurality of VCSEL emitters, wherein the driver IC is coupled to the second major surface of the TE-VCSEL die to form a die stack, wherein the driver IC has a flip-chip interconnect configuration, as described above.

[0078] like Figure 4 As further shown, process 400 may include attaching the TE-VCSEL die to a circuit substrate (block 420). The circuit substrate may include a first substrate surface and a second substrate surface disposed opposite the first substrate surface, wherein a first major surface of the TE-VCSEL die is coupled to the first substrate surface of the circuit substrate such that the TE-VCSEL die is disposed between the circuit substrate and the driver IC, as described above.

[0079] like Figure 4 As further shown, process 400 may include electrically coupling a driver IC to a first substrate surface of a circuit substrate (block 430). The driver IC may include a semiconductor substrate including a third major surface coupled to a second major surface of the TE-VCSEL die, a fourth major surface disposed opposite the third major surface, and a driver circuit system integrated in the semiconductor substrate, wherein the driver IC includes a first plurality of conductive interconnect structures coupled to the third major surface, wherein the first plurality of conductive interconnect structures includes a first subset of conductive interconnect structures electrically coupled to the driver circuit system and the plurality of VCSEL emitters, and a second subset of conductive interconnect structures electrically coupled to the driver circuit system and the circuit substrate, as described above.

[0080] Process 400 may include other implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein.

[0081] although Figure 4 An example block diagram of process 400 is shown, but in some implementations, Figure 4 Process 400 includes more blocks, fewer blocks, different blocks, or differently arranged blocks than shown. Additionally or alternatively, two or more blocks of process 400 may be performed in parallel.

[0082] The above disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications and variations may be made based on the above disclosure, or may be obtained from the practice of the implementation. In addition, any implementation described herein may be combined, unless the above disclosure explicitly provides reasons why one or more implementations cannot be combined.

[0083] As used herein, the term "element" is intended to be broadly interpreted as hardware, firmware, and / or a combination of hardware and software. It is apparent that the systems and / or methods described herein can be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods does not limit these implementations. Therefore, the operation and behavior of the systems and / or methods are described herein without reference to specific software codes--it is understood that software and hardware can be designed to implement these systems and / or methods based on the description herein.

[0084] Although the specific combination of features is cited in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of various implementations. In fact, many of these features can be combined in a manner that is not specifically cited in the claims and / or is not disclosed in the specification. Although each dependent claim listed below can only directly depend on one claim, the disclosure of various implementations includes the combination of each dependent claim with each other claim in the claim set. As used herein, the phrase "at least one" in the referenced item list refers to any combination of these items, including single members. For example, "at least one of a, b or c" is intended to cover a, b, c, ab, ac, bc and abc, and the combination of multiple items in the same item.

[0085] When one or more elements (e.g., a laser emitter or one or more laser emitters) are described or claimed (either within a single claim or across multiple claims) as performing multiple operations or being configured to perform multiple operations, such language is intended to broadly encompass a variety of architectures and environments. For example, unless otherwise expressly claimed (e.g., by using "first element" and "second element" or other language that distinguishes elements in a claim), the language is intended to encompass a single element performing or being configured to perform all operations, a group of elements collectively performing or being configured to perform all operations, a first element performing or being configured to perform a first operation and a second element performing or being configured to perform a second operation, or any combination of elements performing or being configured to perform operations. For example, when a claim is of the form "One or more elements are configured to: perform X; perform Y; and perform Z," the claim should be interpreted as "One or more elements are configured to perform X; one or more (possibly different) elements are configured to perform Y; and one or more (possibly different) elements are configured to perform Z."

[0086] Unless explicitly stated, any element, behavior or instruction used in this article should not be interpreted as critical or essential. In addition, as used in this article, the article "one" and "an" are intended to include one or more projects, and can be used interchangeably with "one or more". In addition, as used in this article, the article "said" is intended to include one or more projects quoted in combination with the article "said", and can be used interchangeably with "one or more". In addition, the word "set" used in this article is intended to include one or more projects (for example, a combination of related projects, unrelated projects, or related and unrelated projects), and can be used interchangeably with "one or more". If only one project is intended to be used, the phrase "only one" or similar language is used. In addition, as used in this article, the term "having", "having", "containing" etc. is intended to be an open term. In addition, unless otherwise explicitly stated, the word "based on" is intended to represent "at least partially based on". In addition, as used in this article, the term "or" is inclusive when used in series, and can be used interchangeably with "and / or", unless otherwise explicitly stated (for example, if used in combination with "any one of ... or "only one of ... "). Additionally, for ease of description, spatially relative terms (such as "below," "lower," "above," "upper," etc.) may be used herein to describe the relationship of one element or feature to other elements or features shown in the figures. Spatially relative terms are intended to encompass different orientations of the device, equipment, and / or elements in use or operation in addition to the orientations shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

Claims

1. A packaging component, comprising: A circuit substrate, comprising a first substrate surface and a second substrate surface, wherein the second substrate surface is arranged opposite to the first substrate surface; a top-emitting TE vertical cavity surface emitting laser VCSEL die, arranged on the first substrate surface of the circuit substrate, wherein the TE-VCSEL die comprises an emitter array, the emitter array comprises a plurality of VCSEL emitters, the emitter array is two-dimensionally 2D matrix addressable, wherein the TE-VCSEL die comprises a first main surface and a second main surface, wherein the first main surface is coupled to the first substrate surface, and the second main surface is arranged opposite to the first main surface, and wherein the TE-VCSEL die comprises a light output portion, the light output portion is arranged at the second main surface, and the light output portion is configured to output light generated by one or more VCSEL emitters among the plurality of VCSEL emitters; as well as a driver integrated circuit IC arranged on the second main surface of the TE-VCSEL die and coupled to the second main surface, so that the TE-VCSEL die and the driver IC form a die stack on the first substrate surface of the circuit substrate, wherein the driver IC has a flip-chip interconnect configuration, and wherein the driver IC is electrically coupled to the TE-VCSEL die to drive each of the plurality of VCSEL emitters individually according to a 2D matrix address, The driver IC comprises a driver substrate, the driver substrate comprises a third main surface, a fourth main surface and a driver circuit system, the third main surface is coupled to the second main surface of the TE-VCSEL tube core, the fourth main surface is arranged opposite to the third main surface, and the driver circuit system is integrated in the driver substrate, wherein the driver IC comprises a first plurality of conductive interconnect structures coupled to the third main surface, wherein the first plurality of conductive interconnect structures comprises a first subset of conductive interconnect structures and a second subset of conductive interconnect structures, the first subset of conductive interconnect structures is electrically coupled to the driver circuit system and the multiple VCSEL emitters, and the second subset of conductive interconnect structures is electrically coupled to the driver circuit system and the circuit substrate. 2 . The package assembly of claim 1 , wherein the second subset of the conductive interconnect structures is configured to receive power signals and transmitter control signals from the circuit substrate. 3 . The package assembly of claim 1 , wherein the driver circuitry comprises a digital control circuit configured to generate drive signals for driving the plurality of VCSEL emitters.

4. The package assembly according to claim 1, further comprising: A conductive pillar is coupled to the second subset of the conductive interconnect structures and the circuit substrate, wherein the conductive pillar extends between the circuit substrate and the driver IC.

5. The package assembly of claim 1 , wherein the TE-VCSEL die comprises a second plurality of conductive interconnect structures, the second plurality of conductive interconnect structures being arranged at the second major surface of the TE-VCSEL die, and Wherein the second plurality of conductive interconnect structures are electrically coupled to a first subset of the conductive interconnect structures.

6. The package assembly according to claim 5, further comprising: a bonding layer comprising an inorganic material, wherein the bonding layer is arranged over the emitter array, between the TE-VCSEL die and the driver IC, and wherein the bonding layer is configured to bond the second major surface to the third major surface, Wherein the second plurality of conductive interconnect structures are coupled to the first subset of conductive interconnect structures by metal-to-metal bonding.

7. The package assembly according to claim 1, further comprising: A packaging housing is disposed over the die stack, wherein the packaging housing is coupled to the fourth major surface of the driver IC, and wherein the packaging housing includes an optical window configured to allow the light to exit the package assembly.

8. The package assembly of claim 7, wherein the driver substrate is optically transparent to the light, wherein the TE-VCSEL die is configured to transmit the light through a light path region of the driver substrate to the optical window.

9. The package assembly of claim 8, wherein the driver substrate comprises a blank semiconductor region disposed above the emitter array and in the light path region of the driver substrate, and The blank semiconductor region is a component-free region of the original semiconductor material, and the component-free region is configured to receive the light from the emitter array and pass the light to the optical window.

10. The package assembly of claim 8, wherein the TE-VCSEL die is configured to generate the light at a wavelength of 1150 nanometers (nm) or greater.

11. The package assembly of claim 7, wherein the driver substrate comprises a cavity extending through the driver substrate between the third major surface and the fourth major surface, and Wherein the TE-VCSEL die is configured to transmit the light through the cavity to the optical window.

12. The package assembly according to claim 11, further comprising: a lens coupled to the fourth major surface and disposed within the optical window and over the cavity, The lens is configured to receive the light from the TE-VCSEL die and transmit the light out of the package assembly.

13. The package assembly of claim 11, wherein the TE-VCSEL die is configured to generate the light at a wavelength less than 1150 nanometers (nm).

14. The package assembly of claim 1, wherein the TE-VCSEL die is configured to generate heat during operation, wherein the TE-VCSEL die is thermally coupled to the circuit substrate, and Wherein the circuit substrate is configured to dissipate at least a portion of the heat.

15. The package assembly of claim 1, wherein the TE-VCSEL die is configured to generate heat during operation, wherein the TE-VCSEL die is thermally coupled to the driver substrate and the circuit substrate, wherein the driver substrate is configured to dissipate a first portion of the heat, and The circuit substrate is configured to dissipate a second portion of the heat.

16. The package assembly of claim 15, wherein the driver substrate comprises a blank semiconductor region disposed over the entire area of ​​the emitter array, and The blank semiconductor region is a component-free region configured to receive a first portion of the heat and to distribute the first portion of the heat laterally toward an edge of the driver substrate. 17 . The package assembly of claim 16 , wherein the blank semiconductor region is configured to distribute a first portion of the heat away from the driver circuitry.

18. The package assembly of claim 1, further comprising: at least one capacitor die including a plurality of capacitors, wherein the driver IC includes a second plurality of conductive interconnect structures coupled to the third major surface, wherein the at least one capacitor die is coupled to the third major surface of the driver IC and is electrically coupled to the second plurality of conductive interconnect structures, and Wherein the plurality of capacitors are electrically coupled to the transmitter array via the second plurality of conductive interconnect structures.

19. The package assembly of claim 1, wherein the package assembly is free of wire bonds.

20. A method comprising: Attaching a top emitting TE vertical cavity surface emitting laser VCSEL die to a driver integrated circuit IC to form a die stack, wherein the TE-VCSEL die comprises an emitter array, the emitter array comprising a plurality of VCSEL emitters, wherein the TEE-VCSEL die comprises a first main surface and a second main surface, the second main surface being arranged opposite to the first main surface, and wherein the TE-VCSEL die comprises a light output portion, the light output portion being arranged at the second main surface, the light output portion being configured to output light generated by one or more VCSEL emitters of the plurality of VCSEL emitters, wherein the driver IC is coupled to the second major surface of the TE-VCSEL die to form the die stack, wherein the driver IC has a flip-chip interconnect configuration; attaching the TE-VCSEL die to a circuit substrate, the circuit substrate comprising a first substrate surface and a second substrate surface, the second substrate surface being arranged opposite to the first substrate surface, wherein the first major surface of the TE-VCSEL die is coupled to the first substrate surface of the circuit substrate such that the TE-VCSEL die is arranged between the circuit substrate and the driver IC; as well as electrically coupling the driver IC to the first substrate surface of the circuit substrate, The driver IC comprises a driver substrate, the driver substrate comprises a third main surface, a fourth main surface and a driver circuit system, the third main surface is coupled to the second main surface of the TE-VCSEL tube core, the fourth main surface is arranged opposite to the third main surface, and the driver circuit system is integrated in the driver substrate, wherein the driver IC comprises a first plurality of conductive interconnect structures coupled to the third main surface, wherein the first plurality of conductive interconnect structures comprises a first subset of conductive interconnect structures and a second subset of conductive interconnect structures, the first subset of conductive interconnect structures is electrically coupled to the driver circuit system and the multiple VCSEL emitters, and the second subset of conductive interconnect structures is electrically coupled to the driver circuit system and the circuit substrate.

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