Method and controller for balancing voltage

Abstract

The invention discloses a method and a controller for balancing voltage. The method is used for balancing voltage on a flying capacitor in a multi-level power converter. The power converter includes one or more flying capacitors. Switching pairs in the power converter are controlled by a pulse width modulation (PWM) control signal. The different switch pairs are controlled by a PWM control signal having a phase / timing offset between them. To balance the voltage across one or more flying capacitors, one set of pulses may be widened or narrowed while the other set of pulses may be narrowed or widened. In order to vary their width, one edge of each pulse is modulated while the other edge is unchanged. More specifically, the leading edge of one set of pulses is modulated, while the trailing edge of the other set of pulses is modulated.

Description

Technical Field

[0001] The present invention relates to the control of a multi-level converter. In particular, the present invention relates to balancing the voltage on one or more flying capacitors in a multi-level converter. Background Art

[0002] Multilevel converters are attractive for applications that require high efficiency and small size. Multilevel topologies with N levels can reduce the inductance of the converter. Compared with the traditional two-level architecture, such a converter can also reduce the voltage stress across the switching device times. In general, a multi-level flying capacitor converter consists of 2(N-1) switches and (N-2) interconnected flying capacitors. The 2(N-1) switches can be logically divided into (N-1) switch pairs. Each pair has two switches driven in a complementary manner, and each pair differs from the previous pair by phase. For example, in Figure 1 In the exemplary three-level converter shown, the converter has a flying capacitor C fly and two switch pairs A and B. The switch pairs are driven 180° out of phase. Each switch pair, and It consists of two switches driven in a complementary manner.

[0003] A switch (also referred to herein as a "switching element") is typically a controlled switching element, typically implemented as a transistor. Figure 1 In the example of FIG. 1 , the switch is a metal oxide semiconductor field effect transistor (MOSFET).

[0004] The voltage stress reduction and ripple frequency increase (lower inductance) come from the voltage across the flying capacitor at The fact of balance, where n is the index of the flying capacitor, which is also used as the switch pair index for the "inner" switch pairs, which for this purpose ranges between 1 and N-2. The index n=1 refers to the innermost switch pair ( exist Figure 1 In the example of ). Index n=N-1 refers to the outermost switch pair ( exist Figure 1 ), which is coupled to the supply voltage instead of the flying capacitor. For buck-based topologies, V total =V in For boost-based topologies, V total =V out For the buck-boost topology, V total =V in +V out .

[0005] Any voltage mismatch on the flying capacitor may lead to higher voltage stress and subharmonic oscillations in the inductor current. In theory, in many topologies, interleaved operation of the switch pairs helps to provide a natural balance for the flying capacitor (FC) voltage. However, in practice, the FC voltage is sensitive to gate drive circuitry mismatch and other circuit imperfections. Therefore, active balancing of the flying capacitor (FC) is required in such architectures. Summary of the invention

[0006] The inventors have recognized that there is a need for an improved control scheme for better balancing the flying capacitor voltages.

[0007] A method for balancing the voltage on a flying capacitor in a multilevel power converter (together with an associated controller) is provided. The power converter includes one or more flying capacitors. The switch pairs in the power converter are controlled by a pulse width modulation (PWM) control signal. Different switch pairs are controlled by a PWM control signal with a phase / timing offset between them. In order to balance the voltage on one or more flying capacitors, one group of pulses can be widened or narrowed, while another group of pulses is narrowed or widened. In order to change their width, one edge of each pulse is modulated, while the other edge is unchanged. More specifically, the leading edge of one group of pulses is modulated, while the trailing edge of another group of pulses is modulated.

[0008] According to one aspect, a method for balancing voltages on one or more flying capacitors in a multilevel power converter is disclosed, the multilevel power converter comprising: a plurality of switch element pairs arranged in a nested manner, the plurality of switch element pairs comprising at least a first switch element pair and a second switch element pair, wherein the first pair is an innermost pair, wherein the switch elements in the first switch element pair are coupled together at a switch node, wherein the switch elements in the second switch element pair are coupled to corresponding switch elements in the first switch element pair, the multilevel power converter further comprising: one or more flying capacitors comprising at least a first flying capacitor connected across the first switch element pair, the method comprising:

[0009] obtaining a duty cycle command value for driving a switching element;

[0010] generating a first pulse width modulation, PWM, control signal for a first switching element pair and a second PWM control signal for a second switching element pair based on the duty cycle command value,

[0011] The first PWM control signal comprises a series of first pulses at a switching frequency, and the second PWM control signal comprises a series of second pulses at the switching frequency, each pulse having a start and an end,

[0012] wherein one switching element in the first switching element pair is controlled by a first PWM control signal, and the other switching element in the first switching element pair is controlled by a complementary signal of the first PWM control signal,

[0013] wherein one switch element in the second switch element pair is controlled by a second PWM control signal, and the other switch element in the second switch element pair is controlled by a complementary signal of the second PWM control signal;

[0014] detecting a difference between a voltage on the first flying capacitor and a reference voltage of the flying capacitor; and

[0015] In response to detecting the difference, modifying the width of the first pulse,

[0016] The method further includes modifying the width of the second pulse,

[0017] wherein the width of the first pulses is modified by changing the timing of the start of each first pulse, and the width of the second pulses is modified by changing the timing of the end of each second pulse, or

[0018] Therein, the width of the first pulse is modified by changing the timing of the end of each first pulse, and the width of the second pulse is modified by changing the timing of the start of each second pulse.

[0019] Balancing the capacitor voltages by varying the alternate edges of the PWM pulses can help ensure system stability.

[0020] In some cases, the width of the second pulse can be modified to balance the voltage on the second flying capacitor. The second flying capacitor can be coupled across the second switch element pair. In this case, the second pulse and the first pulse can be modified in the same direction or in different directions depending on the voltage on the first flying capacitor and the second flying capacitor.

[0021] In one case, the width of the second pulse can be modified to balance the voltage on the first flying capacitor. In this case, the method can include modifying the width of the first pulse in one direction and modifying the width of the second pulse in the opposite direction in response to detecting the difference. For example, this case is applicable to a three-level power converter. By modifying the width of both the first pulse and the second pulse, the method can promote faster balancing of the voltage on the first flying capacitor.

[0022] Here, "one sense" and "opposite sense" mean that the width of one set of pulses increases, while the width of the other set of pulses decreases. Whether to increase or decrease the width of the first pulse depends on whether the voltage on the first flying capacitor is higher or lower than the reference voltage. It also depends on which switching elements are controlled by the PWM signal and which are controlled by their complementary signals. By widening the pulses of one PWM control signal and correspondingly narrowing the pulses of the other PWM control signal, the average duty cycle can be maintained while correcting the voltage on the flying capacitor.

[0023] The PWM control signal may be generated in an interleaved manner. Under some conditions (related to the voltage conversion ratio of the converter), the first pulse may not overlap with the second pulse. Under other conditions, the first pulse and the second pulse may overlap.

[0024] When modifying the width of a pulse, a widened pulse may be widened by a first amount; and a narrowed pulse may be narrowed by a second amount. The first amount may be the same as the second amount. The timing of the end of each first pulse relative to the beginning of each second pulse may remain unchanged. This helps ensure stability over a wider range of load conditions.

[0025] The first PWM control signal and the second PWM control signal may be generated to have a predetermined time or phase shift therebetween (particularly in a steady state, when one or more flying capacitors are balanced).

[0026] Depending on the topology of the power converter, the switch node may be configured to deliver a load current to the load. In other topologies, the switch node may be configured to be coupled to a supply voltage.

[0027] The width of the first pulse can be modified by changing the timing of the start of each first pulse, and the width of the second pulse can be modified by changing the timing of the end of each second pulse, wherein when the width of the first pulse and the second pulse is modified, the time interval between the start of the first pulse and the end of the second pulse can optionally be kept constant.

[0028] The width of the first pulse can be modified by changing the timing of the end of each first pulse, and the width of the second pulse can be modified by changing the timing of the start of each second pulse, wherein when the width of the first pulse and the second pulse is modified, the time interval between the end of the first pulse and the start of the second pulse can optionally be kept constant.

[0029] Specifically, the above-mentioned condition may be maintained between each first pulse and its adjacent second pulse.

[0030] The first PWM control signal may be generated from a first carrier wave, and the second PWM control signal may be generated from a second carrier wave, wherein one of the first carrier wave and the second carrier wave is a ramp-up sawtooth function with a sharp trailing edge, and the other carrier wave is a ramp-down sawtooth function with a sharp leading edge. The PWM control signal may be generated by comparing the corresponding carrier wave with a threshold value. The threshold value may be based on a duty cycle command value.

[0031] The timing of the first carrier wave may be set based on the timing of a carrier wave used to generate a PWM control signal for an outermost switching element pair among the plurality of switching element pairs.

[0032] The multi-level power converter can be configured for N levels, and the multiple switch element pairs can be composed of N-1 switch element pairs, and the method optionally includes generating a PWM control signal for each switch element pair based on a corresponding carrier including a sawtooth function, wherein the sawtooth function alternates between a ramp-up sawtooth function and a ramp-down sawtooth function.

[0033] Alternation can be thought of in terms of a sequence starting with the innermost pair of switching elements in a nested arrangement and ending with the outermost pair of switching elements. Likewise, it can be thought of as a sequence in the opposite direction, from the outermost pair to the innermost pair. In either interpretation, the alternating definition is the same. Each subsequent pair of switching elements inside (or outside) its preceding pair of switching elements is controlled in an opposite manner to the previous pair. Thus, successive switching elements are controlled in opposite manners (using opposite edges of the corresponding PWM pulses).

[0034] The innermost pair of switch elements may be numbered n=1; the outermost pair of switch elements (which are not associated with a flying capacitor) may be numbered n=N-1.

[0035] The PWM control signal may be generated by comparing the sawtooth function to one or more thresholds. Each pulse may correspond to a time period during which the sawtooth function is below a corresponding threshold.

[0036] In some examples, odd-numbered pairs of switching elements may be controlled based on a ramp-down sawtooth function. That is, PWM control signals for the first (innermost), third, fifth, etc. pairs may be generated based on a ramp-down sawtooth function with a sharp leading edge. Even-numbered pairs of switching elements may be controlled based on a ramp-up sawtooth function, that is, PWM control signals for the second, fourth, sixth, etc. pairs may be generated based on a ramp-up sawtooth function with a sharp trailing edge.

[0037] In other examples, odd-numbered pairs of switching elements may be controlled based on a ramp-up sawtooth function. That is, PWM control signals for the first (innermost), third, fifth, etc. pairs may be generated based on a ramp-up sawtooth function with a sharp trailing edge. Even-numbered pairs of switching elements may be controlled based on a ramp-down sawtooth function, that is, PWM control signals for the second, fourth, sixth, etc. pairs may be generated based on a ramp-down sawtooth function with a sharp leading edge.

[0038] The timing delay between the PWM control signals for consecutive switching element pairs may be equal to where f s is the switching frequency.

[0039] The timing delay of the trailing edge of each ramp-up sawtooth function can be set equal to: Where n is the index of the switch element pair. The timing delay may be set relative to the edge of the carrier of the outermost switch element pair (specifically, relative to the trailing edge of the ramping sawtooth function of the outermost pair).

[0040] The timing delay of the leading edge of each ramp-down sawtooth function can be set equal to: Where n is the index of the switching element pair and d is the duty cycle command value.

[0041] Likewise, the timing delay may be set relative to the edge of the carrier of the outermost pair of switching elements (specifically, relative to the trailing edge of the ramping sawtooth function of the outermost pair).

[0042] The leading or trailing edge of one carrier can be triggered by another carrier reaching a threshold.

[0043] In some examples, the plurality of switch element pairs may consist of two pairs, wherein the second switch element pair is the outermost pair. In this case, the timing of the first carrier (used to generate the first PWM control signal for the inner switch element pair) may be set based on the second carrier (used to generate the second PWM control signal for the outer switch element pair).

[0044] Specifically, the first PWM control signal may be generated such that a time interval between the start of the second pulse and the end of the first pulse is determined by the duty cycle command value plus or minus a predetermined offset.

[0045] According to some examples, the resetting of the first carrier (determining the end of the first pulse) can be triggered by the second carrier reaching a threshold. The threshold can depend on the duty cycle command value. Specifically, the threshold can be determined by adding or subtracting a predetermined offset from the duty cycle command value.

[0046] In some examples, the plurality of switch element pairs includes three or more pairs, and the one or more flying capacitors also include a second flying capacitor connected across a second switch element pair, wherein the second switch element pair is the next innermost switch element pair after the first switch element pair.

[0047] A controller for a multi-level flying capacitor power converter is also provided, the multi-level flying capacitor power converter comprising: a plurality of switch element pairs arranged in a nested manner, comprising: at least a first switch element pair and a second switch element pair, wherein the first switch element pair is the innermost switch element pair, wherein the switch elements in the first switch element pair are coupled together at a switch node, wherein the switch elements in the second switch element pair are coupled to corresponding switch elements in the first switch element pair, the multi-level power converter further comprising: one or more flying capacitors, comprising at least a first flying capacitor connected across the first switch element pair, the controller comprising:

[0048] a first control logic configured to calculate a duty cycle command value for driving a switching element; and

[0049] a second control logic configured to generate a first pulse width modulation, PWM, control signal for the first switching element pair and a second PWM control signal for the second switching element pair based on the duty cycle command value,

[0050] The first PWM control signal comprises a series of first pulses at a switching frequency, and the second PWM control signal comprises a series of second pulses at the switching frequency, each pulse having a start and an end,

[0051] wherein one switching element in the first switching element pair is controlled by a first PWM control signal, and the other switching element in the first switching element pair is controlled by a complementary signal of the first PWM control signal,

[0052] wherein one switching element in the second switching element pair is controlled by a second PWM control signal, and the other switching element in the second switching element pair is controlled by a complementary signal of the second PWM control signal,

[0053] Wherein, the second control logic comprises: a voltage balancing logic configured to detect a difference between a voltage on the first flying capacitor and a reference voltage of the flying capacitor; and

[0054] In response to detecting the difference, modifying the width of the first pulse,

[0055] wherein the voltage balancing logic is further configured to modify the width of the second pulse,

[0056] wherein the width of the first pulses is modified by changing the timing of the start of each first pulse, and the width of the second pulses is modified by changing the timing of the end of each second pulse, or

[0057] Therein, the width of the first pulse is modified by changing the timing of the end of each first pulse, and the width of the second pulse is modified by changing the timing of the start of each second pulse.

[0058] The voltage balancing logic may be configured to modify the timing of each pulse by an amount proportional to a difference between a voltage on the first flying capacitor and a reference voltage of the flying capacitor.

[0059] A multi-level power converter is also provided, comprising a controller as described above. The multi-level converter can be used to power a power amplifier in a mobile communication network. For example, a multi-level power converter according to the present disclosure can be integrated in a mobile communication base station to power a power amplifier for sending a downlink signal to a user equipment. The base station can be, for example, a 5G base station.

[0060] There is also provided a computer program code configured to cause a programmable controller for a multilevel power converter to perform the method as described above when the code is run on said programmable controller.The computer program code may be stored on a computer readable medium (optionally non-transitory). BRIEF DESCRIPTION OF THE DRAWINGS

[0061] The present invention will now be described by way of example with reference to the accompanying drawings, in which:

[0062] Figure 1 is a circuit diagram of a three-level converter having a buck topology with a flying capacitor;

[0063] Figure 2 A comparative example is shown. Figure 1 The control scheme of the converter;

[0064] Figure 3 is a circuit diagram illustrating flying capacitor voltage balancing according to an example;

[0065] Figure 4A It shows that when the duty cycle is less than 50%, Figure 3 A control signal generated in a circuit;

[0066] Figure 4B It shows that when the duty cycle is greater than 50%, Figure 3 A control signal generated in a circuit;

[0067] Figure 5 is a circuit diagram of a generalized multi-level converter;

[0068] Figure 6 Shown for Figure 5 Flying capacitor voltage balancing for generalized multilevel converters;

[0069] Fig. 7A , Figure 7B and Figure 7C The timing of the carrier of an exemplary four-level converter is shown;

[0070] Fig. 8A , Figure 8B , Figure 8C and Fig.8D shows the timing of the carrier of an exemplary five-level converter; and

[0071] Fig. 9 is shown for generating a Figures 6 to 9 Block diagram of the converter's timed reset generator.

[0072] It should be noted that these drawings are schematic and not drawn to scale. For clarity and convenience in the drawings, the relative sizes and proportions of parts of these drawings are exaggerated or reduced in size. DETAILED DESCRIPTION

[0073] exist Figure 2 The control scheme according to the comparative example is shown in FIG. The control scheme seeks to balance the flying capacitor voltage, i.e. keep it as close as possible to the nominal target voltage for Figure 1 The three-level buck converter with a nominal target FC voltage of

[0074] exist Figure 1 In the example, the target output voltage of the converter is V ref . Closed-loop feedback is used to transmit this output voltage. Specifically, from V ref Subtract the measured output voltage v o To generate a voltage difference. The voltage difference is processed by a proportional integral derivative (PID) controller to generate a duty cycle command value d. The value d controls the duty cycle of a pulse width modulation (PWM) control signal generated by a gate signal generator.

[0075] The error in the FC voltage (i.e., The deviation of Δd) is used to change the duty cycle command value by Δd. The duty cycle correction Δd modifies the original duty cycle reference (d), which is set by the output voltage regulation loop. The duty cycle correction is applied differentially to the two switch pairs within the same switching cycle to keep the average duty cycle constant while providing a negative feedback effect on the FC voltage.

[0076] However, it has been found that Figure 2The feedback sign of the scheme shown is not always negative. The stability of this control scheme can depend on the load current. For example, Figure 2 The architecture shown in may have stability issues under light load conditions, especially when a single edge PWM modulation scheme is applied. These stability issues can be addressed by applying double edge modulation. However, the resolution of a double edge modulator is reduced compared to a single edge modulator.

[0077] Examples according to the present disclosure can solve Figure 2 The invention solves the stability problem of the comparative example in FIG. 1 and provides reliable, load-independent FC voltage balancing with high resolution. This can be achieved without significantly increasing the complexity of the controller circuitry, without introducing jitter, and without requiring complex modifications such as oversampling the inductor current to detect and measure valley points.

[0078] Figure 3 An example of FC voltage balancing according to the present disclosure is shown. Figure 4A and Figure 4B Shown in Figure 3 For ease of illustration, this example is based on Figure 1 A three-level buck converter. However, it should be understood that the scope of the present disclosure is neither limited to buck converters nor to three-level converters. The multi-level flying capacitor topology can be applied to various types of power converters. The principles disclosed herein are applicable to any type of flying capacitor converter, regardless of the specific topology or number of levels.

[0079] In order to generate the PWM signal for the switch pair in this example, an interleaving mechanism is used. n ) generates an interlaced PWM signal, which is then compared with the duty cycle reference signal d. However, this is merely exemplary. It should be understood that using an interlaced carrier is not the only way to generate the desired interlaced angle / time.

[0080] It is recognized that instability in a single edge modulator occurs because the PWM control signals for all switch pairs are modulated from the same edge, i.e., either the leading edge (start) of each pulse is modulated or the trailing edge (end) of each pulse is modulated. Therefore, the inductor current has two different feedback effects on the flying capacitor voltage. The DC current component has a negative feedback effect, while the inductor current ripple has a positive feedback effect. Under load conditions, when the ripple current has a dominant effect on the DC component, the positive feedback effect takes precedence, resulting in instability.

[0081] Reference Figure 3, the control logic 110 generates a duty cycle command value d based on the error (difference) between the output voltage of the converter and the reference output voltage. Then, two carrier generators 120 and 122 generate carrier signals from which PWM control signals for the switches can be derived. The relationship between the two carriers depends on the value d.

[0082] In the three-level architecture shown, two PWM signals with a phase shift of 180° between them are used to modulate the two switch pairs. and The proposed technique uses two different carriers to generate these PWM signals. The trailing edge carrier generator 120 generates a PWM signal with a fixed frequency f s The carrier C A The trailing edge carrier is a ramp-up sawtooth wave that changes sharply to zero at its trailing edge. B , using the leading edge carrier generator 122. The leading edge carrier is a ramp-down sawtooth wave that sharply transitions from zero at its leading edge. The leading edge carrier generator 122 has a reset signal provided from the Φ generator block.

[0083] The Φ generator block 126 operates in two modes as follows. If the duty cycle d provided by the output voltage (or inductor current) control loop is lower than 50%, then at the carrier C A A compare match event with the reference value d+0.5 generates a reset signal. In other words, when the carrier C A A reset signal is generated when the rising slope of becomes equal to (or greater than) a reference value d+0.5. In another mode, if the duty cycle command d is higher than 50%, then a reset signal is generated when it is compared and matched with a reference value d-0.5.

[0084] Carrier C A and C B With the flying capacitor voltage v FC The measurement of is provided to the flying capacitor voltage balancing loop 130. From the nominal target FC voltage The flying capacitor voltage is subtracted from .The resulting error is fed to the PID controller 132, which generates a duty cycle correction Δd that is proportional to the error.

[0085] The duty cycle correction is used to modulate the duty cycle command value d. Specifically, for the innermost switch pair The duty cycle correction Δd is subtracted from the duty cycle command value d. PWM control signal PWM B By comparing the carrier C B The obtained modulation duty cycle value d B This means that for positive values ​​of the duty cycle correction Δd, PWM BThe start of each pulse in the PWM is delayed (making the pulse narrower). For negative values ​​of duty cycle correction, the PWM B In both cases, PWM B The end of each pulse in is constant. Note that the two PWM control signals PWM A and PWM B The edges of the pulses in are modified by the same amount (although in opposite directions).

[0086] For the outermost switch pair The duty cycle correction is added to the duty cycle command value d. PWM control signal PWM A By comparing the carrier C A The obtained modulation duty cycle value d A This means that for positive values ​​of the duty cycle correction Δd, PWM A The end of each pulse in the PWM is delayed (making the pulse wider). For negative values ​​of duty cycle correction, the PWM A The end of each pulse in the PWM is advanced (making the pulse narrower). In both cases, the PWM A The beginning of each pulse is constant.

[0087] This enables the desired balance to be achieved. When the FC voltage is above the reference, the width of the pulse controlling switch A is reduced and the width of the pulse controlling switch B is increased. This allows the flying capacitor to discharge for a slightly longer period of time and charge for a slightly shorter period of time, resulting in a net decrease in its voltage. Conversely, when the FC voltage is below the reference, the width of the pulse controlling switch A is increased and the width of the pulse controlling switch B is reduced. This allows the flying capacitor to charge for a slightly longer period of time and discharge for a slightly shorter period of time, resulting in a net increase in its voltage. Note that by modulating PWM A and PWM B The pulse width is changed by the opposite edge of the pulse in the circuit.

[0088] Modify the PWM control signal PWM in the opposite direction A and PWM B A pulse width of 0.15 V can help balance the flying capacitor voltages faster while maintaining stability and the same average duty cycle command value - at least in the three-level case. In principle, modifying the pulse of only one of these control signals will be enough to start balancing the flying capacitor voltages, and the correction of the entire duty cycle can be left to the control logic 110. For multi-level converters with more than three levels, the symmetrical modification of the pulse width is optional. Typically, the flying capacitors in such a converter can be balanced by adjusting the pulse of one PWM control per flying capacitor.

[0089] Back to Figure 3 3-level example for the outermost switch pair PWM control signal PWM A Provided to the gate driver circuit 140 for driving the gate of one switch in the pair. PWM control signal PWM A The complementary signal of is also provided to the gate driver circuit 140 for driving the other switch in the pair. Similarly, the complementary signal for the innermost switch pair is PWM control signal PWM B Provided to the gate driver circuit 142 for driving the gate of one switch in the pair. PWM control signal PWM B The complementary signal of is also provided to the gate driver circuit 142 for driving the other switch in the pair.

[0090] The waveforms of the two operation modes (depending on the duty cycle command value d) are respectively Figure 4A and Figure 4B As shown in the figure, in the switch pair for the outermost PWM control signal (PWM A ), the pulse starts at the carrier C A When the carrier C A When the rising slope of becomes equal to (or greater than) the duty cycle command value d, the pulse ends. PWM control signal (PWM B ), when the carrier C B When the falling slope of the carrier C becomes equal to (or less than) the duty cycle command value d, the pulse starts. The pulse ends at the carrier C B Sharp front edge.

[0091] exist Figure 4A When the duty cycle value d is less than 50%, the carrier C B The leading edge of the carrier C A The rising slope of PWM is triggered when it becomes equal to (or greater than) the reference value d+0.5. This ensures that PWM A The start of the pulse in PWM B The time interval between the end of the pulses in the s ). When no balancing of the flying capacitor occurs, that is, under steady-state equilibrium conditions, this would mean that PWM B The pulses in PWM A The start and end of the pulse in the half switching cycle start and end. When the duty cycle value d is greater than 50%, according to Figure 4B This produces a phase relationship similar to 180°. However, Figure 4B In the case of PWM A and PWM B In other words, the pulses are staggered so that in steady state, the PWM B Each pulse in the PWM A The start of the corresponding pulse in d is offset by 180°. This is the case in both modes d<0.5 or d>0.5. Therefore, even if the two PWM signals overlap in mode d>0.5, the PWM B The start is still from PWM A The start of the shift is half a cycle.

[0092] The control scheme described above has been demonstrated to achieve successful balancing of the flying capacitor voltage under light and heavy loads. Figure 2 The instabilities observed in the comparative examples are eliminated.

[0093] Figure 5 A general N-level flying capacitor switch pair architecture 500 is shown in FIG. Figure 3 The architecture shown in is extended to more than three levels. There are (N-1) switch pairs. Starting from the innermost pair B1 to switch pair B N-2 , and ends with the outermost switch pair A. Each pair has two switching elements Where n ranges from 1 to (N-2) and is the index of the switch pair. The outermost switch pair has two switch elements Therefore, there are a total of 2(N-1) active switching elements. Each internal switch pair Having a flying capacitor connected across the switching element From the connection to the innermost pair Start with the switch connected to pair B N-2 of End, such as Figure 5 As shown. In general, the N-level converter has (N-2) flying capacitors. As shown, from the outermost switch pair to the innermost switch pair, each pair is connected to the previous pair, except that the innermost switch pair B1 has a common node that will be connected to other system components (e.g., to an inductor in a buck converter). From the innermost pair to the outermost pair, each pair is connected to the next switch pair, except that the outermost pair has a terminal that will be connected to other system components (e.g., to a supply voltage).

[0094] Figure 5 The details of the multi-level architecture other than those shown are beyond the scope of this disclosure. However, Figure 5Portions of the architecture relevant for understanding the present disclosure are shown.As mentioned above, the scope of application of the proposed control architecture is not limited to any specific multi-level converter architecture; it is basically applicable to any multi-level flying capacitor converter topology (buck, boost, buck-boost, etc.).

[0095] like Figure 5 As shown, an exemplary N-level converter has (N-2) flying capacitors for balancing, and (for example) one output voltage and one inductor current for control. (The output voltage and inductor current are not shown in FIG. Figure 5 ) In addition, an N-level converter requires (N-1) PWM control signals to operate the switch pairs. Examples according to the present disclosure use a leading edge carrier and a trailing edge carrier based modulator together to generate a PWM signal with a consistent negative feedback sign, which eliminates the stability dependency on the load current in a multi-level converter.

[0096] Figure 6 An example control scheme using the present disclosure is shown. Figure 5 The output voltage controller block 510 may be a block diagram of an N-level converter 500 of the type shown. o Any controller type that controls the output voltage and other converter parameters (such as the inductor current i L ) multi-loop controller. The inputs of the output voltage controller block 510 are the output voltage, the reference output voltage and the inductor current (v o ,V ref and i L ). These inputs are typical for a control scheme with a dual loop controlling the output voltage and the inductor current. However, it should be understood that the scope of the present disclosure is not limited to this type of output voltage controller block. The output voltage controller block 510 provides a duty cycle command value d. Additional control logic is provided to balance the flying capacitor voltage. The N-level converter has up to N-2 controllers 530-1 to 530-N-2 to balance the flying capacitor voltage. Typically, the controller 530-n controls Where n is an index in the range 1≤n≤(N-2). An error in the FC voltage is detected (note that the present disclosure is not limited to methods of detecting or measuring the FC voltage). The controller 530-n processes the error and generates a duty cycle correction Δd n This correction is then subtracted from the original duty cycle command value d that has been generated by the output voltage controller block 510. The corrected duty cycle is compared to the carrier reference to generate the necessary PWM signal to operate the switches of the converter. This example uses a combination of a leading edge carrier and a trailing edge carrier to generate the carrier signal C A -Cn , where n is an index that varies in the range 1≤n≤(N-2) to generate the (N-1) PWM signals required to operate the switches of the converter. Figure 6 As shown, the carrier signal C A is generated by block 520-A as a trailing edge carrier (i.e., a ramping sawtooth function). However, if the carrier C A is the leading edge carrier (i.e., a ramp-down sawtooth function), the disclosed balance control scheme will also be effective. As shown in the figure, the carrier signal C for the next switch pair N-2 is generated by block 522-N-2 as the front edge carrier, and as the index n changes one by one, the carrier continues to alternate between the rear edge carrier (e.g., carrier generator block 520-N-3) and the front edge carrier until the carrier C1 for the innermost pair is reached. If the number of N levels is odd, this will be the front edge carrier, and the reference carrier C1 for the outermost pair A A On the other hand, if the number of N levels is even, C1 will be the trailing edge carrier, and the reference carrier C of the outermost pair A A is the trailing edge carrier. However, again, it should be understood that the scope of the present disclosure is not limited to this combination of carriers. These are for explanation purposes; however, other combinations may also achieve system stability in general.

[0097] Block 524 represents a general carrier generator, which can generate a leading edge carrier or a trailing edge carrier as needed.

[0098] Finally, the control scheme provides (N-1) PWM signals for generating the 2(N-1) gate drive signals required to operate the switches of the converter. Typically, for the operation of an N-level flying capacitor converter, the PWM signals are The angle is staggered between every two consecutive PWM signals. This can be expressed as s The time offset of the converter operation To achieve this, for Figure 5 and Figure 6 In the case of the N-level converter shown in the figure, the carrier signal is A Again, it should be understood that this does not limit the scope of the present disclosure. It is also possible to use a method that combines the leading edge carrier and the trailing edge carrier and implements a delay time between each two consecutive PWM signals. In this example, the carrier signal C for the outermost switch pair A The switching frequency is generated as f s For other switch pairs, the carrier C nAlternate between the leading edge carrier and the trailing edge carrier. Again, n is an integer index ranging from 1 to (N-2).

[0099] like Figure 6 As shown, due to the carrier C A Generated as the trailing edge carrier, the next carrier C N-2 The generated is the front edge carrier, followed by the rear edge carrier C N-3 Here, "next" means moving inward from the outermost switch pair toward the innermost switch pair. Therefore, for a converter with an odd number of N levels, the carrier C1 for the innermost switch pair will be the leading edge carrier. On the other hand, for a converter with an even number of N levels, the carrier C1 will be the trailing edge carrier. In general, with the above settings, for any trailing edge carrier C n , relative to the reference / outermost carrier C A The time delay is given by:

[0100]

[0101] Meanwhile, the time delay of each leading edge carrier delay depends on the value of the duty cycle and is given by:

[0102]

[0103] Synchronize the reset signal of the carrier generator with the required delay as shown and results in the desired interleaving time between the carriers, thus resulting in a Delay.

[0104] The equation described above for Figure 6 The situations shown are valid; however, it should be understood that they do not necessarily limit the scope of the present disclosure. In an alternative example, a voltage between each two consecutive PWM signals may be used. Other equations or settings for delay.

[0105] By combining the duty cycle command value d with the carrier C A The PWM control signal PWM for the outermost switching element pair is generated by comparing A The control signal PWMA is supplied to the outermost switching element pair The gate driver circuit 540. The control signal PWM A The complementary signal of is generated by the inverter and is also supplied to the gate driver circuit 540.

[0106] To generate PWM control signals for the internal switching element pairs The associated duty cycle correction Δd n First, it is subtracted from the duty cycle command value d. Then the resulting modulation duty cycle value is compared with the associated carrier C n Compare to generate PWM control signal Control Signal is supplied to the relevant switching element pair The gate driver circuit 542-n. The control signal A complementary signal of is generated by an inverter and is also supplied to the gate driver circuit 542-n.

[0107] When the corresponding PWM control signal is generated To balance the flying capacitor voltage, the relevant duty cycle correction Δd is subtracted from the duty cycle command value. n is sufficient. Optionally, compensating load corrections can be added elsewhere to speed up balancing when imbalance occurs. However, this is not usually necessary. It may be more straightforward to treat each capacitor and the corresponding PWM control signal individually, and for simplicity this is the approach taken in this general example.

[0108] As an example of how to generate a reset signal for a leading edge modulator, an additional comparison unit can be added to the PWM A generator; however, it should be understood that the scope of the present disclosure is not limited in this regard. The reset signal may be generated in other ways. For example, additional comparison units may be distributed between all trailing edge carrier generators, wherein each trailing edge carrier generator generates a reset signal for the previous (or next) leading edge carrier generator. The additional comparison unit compares the carrier of the trailing edge modulator (in this example, PWM A Carrier) and reference value As an example, the four-level case is shown in Figure 7A-7C The timing diagram for the five-level case is shown in Figure 8A-8D middle.

[0109] In some examples, the N-level converter may have (N-1) operating modes depending on the duty cycle value. Therefore, the three-level converter has two operating modes (d<0.5, d>0.5), as described above for Figure 3 The four-level converter has three operating modes. Similarly, for five-level, there are four operating modes divided by duty cycle thresholds of 0.25, 0.5 and 0.75.

[0110] Consistent with the earlier description above, in a 4-level converter, there are three carriers: C A ,C1 and C2. Carrier C Aand C1 (for the outermost and innermost switching element pairs, respectively) are trailing edge carriers. Carrier C1 has a relative A The constant delay is set according to the following formula:

[0111]

[0112] To generate the leading edge carrier C2 for the middle switching element pair, the reference value With carrier C A Compare, and when the comparison matches, generate the reset signal of carrier C2. Fig. 7A , Figure 7B and Figure 7C As shown, according to the description delay time In the first two operation modes, In the third operating mode Finally, as shown in the figure, every two consecutive PWM signals have a offset.

[0113] For the N=5 level, the converter has four carriers to generate corresponding four PWM control signals. In this example, there are two trailing edge carriers C A and C2 and two front edge carriers C1 and C3. The rear edge carrier C2 is offset in time If respectively Fig. 8A , Figure 8B , Figure 8C and Fig.8D As shown in FIG, the reference r3 in the first three operating modes is set equal to d+0.25, but in the last operating mode r3=d-0.75. Meanwhile, the reference r1=d+0.75 only in the first operating mode, but is set equal to d-0.25 in the other operating modes. Again, as shown in the figure, by A When the comparison matches with r1 and r3 respectively, reset signals for C1 and C3 are generated, and the desired switching between continuous PWM signals can be achieved. Staggered time.

[0114] An exemplary generalized reset signal (r n ) The block diagram of the generator is as follows Fig. 9 Constant value Subtract it from the original duty cycle command value d; compare the result with zero; and add the digital output value of the comparator to The resulting sum value will be or depends on the value of the duty cycle and the corresponding operating mode of the converter. A The reset signal r is generated when the comparison match between the generated sum value is n Will offset time Here, it should be emphasized that the original duty cycle command value d or any conditional version thereof can be used to implement the flying capacitor voltage control loop.The scope of the present disclosure is not limited to directly using the duty cycle command value generated by the output voltage controller.

[0115] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims.

[0116] For example, in the above examples, the switching element is shown as a MOSFET. This is of course not required.

[0117] In the claims, any reference signs placed between brackets shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. An embodiment may be implemented by means of hardware comprising several different elements. In a device claim enumerating several means, several of these means may be implemented by the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Furthermore, in the appended claims, comprising "at least one of: A; B; and C" shall be interpreted as (A and / or B) and / or C.

[0118] The embodiments discussed herein may be practiced in various components such as integrated circuit modules. The design of integrated circuits is generally a highly automated process. Complex and powerful software tools are available to convert logic-level designs into semiconductor circuit designs that are ready to be etched and formed on semiconductor substrates.

[0119] Programs such as those offered by Synopsys, Inc. of Mountain View, Calif., and Cadence Design, Inc. of San Jose, Calif., automatically route conductors and position components on a semiconductor chip using well-established design rules and a library of pre-stored design modules. Once the design of a semiconductor circuit is complete, the resulting design in a standardized electronic format (e.g., Opus, GDSII, etc.) can be transmitted to a semiconductor fabrication plant or "fab" for fabrication.

Claims

1. A method for balancing voltages on one or more flying capacitors in a multi-level power converter, the multi-level power converter comprising: A plurality of switch element pairs arranged in a nested manner, comprising at least a first switch element pair and a second switch element pair, wherein the first switch element pair is the innermost switch element pair of the plurality of switch element pairs, wherein the switch elements in the first switch element pair are coupled together at a switch node, wherein the switch elements in the second switch element pair are coupled to corresponding switch elements in the first switch element pair, the one or more flying capacitors in the multilevel power converter comprising at least a first flying capacitor connected across the first switch element pair, the method comprising: obtaining a duty cycle command value for driving the switching elements in the plurality of switching element pairs; generating a first pulse width modulation (PWM) control signal for the first switching element pair and a second PWM control signal for the second switching element pair based on the duty ratio command value, The first PWM control signal comprises a series of first pulses having a switching frequency, and the second PWM control signal comprises a series of second pulses having the switching frequency, each pulse having a start and an end, wherein one switching element in the first switching element pair is controlled by the first PWM control signal, and the other switching element in the first switching element pair is controlled by a complementary signal of the first PWM control signal, wherein one switch element in the second switch element pair is controlled by the second PWM control signal, and the other switch element in the second switch element pair is controlled by a complementary signal of the second PWM control signal; detecting a difference between a voltage on the first flying capacitor and a reference voltage for the first flying capacitor; and In response to detecting the difference, modifying the width of the first pulse, The method also includes modifying a width of the second pulse.

2. The method according to claim 1, in, modifying the width of each first pulse by changing the timing of the start of each first pulse, and modifying the width of each second pulse by changing the timing of the end of each second pulse, Wherein, when the widths of the first pulse and the second pulse are modified, the time interval between the start of the first pulse and the end of the second pulse remains constant.

3. The method according to claim 1, in, modifying the width of each first pulse by changing the timing of the end of each first pulse, and modifying the width of each second pulse by changing the timing of the start of each second pulse, Wherein, when the widths of the first pulse and the second pulse are modified, the time interval between the end of the first pulse and the beginning of the second pulse remains constant.

4. A method according to any one of the preceding claims, wherein: generating the first PWM control signal according to a first carrier wave, and generating the second PWM control signal according to a second carrier wave, One of the first carrier and the second carrier is a ramp-up sawtooth function with a sharp rear edge, and the other carrier is a ramp-down sawtooth function with a sharp front edge.

5. The method according to claim 4, wherein: The timing of the first carrier wave is set based on the timing of a carrier wave used to generate a PWM control signal for an outermost switching element pair among the plurality of switching element pairs.

6. A method according to any one of the preceding claims, wherein: The multilevel power converter is configured for N levels, and the plurality of switch element pairs consists of N-1 switch element pairs, The method comprises: generating a PWM control signal for each switching element pair based on a corresponding carrier wave comprising a sawtooth function, The sawtooth function alternates between a ramp-up sawtooth function and a ramp-down sawtooth function.

7. The method according to claim 6, wherein: The timing delay between the PWM control signals for successive pairs of switching elements is equal to Among them, f s is the switching frequency.

8. The method according to claim 6 or claim 7, wherein: The timing delay of the trailing edge of each ramp-up sawtooth function is set equal to: Wherein, n is the index of the switch element pair.

9. The method according to any one of claims 6 to 8, wherein: The timing delay of the leading edge of each ramp-down sawtooth function is set equal to: Wherein, n is the index of the switching element pair, and d is the duty cycle command value.

10. The method according to any one of claims 6 to 9, wherein: The leading or trailing edge of one carrier is triggered by the other carrier reaching the threshold.

11. A method according to any one of the preceding claims, wherein: The plurality of switching element pairs include two switching element pairs, wherein the second switching element pair is an outermost switching element pair of the plurality of switching element pairs.

12. The method according to any one of claims 1 to 10, wherein: The multiple switch element pairs include three or more switch element pairs, and the one or more flying capacitors also include a second flying capacitor connected across the second switch element pair, wherein the second switch element pair is the next innermost switch element pair after the first switch element pair among the multiple switch element pairs.

13. A controller for a multi-level flying capacitor power converter, the multi-level flying capacitor power converter comprising a plurality of switch element pairs arranged in a nested manner, the plurality of switch element pairs comprising at least a first switch element pair and a second switch element pair, wherein: The first switch element pair is the innermost switch element pair of the plurality of switch element pairs, wherein the switch elements in the first switch element pair are coupled together at a switch node, wherein the switch elements in the second switch element pair are coupled to corresponding switch elements in the first switch element pair, the multilevel power converter further comprises one or more flying capacitors, the one or more flying capacitors comprising at least a first flying capacitor connected across the first switch element pair, the controller comprising: a first control logic (110, 510) configured to calculate a duty cycle command value for driving a switching element in the plurality of switching element pairs; and a second control logic (130) configured to generate a first pulse width modulation (PWM) control signal for the first switching element pair and a second PWM control signal for the second switching element pair based on the duty cycle command value, The first PWM control signal comprises a series of first pulses having a switching frequency, and the second PWM control signal comprises a series of second pulses having the switching frequency, each pulse having a start and an end, wherein one switching element in the first switching element pair is controlled by the first PWM control signal, and the other switching element in the first switching element pair is controlled by a complementary signal of the first PWM control signal, wherein one switch element in the second switch element pair is controlled by the second PWM control signal, and the other switch element in the second switch element pair is controlled by a complementary signal of the second PWM control signal, The second control logic includes: a voltage balancing logic (132) configured to detect a difference between a voltage on the first flying capacitor and a reference voltage for the first flying capacitor; and In response to detecting the difference, modifying the width of the first pulse, Wherein, the voltage balancing logic is further configured to modify the width of the second pulse.

14. The controller according to claim 13, wherein: The voltage balancing logic is configured to modify the timing of each pulse by an amount proportional to a difference between a voltage on the first flying capacitor and a reference voltage of the first flying capacitor.

15. A computer program product comprising a computer program which, when executed by a programmable controller used for a multilevel power converter, causes the programmable controller to implement the method according to any one of claims 1 to 12.

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