Low-side active clamping drive circuit suitable for bridge rectifier circuit

Abstract

The invention relates to a low-side active clamping drive circuit suitable for a bridge rectifier circuit. Comprising a full-bridge topology and bridge type rectification circuit unit, a PWM controller circuit unit, a signal isolation circuit unit, a time sequence adjustment circuit unit, a signal logic processing circuit unit, a signal driving amplification and level shift circuit unit and a low-side active clamping circuit unit. Two paths of driving signals generated by a primary PWM controller are collected and are subjected to signal isolation transmission through a signal isolation circuit, and after a time sequence adjusting circuit finely adjusts a signal rising edge time sequence, the two paths of signals are converted into one path of frequency doubling signal through a signal logic processing circuit unit; and finally, after driving amplification and level shifting are carried out through the signal driving amplification and level shifting circuit, the low-side active clamping circuit is driven to work. The whole control circuit is simple in principle and structure, and can provide a required frequency doubling negative voltage driving signal for a bridge rectifier circuit.

Description

Technical Field

[0001] The invention relates to the technical field of switching power supplies, and in particular to a low-side active clamping drive circuit suitable for a bridge rectifier circuit. Background Art

[0002] DC / DC converter is an important branch of switching power supply. As the secondary power supply of the system, it is widely used in military and civilian electronic systems such as aerospace, aviation, shipbuilding, weapons, electronics, railways, communications, medical electronics, industrial automation equipment, etc. The full-bridge topology circuit is one of the commonly used topologies for high-power switching power supplies. Due to the influence of transformer leakage inductance, rectifier tube reverse recovery time, and inductance introduced by layout routing, a large switching spike will be generated when the rectifier tube is turned off. Passive RC or active circuits are usually used to absorb voltage spikes. Passive absorption circuits have poor suppression effects and large losses, while active absorption has good suppression effects and small losses. It is now more and more widely used.

[0003] Full-bridge topology circuits are mostly rectified by full-wave rectifier circuits, but in high-voltage output products, bridge rectifier circuits are mostly used to reduce the withstand voltage of rectifier tubes. The active absorption circuits used by full-wave rectifier circuits and bridge rectifier circuits are different. The two rectifier tubes of the full-wave rectifier circuit use a set of active clamp absorption circuits respectively, while the bridge rectifier circuit only needs to use a set of active clamp absorption circuits. Therefore, the driving signal of the active clamp absorption circuit of the bridge rectifier circuit is different from that of the full-wave rectifier circuit, and its frequency is twice that of the full-wave rectifier circuit. Therefore, a circuit that can generate a low-side active clamp driving signal suitable for a bridge rectifier circuit is needed. Summary of the invention

[0004] In order to solve the deficiencies in the prior art, an object of the present invention is to provide a low-side active clamping drive circuit suitable for a bridge rectifier circuit.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A low-side active clamping drive circuit suitable for a bridge rectifier circuit, the low-side active clamping drive circuit comprising: a full-bridge topology and bridge rectifier circuit unit, a PWM controller circuit unit, a signal isolation circuit unit, a timing adjustment circuit unit, a signal logic processing circuit unit, a signal drive amplification and level shifting circuit unit and a low-side active clamping circuit unit.

[0007] The input end of the full-bridge topology and bridge rectifier circuit unit is respectively connected to the input voltage and the output end OUTA and the output end OUTB of the PWM controller circuit unit, and the output end of the full-bridge topology and bridge rectifier circuit unit is used as the output voltage and is connected to the low-side active clamp circuit unit. The full-bridge topology and bridge rectifier circuit unit is the power conversion part of the product, and the switching peak of the bridge rectifier circuit is the problem to be solved by the present invention.

[0008] The output terminal OUTA and the output terminal OUTB of the PWM controller circuit unit are respectively connected to the input terminal of the full-bridge topology and bridge rectifier circuit unit and the input terminal of the signal isolation circuit unit. The PWM controller circuit unit is used to provide a driving signal for the primary power switch tube and provide the required two original signals for the secondary low-side active clamping circuit unit.

[0009] The input end of the signal isolation circuit unit is connected to the output end of the PWM controller circuit unit, and the output end of the signal isolation circuit unit is connected to the input end of the timing adjustment circuit unit. The signal isolation circuit unit is used to isolate the two original signals of the primary and transmit them to the secondary, and then send them to the timing adjustment circuit unit for waveform rising edge timing adjustment.

[0010] The input end of the signal logic processing circuit unit is respectively connected to the output end of the timing adjustment circuit unit, and the output end of the signal logic processing circuit unit is connected to the input end of the signal drive amplification and level shift circuit unit. The signal logic processing circuit unit is used to perform AND, NOT, OR operations on the two-way signals adjusted by the timing adjustment circuit unit to obtain the required single-way signal, and then send it to the signal drive amplification and level shift circuit unit for signal amplification and level shift conversion.

[0011] The input end of the signal drive amplification and level shift circuit unit is connected to the output end of the signal logic processing circuit unit, and the output end of the signal drive amplification and level shift circuit unit is connected to the input end of the low-side active clamp circuit unit. The signal drive amplification and level shift circuit unit is used to amplify the driving capability of the signal and convert the positive level signal into a negative level signal required by the low-side active clamp circuit unit.

[0012] The input end of the low-side active clamp circuit unit is connected to the output end of the signal drive amplifier and level shift circuit unit, and the output end of the low-side active clamp circuit unit is connected to the input end of the full-bridge topology and bridge rectifier circuit unit. The low-side active clamp circuit unit is used to absorb the peak voltage of the rectifier switch of the bridge rectifier circuit.

[0013] As a further improvement of the above technical solution, the full-bridge topology and bridge rectifier circuit unit adopts a typical full-bridge topology and bridge rectifier circuit, including four primary bridge switch MOS tubes Q1-Q4, four secondary bridge rectifier tubes D1-D4, input capacitor C1, DC blocking capacitor C2, output capacitor C3, transformer T1 and output filter inductor L1.

[0014] The drain of the bridge switch MOS tube Q1 is connected to the drain of the bridge switch MOS tube Q3 and then connected to the input voltage VIN+; the source of the bridge switch MOS tube Q1 is connected to the drain of the bridge switch MOS tube Q2 and then connected to the same-name end of the primary winding of the transformer T1 through the DC blocking capacitor C2; the source of the bridge switch MOS tube Q3 is connected to the drain of the bridge switch MOS tube Q4 and then connected to the opposite-name end of the primary winding of the transformer T1; the source of the bridge switch MOS tube Q2 and the source of the bridge switch MOS tube Q4 are connected to the input ground VIN-; one end of the input capacitor C1 is connected to the drain of the bridge switch MOS tube Q1, and the other end is connected to the source of the bridge switch MOS tube Q2. The anode of the bridge rectifier D1 is connected to the cathode of the bridge rectifier D2, and the cathode of the bridge rectifier D1 is connected to the cathode of the bridge rectifier D3 and is also connected to one end of the output filter inductor L1; the other end of the output filter inductor L1 serves as the positive end of the output voltage; the anode of the bridge rectifier D2 is connected to the anode of the bridge rectifier D4 and is also grounded, serving as the negative end of the output voltage; the two ends of the output capacitor C3 are respectively connected to the positive end of the output voltage and the negative end of the output voltage. The anode of the bridge rectifier D1 is connected to the same-name end of the secondary winding of the transformer T1. The anode of the bridge rectifier D3 is connected to the opposite-name end of the secondary winding of the transformer T1.

[0015] As a further improvement of the above technical solution, the PWM controller circuit unit includes a PWM controller, and the PWM controller is a full-bridge or half-bridge PWM controller. The PWM controller circuit unit also includes a peripheral circuit of the PWM controller. The present invention only requires two drive signals OUTA and OUTB output by the PWM controller, and its peripheral circuit is not related to the circuit of the present invention, so it is not repeated here. The OUTA signal is connected to the gate of the primary switch MOS tube Q2 and the 2nd pin of the digital isolator N1 of the signal isolation circuit unit, and the OUTB signal is connected to the gate of the primary switch MOS tube Q4 and the 3rd pin of the digital isolator N1 of the signal isolation circuit unit.

[0016] As a further improvement of the above technical solution, the signal isolation circuit unit includes a digital isolator N1 and its peripheral circuits. Pin 1 of the digital isolator N1 is connected to the primary 5V power supply, pin 2 of the digital isolator N1 is connected to the output signal OUTA of the PWM controller circuit unit, pin 3 of the digital isolator N1 is connected to the output signal OUTB of the PWM controller circuit unit, pin 4 of the digital isolator N1 is connected to the input ground VIN-, pin 4 of the digital isolator N1 is connected to the output ground Vo-, pin 6 of the digital isolator N1 is connected to one end of the charging resistor R2 and the cathode of the discharge diode D6 in the timing adjustment circuit unit, pin 7 of the digital isolator N1 is connected to one end of the charging resistor R1 of the timing adjustment circuit unit and the cathode of the discharge diode D5, and pin 7 of the digital isolator N1 is connected to the secondary 5V power supply.

[0017] As a further improvement of the above technical solution, the timing adjustment circuit unit includes a charging resistor R1, a charging resistor R2, a discharge diode D5, a discharge diode D6, a capacitor C4 and a capacitor C5. One end of the charging resistor R1 is connected to the 7th pin of the digital isolator N1 in the signal isolation circuit unit and the cathode of the discharge diode D5, and the other end of the charging resistor R1 is connected to the anode of the discharge diode D5, one end of the capacitor C4, one input end of the AND gate N4 in the signal logic processing circuit unit and the input end of the NOT gate N2; one end of the charging resistor R2 is connected to the 6th pin of the digital isolator N1 in the signal isolation circuit unit and the cathode of the discharge diode D6, and the other end is connected to the anode of the discharge diode D6, one end of the capacitor C5, the other input end of the AND gate N4 in the signal logic processing circuit unit and the input end of the NOT gate N3; the other ends of the capacitor C4 and the capacitor C5 are connected to the output ground Vo-.

[0018] As a further improvement of the above technical solution, the signal logic processing circuit unit includes a NOT gate N2, a NOT gate N3, an AND gate N4, an AND gate N5 and an OR gate N6. The input end of the NOT gate N2 is connected to one input end of the AND gate N4, the other end of the charging resistor R1 in the timing adjustment circuit unit, the anode of the discharge diode D5, and one end of the capacitor C4; the input end of the NOT gate N3 is connected to the other input end of the AND gate N4, the other end of the charging resistor R2 in the timing adjustment circuit unit, the anode of the discharge diode D6, and one end of the capacitor C5; the two input ends of the AND gate N5 are respectively connected to the output ends of the NOT gate N2 and the NOT gate N3, and the output end of the AND gate N5 is connected to one input end of the OR gate N6; one input end of the OR gate N6 is connected to the output end of the AND gate N4, the other input end of the OR gate N6 is connected to the output end of the AND gate N5, and the output end of the OR gate N6 is connected to the 5th and 6th pins of the driver N7 in the signal drive amplification and level shift circuit unit.

[0019] As a further improvement of the above technical solution, the signal drive amplification and level shift circuit unit includes a driver N7, a level shift capacitor C6, a clamping diode D7 and a discharge resistor R3. Pin 1 of the driver N7 is connected to the secondary 12V voltage, pins 2 and 3 of the driver N7 are connected to one end of the level shift capacitor C6, pin 4 of the driver N7 is connected to the output ground Vo-, and pins 5 and 6 of the driver N7 are connected to the output end of the OR gate N6 in the signal logic processing circuit unit; the other end of the level shift capacitor C6 is connected to the anode of the clamping diode D7, one end of the discharge resistor R3 and the gate of the clamping power PMOS tube Q5 in the low-side active clamping circuit unit; the cathode of the clamping diode D7 is connected to the other end of the discharge resistor R3 and the output ground Vo-.

[0020] As a further improvement of the above technical solution, the low-side active clamping circuit unit includes a clamping power PMOS tube Q5, a clamping capacitor C7 and a current limiting resistor R4. The gate of the clamping power PMOS tube Q5 is connected to one end of the level shifting capacitor C6 in the signal drive amplification and level shifting circuit unit, the anode of the clamping diode D7 and one end of the discharge resistor R3, the drain of the clamping power PMOS tube Q5 is connected to one end of the clamping capacitor C7, and the source of the clamping power PMOS tube Q5 is connected to one end of the current limiting resistor R4; the other end of the clamping capacitor C7 is connected to the cathode of the bridge rectifier D1 and the bridge rectifier D3 in the full-bridge topology and bridge rectifier circuit unit and one end of the output filter inductor L1; the other end of the current limiting resistor R4 is connected to the output ground Vo-.

[0021] Compared with the prior art, the advantages of the present invention are:

[0022] (1) The low-side active clamp driving circuit suitable for the bridge rectifier circuit of the full-bridge topology switching power supply described in the present invention generates two driving signals by collecting the primary PWM controller, and after the signal isolation circuit performs signal isolation transmission and the timing adjustment circuit fine-tunes the rising edge timing of the signal, the two signals are converted into a double frequency signal by the signal logic processing circuit unit, and finally the low-side active clamp circuit is driven to work after driving amplification and level shifting by the signal drive amplification and level shifting circuit. The principle and structure of the entire control circuit are simple, and the required double frequency negative voltage driving signal can be provided for the bridge rectifier circuit. The present invention adopts an active clamping absorption circuit to suppress the peak voltage of the rectifier tube, and can greatly reduce the withstand voltage requirements of the diode. The selection of a low withstand voltage rectifier tube can effectively improve the product conversion efficiency, reduce the product temperature rise, and improve the product reliability.

[0023] (2) The main innovation of the present invention is to use circuits such as timing adjustment and logic processing to shape, multiply and process the two-way signal into an active clamping drive signal that meets the requirements of the full-bridge bridge rectifier circuit, thereby effectively replacing the conventional passive RC absorption circuit, greatly reducing the diode switch peak, and improving product reliability. At present, the absorption circuit commonly used in bridge rectifier circuits is a passive RC circuit, which has the disadvantages of poor absorption effect and high power consumption, and cannot meet the occasions of high power, peak voltage and large energy. Conventional active clamping drive circuits are all for full-wave rectifier circuits, with two sets of clamping circuits, while bridge rectifier circuits only need one set of clamping circuits, so it is necessary to merge the two sets of signals. The innovation of the present invention is to use circuits such as timing adjustment and logic processing to shape, multiply and process the two-way signal into an active clamping drive signal that meets the requirements of the full-bridge bridge rectifier circuit, thereby greatly reducing the diode switch peak, and low-voltage rectifier tubes can be selected, which improves the product conversion efficiency, reduces the product temperature rise, and further improves the product reliability.

[0024] (3) The present invention does not simply add two drive signals, but rather processes the two sets of primary signals into drive signals required by the bridge rectifier circuit by isolating, timing adjusting, and logic processing circuits. At present, analog controlled bridge circuits all use passive RC absorption circuits, and the active clamping drive signals of digital controlled bridge circuits are generated by MCU or DSP, which is different from the principle of the present invention. Compared with the passive RC absorption circuit, the rated voltage of the rectifier tube in the 28V300W product using the present invention is reduced from 200V to 100V, the peak voltage is reduced by 70%, and the efficiency index is improved by 0.6%. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a circuit block diagram of a low-side active clamping drive circuit applicable to a bridge rectifier circuit in the present invention;

[0026] Figure 2 It is a circuit principle diagram of a low-side active clamping drive circuit applicable to a bridge rectifier circuit in the present invention;

[0027] Figure 3 It is a waveform timing diagram of a low-side active clamping drive circuit suitable for a bridge rectifier circuit in the present invention.

[0028] in:

[0029] 1. Full-bridge topology and bridge rectifier circuit unit, 2. PWM controller circuit unit, 3. Signal isolation circuit unit, 4. Timing adjustment circuit unit, 5. Signal logic processing circuit unit, 6. Signal drive amplification and level shifting circuit unit, 7. Low-side active clamping circuit unit. DETAILED DESCRIPTION

[0030] The present invention will be further described below in conjunction with the accompanying drawings:

[0031] like Figure 1 A low-side active clamping drive circuit suitable for a full-bridge topology switching power supply bridge rectifier circuit is shown, and the low-side active clamping drive circuit includes: a full-bridge topology and bridge rectifier circuit unit 1, a PWM controller circuit unit 2, a signal isolation circuit unit 3, a timing adjustment circuit unit 4, a signal logic processing circuit unit 5, a signal drive amplification and level shifting circuit unit 6 and a low-side active clamping circuit unit 7.

[0032] The full-bridge topology and bridge rectifier circuit unit 1 is a typical full-bridge topology and bridge rectifier circuit, and is the power conversion part of the circuit. The PWM controller circuit unit 2 generates two pulse drive signals, which are isolated by the signal isolation circuit unit 3 and sent to the timing adjustment circuit unit 4 and the signal logic processing circuit unit 5 to be processed into a double frequency signal, and then amplified and shifted by the signal drive amplifier and level shift circuit unit 6 to be converted into a negative level drive signal. The negative level drive signal drives the clamping PMOS tube in the low-side active clamping circuit working unit 7 to work and absorb the switching peak of the bridge rectifier tube.

[0033] The purpose of the present invention is to provide a circuit that can generate a low-side active clamping drive signal suitable for a full-bridge topology switching power supply bridge rectifier circuit. The circuit sends two pulse drive signals generated by a primary PWM controller for driving a primary switch tube to a secondary after being isolated by a signal isolation circuit. The two signals are converted into one signal after passing through a signal logic processing circuit, and the signal frequency is doubled at the same time. The processed signal is amplified by a signal drive amplifier circuit, and then the positive level drive signal is converted into a negative level drive signal through a level shift circuit. The generated negative level drive signal is used to drive a PMOS tube in a low-side active drive clamp circuit, thereby effectively suppressing the switching spike of the bridge rectifier circuit.

[0034] like Figure 2 As shown, the full-bridge topology and bridge rectifier circuit unit 1 is composed of four primary bridge switch MOS tubes Q1-Q4, four secondary bridge rectifier tubes D1-D4, input capacitor C1, DC blocking capacitor C2, output capacitor C3, transformer T1 and output filter inductor L1. One end of the input capacitor C1 is connected to the input voltage VIN+, the drain of the switch MOS tube Q1, and the drain of the switch MOS tube Q3, and the other end is connected to the input negative terminal VIN-, the switch MOS tube Q2, and the source of the switch MOS tube Q4; the source of the switch MOS tube Q1 is connected to the drain of the switch MOS tube Q2 and one end of the DC blocking capacitor C2, the source of the switch MOS tube Q3 is connected to the drain of the switch MOS tube Q4 and the primary opposite-name terminal of the transformer T1, and the other end of the DC blocking capacitor C2 is connected to the primary same-name terminal of the transformer T1; the rectifier tube D1 The cathode of the rectifier D3 is connected to the cathode of the rectifier D3, one end of the output inductor L1 and one end of the clamping capacitor C7 in the low-side active clamping circuit unit; the anode of the rectifier D1 is connected to the cathode of the rectifier D2 and the secondary same-name end of the transformer T1; the anode of the rectifier D4 is connected to the anode of the rectifier D2 and one end of the output capacitor C3 to the output ground Vo-, the cathode of the rectifier D4 is connected to the anode of the rectifier D3 and the secondary opposite-name end of the transformer T1; the other end of the output inductor L1 is connected to the other end of the output capacitor C3 and the output positive end Vo+. The use of bridge rectification has the following effects: in applications with higher output voltages, the rated voltage requirements of the rectifier are reduced; the conduction voltage drop, reverse recovery time and other characteristics of the rectifier with low rated voltage under the same working conditions are significantly better than those of the rectifier with high rated voltage.

[0035] like Figure 2As shown, the PWM controller circuit unit 2 includes a PWM controller and its peripheral circuits. The PWM controller is a full-bridge / half-bridge PWM controller. The PWM controller model is not specific to a particular model, and both full-bridge and half-bridge controllers are acceptable. Its peripheral circuits are not strongly related to the circuit of the present invention and are not described here. The OTUA signal and the OUTB signal are symmetrical pulse signals with a certain dead zone, such as Figure 3 As shown; the OUTA signal is connected to the gate of the primary switch MOS tube Q2 and the 2nd pin of the digital isolator N1, and the OUTB signal is connected to the gate of the primary switch MOS tube Q4 and the 3rd pin of the digital isolator N1.

[0036] like Figure 2 As shown, the signal isolation circuit unit 3 includes a digital isolator N1 and its peripheral circuits. Pin 1 of the digital isolator N1 is connected to the primary 5V power supply, pin 2 of the digital isolator N1 is connected to the signal OUTA of the PWM controller circuit unit, pin 3 of the digital isolator N1 is connected to the signal OUTB of the PWM controller circuit unit, pin 4 of the digital isolator N1 is connected to the input ground, pin 4 of the digital isolator N1 is connected to the output ground, pin 6 of the digital isolator N1 is connected to one end of the charging resistor R2 of the timing adjustment circuit unit and the anode of the discharge diode D6, pin 7 of the digital isolator N1 is connected to one end of the charging resistor R1 in the timing adjustment circuit unit and the anode of the discharge diode D5, and pin 7 of the digital isolator N1 is connected to the secondary 5V power supply. The function of the signal isolation circuit unit 3 is to transmit the signal isolation to the secondary to meet the product isolation requirements.

[0037] like Figure 2 As shown, the timing adjustment circuit unit 4 includes a charging resistor R1, a charging resistor R2, a discharge diode D5, a discharge diode D6, a capacitor C4 and a capacitor C5. One end of the charging resistor R1 is connected to the 7th pin of the digital isolator N1 in the signal isolation circuit unit and the cathode of the discharge diode D5, and the other end is connected to the anode of the discharge diode D5, one end of the capacitor C4, one input end of the AND gate N4 in the signal logic processing circuit unit and the input end of the NOT gate N2; one end of the charging resistor R2 is connected to the 6th pin of the digital isolator N1 in the signal isolation circuit unit and the cathode of the discharge diode D6, and the other end is connected to the anode of the discharge diode D6, one end of the capacitor C5, the other input end of the AND gate N4 of the signal logic processing circuit unit and the input end of the NOT gate N3; the other ends of the capacitor C4 and the capacitor C5 are connected to the output ground Vo-. After passing through the timing adjustment circuit unit, the rising edges of the OUTA and OUTB signals have a certain delay, corresponding to Figure 3The function of the timing adjustment circuit unit 4 is to use the time difference between the RC charging and DC discharging circuits to delay the rising edge of the OUTA and OUTB signals respectively, and keep the falling edge unchanged to meet the driving timing waveform requirements.

[0038] like Figure 2 As shown, the signal logic processing circuit unit 5 includes a NOT gate N2, a NOT gate N3, an AND gate N4, an AND gate N5, and an OR gate N6. The input end of the NOT gate N2 is connected to one input end of the AND gate N4 and the other end of the charging resistor R1 in the timing adjustment circuit unit, the anode of the discharge diode D5, and one end of the capacitor C4; the input end of the NOT gate N3 is connected to the other input end of the AND gate N4 and the other end of the charging resistor R2 in the timing adjustment circuit unit, the anode of the discharge diode D6, and one end of the capacitor C5; the two input ends of the AND gate N5 are respectively connected to the output ends of the NOT gate N2 and the NOT gate N3, and the output end of the AND gate N5 is connected to one input end of the OR gate N6; one input end of the OR gate N6 is connected to the output end of the AND gate N4, the other input end of the OR gate N6 is connected to the output end of the AND gate N5, and the output end of the OR gate N6 is connected to the 5th and 6th pins of the driver N7 in the signal drive amplification and level shift circuit unit. As shown Figure 3 As shown, after being processed by the signal logic processing circuit unit, the A signal and the B signal become a Y signal with a doubled frequency. The function of the signal logic processing circuit unit 5 is to perform a logical operation of AND, first NOT, then AND, and finally OR on the A and B signals to process them into a signal with a doubled frequency and pulse width that meets the requirements.

[0039] like Figure 2 As shown, the signal drive amplification and level shift circuit unit 6 includes a driver N7, a level shift capacitor C6, a clamping diode D7 and a discharge resistor R3. Pin 1 of the driver N7 is connected to the secondary 12V voltage, pins 2 and 3 are connected to one end of the level shift capacitor C6, pin 4 is connected to the output ground Vo-, and pins 5 and 6 are connected to the output end of the OR gate N6 of the signal logic processing circuit unit; the other end of the level shift capacitor C6 is connected to the anode of the clamping diode D7, one end of the discharge resistor R3 and the gate of the clamping power PMOS tube Q5 of the low-side active clamping circuit unit; the cathode of the clamping diode D7 is connected to the other end of the discharge resistor R3 and the output ground Vo-. As shown Figure 3 As shown, the Y signal becomes a negative level driving signal G after passing through the signal driving amplification and level shifting circuit unit. The function of the signal driving amplification and level shifting circuit unit 6 is to perform power amplification and level shifting on the Y signal processed by the signal logic processing circuit to generate a negative voltage driving signal required for driving the PMOS tube.

[0040] like Figure 2As shown, the low-side active clamping circuit unit 7 includes a clamping power PMOS tube Q5, a clamping capacitor C7 and a current limiting resistor R4. The gate of the clamping power PMOS tube Q5 is connected to one end of the level shifting capacitor C6 in the signal drive amplification and level shifting circuit unit, the anode of the clamping diode D7 and one end of the discharge resistor R3, the drain of the clamping power PMOS tube Q5 is connected to one end of the clamping capacitor C7, and the source of the clamping power PMOS tube Q5 is connected to one end of the current limiting resistor R4; the other end of the clamping capacitor C7 is connected to the cathode of the bridge rectifier tube D1 and the bridge rectifier tube D3 in the full-bridge topology and bridge rectifier circuit unit and one end of the output filter inductor L1; the other end of the current limiting resistor R4 is connected to the output ground Vo-.

[0041] The working principle of the low-side active clamping driving circuit applicable to the bridge rectifier circuit described in the present invention is:

[0042] When the power supply is powered on, the PWM controller generates two drive signals OUTA and OUTB to drive the switch MOS tubes Q2 and Q4 in the primary full-bridge topology in the full-bridge topology and the bridge rectifier circuit (Q1 and Q3 drive requires an additional bootstrap circuit). The switch MOS tubes Q1 and Q4 and the switch MOS tubes Q2 and Q3 are turned on alternately to drive the transformer T1 to alternate between positive and negative, and transmit energy to the secondary. After the rectifier tubes D1 and D4 and the rectifier tubes D2 and D3 are rectified alternately, they are filtered by the output filter inductor L1 and the output capacitor C3 to form a DC output voltage. At the same time, the PWM controller generates two drive signals OUTA and OUTB, which are transmitted to the secondary of the transformer T1 after passing through the signal isolation circuit 3, and respectively pass through the charging resistor R1, the capacitor C4 and the charging resistor C3. After a certain dead zone delay, the signal enters the signal logic processing circuit 5 for AND (implemented by AND gate N4), NOT (implemented by NOT gates N2 and N3), AND (implemented by AND gate N5), and finally OR (implemented by OR gate N6) operations to become a frequency-doubled signal, which is then driven and amplified by the driver N7 in the signal drive amplification and level shifting circuit 6, and shifted to a negative level by the level shifting capacitor C6, the clamping diode D7, and the discharge resistor R3 to drive the clamping power PMOS tube Q5 to work. At this time, the clamping capacitor C7 absorbs the switching peaks of the clamping bridge rectifier tubes D1-D4, and the current limiting resistor R4 limits the current peak value flowing through the PMOS tube during clamping to protect the PMOS tube from working in a safe state.

[0043] From the above, it can be seen that the low-side active clamping drive circuit suitable for a bridge rectifier circuit described in the present invention is suitable for a full-bridge topology switching power supply. It can utilize the two-way drive signal of the primary switch tube. After isolation and signal processing, it can provide the required single-way doubled frequency negative voltage drive signal for the bridge rectifier circuit, and can effectively absorb the rectifier tube switch peak voltage. The circuit is simple, which not only reduces the voltage stress of the rectifier tube, but also reduces the loss and improves the efficiency.

[0044] The above-described embodiments are merely descriptions of preferred implementations of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various modifications and improvements made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the scope of protection determined by the claims of the present invention.

Claims

1. A low-side active clamping drive circuit suitable for a bridge rectifier circuit, characterized in that: The low-side active clamping drive circuit comprises: a full-bridge topology and bridge rectification circuit unit (1), a PWM controller circuit unit (2), a signal isolation circuit unit (3), a timing adjustment circuit unit (4), a signal logic processing circuit unit (5), a signal drive amplification and level shifting circuit unit (6) and a low-side active clamping circuit unit (7); The input end of the full-bridge topology and bridge rectifier circuit unit (1) is respectively connected to the input voltage and the output end OUTA and the output end OUTB of the PWM controller circuit unit (2); the output end of the full-bridge topology and bridge rectifier circuit unit (1) outputs the output voltage and is connected to the low-side active clamping circuit unit (2); The output end OUTA and the output end OUTB of the PWM controller circuit unit (2) are respectively connected to the input end of the full-bridge topology and bridge rectifier circuit unit (1) and the input end of the signal isolation circuit unit (3); the PWM controller circuit unit (2) is used to provide a driving signal for the primary power switch tube in the full-bridge topology and bridge rectifier circuit unit (1), and to provide two required original signals for the secondary low-side active clamping circuit unit (7); The input end of the signal isolation circuit unit (3) is connected to the output end of the PWM controller circuit unit (2), and the output end of the signal isolation circuit unit (3) is connected to the input end of the timing adjustment circuit unit (4); the signal isolation circuit unit (3) is used to isolate the two original signals of the primary side and transmit them to the secondary side, and then send them to the timing adjustment circuit unit (4) for waveform rising edge timing adjustment; The input end of the signal logic processing circuit unit (5) is respectively connected to the output end of the timing adjustment circuit unit (4), and the output end of the signal logic processing circuit unit (5) is connected to the input end of the signal drive amplification and level shift circuit unit (6); the signal logic processing circuit unit (5) is used to perform AND, NOT, or OR operations on the two signals adjusted by the timing adjustment circuit unit (4) to obtain a required single signal, and then send the single signal to the signal drive amplification and level shift circuit unit (6) for signal amplification and level shift conversion; The input end of the signal drive amplification and level shift circuit unit (6) is connected to the output end of the signal logic processing circuit unit (5), and the output end of the signal drive amplification and level shift circuit unit (6) is connected to the input end of the low-side active clamp circuit unit (7); the signal drive amplification and level shift circuit unit (6) is used to amplify the driving capability of the signal and convert the positive level signal into a negative level signal required by the low-side active clamp circuit unit (7); The input end of the low-side active clamping circuit unit (7) is connected to the output end of the signal drive amplification and level shifting circuit unit (6), and the output end of the low-side active clamping circuit unit (7) is connected to the input end of the full-bridge topology and bridge rectifier circuit unit (1); the low-side active clamping circuit unit is used to absorb the peak voltage of the rectifier switch of the bridge rectifier circuit.

2. The low-side active clamping driving circuit suitable for a bridge rectifier circuit according to claim 1, characterized in that: The full-bridge topology and bridge rectifier circuit unit (1) comprises four primary bridge switch MOS tubes Q1-Q4, four secondary bridge rectifier tubes D1-D4, an input capacitor C1, a DC blocking capacitor C2, an output capacitor C3, a transformer T1 and an output filter inductor L1; The drain of the bridge switch MOS tube Q1 is connected to the drain of the bridge switch MOS tube Q3 and then connected to the input voltage VIN+; the source of the bridge switch MOS tube Q1 is connected to the drain of the bridge switch MOS tube Q2 and then connected to the same-name end of the primary winding of the transformer T1 through the DC blocking capacitor C2; the source of the bridge switch MOS tube Q3 is connected to the drain of the bridge switch MOS tube Q4 and then connected to the opposite-name end of the primary winding of the transformer T1; the source of the bridge switch MOS tube Q2 and the source of the bridge switch MOS tube Q4 are then connected to the input ground VIN-; one end of the input capacitor C1 is connected to the drain of the bridge switch MOS tube Q1, and the other end is connected to the bridge switch The source of the MOS tube Q2 is connected; the anode of the bridge rectifier D1 is connected to the cathode of the bridge rectifier D2, the cathode of the bridge rectifier D1 is connected to the cathode of the bridge rectifier D3 and is also connected to one end of the output filter inductor L1; the other end of the output filter inductor L1 serves as the positive end of the output voltage; the anode of the bridge rectifier D2 is connected to the anode of the bridge rectifier D4 and is also grounded, serving as the negative end of the output voltage; the two ends of the output capacitor C3 are respectively connected to the positive end of the output voltage and the negative end of the output voltage; the anode of the bridge rectifier D1 is connected to the same-name end of the secondary winding of the transformer T1; the anode of the bridge rectifier D3 is connected to the opposite-name end of the secondary winding of the transformer T1.

3. The low-side active clamping driving circuit suitable for a bridge rectifier circuit according to claim 2, characterized in that: The PWM controller circuit unit (2) comprises a PWM controller, which is a full-bridge or half-bridge PWM controller; two output ends of the PWM controller output two drive signals, OUTA and OUTB, the OUTA signal is connected to the gate of the primary switch MOS tube Q2 and the 2nd pin of the digital isolator N1 in the signal isolation circuit unit (3), and the OUTB signal is connected to the gate of the primary switch MOS tube Q4 and the 3rd pin of the digital isolator N1 in the signal isolation circuit unit (3).

4. The low-side active clamping driving circuit suitable for a bridge rectifier circuit according to claim 3, characterized in that: The signal isolation circuit unit (3) comprises a digital isolator N1; pin 1 of the digital isolator N1 is connected to a primary 5V power supply, pin 2 of the digital isolator N1 is connected to an OUTA signal output by the PWM controller circuit unit (2), pin 3 of the digital isolator N1 is connected to an OUTB signal output by the PWM controller circuit unit (2), pin 4 of the digital isolator N1 is connected to an input ground VIN-, pin 4 of the digital isolator N1 is connected to an output ground Vo-, pin 6 of the digital isolator N1 is connected to one end of a charging resistor R2 and a cathode of a discharge diode D6 in the timing adjustment circuit unit (4), pin 7 of the digital isolator N1 is connected to one end of a charging resistor R1 and a cathode of a discharge diode D5 in the timing adjustment circuit unit (4), and pin 7 of the digital isolator N1 is connected to a secondary 5V power supply.

5. The low-side active clamping driving circuit suitable for a bridge rectifier circuit according to claim 4, characterized in that: The timing adjustment circuit unit (4) comprises a charging resistor R1, a charging resistor R2, a discharge diode D5, a discharge diode D6, a capacitor C4 and a capacitor C5; one end of the charging resistor R1 is connected to the 7th pin of the digital isolator N1 in the signal isolation circuit unit (3) and the cathode of the discharge diode D5, and the other end of the charging resistor R1 is connected to the anode of the discharge diode D5, one end of the capacitor C4, one input end of the AND gate N4 in the signal logic processing circuit unit (5) and the input end of the NOT gate N2; one end of the charging resistor R2 is connected to the 6th pin of the digital isolator N1 in the signal isolation circuit unit (3) and the cathode of the discharge diode D6, and the other end is connected to the anode of the discharge diode D6, one end of the capacitor C5, the other input end of the AND gate N4 in the signal logic processing circuit unit (5) and the input end of the NOT gate N3; the other ends of the capacitor C4 and the capacitor C5 are connected to the output ground Vo-.

6. The low-side active clamping driving circuit suitable for a bridge rectifier circuit according to claim 5, characterized in that: The signal logic processing circuit unit (5) comprises a NOT gate N2, a NOT gate N3, an AND gate N4, an AND gate N5 and an OR gate N6; the input end of the NOT gate N2 is connected to an input end of the AND gate N4 and the other end of the charging resistor R1 in the timing adjustment circuit unit (4), the anode of the discharge diode D5 and one end of the capacitor C4; the input end of the NOT gate N3 is connected to the other input end of the AND gate N4 and the other end of the charging resistor R2 in the timing adjustment circuit unit (4), the anode of the discharge diode D5 and one end of the capacitor C4. The anode of the tube D6 is connected to one end of the capacitor C5; the two input ends of the AND gate N5 are respectively connected to the output ends of the NOT gate N2 and the NOT gate N3, and the output end of the AND gate N5 is connected to one input end of the OR gate N6; one input end of the OR gate N6 is connected to the output end of the AND gate N4, the other input end of the OR gate N6 is connected to the output end of the AND gate N5, and the output end of the OR gate N6 is connected to the 5th and 6th pins of the driver N7 in the signal drive amplification and level shift circuit unit (6).

7. The low-side active clamping driving circuit suitable for a bridge rectifier circuit according to claim 6, characterized in that: The signal drive amplification and level shift circuit unit (6) comprises a driver N7, a level shift capacitor C6, a clamping diode D7 and a discharge resistor R3; pin 1 of the driver N7 is connected to a secondary 12V voltage, pins 2 and 3 of the driver N7 are connected to one end of the level shift capacitor C6, pin 4 of the driver N7 is connected to an output ground Vo-, and pins 5 and 6 of the driver N7 are connected to an output end of an OR gate N6 in the signal logic processing circuit unit (5); the other end of the level shift capacitor C6 is connected to an anode of the clamping diode D7, one end of the discharge resistor R3 and a gate of a clamping power PMOS tube Q5 in the low-side active clamping circuit unit (7); and the cathode of the clamping diode D7 is connected to the other end of the discharge resistor R3 and the output ground Vo-.

8. The low-side active clamping driving circuit suitable for a bridge rectifier circuit according to claim 7, characterized in that: The low-side active clamping circuit unit (7) comprises a clamping power PMOS tube Q5, a clamping capacitor C7 and a current limiting resistor R4; the gate of the clamping power PMOS tube Q5 is connected to one end of the level shifting capacitor C6 in the signal drive amplification and level shifting circuit unit (6), the anode of the clamping diode D7 and one end of the discharge resistor R3, the drain of the clamping power PMOS tube Q5 is connected to one end of the clamping capacitor C7, and the source of the clamping power PMOS tube Q5 is connected to one end of the current limiting resistor R4; the other end of the clamping capacitor C7 is connected to the cathode of the bridge rectifier tube D1 and the bridge rectifier tube D3 in the full-bridge topology and bridge rectifier circuit unit (1) and one end of the output filter inductor L1; the other end of the current limiting resistor R4 is connected to the output ground Vo-.

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