Bus current ripple suppression method for four-inverter system

Abstract

The invention discloses a bus current ripple suppression method for a four-inverter system, and relates to the technical field of power electronics. The suppression method comprises the following steps: acquiring load current for each inverter, and determining a zero vector and an active vector; adjusting a vector action sequence to obtain 16 combinations; after fundamental waves of any two inverters are subjected to phase shifting by 60 degrees, a zero vector is updated according to bus current generated by the first active vector and the second active vector, and a seventeenth combination is obtained; for all combinations, carrier phases of two inverters are shifted, and then the same number of combinations are obtained; and traversing all the combinations by using a bus current effective value function, and selecting the combination with the minimum value so as to suppress the bus current ripple. According to the suppression method, the bus current ripples of the four-inverter system can be fully suppressed, the direct-current bus capacitor volume of the four-inverter system is greatly reduced, and the power density and reliability of the four-inverter system are improved.

Description

Technical Field

[0001] The invention relates to the technical field of power electronics, and in particular to a bus current ripple suppression method for a four-inverter system. Background Art

[0002] As some applications have higher and higher power requirements, the limitations of traditional single-inverter systems have gradually become apparent. Therefore, quad-inverter systems have been used in fields with relatively high power requirements, such as aerospace, rail transportation, low-altitude economic aircraft, ship propulsion, and wind power generation.

[0003] Compared with a single inverter system, a four-inverter system has the following advantages: (1) Low-power power electronic device level to achieve high power output: Due to the limitation of single-phase current, the power of a single inverter system will be limited by the voltage level. If the power level is to be increased, higher requirements are placed on the voltage resistance level of the inverter. In contrast, the four-inverter system increases the power level of the drive system by increasing the number of phases when the single-phase current is limited.

[0004] (2) Different inverters use different modulation strategies to achieve better performance: The modulation strategy used by the single inverter system is unique, which will limit the performance improvement of the drive system. In contrast, different inverters in the four-inverter system can use different modulation strategies to achieve better performance, such as high power quality and high power density.

[0005] (3) High reliability: When a phase winding or power electronic device in the inverter system fails, the remaining windings cannot build an equivalent rotating magnetic force, and it is necessary to shut down immediately or add auxiliary circuits for fault-tolerant control. In contrast, when a phase winding or power electronic device in a four-inverter system fails, the system can be guaranteed to operate fault-tolerantly by simply changing the control algorithm without adding auxiliary circuits.

[0006] The DC bus capacitor is an important component of the four-inverter system. It stabilizes the DC bus voltage, absorbs ripple current and suppresses voltage spikes. However, the DC bus capacitor is bulky and will reduce the power density of the drive system.

[0007] For a four-inverter system, the DC bus current ripple is four times that of a single-inverter system when using a traditional modulation strategy, requiring a larger capacitor, which further reduces the power density. In addition, the DC bus capacitor is a device that is prone to failure. The heating problem caused by the large DC bus current ripple is the main cause of DC bus capacitor failure.

[0008] Therefore, it is necessary to use a suitable modulation strategy to reduce the DC bus current ripple to increase the life of the DC bus capacitor. To reduce the DC bus current ripple, it is mainly achieved by interleaving the carrier phases of different inverters or adjusting the vector order of different inverters.

[0009] However, existing research focuses on dual-inverter drive systems. For quad-inverter systems, the existing technology uses a method of staggering the carrier phase by 90° to reduce the DC bus current ripple. In this suppression method, only the carrier phase shift is considered, which cannot fully suppress the DC bus current ripple of the quad-inverter system.

[0010] In summary, the existing technology uses relatively simple means to suppress the DC bus current ripple in the four-inverter system, and the suppression effect is poor. Summary of the invention

[0011] In order to solve the above technical problems existing in the prior art, the present invention aims to provide a method for effectively suppressing the DC bus current ripple in a four-inverter system. Therefore, the present invention proposes a bus current ripple suppression method for a four-inverter system, which fully suppresses the DC bus current ripple without increasing the switching frequency through two-step DC bus current effective value prediction.

[0012] Specifically, the present invention provides a bus current ripple suppression method for a four-inverter system, and the technical solution includes: In the four-inverter system, the DC buses connected to the DC ends of the inverters are connected in parallel, and the AC ends are connected to the loads; the capacitors are connected in parallel to the DC power supply; The bus current ripple suppression method includes the following steps: Step S1: for each inverter, collect the load current, determine the zero vector, the first active vector and the second active vector; adjust the vector action sequence in each inverter to obtain 16 candidate pulse combinations; Step S2: After the load current fundamental waves of any two inverters are phase-shifted by 60°, the load current relationship of the four inverters is obtained; updating a first active vector and a second active vector of each inverter according to the load current relationship, and updating a zero vector according to bus currents generated by the first active vector and the second active vector, so as to obtain a 17th candidate pulse combination; Step S3: for all candidate pulse combinations, select two inverters to perform a 90° carrier phase shift, and then obtain the same number of candidate pulse combinations; Step S4: Use bus current effective value function F i All candidate pulse combinations are traversed, and the candidate pulse combination that minimizes the bus current effective value function is selected to suppress the bus current ripple of the four-inverter system.

[0013] Compared with the prior art, the technical solution provided by the present invention fully considers the three degrees of freedom of vector action order, load current fundamental phase and carrier phase in the four-inverter system, and determines the optimal pulse combination to act on the inverter by traversing the effective value function of the DC bus current, which can fully suppress the bus current ripple of the four-inverter system, greatly reduce the DC bus capacitor volume of the four-inverter system, and improve the power density and reliability of the four-inverter system. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. 4 is a topological diagram of a four-inverter system in an embodiment of the present invention.

[0015] Figure 2 The figure is a flow chart of a bus current ripple suppression method for a four-inverter system according to an embodiment of the present invention.

[0016] Figure 3 is a space vector diagram of the first inverter in one embodiment of the present invention.

[0017] Figure 4 1 is a switching pulse diagram of the first inverter when the vector action sequence is not adjusted within a switching cycle in one embodiment of the present invention.

[0018] Figure 5 4 is a switching pulse diagram of the 17th candidate pulse combination in a switching cycle in one embodiment of the present invention.

[0019] Figure 6 4 is a switching pulse diagram of the fourth candidate pulse combination in a switching cycle in one embodiment of the present invention.

[0020] Figure 7 1 is a carrier diagram of different inverters after carrier phase shifting in one embodiment of the present invention.

[0021] Figure 8 This is a DC bus current diagram generated by the 17th candidate pulse combination in a switching cycle in one embodiment of the present invention. DETAILED DESCRIPTION

[0022] Hereinafter, the technical solution provided by the present invention will be further elaborated in combination with embodiments and drawings.

[0023] Embodiment 1: The topology of the four-inverter system used in this embodiment is as follows: Figure 1 shown.

[0024] The four-inverter system includes a first inverter, a second inverter, a third inverter and a fourth inverter, and the four inverters share a DC power supply. U dcand a DC bus capacitor C The DC buses of the first inverter, the second inverter, the third inverter and the fourth inverter are connected in parallel, and the capacitor C Connect in parallel with the DC power supply. i dc1 , i dc2 , i dc3 and i dc4 They are the DC bus currents generated by the four inverters, i dc is the total DC bus current, I dc is the input current of the DC power supply. The AC ends of the first inverter, the second inverter, the third inverter and the fourth inverter are connected with a load, which is a resistive inductive load or a motor. R is the load resistance, L is the load inductance.

[0025] The four-inverter system can power four independent resistive-inductive loads or motors. The load voltage and load current expressions are: ; ; In the formula, x is the inverter serial number, x =1,2,3,4; u Ax For the x The A phase voltage of the load corresponding to each inverter, u Bx For the x The B-phase voltage of the load corresponding to each inverter, u Cx For the x The C phase voltage of the load corresponding to each inverter, i Ax For the x The A-phase current of the load corresponding to each inverter, i Bx For the x The B-phase current of the load corresponding to each inverter, i Cx is the C-phase current of the load corresponding to the x-th inverter; U and I are the amplitudes of phase voltage and phase current respectively, is the angular frequency of the load current, , f is the fundamental frequency of the load current, is the angle between the phase voltage and the phase current.

[0026] The flow chart of the bus current ripple suppression method of the four-inverter system is as follows Figure 2 shown.

[0027] First, we need to determine 17 candidate pulse combinations for the four inverters. Taking the first inverter as an example, the vectors of the first inverter are S A1 S B1 S C1 = 100, 110, 010, 011, 001, 101, 000 and 111, S k (k = A1, B1, C1) represents the state of the switch tube in each phase bridge arm. S k =1 means the upper switch is turned on and the lower switch is turned off. S k =0 means the lower switch is turned on and the upper switch is turned off.

[0028] The DC bus current generated by the first inverter i dc1 The expression is: ; Based on the above expression, different S A1 S B1 S C1 Substituting into, we get the corresponding DC bus current i dc1 The expression of is shown in Table 1.

[0029] Table 1 Relationship between DC bus current and the on / off state of the bridge arm switch tube .

[0030] In order to better explain the generation mechanism of DC bus current, f = 100 Hz, cos = 0.95, ωt = 5π / 8 as an example. ωt and Substituting into the load current expression, we can calculate i A1 , i B1 , i C1 0.997 respectively I , -0.434 I , -0.563I .

[0031] Further, the sectors and active vectors are determined according to SVPWM (Space Vector Pulse Width Modulation). The space vector diagram of the first inverter is as follows: Figure 3 As shown in the figure, it can be seen that the space vector diagram is composed of six sectors, namely sector-I, sector-II, sector-III, sector-IV, sector-V, and sector-VI. In each sector, the reference voltage vector is synthesized by two adjacent active vectors and a zero vector. In order to determine the active vector and zero vector used in the current switching cycle, it is necessary to determine the sector where the reference voltage vector is located. Assume that the reference voltage vector is αβ The component on the axis is u α and u β , and define three intermediate variables U ref1 , U ref2 , U ref3 : ; ; ; Define three variables U , V , W , and their values ​​satisfy the following formula: like U ref1 >0, then U =1, otherwise U =0; if U ref2 >0, then V =1, otherwise V =0; if U ref3 >0, then W =1, otherwise W =0.

[0032] make J = 4 W + 2 V + U ,get J The relationship with sectors is shown in Table 2.

[0033] Table 2 Sector correspondence table .

[0034] With a modulation index of 0.9,U dc = 80V as an example. When the modulation index is 0.9, the amplitude of the reference voltage when using space vector pulse width modulation is 80×0.577×0.9 = 41.544V.

[0035] Assume that the d-axis voltage u d = 0V, q-axis voltage u q = 41.544V. The reference voltage vector is calculated to be αβ The component on the axis is given by the following formula: ; In the formula, θ e is the electrical angle of the motor. In this embodiment, θ e = 13π / 8. By calculating from the above formula, we can get: u α =38.38V, u β =15.9V.

[0036] Further, three intermediate variables can be obtained U ref1 >0, U ref2 >0, U ref3 <0, then J = 3, that is, the reference voltage is located in sector -Ⅰ.

[0037] Depend on Figure 3 It can be seen that the reference voltage in sector-I selects vectors 100 and 110 as active vectors, wherein vector 100 is the first active vector and vector 110 is the second active vector.

[0038] Furthermore, the durations of the first active vector and the second active vector are T 100 and T 110 They are: ; Can get T 100 and T 110 0.55 respectively T s and 0.35 T s .in, T s for one switching cycle.

[0039] therefore, ωt = 5π / 8, the corresponding switching pulse of one switching cycle is as follows Figure 4 As shown, no adjustments are made to the switching sequence at this time.

[0040] According to Table 1, the first active vector, the second active vector and vector 000 generate i dc1 They are i A1 、- i C1 and 0. Therefore, Figure 4 In area 1, area 2, and area 3 i dc1 They are 0, 0.997I, and 0.563I respectively. It can be found that the bus current ripples in area-1, area-2, and area-3 are irregular.

[0041] Among them, after determining the vector action sequence, in one switching cycle, the DC bus current generated by the vectors acting on both sides constitutes area-1, the DC bus current generated by the vectors acting in the middle constitutes area-3, and the other areas constitute area-2, such as Figure 4 shown.

[0042] The vector action sequence of different inverters will be adjusted to lay the foundation for suppressing DC bus current ripple.

[0043] If the DC bus current satisfies area-1≥area-2≥area-3 within one switching cycle after adjustment, it is defined as " i dc +”, that is, the maximum DC bus current value is centered.

[0044] If the DC bus current satisfies area-1≤area-2≤area-3 within one switching cycle after adjustment, it is defined as " i dc -”, that is, the minimum DC bus current value is in the middle.

[0045] Since each inverter can work in i dc +" state, and can also work in " i dc -” state, so the four-inverter system has a total of 2 4 = 16 possible candidate pulse combinations, as shown in Table 3.

[0046] Table 3 Possible pulse combinations after adjusting the vector action sequence .

[0047] Further, the 17th candidate pulse combination is determined.

[0048] After the load current fundamental wave of the second inverter is phase-shifted by 60°, the load current relationship between the first inverter and the second inverter is: ; When the phase of the first inverter ωt When the phase of the second inverter is 5π / 8, ωt =7π / 24. ωt =7π / 24 Load current expression is calculated i A2 , i B2 , i C2 They are 0.563I, -0.997I and 0.434I respectively. According to the SVPWM principle, ωt When the modulation index is 7π / 24, the reference voltage of the second inverter is located in sector VI. Vectors 100 and 101 are selected as active vectors, wherein vector 100 is the first active vector and vector 101 is the second active vector. When the modulation index is 0.9, the duration of the first active vector and the second active vector is T 100 and T 101 0.35 respectively T s and 0.55 T s According to Table 1, the first active vector and the second active vector generate i dc2 They are i A2 and- i B2 .

[0049] Further, it can be found that for the first inverter, the DC bus current generated by the first active vector i A1 is less than the DC bus current generated by the second active vector - i C1 , therefore, 111 is selected as the zero vector. For the second inverter, the DC bus current generated by the first active vector i A2 is less than the DC bus current generated by the second active vector - i B2 , therefore, 000 is chosen as the zero vector.

[0050] Furthermore, the pulse of the third inverter is the same as that of the first inverter, and the pulse of the fourth inverter is the same as that of the second inverter, so the 17th candidate pulse combination is obtained as follows: Figure 5 shown.

[0051] It should be noted that the topology of the four-inverter system used in the present invention is fixed, and the positions of the first inverter, the second inverter, the third inverter and the fourth inverter are equivalent, so the 60° phase shift of the load current fundamental wave can be performed on any two inverters, thereby determining the load current relationship with the remaining two inverters in a one-to-one correspondence.

[0052] After determining the 17 candidate pulse combinations, in order to avoid the candidate pulse combinations that increase the switching frequency from entering the next step of DC bus current effective value prediction, the value function is first used F s Perform a preliminary screening of candidate pulse combinations. Value function F s The expression is: ; In the formula, y is the phase sequence number, f c To control the frequency, K y is the number of switch actions. F s If it is not equal to 0, the candidate pulse combination that will increase the switching frequency will be eliminated. Taking candidate pulse combination-4 as an example, the switching pulses of different inverters are as follows Figure 6 shown.

[0053] When the control frequency f c When the frequency is 10kHz, the switching action times of the A-phase inverter are all 1, the switching action times of the B-phase inverter are all 2, and the switching action times of the C-phase inverter are all 0. F s = 3.33 So candidate pulse combination -4 will make F s If it is not equal to 0, it will be eliminated and will not participate in the next step of DC bus current effective value prediction. Figure 6 In the candidate pulse combination -17, in each inverter, two phases have one switching action, and one phase does not have a switching action. The calculation results are F s If it is equal to 0, the next step of DC bus current effective value prediction is retained.

[0054] After the first step of traversing the value function, the remaining n The candidate pulse combinations can enter the next step of DC bus current effective value prediction. In order to fully suppress the DC bus current ripple, the carrier phase of two inverters in the four-inverter system is selected to shift by 90°, and thenn candidate pulse combinations, using the value function F i Traverse 2n candidate pulse combinations. After the carrier phase shift, the carriers of different inverters are as follows Figure 7 shown.

[0055] Among them, for the 1st to 16th candidate pulse combinations, if the vector action order of the four inverters is the same, the carrier phases of any two inverters are shifted by 90°, otherwise the carrier phases of any two inverters with different vector action orders are shifted by 90°; for the 17th candidate pulse combination, otherwise the carrier phases of any two inverters with different fundamental wave phases are shifted by 90°.

[0056] Determine all 2 factors involved in the prediction of the effective value of the DC bus current n After the candidate pulses are combined, the value function is used F i Traversing, DC bus current value function F i The expression is: ; In the formula, z is the DC bus current serial number, N is the number of different DC bus currents in one switching cycle, x is the inverter serial number, T z is the action time of the zth DC bus current, T s is the switching cycle, S Ax-z To produce the z The DC bus current x The on / off state of the switch tube on the A phase bridge arm of each inverter, S Bx-z To produce the z The DC bus current x The on / off state of the switch tube on the B phase bridge arm of each inverter, S Cx-z To produce the z The DC bus current x The on and off status of the switch tube on the C phase bridge arm of the inverter.

[0057] Taking candidate pulse combination-17 as an example, the generated DC bus current ripple is as follows: Figure 8 As shown. It can be seen that the DC bus current in one switching cycle i dc There are three values, namely 1.994 I , 3.12 I and 3.988I , corresponding to T z Also contains three. Further, using the formula F i The effective value of the DC bus current of the current candidate pulse combination can be calculated. n After traversing the candidate pulse combinations, F i Get the minimum value S The pulse combination acting on the inverter can fully suppress the bus current ripple of the four-inverter system.

[0058] Optionally, the switching frequency merit function may not be used F s Eliminate candidate pulse combinations that will increase the switching frequency and directly use the DC bus current value function F i Select the most appropriate pulse combination.

[0059] In combination with the above embodiments, it can be seen that compared with the prior art, the technical solution provided by the present invention fully considers the three degrees of freedom of the vector action order, load current fundamental phase and carrier phase in the four-inverter system, and determines the optimal pulse combination to act on the inverter by traversing the DC bus current effective value value function, which can fully suppress the bus current ripple of the four-inverter system, greatly reduce the DC bus capacitor volume of the four-inverter system, and improve the power density and reliability of the four-inverter system. Furthermore, by traversing the switching frequency value function, the pulse combination that will increase the switching frequency is eliminated, which can reduce the cost consumption and computational complexity of the four-inverter system.

Claims

1. A bus current ripple suppression method for a four-inverter system, characterized in that: In the four-inverter system, the DC busbars connected to the DC ends of the inverters are connected in parallel, and the AC ends are connected to the loads; the capacitors are connected in parallel to the DC power supply; and the following steps are included: Step S1: for each inverter, collect the load current, determine the zero vector, the first active vector and the second active vector; adjust the vector action sequence in each inverter to obtain 16 candidate pulse combinations; Step S2: After the load current fundamental waves of any two inverters are phase-shifted by 60°, the load current relationship of the four inverters is obtained; updating a first active vector and a second active vector of each inverter according to the load current relationship, and updating a zero vector according to bus currents generated by the first active vector and the second active vector, respectively, to obtain a 17th candidate pulse combination; Step S3: for all candidate pulse combinations, select two inverters to perform a 90° carrier phase shift, and then obtain the same number of candidate pulse combinations; Step S4: Use bus current effective value function F i All candidate pulse combinations are traversed, and the candidate pulse combination that minimizes the bus current effective value function is selected to suppress the bus current ripple of the four-inverter system.

2. A bus current ripple suppression method for a quad-inverter system according to claim 1, characterized in that: The vector action sequence in each inverter is adjusted to obtain 16 candidate pulse combinations, including: For each inverter, by adjusting the action order of the zero vector, the first active vector and the second active vector, two kinds of pulses are obtained, namely, the maximum DC bus current value is centered and the minimum DC bus current value is centered; One pulse is selected from each inverter for combination, and 16 candidate pulse combinations are obtained.

3. The bus current ripple suppression method for a quad-inverter system according to claim 1, characterized in that: The zero vector, the first active vector and the second active vector are all represented by 3-bit binary numbers, corresponding to the on / off states of the switch tubes on the A-phase bridge arm, the B-phase bridge arm and the C-phase bridge arm of the inverter; For any phase bridge arm, if the upper switch is turned on and the lower switch is turned off, the value of the corresponding digit is 1; If the upper switch is turned off and the lower switch is turned on, the value of the corresponding digit is 0.

4. A bus current ripple suppression method for a quad-inverter system according to claim 3, characterized in that: The updating of the zero vector according to the bus currents generated by the first active vector and the second active vector specifically includes: For each inverter, when the DC bus current generated by the first active vector is greater than that of the second active vector, 000 is selected as the zero vector; when the DC bus current generated by the first active vector is less than that of the second active vector, 111 is selected as the zero vector; when the DC bus current generated by the first active vector is equal to the second active vector, if the inverter does not perform load current fundamental phase shift, 000 is selected as the zero vector, otherwise 111 is selected as the zero vector.

5. The bus current ripple suppression method for a quad-inverter system according to claim 1, characterized in that: The selecting of two inverters to perform a 90° carrier phase shift specifically includes: For the 1st to 16th candidate pulse combinations, if the vector action order of the four inverters is the same, the carrier phases of any two inverters are shifted by 90°, otherwise the carrier phases of any two inverters with different vector action orders are shifted by 90°; For the 17th candidate pulse combination, the carrier phases of any two inverters with different fundamental wave phases are shifted by 90°.

6. A bus current ripple suppression method for a quad-inverter system according to claim 1, characterized in that: The bus current effective value function F i The expression is as follows: ； In the formula, z is the DC bus current serial number, N is the number of different DC bus currents in one switching cycle, x is the inverter serial number, T z For the z The action time of the DC bus current is T s is the switching cycle, S Ax-z To produce the z The DC bus current x The on / off state of the switch tube on the A phase bridge arm of each inverter, S Bx-z To produce the z The DC bus current x The on / off state of the switch tube on the B phase bridge arm of each inverter, S Cx-z To produce the z The DC bus current x The on / off status of the switch tube on the C-phase bridge arm of each inverter; i Ax For the x The A-phase current of the load corresponding to each inverter, i Bx For the x The B-phase current of the load corresponding to each inverter, i Cx For the x The C-phase current of the load corresponding to each inverter; Among them, if the upper switch tube in a certain phase bridge arm is turned on and the lower switch tube is turned off, the switching state is 1; if the upper switch tube in a certain phase bridge arm is turned off and the lower switch tube is turned on, the switching state is 0.

7. A bus current ripple suppression method for a quad-inverter system according to claim 1, characterized in that: After step S2, the method further includes: using a switching frequency value function F s Traverse 17 candidate pulse combinations; for any candidate pulse combination, if F s ≠0, then remove it.

8. A bus current ripple suppression method for a quad-inverter system according to claim 7, characterized in that: The switching frequency value function F s The expression is as follows: ； In the formula, x is the inverter serial number, y is the phase sequence number, f c To control the frequency, K y is the number of switching actions of the corresponding inverter in one switching cycle.

Images