DC voltage conversion circuit and conversion method

Abstract

The present invention provides a DC voltage conversion circuit and a conversion method, which can be applied to the field of voltage conversion technology. The circuit includes: a series-parallel switched-capacitor current reduction module and a stacked switched-capacitor module; wherein, the series-parallel switched-capacitor current reduction module is electrically connected to the input power supply module, and the series-parallel switched-capacitor current reduction module includes a power inductor and N cascaded capacitor current reduction units. The series-parallel switched-capacitor current reduction module is used to control the charge and discharge states of the N capacitor current reduction units to regulate the potential difference across the power inductor, so as to reduce the average inductance current of the power inductor to a first current; the stacked switched-capacitor module is electrically connected to the series-parallel switched-capacitor current reduction module, and the stacked switched-capacitor module includes M cascaded capacitor boost units. The stacked switched-capacitor module is used to alternately control the charge and discharge states of the M capacitor boost units based on the potential difference across the power inductor to boost the input voltage and output a target voltage.

Description

Technical Field

[0001] The present invention relates to the technical field of voltage conversion, and more particularly to a DC voltage conversion circuit and a conversion method. Background Art

[0002] Since a DC voltage conversion circuit can convert a small input voltage into a large output voltage, the DC voltage conversion circuit is widely used in fields such as diode driving, optical modules, and micro-robots. However, existing DC voltage conversion circuits often require the use of large-sized inductors to reduce inductance losses and have low power conversion efficiency.

[0003] In the process of implementing the above inventive concept, it has been found through research that: the voltage conversion ratio of existing DC voltage conversion circuits is low, the power conversion efficiency is low, and due to the relatively high average current of the inductor and the voltage of the switching transistor in the DC voltage conversion circuit, it is necessary to use large-sized, low-loss inductors and high-voltage withstand switching transistors, resulting in a low power density and high cost of the DC voltage conversion circuit. Summary of the Invention

[0004] In view of the above problems, the present invention provides a DC voltage conversion circuit and a conversion method.

[0005] According to a first aspect of the present invention, there is provided a DC voltage conversion circuit, comprising: a series-parallel switched capacitor current reduction module, a stacked switched capacitor module; the series-parallel switched capacitor current reduction module is electrically connected to an input power module, the series-parallel switched capacitor current reduction module includes a power inductor and N cascaded capacitor current reduction units, and the series-parallel switched capacitor current reduction module is configured to control the charging and discharging states of the N capacitor current reduction units to regulate the potential difference across the power inductor, so as to reduce the inductor average current of the power inductor to a first current, where N≥2 and N is an integer; the stacked switched capacitor module is electrically connected to the series-parallel switched capacitor current reduction module, the stacked switched capacitor module includes M cascaded capacitor boosting units, and the stacked switched capacitor module is configured to alternately control the charging and discharging states of the M capacitor boosting units based on the potential difference across the power inductor to boost the input voltage and output a target voltage, where M≥2 and M is an integer.

[0006] According to an embodiment of the present invention, the N cascaded capacitor current reduction units include N-1 first capacitor shunt sub-units and a second capacitor shunt sub-unit; the first ends of the N-1 first capacitor shunt sub-units are electrically connected to the input power module, and the second ends of the N-1 first capacitor shunt sub-units are electrically connected to the first end of the second capacitor shunt sub-unit; the second end of the second capacitor shunt sub-unit is electrically connected to the first end of the power inductor, and the third end of the second capacitor shunt sub-unit is electrically connected to the stacked switched capacitor module.

[0007] According to an embodiment of the present invention, the nth first capacitor shunting sub-unit among N-1 first capacitor shunting sub-units includes a first switch, a second switch, a third switch, and a first capacitor, where 1 ≤ n ≤ N-1; the first end of the first switch of the nth first capacitor shunting sub-unit is electrically connected to the first end of the first capacitor of the (n+1)th first capacitor shunting sub-unit, and the second end of the first switch is electrically connected to the second end of the first capacitor, wherein the first end of the (N-1)th first capacitor shunting sub-unit is electrically connected to the input power module; the first end of the second switch of the nth first capacitor shunting sub-unit is electrically connected to the input power module, and the second end of the second switch is electrically connected to the first end of the first capacitor; the first end of the third switch of the nth first capacitor shunting sub-unit is electrically connected to the second end of the first capacitor, and the second end of the third switch is grounded.

[0008] According to an embodiment of the present invention, the second capacitor shunting sub-unit includes a fourth switch, a fifth switch, a sixth switch, and a second capacitor; the first end of the fourth switch of the second capacitor shunting sub-unit is electrically connected to the first end of the first capacitor in the first first capacitor shunting sub-unit, and the second end of the fourth switch is electrically connected to the second end of the second capacitor; the first end of the fifth switch of the second capacitor shunting sub-unit is electrically connected to the input power module, and the second end of the fifth switch is electrically connected to the first end of the second capacitor; the first end of the sixth switch of the second capacitor shunting sub-unit is electrically connected to the first end of the second capacitor, and the second end of the sixth switch is electrically connected to the stacked switch capacitor module; the first end of the second capacitor of the second capacitor shunting sub-unit is electrically connected to the second end of the fifth switch, and the second end of the second capacitor is electrically connected to the first end of the power inductor.

[0009] According to an embodiment of the present invention, the switching period of each switch includes a first time period and a second time period; within the first time period, N - 1 first switches in N - 1 first capacitor shunting sub - units are closed, N - 1 second switches and N - 1 third switches are open, the fourth switch and the sixth switch in the second capacitor shunting sub - unit are closed, and the fifth switch is open, so that N - 1 first capacitors are in series, the second capacitor and the power inductor are in parallel. When N - 1 first capacitors are in series and the second capacitor and the power inductor are in parallel, the N - 1 first capacitors are in a discharging state, and the voltage at the first end of the power inductor rises, so that the power inductor is in a magnetizing state and the potential difference across the power inductor is positive; within the second time period, N - 1 first switches in N - 1 first capacitor shunting sub - units are open, N - 1 second switches and N - 1 third switches are closed, the fourth switch and the sixth switch in the second capacitor shunting sub - unit are open, and the fifth switch is closed, so that N - 1 first capacitors are in parallel, the second capacitor and the power inductor are in series. When N - 1 first capacitors are in parallel and the second capacitor and the power inductor are in series, the N - 1 first capacitors are in a charging state, and the voltage at the first end of the power inductor drops, so that the power inductor is in a demagnetizing state and the potential difference across the power inductor is negative, wherein, through the first capacitors in N - 1 first capacitor shunting sub - units, the switching between the charging and discharging states within the first time period and the second time period enables the average inductor current of the power inductor to be reduced to the first current.

[0010] According to an embodiment of the present invention, M cascaded capacitor boosting units include a first capacitor boosting sub - unit and M - 1 second capacitor boosting sub - units; the first end of the first capacitor boosting unit is electrically connected to the series - parallel switching capacitor current - reducing module, the second end of the first capacitor boosting unit is electrically connected to the first end of the (M - 1)th second capacitor boosting sub - unit, the third end of the first capacitor boosting unit is electrically connected to the power inductor; the first end of the mth second capacitor boosting sub - unit is electrically connected to the second end of the (m + 1)th second capacitor boosting sub - unit, the second end of the mth second capacitor boosting sub - unit is electrically connected to the first end of the (m - 1)th second capacitor boosting sub - unit, the third end of the mth second capacitor boosting sub - unit is grounded, the fourth end of the mth second capacitor boosting sub - unit is electrically connected to the power inductor, wherein, the first end of the (M - 1)th second capacitor boosting sub - unit is electrically connected to the second end of the first capacitor boosting unit, the second end of the first second capacitor boosting sub - unit is electrically connected to the output terminal, 2 ≤ m ≤ M - 1.

[0011] According to an embodiment of the present invention, the first capacitor boost sub-unit includes a seventh switch, an eighth switch and a third capacitor, and the m-th second capacitor boost sub-unit includes a ninth switch, a tenth switch, a fourth capacitor and a fifth capacitor; the first end of the seventh switch of the first capacitor boost sub-unit is electrically connected to the series-parallel switched capacitor current reduction module, and the second end of the seventh switch is electrically connected to the first end of the third capacitor; the first end of the eighth switch of the first capacitor boost sub-unit is electrically connected to the first end of the third capacitor, and the second end of the eighth switch is electrically connected to the fourth capacitor of the (M-1)-th second capacitor boost sub-unit; the second end of the third capacitor of the first capacitor boost sub-unit is electrically connected to the power inductor; the first end of the ninth switch in the m-th second capacitor boost sub-unit is electrically connected to the first end of the fourth capacitor, and the second end of the ninth switch is electrically connected to the first end of the tenth switch; the first end of the tenth switch in the m-th second capacitor boost sub-unit is electrically connected to the first end of the fifth capacitor, and the second end of the tenth switch is electrically connected to the first end of the ninth switch in the (m-1)-th second capacitor boost sub-unit; the second end of the fourth capacitor in the m-th second capacitor boost sub-unit is grounded, and the second end of the fifth capacitor is electrically connected to the power inductor.

[0012] According to an embodiment of the present invention, the circuit includes: in the first time period, the seventh switch in the first capacitor boost sub-unit is turned off, the eighth switch is turned on, the M-1 ninth switches in the M-1 second capacitor boost sub-units are turned off, the M-1 tenth switches are turned on, the third capacitor in the first capacitor boost sub-unit is in series with the fourth capacitor in the (M-1)-th second capacitor boost sub-unit, and the fifth capacitor in the m-th second capacitor boost sub-unit is in series with the fourth capacitor in the (m-1)-th second capacitor boost sub-unit. Based on the potential difference across the power inductor being positive, the third capacitor charges the fourth capacitor in the (M-1)-th second capacitor boost sub-unit, and the fifth capacitor in the m-th second capacitor boost sub-unit charges the fourth capacitor in the (m-1)-th second capacitor boost sub-unit, so as to boost the input voltage and output the target voltage; in the second time period, the seventh switch in the first capacitor boost sub-unit is turned on, the eighth switch is turned off, the M-1 ninth switches in the M-1 second capacitor boost sub-units are turned on, the M-1 tenth switches are turned off, the third capacitor in the first capacitor boost sub-unit is in parallel with the fourth and fifth capacitors in the m-th second capacitor boost sub-unit, and the fourth capacitor in the m-th second capacitor boost sub-unit is in series with the fifth capacitor in the m-th second capacitor boost sub-unit. Based on the potential difference across the power inductor being negative, the fourth capacitor in the m-th second capacitor boost sub-unit charges the fifth capacitor in the m-th second capacitor boost sub-unit.

[0013] According to an embodiment of the present invention, the circuit further includes a seventh capacitor; a first end of the seventh capacitor is electrically connected to the output terminal, and a second end of the seventh capacitor is grounded. When the potential difference across the power inductor is positive, the fifth capacitor in the first second-capacitor boosting sub-unit charges the seventh capacitor; when the potential difference across the power inductor is negative, the seventh capacitor discharges to the output terminal to facilitate maintaining the target voltage.

[0014] A second aspect of the present invention provides a DC voltage conversion method, including: an input power supply module sends an input voltage to a series-parallel switched-capacitor current reduction module; the series-parallel switched-capacitor current reduction module boosts the input voltage to obtain a potential difference across the power inductor, where during a first period, the potential difference across the power inductor is positive, and during a second period, the potential difference across the power inductor is negative; based on the potential difference across the power inductor, a stacked switched-capacitor module boosts the input voltage to output a target voltage.

[0015] According to the DC voltage conversion circuit and conversion method of the present invention, a DC voltage conversion circuit is formed by adopting a series-parallel switched-capacitor current reduction module and a stacked switched-capacitor module. The series-parallel switched-capacitor current reduction module includes a power inductor and N cascaded capacitor current reduction units, and the stacked switched-capacitor module includes M cascaded capacitor boosting units. The input power supply module powers the circuit, controls the charge and discharge states of the N capacitor current reduction units in the series-parallel switched-capacitor current reduction module, so that the voltage at the first end of the power inductor changes, thereby changing the magnetization and demagnetization states of the power inductor, and regulating the positive and negative of the potential difference across the power inductor. In response to the positive and negative of the potential difference across the power inductor, alternately control the charge and discharge states of the M capacitor boosting units, so that the voltages of each capacitor boosting unit are stacked step by step, achieving the effect of boosting the input voltage, obtaining an output voltage that meets a high conversion ratio, realizing efficient amplification of the input voltage, and reducing the duty cycle of the circuit in the case of a high voltage conversion ratio, thereby increasing the equivalent conduction time of the circuit and reducing the difficulty of circuit design, control, and drive.

[0016] According to an embodiment of the present invention, further, through N capacitor current reduction units electrically connected to the power inductor, a current path other than the power inductor can be provided for the current, so that the power inductor does not need to bear all the input current and input charge input at the input end, the average inductor current flowing through the power inductor in each switching cycle can be reduced, the conduction loss of the power inductor can be reduced, and the power conversion efficiency can be improved. Thus, a power inductor with a small size and a large on-resistance can be adopted in the DC voltage conversion circuit while keeping the inductor conduction loss constant, so as to improve the power density of the DC voltage conversion circuit and reduce the circuit cost. By alternately controlling the charging and discharging states of M capacitor boosting units cascaded in the stacked switch capacitor module, the breakdown voltage of the switches inside the M capacitor boosting units can be reduced during the process of efficient voltage conversion, so that low-breakdown-voltage and high-quality-factor switches can be used in the DC voltage conversion circuit, and the power-voltage conversion efficiency of the DC voltage conversion circuit can be further improved. At the same time, through the DC voltage conversion circuit of the present invention, even when achieving the same voltage conversion ratio, the present invention also has a lower duty cycle, so that the equivalent on-time of the circuit of the present invention is longer, and the circuit is easier to control and drive. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above content and other objects, features, and advantages of the present invention will become clearer through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0018] Figure 1 FIG. shows a schematic structural diagram of a DC voltage conversion circuit according to an embodiment of the present invention.

[0019] Figure 2 FIG. shows a schematic structural diagram of a series-parallel switch capacitor current reduction module according to an embodiment of the present invention.

[0020] Figure 3 FIG. shows a schematic structural diagram of an equivalent circuit of a stacked switch capacitor module in a second time period according to an embodiment of the present invention.

[0021] Figure 4 FIG. shows a schematic structural diagram of an equivalent circuit of a stacked switch capacitor module in a first time period according to an embodiment of the present invention.

[0022] Figure 5 FIG. shows a schematic structural diagram of a stacked switch capacitor module according to an embodiment of the present invention.

[0023] Figure 6 FIG. shows a schematic structural diagram of a DC voltage conversion circuit including a seventh capacitor according to an embodiment of the present invention.

[0024] Figure 7Shows a schematic structural diagram of a DC voltage conversion circuit including a seventh capacitor in the case of multiplexing a second capacitor shunt sub-unit and a first capacitor boost sub-unit according to an embodiment of the present invention.

[0025] Figure 8 Shows a schematic structural diagram of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor boost units according to an embodiment of the present invention.

[0026] Figure 9 Shows a schematic structural diagram of an equivalent circuit of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor boost units according to an embodiment of the present invention during a first period.

[0027] Figure 10 Shows a schematic structural diagram of an equivalent circuit of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor boost units according to an embodiment of the present invention during a second period.

[0028] Figure 11 Shows a schematic diagram of the ratio of the average inductor current to the average input current of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor boost units according to an embodiment of the present invention and a prior art circuit under a voltage input of 2.5 - 5V and a voltage output of 70V.

[0029] Figure 12 Shows a schematic diagram of the relationship between the voltage conversion ratio and the duty cycle obtained by a DC voltage conversion circuit including three capacitor current reduction units and three capacitor boost units according to an embodiment of the present invention and a prior art circuit under a voltage input of 2.5 - 5V and a voltage output of 70V.

[0030] Figure 13 Shows a waveform diagram of the operating states of a power inductor, inductor current, and inductor voltage of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor boost units according to an embodiment of the present invention within multiple switching cycles.

[0031] Figure 14 Shows a schematic structural diagram of the entire circuit of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor boost units according to an embodiment of the present invention.

[0032] Figure 15 Shows a flowchart of a DC voltage conversion method according to an embodiment of the present invention. Detailed implementation manners

[0033] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In the following detailed description, for the sake of explanation, numerous specific details are set forth to provide a comprehensive understanding of the embodiments of the present invention. However, it is obvious that one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present invention.

[0034] The terms used herein are merely for describing specific embodiments and are not intended to limit the present invention. The terms "comprising", "including" and the like used herein indicate the presence of the described features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0035] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having meanings consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0036] In cases where expressions similar to "at least one of A, B, and C, etc." are used, generally, it should be interpreted according to the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include, but not be limited to, a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0037] In the technical solution of the present invention, the user information involved (including but not limited to user personal information, user image information, user device information, such as location information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) are all information and data authorized by the user or fully authorized by all parties. Moreover, the processing of relevant data, such as collection, storage, use, processing, transmission, provision, invention, and application, all comply with relevant laws, regulations and standards, take necessary confidentiality measures, do not violate public order and good customs, and provide corresponding operation entrances for users to choose to authorize or reject.

[0038] Since the DC voltage conversion circuit can convert a small input voltage into a large output voltage, the DC voltage conversion circuit is widely used in fields such as light-emitting diode driving, optical modules, and micro-robots to provide a high-voltage bias for them. Due to the problems of low conversion efficiency, low power density, and short conduction time in traditional boost DC-DC converters, a hybrid topology DC-DC converter is proposed based on this. The hybrid topology DC-DC converter reduces the withstand voltage of the switching tube and the average current of the inductor by introducing flying capacitors, so that low-withstand-voltage switching tubes with high quality factors can be used and the dependence on large-size high-performance inductors can be reduced.

[0039] However, the hybrid topology DC-DC converter with flying capacitors still has technical problems such as relatively high average inductor current and withstand voltage value of the switching tube, and low power conversion efficiency. During the R & D process, it is found that the voltage conversion ratio of the existing DC voltage conversion circuit is low, the power conversion efficiency is poor, and due to the relatively high average inductor current and switching tube voltage of the DC voltage conversion circuit, it is necessary to use large-size, low-loss inductors and high-withstand-voltage switching tubes, resulting in low power density and high cost of the DC voltage conversion circuit.

[0040] In view of this, an embodiment of the present invention provides a DC voltage conversion circuit, including: a series-parallel switched-capacitor current reduction module, a stacked switched-capacitor module; wherein, the series-parallel switched-capacitor current reduction module is electrically connected to the input power supply module, and the series-parallel switched-capacitor current reduction module includes a power inductor and N cascaded capacitor current reduction units, and the series-parallel switched-capacitor current reduction module is used to control the charging and discharging states of the N capacitor current reduction units to regulate the potential difference across the power inductor, N≥2, and N is an integer; the stacked switched-capacitor module is electrically connected to the series-parallel switched-capacitor current reduction module, and the stacked switched-capacitor module includes M cascaded capacitor boosting units, and the stacked switched-capacitor module is used to alternately control the charging and discharging states of two adjacent capacitor boosting units based on the potential difference across the power inductor to boost the input voltage and output the target voltage, M≥2, and M is an integer.

[0041] Figure 1 The structural schematic diagram of the DC voltage conversion circuit according to an embodiment of the present invention is shown.

[0042] As Figure 1 shown, the DC voltage conversion circuit of this embodiment may include a series-parallel switched-capacitor current reduction module 101 and a stacked switched-capacitor module 102, V IN can be the input voltage input by the input power supply module, V O can be the output voltage.

[0043] According to an embodiment of the present invention, the series-parallel switched-capacitor current reduction module 101 is electrically connected to the input power module. The series-parallel switched-capacitor current reduction module 101 includes a power inductor and N cascaded capacitor current reduction units. The series-parallel switched-capacitor current reduction module 101 is configured to control the charging and discharging states of the N capacitor current reduction units to regulate the potential difference across the power inductor, so as to reduce the average inductor current of the power inductor to a first current, where N≥2 and N is an integer.

[0044] According to an embodiment of the present invention, the first ends of the N cascaded capacitor current reduction units are electrically connected to the input power module, the second ends of the N cascaded capacitor current reduction units are electrically connected to the first end of the power inductor, and the second end of the power inductor is grounded.

[0045] According to an embodiment of the present invention, the capacitor current reduction unit can be characterized as a circuit unit for assisting in reducing the average inductor current of the power inductor. By controlling multiple circuit switches inside the series-parallel switched-capacitor current reduction module 101, the connection state between the internal circuit devices of the N capacitor current reduction units and the power inductor and the charging and discharging states of the N capacitor current reduction units can be switched, so that the N capacitor current reduction units can copy and multiply the charge flowing through the power inductor, providing a current path other than the power inductor at the input end, so that the power inductor does not need to bear all the input current and input charge, thereby reducing the average inductor current flowing through the power inductor in each switching cycle.

[0046] According to an embodiment of the present invention, further, by switching the connection state between the internal circuit devices of the N capacitor current reduction units and the power inductor and the charging and discharging states of the N capacitor current reduction units, the power inductor is switched between the magnetizing state and the demagnetizing state to regulate the positive and negative of the potential difference across the power inductor.

[0047] According to an embodiment of the present invention, the stacked switched-capacitor module 102 is electrically connected to the series-parallel switched-capacitor current reduction module 101. The stacked switched-capacitor module 102 includes M cascaded capacitor boosting units. The stacked switched-capacitor module 102 is configured to alternately control the charging and discharging states of the M capacitor boosting units based on the potential difference across the power inductor to boost the input voltage and output a target voltage, where M≥2 and M is an integer.

[0048] According to an embodiment of the present invention, the capacitor boosting unit can be characterized as a circuit unit for boosting the input voltage. By alternately turning on and off the circuit devices in the M capacitor boosting units, the voltage value between the input end and the output end of the stacked switched-capacitor module 102 can be evenly divided, so that the withstand voltage values of some circuit devices in the M capacitor boosting units are reduced.

[0049] According to an embodiment of the present invention, a DC voltage conversion circuit is constituted by adopting a series-parallel switched-capacitor current-reducing module and a stacked switched-capacitor module. The series-parallel switched-capacitor current-reducing module includes a power inductor and N cascaded capacitor current-reducing units, and the stacked switched-capacitor module includes M cascaded capacitor boosting units. The input power supply module is used to supply power to the circuit, and the charging and discharging states of the N capacitor current-reducing units in the series-parallel switched-capacitor current-reducing module are controlled, so that the voltage at the first end of the power inductor changes, thereby changing the magnetization and demagnetization states of the power inductor, and regulating the positive and negative of the potential difference across the power inductor. In response to the positive and negative of the potential difference across the power inductor, the charging and discharging states of the M cascaded capacitor boosting units are alternately controlled, so that the voltage of each capacitor boosting unit is stacked step by step, achieving the effect of boosting the input voltage, obtaining an output voltage that meets a high conversion ratio, realizing efficient amplification of the input voltage, reducing the duty cycle of the circuit in the case of a high voltage conversion ratio, thereby increasing the equivalent conduction time of the circuit, and reducing the difficulty of circuit design, control, and drive.

[0050] According to an embodiment of the present invention, further, the N capacitor current-reducing units electrically connected to the power inductor can provide a current path for the current in addition to the power inductor, so that the power inductor does not need to bear all the input current and input charge input at the input end, which can reduce the average inductor current flowing through the power inductor in each switching cycle, reduce the conduction loss of the power inductor, improve the power conversion efficiency, and thus a small-size power inductor can be adopted in the DC voltage conversion circuit to improve the power density of the DC voltage conversion circuit and reduce the circuit cost. By alternately controlling the charging and discharging states of the M cascaded capacitor boosting units in the stacked switched-capacitor module, the withstand voltage value of the circuit devices inside the M capacitor boosting units can be reduced during the process of efficient voltage conversion, so that low-withstand-voltage and high-quality-factor switches can be used in the DC voltage conversion circuit, further improving the power-voltage conversion efficiency of the DC voltage conversion circuit. At the same time, through the DC voltage conversion circuit of the present invention, even when achieving the same voltage conversion ratio, the present invention has a lower duty cycle, so that the equivalent conduction time of the circuit of the present invention is longer, and the circuit is easier to control and drive.

[0051] According to an embodiment of the present invention, during the conversion period of using the DC voltage conversion circuit to perform a boosting conversion on the input voltage, each conversion period may include a first time period and a second time period. By switching the working state of the circuit within the first time period and the second time period, the DC voltage conversion circuit can complete the conversion of the input voltage to obtain a highly converted output voltage.

[0052] According to an embodiment of the present invention, the cascaded N capacitor current-reducing units include N - 1 first capacitor shunt sub-units and a second capacitor shunt sub-unit.

[0053] According to an embodiment of the present invention, the first ends of N-1 first capacitor shunt sub-units are electrically connected to an input power supply module, and the second ends of the N-1 first capacitor shunt sub-units are electrically connected to the first end of a second capacitor shunt sub-unit.

[0054] According to an embodiment of the present invention, the second end of the second capacitor shunt sub-unit is electrically connected to the first end of a power inductor, and the third end of the second capacitor shunt sub-unit is electrically connected to a stacked switched capacitor module.

[0055] According to an embodiment of the present invention, the cascaded N capacitor current reduction units can be characterized as units including N capacitors and 3N switches. The N-1 first capacitor shunt sub-units include N-1 capacitors and 3N-3 switches, and the second capacitor shunt sub-unit includes one capacitor and three switches.

[0056] According to an embodiment of the present invention, by setting the N-1 first capacitor shunt sub-units and the second capacitor shunt sub-unit, the N-1 first capacitor shunt sub-units can copy or multiply the charge flowing through the inductor in different charge and discharge states, so as to provide a current path other than the inductor for the inductor at the input end, thereby reducing the average inductor current flowing through the inductor in one cycle. Thus, an inductor with a small size but a large conduction loss characteristic (large on-resistance) can be used to improve the power density and power conversion efficiency of the circuit while achieving the target conversion ratio.

[0057] According to an embodiment of the present invention, the cascaded N capacitor current reduction units can include 3N switches and N capacitors.

[0058] According to an embodiment of the present invention, the nth first capacitor shunt sub-unit among the N-1 first capacitor shunt sub-units includes a first switch, a second switch, a third switch, and a first capacitor, where n≥1.

[0059] According to an embodiment of the present invention, the first end of the first switch of the nth first capacitor shunt sub-unit is electrically connected to the first end of the first capacitor of the (n + 1)th first capacitor shunt sub-unit, and the second end of the first switch is electrically connected to the second end of the first capacitor. Among them, the first end of the first switch of the (N-1)th first capacitor shunt sub-unit is electrically connected to the input power supply module.

[0060] According to an embodiment of the present invention, the first end of the second switch of the nth first capacitor shunt sub-unit is electrically connected to the input power supply module, and the second end of the second switch is electrically connected to the first end of the first capacitor.

[0061] According to an embodiment of the present invention, the first end of the third switch of the nth first capacitor shunt sub-unit is electrically connected to the second end of the first capacitor, and the second end of the third switch is grounded.

[0062] According to an embodiment of the present invention, the second capacitor shunt sub-unit includes a fourth switch, a fifth switch, a sixth switch, and a second capacitor.

[0063] According to an embodiment of the present invention, the first end of the fourth switch of the second capacitor shunt sub-unit is electrically connected to the first end of the first capacitor in the first first capacitor shunt sub-unit, and the second end of the fourth switch is electrically connected to the second end of the second capacitor.

[0064] According to an embodiment of the present invention, the first end of the fifth switch of the second capacitor shunt sub-unit is electrically connected to the input power supply module, and the second end of the fifth switch is electrically connected to the first end of the second capacitor.

[0065] According to an embodiment of the present invention, the first end of the sixth switch of the second capacitor shunt sub-unit is electrically connected to the first end of the second capacitor, and the second end of the sixth switch is electrically connected to the stacked switch capacitor module.

[0066] According to an embodiment of the present invention, the first end of the second capacitor of the second capacitor shunt sub-unit is electrically connected to the second end of the fifth switch, and the second end of the second capacitor is electrically connected to the first end of the power inductor.

[0067] Figure 2 The structural schematic diagram of the series-parallel switch capacitor current-dropping module according to an embodiment of the present invention is shown.

[0068] As Figure 2 shown, the series-parallel switch capacitor current-dropping module includes N-1 first capacitor shunt sub-units 201, a second capacitor shunt sub-unit 202, and a power inductor L. The N-1 first capacitor shunt sub-units 201 include 3N-3 switches and N-1 capacitors, and the second capacitor shunt sub-unit 202 includes 3 switches and 1 capacitor. The negative pole of the input power supply module is grounded to GND, and the positive pole of the input power supply module is electrically connected to the first ends of the first switch S 3N-2 and the second switch S 3N-1 of the (N-1)th first capacitor shunt sub-unit. The second end of the first switch S 3N-2 of the (N-1)th first capacitor shunt sub-unit is electrically connected to the second end of the first capacitor C FN of the (N-1)th first capacitor shunt sub-unit. The second end of the second switch S 3N-1 of the (N-1)th first capacitor shunt sub-unit is electrically connected to the first end of the first capacitor C FN of the (N-1)th first capacitor shunt sub-unit. The second end of the first capacitor C FN of the (N-1)th first capacitor shunt sub-unit is electrically connected to the first end of the third switch S 3N of the (N-1)th first capacitor shunt sub-unit. The second end of the third switch S 3N of the (N-1)th first capacitor shunt sub-unit is grounded to GND.

[0069] According to an embodiment of the present invention, based on the above connection method, the (N - 2)nd to the 3rd first capacitor shunt sub-units are all connected in the same way as the (N - 1)st first capacitor shunt sub-unit.

[0070] According to an embodiment of the present invention, the first switch S7 of the 2nd first capacitor shunt sub-unit is electrically connected to the first end of the first capacitor C of the 3rd first capacitor shunt sub-unit. F4 The second end of the first switch S7 of the 2nd first capacitor shunt sub-unit is electrically connected to the second end of the first capacitor C of the 2nd first capacitor shunt sub-unit. F3 The first end of the second switch S8 of the 2nd first capacitor shunt sub-unit is electrically connected to the positive pole of the input power supply module. The second end of the second switch S8 of the 2nd first capacitor shunt sub-unit is electrically connected to the first end of the first capacitor C of the 2nd first capacitor shunt sub-unit. F3 The second end of the first capacitor C of the 2nd first capacitor shunt sub-unit is electrically connected to the first end of the third switch S9 of the 2nd first capacitor shunt sub-unit. The second end of the third switch S9 of the 2nd first capacitor shunt sub-unit is grounded. F3

[0071] According to an embodiment of the present invention, the first switch S4 of the 1st first capacitor shunt sub-unit is electrically connected to the first end of the first capacitor C of the 2nd first capacitor shunt sub-unit. F3 The second end of the first switch S4 of the 1st first capacitor shunt sub-unit is electrically connected to the second end of the first capacitor C of the 1st first capacitor shunt sub-unit. F2 The first end of the second switch S5 of the 1st first capacitor shunt sub-unit is electrically connected to the positive pole of the input power supply module. The second end of the second switch S5 of the 1st first capacitor shunt sub-unit is electrically connected to the first end of the first capacitor C of the 1st first capacitor shunt sub-unit. F2 The second end of the first capacitor C of the 1st first capacitor shunt sub-unit is electrically connected to the first end of the third switch S6 of the 1st first capacitor shunt sub-unit. The second end of the third switch S6 of the 1st first capacitor shunt sub-unit is grounded. F2

[0072] According to an embodiment of the present invention, the first end of the fourth switch S1 of the second capacitor shunt sub-unit 202 is electrically connected to the first end of the first capacitor C of the 1st first capacitor shunt sub-unit. F2 The second end of the fourth switch S1 of the second capacitor shunt sub-unit 202 is electrically connected to the second end of the second capacitor C of the second capacitor shunt sub-unit 202. F1 The first end of the fifth switch S2 is electrically connected to the positive pole of the input power supply module. The second end of the fifth switch S2 is electrically connected to the second capacitor C. F1 ​​is electrically connected to the first end, the first end of the sixth switch S3 is electrically connected to the first end of the second capacitor C F1 is electrically connected to the first end, the second end of the sixth switch S3 is electrically connected to the stacked switched capacitor module, and the second end of the second capacitor C F1 is electrically connected to the first end of the power inductor L, and the second end of the power inductor L is grounded.

[0073] According to an embodiment of the present invention, during the conversion period of increasing the input voltage by using the DC voltage conversion circuit, each conversion period and switching period may include a first period and a second period. By switching the working state of the circuit within the first period and the second period, the DC voltage conversion circuit can complete the conversion of the input voltage to obtain a high-conversion output voltage.

[0074] According to an embodiment of the present invention, within the first period, N - 1 first switches in the N - 1 first capacitor shunting sub-units are closed, the N - 1 second switches and the N - 1 third switches are opened, the fourth switch and the sixth switch of the second capacitor shunting sub-unit are closed, and the fifth switch is opened, so that the N - 1 first capacitors are connected in series, the second capacitor and the power inductor are connected in parallel. When the N - 1 first capacitors are connected in series and the second capacitor and the power inductor are connected in parallel, the N - 1 first capacitors are in a discharging state, the voltage at the first end of the power inductor rises, so that the power inductor is in a magnetizing state and the potential difference across the power inductor is positive.

[0075] According to an embodiment of the present invention, within the first period, the combination of the N - 1 first capacitors in the N - 1 first capacitor shunting sub-units is connected in series with the parallel connection of the second capacitor and the power inductor. The N - 1 first capacitors and the second capacitor are both in a discharging state. The N - 1 first capacitors discharge the charge accumulated in the second period to the power inductor within the first period, so that the power inductor is in a magnetizing state, and the voltage at the first end of the power inductor rises to N V IN , and then the potential difference across the power inductor is positive. In combination with the second period, the N - 1 first capacitors are connected in parallel with the power inductor, and the second capacitor helps the power inductor share the charge to reduce the current flowing through the power inductor, achieving the effect of reducing the average inductor current of the power inductor within one cycle. At the same time, the N - 1 first capacitors can also discharge the charge accumulated in the second period to the second capacitor within the first period, and jointly transfer and output the charge to the stacked switched capacitor module in combination with the discharging second capacitor.

[0076] According to an embodiment of the present invention, during the second time period, N - 1 first switches in N - 1 first capacitor shunt sub - units are turned off, N - 1 second switches and N - 1 third switches are closed, the fourth switch and the sixth switch of the second capacitor shunt sub - unit are turned off, and the fifth switch is closed, so that N - 1 first capacitors are connected in parallel, the second capacitor and the power inductor are connected in series. When N - 1 first capacitors are connected in parallel and the second capacitor and the power inductor are connected in series, the N - 1 first capacitors are in a charging state, and the voltage at the first end of the power inductor drops, so that the power inductor is in a demagnetization state and the potential difference across the power inductor is negative. Among them, through the first capacitor in the N - 1 first capacitor shunt sub - units, the switching of the charge - discharge state during the first time period and the second time period is used to reduce the average inductance current of the power inductor to the first current.

[0077] According to an embodiment of the present invention, during the second time period, the combination of N - 1 first capacitors in N - 1 first capacitor shunt sub - units is connected in parallel with the combination of the second capacitor and the power inductor in parallel. The N - 1 first capacitors and the second capacitor are both in a charging state. The N - 1 first capacitors are used to accumulate charges during the second time period for discharging during the first time period. The potential difference across the power inductor is negative, the power inductor is in a demagnetization state, and since the N - 1 first capacitors are all connected in parallel with the power inductor, the charge flowing through the power inductor is reduced, achieving the effect of reducing the average inductance current of the power inductor in one cycle.

[0078] Figure 3 The schematic structural diagram of the equivalent circuit of the series - parallel switched - capacitor current - reducing module according to an embodiment of the present invention during the second time period is shown.

[0079] As Figure 3 shown, the series - parallel switched - capacitor current - reducing module includes N - 1 first capacitor shunt sub - units 201, a second capacitor shunt sub - unit 202 and a power inductor L. The N - 1 first capacitor shunt sub - units 201 include 3N - 3 switches and N - 1 capacitors, and the second capacitor shunt sub - unit 202 includes 3 switches and 1 capacitor. During the second time period, N - 1 first switches are turned off, N - 1 second switches and N - 1 third switches are closed, the fourth switch and the sixth switch are turned off, and the fifth switch is closed. The first capacitor C FN 、··· The first capacitor C F3 、The first capacitor C F2 are connected in parallel with the second capacitor C F1 and the power inductor L, and the input power supply V IN powers the capacitors and the inductor. The charges accumulated by the parallel - connected first capacitor C FN 、··· The first capacitor C F3 、The first capacitor C F2 during the second time period are equal, that is, Q F2 = Q F3= ··· = Q FN , the second capacitor C F1 The accumulated charge is equal to the charge released by the power inductor L, and both are the third charge. The third charge can be expressed according to formula (1).

[0080] Q L2 = I LA ·(1 - D)T (1);

[0081] Among them, Q L2 can be characterized as the third charge, that is, the charge flowing through the power inductor L during the second period. I LA can be characterized as the current of the power inductor L during the first period, D can be characterized as the duty cycle, and T can be characterized as the period.

[0082] Figure 4 Shows a schematic structural diagram of the equivalent circuit of the series - parallel switched - capacitor current - reducing module according to an embodiment of the present invention during the first period.

[0083] As Figure 4 shown, the series - parallel switched - capacitor current - reducing module includes N - 1 first capacitor shunt sub - units 201, a second capacitor shunt sub - unit 202 and a power inductor L. The N - 1 first capacitor shunt sub - units 201 include 3N - 3 switches and N - 1 capacitors, and the second capacitor shunt sub - unit 202 includes 3 switches and 1 capacitor. During the first period, N - 1 first switches are closed, N - 1 second switches and N - 1 third switches are open, the fourth switch and the sixth switch are closed, and the fifth switch is open. The first capacitor C FN , ··· the first capacitor C F3 , the first capacitor C F2 are in series, the second capacitor C F1 is in parallel with the power inductor L, the input power supply V IN supplies power to the capacitors and the inductor. The charge flowing through the power inductor L during the first period is the second charge, and the second charge can be expressed according to formula (2). The series - connected first capacitor C FN , ··· the first capacitor C F3 , the first capacitor C F2 release equal charges during the first period, and both are the first charge. The first charge can be expressed according to formula (3). The voltage of the first end V SWL of the power inductor L rises to N V IN , and the charge released by the second capacitor C F1 is Q CF1 .

[0084] Q L1 = I LA ·DT (2);

[0085] Among them, Q L1 can be characterized as the charge flowing through the power inductor L during the first period, that is, the second charge, and D can be characterized as the duty cycle.

[0086] Q CF2 = Q CF3 =···= Q CFN =I LA ·T (3);

[0087] Among them, Q CF2 can be characterized as the charge released by the first capacitor C F2 Q CF3 can be characterized as the charge released by the first capacitor C F3 Q CFN can be characterized as the charge released by the first capacitor C FN Q LA ·T can be characterized as the first charge. Thus, it can be seen from formulas (1) and (2) that the capacitors C F2 to C FN can copy the charge flowing through the power inductor in one period.

[0088] According to an embodiment of the present invention, according to the number N of capacitors in the series-parallel switched-capacitor current-dropping module, the charge amount of the power inductor in the first period, and the charge amount of the power inductor in the second period, it can be obtained that in one period, the average inductor current in the series-parallel switched-capacitor current-dropping module can be reduced to a first current, and a first relationship is satisfied between the average inductor current and the input current, and the first relationship can be expressed according to formula (4).

[0089] (4);

[0090] Among them, I LA can be characterized as the first current, that is, when the second end of the series-parallel switched-capacitor current-dropping module is electrically connected to the output end, the voltage output by the series-parallel switched-capacitor current-dropping module, and I INN can be characterized as the input current input to the series-parallel switched-capacitor current-dropping module, and N can be characterized as the number of capacitors included in the series-parallel switched-capacitor current-dropping module.

[0091] According to an embodiment of the present invention, by controlling the on / off states of the first switch, the second switch, and the third switch in N-1 first capacitor shunt sub-units and the on / off states of the fourth switch, the fifth switch, and the sixth switch in the second capacitor shunt sub-unit respectively within the first time period and the second time period, the capacitors and inductors in the series-parallel switched-capacitor current reduction module are switched between series-parallel states and charge-discharge states, so that the charge flowing through the power inductor can be replicated and multiplied by the first capacitor, and the average inductor current can be reduced to the first current when satisfying the first relationship. From formula (4), the average inductor current is always less than 1 / N of the input average current, and the inductor conduction loss is reduced by N 2 times compared with the traditional boost converter. Therefore, a power inductor with a small size and a large on-resistance can be adopted in the DC voltage conversion circuit while maintaining a certain inductor conduction loss. At the same time, by switching the capacitors and inductors in the series-parallel switched-capacitor current reduction module between series-parallel states and charge-discharge states, the potential difference across the power inductor is regulated, so that the stacked switched-capacitor module can control the circuit devices in the stacked switched-capacitor module according to the potential difference across the power inductor, and amplify the input voltage to obtain the target voltage.

[0092] According to an embodiment of the present invention, M cascaded capacitor boost units include a first capacitor boost sub-unit and M-1 second capacitor boost sub-units.

[0093] According to an embodiment of the present invention, the first end of the first capacitor boost unit is electrically connected to the series-parallel switched-capacitor current reduction module, the second end of the first capacitor boost unit is electrically connected to the first end of the (M-1)th second capacitor boost sub-unit, and the third end of the first capacitor boost unit is electrically connected to the power inductor.

[0094] According to an embodiment of the present invention, the first end of the mth second capacitor boost sub-unit is electrically connected to the second end of the (m + 1)th second capacitor boost sub-unit, the second end of the mth second capacitor boost sub-unit is electrically connected to the first end of the (m - 1)th second capacitor boost sub-unit, the third end of the mth second capacitor boost sub-unit is grounded, and the fourth end of the mth second capacitor boost sub-unit is electrically connected to the power inductor, where the first end of the (M-1)th second capacitor boost sub-unit is electrically connected to the second end of the first capacitor boost unit, and the second end of the first second capacitor boost sub-unit is electrically connected to the output end, 1 ≤ m ≤ M-1.

[0095] According to an embodiment of the present invention, M cascaded capacitor boost units can be characterized as a unit including 2M-1 capacitors and 2M switches. The (M-1) second capacitor boost sub-units include 2M-2 capacitors and 2M-2 switches, and the first capacitor boost unit includes one capacitor and two switches.

[0096] According to an embodiment of the present invention, by providing a first capacitor boosting sub-unit and M - 1 second capacitor boosting sub-units, in response to the potential difference across the power inductor, the charging and discharging states of the first capacitor boosting sub-unit and the M - 1 second capacitor boosting sub-units can be alternately controlled, so that the charging and discharging state inside the m-th second capacitor boosting sub-unit and the charging and discharging state from the m-th second capacitor boosting sub-unit to the (m + 1)-th second capacitor boosting sub-unit can be utilized, thereby enabling the voltage of the capacitor to be gradually increased, and further enabling the input voltage to be amplified to output a target voltage. Further, the voltage input to the stacked switched capacitor module and the voltage output through the stacked switched capacitor module can be equalized by the capacitor devices in the M - 1 second capacitor boosting sub-units, so as to reduce the voltage withstand of the switching devices in the stacked switched capacitor module. According to an embodiment of the present invention, the first capacitor boosting sub-unit includes a seventh switch, an eighth switch, and a third capacitor, and the m-th second capacitor boosting sub-unit includes a ninth switch, a tenth switch, a fourth capacitor, and a fifth capacitor.

[0097] According to an embodiment of the present invention, the first end of the seventh switch of the first capacitor boosting sub-unit is electrically connected to the series-parallel switched capacitor current reduction module, and the second end of the seventh switch is electrically connected to the first end of the third capacitor.

[0098] According to an embodiment of the present invention, the first end of the eighth switch of the first capacitor boosting sub-unit is electrically connected to the first end of the third capacitor, and the second end of the eighth switch is electrically connected to the fourth capacitor of the (M - 1)-th second capacitor boosting sub-unit.

[0099] According to an embodiment of the present invention, the second end of the third capacitor of the first capacitor boosting sub-unit is electrically connected to the power inductor.

[0100] According to an embodiment of the present invention, since in the first time period, both the seventh switch and the eighth switch are closed, the voltage across the third capacitor is equal in the first time period. Thus, the fifth switch, the sixth switch in the second capacitor shunting sub-unit, the second capacitor, the seventh switch, the eighth switch, and the third capacitor in the first capacitor boosting sub-unit can be reused, thereby reducing the number of capacitors in the circuit.

[0101] According to an embodiment of the present invention, the first end of the ninth switch in the m-th second capacitor boosting sub-unit is electrically connected to the first end of the fourth capacitor, and the second end of the ninth switch is electrically connected to the first end of the tenth switch.

[0102] According to an embodiment of the present invention, the first end of the tenth switch in the m-th second capacitor boosting sub-unit is electrically connected to the first end of the fifth capacitor, and the second end of the tenth switch is electrically connected to the first end of the ninth switch in the (m - 1)-th second capacitor boosting sub-unit.

[0103] According to an embodiment of the present invention, the second terminal of the fourth capacitor in the m-th second capacitor boosting sub-unit is grounded, and the second terminal of the fifth capacitor is electrically connected to the power inductor.

[0104] Figure 5 FIG. shows a schematic structural diagram of a stacked switched capacitor module according to an embodiment of the present invention.

[0105] As Figure 5 shown, the stacked switched capacitor module includes a first capacitor boosting sub-unit 501 and M-1 second capacitor boosting sub-units 502. The first capacitor boosting sub-unit includes a seventh switch, an eighth switch, and a third capacitor. The M-1 second capacitor boosting sub-units include M-1 ninth switches, M-1 tenth switches, M-1 fourth capacitors, and M-1 fifth capacitors. The first terminal of the seventh switch S 2M of the first capacitor boosting sub-unit is electrically connected to the series-parallel switched capacitor current reducing module. The second terminal of the seventh switch S 2M of the first capacitor boosting sub-unit is electrically connected to the first terminal of the third capacitor C F（2M-1） . The first terminal of the eighth switch S 2M-1 is electrically connected to the first terminal of the third capacitor C F（2M-1） . The second terminal of the eighth switch S 2M-1 is electrically connected to the first terminal of the fourth capacitor C F（2M-2） of the (M-1)-th second capacitor boosting sub-unit. The second terminal of the third capacitor C F（2M-1） is electrically connected to the power inductor L in the series-parallel switched capacitor current reducing module.

[0106] According to an embodiment of the present invention, the first terminal of the ninth switch S 2M-2 of the (M-1)-th second capacitor boosting sub-unit is electrically connected to the second terminal of the fourth capacitor C F（2M-2） of the (M-1)-th second capacitor boosting sub-unit. The second terminal of the ninth switch S 2M-2 of the (M-1)-th second capacitor boosting sub-unit is electrically connected to the first terminal of the tenth switch S 2M-3 of the (M-1)-th second capacitor boosting sub-unit. The second terminal of the fourth capacitor C F（2M-2） of the (M-1)-th second capacitor boosting sub-unit is grounded to GND. The first terminal of the tenth switch S 2M-3 of the (M-1)-th second capacitor boosting sub-unit is electrically connected to the first terminal of the fifth capacitor C F（2M-3） of the (M-1)-th second capacitor boosting sub-unit. The second terminal of the tenth switch S 2M-3 of the (M-1)-th second capacitor boosting sub-unit is electrically connected to the first terminal of the ninth switch S 2M-4 of the (M-2)-th second capacitor boosting sub-unit. The second terminal of the fifth capacitor C F（2M-3） of the (M-1)-th second capacitor boosting sub-unit is electrically connected to the power inductor L in the series-parallel switched capacitor current reducing module.

[0107] According to an embodiment of the present invention, based on the above connection method, the (M-2)-th to the 2-nd second capacitor boost sub-units are all connected in the same way as the (M-1)-th second capacitor boost sub-unit.

[0108] According to an embodiment of the present invention, the first end of the ninth switch S2 of the first second capacitor boost sub-unit is electrically connected to the first end of the fourth capacitor C of the first second capacitor boost sub-unit. F（2M-（2M-2）） of the first second capacitor boost sub-unit, and the second end of the ninth switch S 2M-（2M-2） of the first second capacitor boost sub-unit is electrically connected to the first end of the ninth switch S 2M-（2M-2） of the first second capacitor boost sub-unit. The second end of the fourth capacitor C F（2M-（2M-2）） of the first second capacitor boost sub-unit is grounded to GND. The first end of the tenth switch S 2M-（2M-1） of the first second capacitor boost sub-unit is electrically connected to the first end of the fifth capacitor C F（2M-（2M-1）） of the first second capacitor boost sub-unit. The second end of the tenth switch S 2M-（2M-1） of the first second capacitor boost sub-unit is electrically connected to the output terminal. The second end of the fifth capacitor C F（2M-（2M-1）） of the first second capacitor boost sub-unit is electrically connected to the power inductor L in the series-parallel switched-capacitor current reduction module.

[0109] According to an embodiment of the present invention, in the first time period, the seventh switch in the first capacitor boost sub-unit is turned off, the eighth switch is turned on, the (M-1) ninth switches in the (M-1) second capacitor boost sub-units are turned off, and the (M-1) tenth switches are turned on. The third capacitor in the first capacitor boost sub-unit is connected in series with the fourth capacitor in the (M-1)-th second capacitor boost sub-unit, and the fifth capacitor in the m-th second capacitor boost sub-unit is connected in series with the fourth capacitor in the (m-1)-th second capacitor boost sub-unit. Based on the potential difference across the power inductor being positive, the third capacitor charges the fourth capacitor in the (M-1)-th second capacitor boost sub-unit, and the fifth capacitor in the m-th second capacitor boost sub-unit charges the fourth capacitor in the (m-1)-th second capacitor boost sub-unit, so as to boost the input voltage and output the target voltage.

[0110] According to an embodiment of the present invention, in response to the potential difference across the power inductor being positive, during the first period, the third capacitor and the fourth capacitor in the first capacitor boosting sub-unit and the (M - 1)-th second capacitor boosting sub-unit are connected in series. The third capacitor in the first capacitor boosting sub-unit is in a discharging state, and the fourth capacitor in the (M - 1)-th second capacitor boosting sub-unit is in a charging state. The third capacitor in the first capacitor boosting sub-unit discharges to the fourth capacitor in the (M - 1)-th second capacitor boosting sub-unit. The fifth capacitor in the (M - 1)-th second capacitor boosting sub-unit is connected in series with the fourth capacitor in the (M - 2)-th second capacitor boosting sub-unit. The fifth capacitor in the (M - 1)-th second capacitor boosting sub-unit is in a discharging state, and the fourth capacitor in the (M - 2)-th second capacitor boosting sub-unit is in a charging state. The fifth capacitor in the (M - 1)-th second capacitor boosting sub-unit and the fourth capacitor in the (M - 2)-th second capacitor boosting sub-unit discharge.

[0111] According to an embodiment of the present invention, until the fifth capacitor in the second second capacitor boosting sub-unit is connected in series with the fourth capacitor in the first second capacitor boosting sub-unit, the fifth capacitor in the second second capacitor boosting sub-unit is in a discharging state, the fourth capacitor in the first second capacitor boosting sub-unit is in a charging state, the fifth capacitor in the second second capacitor boosting sub-unit and the fourth capacitor in the first second capacitor boosting sub-unit discharge, and the fifth capacitor in the first second capacitor boosting sub-unit is in a discharging state and directly outputs the target voltage to the output terminal.

[0112] According to an embodiment of the present invention, during the second period, the seventh switch in the first capacitor boosting sub-unit is closed, the eighth switch is opened, the (M - 1) ninth switches in the (M - 1) second capacitor boosting sub-units are closed, the (M - 1) tenth switches are opened. The third capacitor in the first capacitor boosting sub-unit is connected in parallel with the fourth capacitor and the fifth capacitor in the m-th second capacitor boosting sub-unit. The fourth capacitor in the m-th second capacitor boosting sub-unit is connected in series with the fifth capacitor in the m-th second capacitor boosting sub-unit. Based on the potential difference across the power inductor being negative, the fourth capacitor in the m-th second capacitor boosting sub-unit charges the fifth capacitor in the m-th second capacitor boosting sub-unit.

[0113] According to an embodiment of the present invention, in response to the potential difference across the power inductor being positive, during the second period, the first capacitor boosting sub-unit is disconnected from the (M - 1)-th second capacitor boosting sub-unit, and the first second capacitor boosting sub-unit is disconnected from the output terminal. The fourth capacitor in the (M - 1)-th second capacitor boosting sub-unit and the fifth capacitor in the (M - 1)-th second capacitor boosting sub-unit are connected in series. The fourth capacitor in the (M - 1)-th second capacitor boosting sub-unit is in a discharging state, and the fifth capacitor in the (M - 1)-th second capacitor boosting sub-unit is in a charging state. The fourth capacitor in the (M - 1)-th second capacitor boosting sub-unit discharges to the fifth capacitor in the (M - 1)-th second capacitor boosting sub-unit. Until the fourth capacitor in the first second capacitor boosting sub-unit and the fifth capacitor in the first second capacitor boosting sub-unit are connected in series, the fourth capacitor in the first second capacitor boosting sub-unit is in a discharging state, the fifth capacitor in the first second capacitor boosting sub-unit is in a charging state, and the fourth capacitor in the first second capacitor boosting sub-unit discharges to the fifth capacitor in the first second capacitor boosting sub-unit.

[0114] According to an embodiment of the present invention, by switching the charging and discharging states of each capacitor in the first capacitor boosting sub-unit and the (M - 1) second capacitor boosting sub-units back and forth during the first period and the second period, the voltage of the capacitor is gradually increased, and thus the input voltage can be amplified to output the target voltage.

[0115] According to an embodiment of the present invention, through the third capacitor, the (M - 1) fourth capacitors, and the (M - 1) fifth capacitors in the stacked switched-capacitor module, the voltage input to the stacked switched-capacitor module and the voltage output through the stacked switched-capacitor module can be evenly divided, so as to reduce the voltage withstand values of the seventh switch, the eighth switch, the (M - 1) ninth switches, and the (M - 1) tenth switches to the first voltage withstand value, and the first voltage withstand value can be represented by formula (5).

[0116] V m =(V OM -V INM ) / M (5);

[0117] Wherein, V m can be characterized as the first voltage withstand value, V OM can be characterized as the voltage output by the stacked switched-capacitor module in the case of only including the stacked switched-capacitor module, that is, the voltage output by the stacked switched-capacitor module when the first end of the first capacitor boosting unit is electrically connected to the positive pole of the input power module, V INM can be characterized as the voltage input to the stacked switched-capacitor module, and M can be characterized as the number of capacitor boosting units in the stacked switched-capacitor module.

[0118] According to an embodiment of the present invention, by responding to the potential difference across the power inductor, the on-off states of the seventh switch and the eighth switch in the first capacitor boost sub-unit and the ninth switch and the tenth switch in M - 1 second capacitor boost sub-units are respectively controlled in the first time period and the second time period, so that the capacitors in the stacked switched-capacitor module are switched between the charging and discharging states, thereby enabling the voltage of the capacitors to be gradually increased, and further enabling the input voltage to be amplified to output the target voltage. At the same time, through the third capacitor, M - 1 fourth capacitors, and M - 1 fifth capacitors, the voltage input to the stacked switched-capacitor module and the voltage output through the stacked switched-capacitor module can be evenly divided, so as to reduce the breakdown voltage of each switch in the stacked switched-capacitor module, and thus low-breakdown-voltage and high-quality-factor switch tube devices can be used to improve the power conversion efficiency of the conversion circuit.

[0119] According to an embodiment of the present invention, the circuit further includes a seventh capacitor. The first end of the seventh capacitor is electrically connected to the output terminal, and the second end of the seventh capacitor is grounded. When the potential difference across the power inductor is positive, the fifth capacitor in the first second capacitor boost sub-unit charges the seventh capacitor; when the potential difference across the power inductor is negative, the seventh capacitor discharges to the output terminal to maintain the target voltage.

[0120] According to an embodiment of the present invention, when the DC voltage conversion circuit includes a series-parallel switched-capacitor current reduction module, a stacked switched-capacitor module, and a seventh capacitor, the average inductor current of the power inductor can be calculated based on the cascaded N capacitor current reduction units, the cascaded M capacitor boost units, the duty cycle, and the input current. The average inductor current can be expressed by formula (6), and the target voltage and the voltage conversion ratio can be calculated based on the cascaded N capacitor current reduction units, the cascaded M capacitor boost units, the duty cycle, and the input voltage. The target voltage and the voltage conversion ratio can be expressed by formula (7).

[0121] (6);

[0122] Wherein, I L can be characterized as the average inductor current of the power inductor in the case where the DC voltage conversion circuit includes a parallel switched-capacitor current reduction module, a stacked switched-capacitor module, and a seventh capacitor, I IN can be characterized as the average input current of the DC voltage conversion circuit in the case where the DC voltage conversion circuit includes a parallel switched-capacitor current reduction module, a stacked switched-capacitor module, and a seventh capacitor, Q L can be characterized as the average inductor charge of the power inductor in the case where the DC voltage conversion circuit includes a parallel switched-capacitor current reduction module, a stacked switched-capacitor module, and a seventh capacitor, Q INIt can be characterized as the input charge of the DC voltage conversion circuit when the DC voltage conversion circuit includes a parallel switched-capacitor current-dropping module, a stacked switched-capacitor module, and a seventh capacitor.

[0123] (7);

[0124] Among them, VCR can be characterized as the voltage conversion ratio, V O It can be characterized as the output voltage, which is the voltage output by the DC voltage conversion circuit when the DC voltage conversion circuit includes a parallel switched-capacitor current-dropping module, a stacked switched-capacitor module, and a seventh capacitor, V IN It can be characterized as the input voltage input by the input power supply module, which is the voltage input by the input power supply module to the circuit when the DC voltage conversion circuit includes a parallel switched-capacitor current-dropping module, a stacked switched-capacitor module, and a seventh capacitor.

[0125] According to an embodiment of the present invention, different numbers of capacitor current-dropping units and capacitor boosting units can be cascaded to make the voltage conversion ratio reach the expected value, and the switch withstand voltage and the average inductor current are further reduced.

[0126] According to an embodiment of the present invention, by increasing the voltage conversion ratio, the equivalent on-time of the switch in the circuit can be equivalently increased. Generally speaking, the equivalent on-time of the present invention can be increased by a multiple similar to the value of the voltage conversion ratio compared with the traditional boost converter, thereby reducing the risk brought by the extremely short on-time to the control and drive circuits and reducing the control difficulty and design difficulty of the circuit.

[0127] Figure 6 The structural schematic diagram of the DC voltage conversion circuit including a seventh capacitor according to an embodiment of the present invention is shown.

[0128] As Figure 6 shown, Figure 6 includes the structure of the series-parallel switched-capacitor current-dropping module 101 as shown in Figure 2 shown and the structure of the stacked switched-capacitor module 102 as shown in Figure 5 shown and the connection manner of its circuit devices. Among them, the first end of the seventh switch S 2M of the first capacitor boosting sub-unit is electrically connected to the second end of the sixth switch S3 of the second capacitor current-sharing sub-unit. The first end of the seventh capacitor C0 is electrically connected to the output end, and the second end of the seventh capacitor C0 is grounded. In the first time period, in response to the potential difference across the power inductor being positive, the fifth capacitor C F（2M-（2M-1））In the discharge state, the target voltage is output to the output terminal, and at the same time, the seventh capacitor C0 is charged. The seventh capacitor C0 is in the charging state. In the second period, in response to the potential difference across the power inductor being negative, the tenth switch S of the first second-capacitor boosting sub-unit 2M-（2M-1） is turned off, and the fifth capacitor C in the first second-capacitor boosting sub-unit F（2M-（2M-1）） is in the charging state and is disconnected from the output terminal. The seventh capacitor C0 is in the discharge state, and the output terminal is powered by the seventh capacitor C0 at this time to maintain the output of the target voltage.

[0129] Figure 7 FIG. shows a schematic structural diagram of a DC voltage conversion circuit including a seventh capacitor in the case of multiplexing a second-capacitor shunting sub-unit and a first-capacitor boosting sub-unit according to an embodiment of the present invention.

[0130] As Figure 7 shown, Figure 7 it includes the structure of the series-parallel switched-capacitor current-dropping module 101 as shown in Figure 2 and the structure of the stacked switched-capacitor module 102 as shown in Figure 5 and the connection manner of its circuit devices, and also includes the connection manner of the seventh capacitor C0 as shown in Figure 6 shown. Among them, the fifth switch S2, the sixth switch S3, and the second capacitor C in the second-capacitor shunting sub-unit F1 and the seventh switch S in the first-capacitor boosting sub-unit 2M , the eighth switch S 2M-1 , and the third capacitor C F（2M-1） are multiplexed. Specifically, by directly connecting the second terminal of the sixth switch S3 in the second-capacitor shunting sub-unit to the first terminal of the fourth capacitor C of the (M-1)th second-capacitor boosting sub-unit F（2M-2） , the seventh switch S 2M , the eighth switch S 2M-1 , and the third capacitor C F（2M-1） in the circuit are cancelled, so that the fifth switch S2 and the seventh switch S 2M are multiplexed, the sixth switch S3 and the eighth switch S 2M-1 are multiplexed, and the second capacitor C F1 and the third capacitor C F（2M-1） are multiplexed. In the first period, the fifth switch S2 (S 2M ) is turned off, the sixth switch S3 (S 2M-1 ) is closed, the second capacitor C F1 (C F(2M-1) ) is in the discharge state, the fourth capacitor C of the (M-1)th second-capacitor boosting sub-unit F（2M-2） is in the charging state, and the second capacitor C F1 (C F(2M-1) ) directly charges the fourth capacitor C of the (M-1)th second-capacitor boosting sub-unitF（2M-2） Charging, during the second period, the fifth switch S2 (S 2M ) is closed, the sixth switch S3 (S 2M-1 ) is open, the second capacitor C F1 (C F(2M-1) ) is in a charging state, so that the voltage drop at the first end of the power inductor L is negative, so that the voltage difference across the power inductor L is negative, and the fourth capacitor C of the (M - 1)-th second-capacitor boost sub-unit F（2M-2） is in a discharging state, the fifth capacitor C of the (M - 1)-th second-capacitor boost sub-unit F（2M-3） is in a charging state, and the fourth capacitor C of the (M - 1)-th second-capacitor boost sub-unit F（2M-2） discharges to the fifth capacitor C of the (M - 1)-th second-capacitor boost sub-unit F（2M-3） .

[0131] According to an embodiment of the present invention, by externally connecting a seventh capacitor to the output end, the seventh capacitor can be charged during the first period and maintain the output of the target voltage at the output end during the second period, so that the continuous output of the target voltage can be maintained within one cycle.

[0132] Figure 8 FIG. shows a schematic structural diagram of a DC voltage conversion circuit including 3 capacitor current reduction units and 3 capacitor boost units according to an embodiment of the present invention.

[0133] As Figure 8 shown,[[]] Figure 8 FIG. shows a DC voltage conversion circuit including 3 capacitor current reduction units 801 and 3 capacitor boost units 801 in the case of multiplexing the second-capacitor shunt sub-unit and the first-capacitor boost sub-unit. This circuit can be applied to high-conversion-ratio boost application scenarios with an input of 2.5 - 5V and an output of 40 - 70V. The 3 capacitor current reduction units 801 include 2 first-capacitor shunt sub-units and a second-capacitor shunt sub-unit (since it has the same structure as the first-capacitor boost sub-unit, this structure is multiplexed and also serves as the first-capacitor boost sub-unit in the 3 capacitor boost units), and the 3 capacitor boost units 802 include a first-capacitor boost sub-unit and 2 second-capacitor boost sub-units.

[0134] According to an embodiment of the present invention, the first end of the first switch S 11 of the second first-capacitor shunt sub-unit is electrically connected to the positive pole of the input power supply module V IN , the second end of the first switch S 11 of the second first-capacitor shunt sub-unit is electrically connected to the second end of the first capacitor C F7 of the second first-capacitor shunt sub-unit, and the first end of the second switch S 12 of the second first-capacitor shunt sub-unit is electrically connected to the input power supply module V INis electrically connected to the positive electrode, and the second terminal of the second switch S of the second first-capacitor shunting sub-unit 12 is electrically connected to the first terminal of the first capacitor C of the second first-capacitor shunting sub-unit F7 The first terminal of is electrically connected to the first terminal of the first capacitor C of the second first-capacitor shunting sub-unit, and the first terminal of the third switch S of the second first-capacitor shunting sub-unit 13 is electrically connected to the first terminal of the first capacitor C of the second first-capacitor shunting sub-unit F7 The second terminal of is electrically connected to the second terminal of the first capacitor C of the second first-capacitor shunting sub-unit, and the second terminal of the third switch S of the second first-capacitor shunting sub-unit 13 is grounded. The first terminal of the first switch S8 of the first first-capacitor shunting sub-unit is electrically connected to the first terminal of the first capacitor C of the second first-capacitor shunting sub-unit F7 The second terminal of the first switch S8 of the first first-capacitor shunting sub-unit is electrically connected to the second terminal of the first capacitor C of the first first-capacitor shunting sub-unit F6 The first terminal of the second switch S9 of the first first-capacitor shunting sub-unit is electrically connected to the positive electrode of the input power supply module V IN The second terminal of the second switch S9 of the first first-capacitor shunting sub-unit is electrically connected to the first terminal of the first capacitor C of the first first-capacitor shunting sub-unit F6 The first terminal of the third switch S of the first first-capacitor shunting sub-unit 10 is electrically connected to the first terminal of the first capacitor C of the first first-capacitor shunting sub-unit F6 The second terminal of the third switch S of the first first-capacitor shunting sub-unit 10 is grounded.

[0135] According to an embodiment of the present invention, the first terminal of the fourth switch S5 of the second capacitor shunting sub-unit is electrically connected to the first terminal of the first capacitor C of the first first-capacitor shunting sub-unit F6 The second terminal is electrically connected to the first terminal of the power inductor L. The first terminal of the fifth switch S6 is electrically connected to the positive electrode of the input power supply module V IN The second terminal is electrically connected to the first terminal of the second capacitor C F5 The second terminal of the second capacitor C F5 is electrically connected to the first terminal of the power inductor L. The second terminal of the power inductor L is grounded. The first terminal of the sixth switch S7 is electrically connected to the first terminal of the second capacitor C F5 The second terminal is electrically connected to the first terminal of the fourth capacitor C of the second second-capacitor boosting sub-unit F4 is electrically connected.

[0136] According to an embodiment of the present invention, the first terminal of the ninth switch S4 of the second second-capacitor boosting sub-unit is connected to the fourth capacitor C of the second second-capacitor boosting sub-unit F4is electrically connected to the first end, and the second end of the ninth switch S4 of the second second-capacitor boost sub-unit is electrically connected to the fifth capacitor C of the second second-capacitor boost sub-unit F3 is electrically connected to the first end, and the fourth capacitor C of the second second-capacitor boost sub-unit F4 has its second end grounded, and the fifth capacitor C of the second second-capacitor boost sub-unit F3 has its second end electrically connected to the first end of the power inductor L, and the first end of the tenth switch S3 of the second second-capacitor boost sub-unit is electrically connected to the fifth capacitor C of the second second-capacitor boost sub-unit F3 has its first end electrically connected, and the second end of the tenth switch S3 of the second second-capacitor boost sub-unit is electrically connected to the fourth capacitor C of the first second-capacitor boost sub-unit F2 has its first end electrically connected. The first end of the ninth switch S2 of the first second-capacitor boost sub-unit is electrically connected to the fourth capacitor C of the first second-capacitor boost sub-unit F2 has its first end electrically connected, and the second end of the ninth switch S2 of the first second-capacitor boost sub-unit is electrically connected to the fifth capacitor C of the first second-capacitor boost sub-unit F1 has its first end electrically connected, and the fourth capacitor C of the first second-capacitor boost sub-unit F2 has its second end grounded, and the fifth capacitor C of the first second-capacitor boost sub-unit F1 has its second end electrically connected to the first end of the power inductor L, and the first end of the tenth switch S1 of the first second-capacitor boost sub-unit is electrically connected to the fifth capacitor C of the first second-capacitor boost sub-unit F1 has its first end electrically connected, and the second end of the tenth switch S1 of one second-capacitor boost sub-unit is electrically connected to the output terminal, and the first end of the seventh capacitor C F0 is electrically connected to the output terminal, and the first end of the seventh capacitor C F0 has its second end grounded.

[0137] Figure 9 shows a schematic structural diagram of an equivalent circuit of a DC voltage conversion circuit including three capacitor current reduction units and three capacitor boost units in the first time period according to an embodiment of the present invention.

[0138] As Figure 9 shown, Figure 9 and Figure 8 are of the same circuit structure. In the first time period, the first switch S 11 , the first switch S8, the fourth switch S5, the sixth switch S7, the tenth switch S3, and the tenth switch S1 are closed, and the remaining switches are open. The first capacitor C F7 , the first capacitor C F6 are in series and in a discharging state. The second capacitor C F5 is in series with the fourth capacitor C F4 , and the fifth capacitor C F3 is in series with the fourth capacitor CF2 connected in series, the fifth capacitor C F1 powering the output terminal, the second capacitor C F5 and the fifth capacitor C F3 and the fifth capacitor C F1 being in a discharging state, the fourth capacitor C F4 and the fourth capacitor C F2 being in a charging state, the power inductor L is magnetized, the current at the first end of the power inductor rises, and the input voltage rises.

[0139] Figure 10 shows a schematic structural diagram of an equivalent circuit of a DC voltage conversion circuit including 3 capacitor current reduction units and 3 capacitor voltage boost units within a second time period according to an embodiment of the present invention.

[0140] As Figure 10 shown, Figure 10 and Figure 8 are of the same circuit structure. Within the second time period, the second switch S 12 , the third switch S 13 , the second switch S9, the third switch S 10 , the fifth switch S6, the ninth switch S4, and the ninth switch S2 are closed, and the remaining switches are open. The first capacitor C F7 , the first capacitor C F6 , and the second capacitor C F5 are connected in parallel and are in a charging state. The fourth capacitor C F4 is connected in series with the fifth capacitor C F3 , the fourth capacitor C F2 is connected in series with the fifth capacitor C F1 , the seventh capacitor C F0 is connected to the output terminal, the fifth capacitor C F3 , and the fifth capacitor C F1 are in a charging state. The fourth capacitor C F4 , and the fourth capacitor C F2 are in a discharging state. The power inductor L is demagnetized, the current at the first end of the power inductor drops, and the input voltage is supplied by the seventh capacitor C F0 .

[0141] According to an embodiment of the present invention, based on Figure 9 and Figure 10During two time periods, the steady-state voltage of each capacitor and the withstand voltages of multiple switches can be obtained. Thus, under this circuit structure, the maximum withstand voltage of each switch is the second withstand voltage. Compared with the prior art, the withstand voltage of the switch is reduced by more than 67%. Therefore, a switch tube with low withstand voltage and high quality factor can be used to achieve high power conversion efficiency. The steady-state voltage of each capacitor can be expressed according to Formulas (8) to (13), the withstand voltages of multiple switches can be expressed according to Formulas (14) to (17), and the second withstand voltage can be expressed according to Formula (18).

[0142] V CF1 = V O3 - 3V IN3 (8);

[0143] Among them, V CF1 can be characterized as the steady-state voltage of the fifth capacitor C F1 , V O3 can be characterized as the target voltage output by a DC voltage conversion circuit including 3 capacitor current reduction units and 3 capacitor voltage boost units, and V IN3 can be characterized as the input voltage input to a DC voltage conversion circuit including 3 capacitor current reduction units and 3 capacitor voltage boost units.

[0144] V CF2 = (2V O 3 + V IN3 ) / 3 (9);

[0145] Among them, V CF2 can be characterized as the steady-state voltage of the fourth capacitor C F2 .

[0146] V CF3 = (2V O3 - 8V IN3 ) / 3 (10);

[0147] Among them, V CF3 can be characterized as the steady-state voltage of the fifth capacitor C F3 .

[0148] V CF4 = (V O3 + 2V IN3 ) / 3 (11);

[0149] Among them, V CF4 can be characterized as the steady-state voltage of the fourth capacitor C F4 .

[0150] V CF5 = (V O3 - 7V IN3 ) / 3 (12);

[0151] Among them, V CF5 can be characterized as the steady-state voltage of the second capacitor C F5 .

[0152] V CF6 = V CF7 = V IN3 (13);

[0153] Among them, V CF6 can be characterized as the steady-state voltage of the first capacitor C F6 .

[0154] V φ1（S1-S4、S6-S7） = (V O3 - V IN3 ) / 3 (14);

[0155] Among them, V φ1（S1-S4、S6-S7） can be characterized as the withstand voltage values of the tenth switch S1, ninth switch S2, tenth switch S3, ninth switch S4, fifth switch S6, and sixth switch S7 during the first period.

[0156] V φ1（S5） = (V O3 - 7V IN3 ) / 3 (15);

[0157] Among them, V φ1（S5） can be characterized as the withstand voltage value of the fourth switch S5 during the first period.

[0158] V φ2（S9-S10） = 2V IN3 (16);

[0159] Among them, V φ2（S9-S10） can be characterized as the withstand voltage values of the second switch S9 and third switch S 10 during the second period.

[0160] V φ2（S3、S5-S7） = V IN3 (17);

[0161] Among them, V φ2（S3、S5-S7） can be characterized as the withstand voltage values of the tenth switch S3, ninth switch S4, fifth switch S6, and sixth switch S7 during the second period.

[0162] V S = (V O3 - V IN3 ) / 3 (18);

[0163] Among them, V SIt can be characterized as the withstand voltage value of each switch in a DC voltage conversion circuit including three capacitor current-dropping units and three capacitor voltage-boosting units, i.e., the second withstand voltage.

[0164] According to an embodiment of the present invention, based on the charge conservation of the capacitor, it can be obtained that the ratio of the average inductor current to the input current in a DC voltage conversion circuit including three capacitor current-dropping units and three capacitor voltage-boosting units, and the ratio of the average inductor current to the average input current can be expressed according to formula (19).

[0165] (19);

[0166] Wherein, I L3 can be characterized as the target current output by a DC voltage conversion circuit including three capacitor current-dropping units and three capacitor voltage-boosting units, I IN3 can be characterized as the average input current input to a DC voltage conversion circuit including three capacitor current-dropping units and three capacitor voltage-boosting units, Q L3 can be characterized as the target charge flowing out of a DC voltage conversion circuit including three capacitor current-dropping units and three capacitor voltage-boosting units, Q IN3 can be characterized as the inflowing charge input to a DC voltage conversion circuit including three capacitor current-dropping units and three capacitor voltage-boosting units.

[0167] Figure 11 Fig. shows a schematic diagram of the ratio of the average inductor current to the average input current of a DC voltage conversion circuit including three capacitor current-dropping units and three capacitor voltage-boosting units according to an embodiment of the present invention and a prior art circuit under a voltage input of 2.5 - 5V and a voltage output of 70V.

[0168] As Figure 11 shown, the abscissa can be characterized as the input voltage, and the ordinate can be characterized as the ratio of the average inductor current to the average input current. Compared with the circuits of the hybrid trapezoidal DC-DC converter of the prior art 1 and the hybrid Dickson-Fibonacci DC-DC converter of the prior art 2, even when the duty cycle gradually increases, the ratio of the average inductor current to the average input current output by the circuit of the present invention is greatly reduced, i.e., the average inductor current output by the circuit of the present invention is lower. Compared with the prior art, the average inductor current of the present invention can be reduced by 66.7%, so that the conduction loss can be fully reduced. While maintaining a high power conversion efficiency, an inductor with a small size and a large on-resistance can be used to reduce the volume of the circuit and improve the power density.

[0169] Figure 12A schematic diagram showing the relationship between the voltage conversion ratio and the duty cycle obtained by the DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units according to an embodiment of the present invention and the circuit of the prior art under the input voltage of 2.5 - 5V and the output voltage of 70V.

[0170] As Figure 12 shown, compared with the circuit of the prior art, the duty cycle of the circuit of the present invention can be 0 to 1. And as the duty cycle gradually increases, it can be seen from the figure that the voltage conversion ratio of the present invention is higher than that of the prior art (conventional circuit, hybrid ladder DC - DC converter, hybrid Dickson - Fibonacci DC - DC converter), which is beneficial to increasing the equivalent conduction time. At the conversion ratio of 28 times required for the input voltage of 2.5V and the output voltage of 70V. The duty cycle D of the circuit of the present invention is 0.67, 1 - D is 0.33, and the duty cycle D of the traditional boost DC - DC converter is 0.96, 1 - D is 0.04. When the DC - DC converter needs to work at a frequency of 1MHz and a period of 1μs, the equivalent conduction time of the traditional circuit is only 40ns, thus posing higher requirements for the drive and control circuits. And due to the higher voltage conversion ratio of the circuit of the present invention, the equivalent conduction time can be 330ns, thereby reducing the difficulty of the drive and control circuits. And this conduction time also has a 32% increase compared with the equivalent conduction time of 250ns of the hybrid Dickson - Fibonacci DC - DC converter. Therefore, the present invention is suitable for high - conversion - ratio application scenarios.

[0171] Figure 13 A waveform diagram showing the operating states of the power inductor, inductor current, and inductor voltage of the DC voltage conversion circuit including three capacitor current reduction units and three capacitor voltage boost units according to an embodiment of the present invention within multiple switching cycles.

[0172] As Figure 13 shown, Figure 13 A timing diagram of the circuit of the present invention within multiple cycles is shown. The abscissa can be characterized as time t, the ordinate of the upper figure can be characterized as the inductor current I of the power inductor L , and the ordinate of the lower figure can be characterized as the voltage of the first end V L of the power inductor. Within the first time period φ1 of each cycle, the capacitors in the series - parallel switched - capacitor current reduction module are in the discharging state, the power inductor is in the magnetizing state, the inductor current of the power inductor gradually rises, and the voltage of the first end of the power inductor within the first time period φ1 is 3V IN3 , and the rising slope of the average inductor current is 3V IN3 / L. Within the second time period φ2 of each cycle, the capacitors in the series - parallel switched - capacitor current reduction module are in the charging state, the power inductor is in the demagnetizing state, the inductor current of the power inductor rapidly decreases, and the voltage of the first end of the power inductor is - (V O3-10V IN3 ) / 3, the slope of the average inductor current decrease in the second time period φ2 is - (V O3 -10V IN3 ) / 3L.

[0173] According to an embodiment of the present invention, based on the volt - second balance of the inductor, the voltage conversion ratio in a DC - voltage conversion circuit including 3 capacitor current - reducing units and 3 capacitor voltage - boosting units can be obtained. This volt - second balance can be expressed by formula (20), and this voltage conversion ratio can be expressed by formula (21).

[0174] (20);

[0175] (21);

[0176] Among them, VCR3 can represent the voltage conversion ratio of a DC - voltage conversion circuit including 3 capacitor current - reducing units and 3 capacitor voltage - boosting units.

[0177] According to an embodiment of the present invention, based on this, it can be known that in a DC - voltage conversion circuit including 3 capacitor current - reducing units and 3 capacitor voltage - boosting units, the minimum voltage conversion ratio is 10, and the equivalent conduction time is increased by approximately 10 times compared with the prior art, which can reduce the risk brought by extremely short conduction time to the control and drive circuits. Since the volume of the inductor is much larger than that of the flying capacitor, and at the same time, the average inductor current of the present invention can be greatly reduced, so a smaller - sized inductor can be used. In the prior art, a capacitor with a volume of 1.6×0.8×0.8mm 3 is usually used. Therefore, compared with the hybrid trapezoidal DC - DC converter that uses 1 inductor of 4.3×4.3×2.1mm 3 and 8 capacitors to achieve a 4 - fold improvement, and the hybrid Dickson - Fibonacci DC - DC converter that uses 2 inductors of 3×3×1.4mm 3 and 5 flying capacitors to achieve a 7 - fold improvement, the present invention can use 1 inductor of 3×3×1.4mm 3 and 7 capacitors to achieve a 10 - fold improvement. The volume of passive devices is smaller, higher power density can be achieved, the cost can be reduced, and it is more suitable for application scenarios with high - conversion - ratio boosting.

[0178] Figure 14 Fig. shows the schematic diagram of the entire circuit of a DC - voltage conversion circuit including 3 capacitor current - reducing units and 3 capacitor voltage - boosting units according to an embodiment of the present invention.

[0179] As Figure 14As shown, the output terminal of the DC voltage conversion circuit 1401 is electrically connected to the output voltage by a resistor voltage division network 1402. The output voltage by the resistor voltage division network 1402 is electrically connected to the control stage circuit 1403. The control stage circuit 1403 is electrically connected to the bootstrap circuit and the drive circuit 1404. Among them, the target voltage samples a feedback signal by the resistor voltage division network 1402. According to the feedback signal, the control stage circuit 1403 performs control and generates a pulse width signal PWM, and generates a gate drive signal via the bootstrap circuit and the drive circuit 1404.

[0180] Figure 15 The flowchart of the DC voltage conversion method according to an embodiment of the present invention is shown.

[0181] As Figure 15 shown, the method for amplifying and resetting the data signal in this embodiment includes operations S1510 to S1530.

[0182] In operation S1510, the input power supply module sends an input voltage to the series-parallel switched capacitor current reduction module.

[0183] In operation S1520, the series-parallel switched capacitor current reduction module performs a boosting process on the input voltage to obtain the potential difference across the power inductor. Among them, within the first time period, the potential difference across the power inductor is positive, and within the second time period, the potential difference across the power inductor is negative.

[0184] In operation S1530, based on the potential difference across the power inductor, the stacked switched capacitor module is used to perform a boosting process on the input voltage and output the target voltage.

[0185] According to an embodiment of the present invention, the required number of cascaded N capacitor current reduction units and cascaded M capacitor boosting units for the DC voltage conversion circuit can be determined according to the required output voltage, so as to build a DC voltage conversion circuit, so as to use the DC voltage conversion circuit to perform a boosting process on the input voltage and output the target voltage.

[0186] Those skilled in the art can understand that the features described in the various embodiments of the present invention can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, without departing from the spirit and teachings of the present invention, the features described in the various embodiments of the present invention can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present invention.

Claims

1. A DC voltage conversion circuit, characterized in that, Comprising: A series-parallel switched-capacitor current reduction module and a stacked switched-capacitor module; wherein, The series-parallel switched-capacitor current reduction module is electrically connected to the input power supply module. The series-parallel switched-capacitor current reduction module includes a power inductor and N cascaded capacitor current reduction units. The series-parallel switched-capacitor current reduction module is used to boost the input voltage by controlling the charge and discharge states of the N capacitor current reduction units, and regulate the potential difference across the power inductor, so that the average inductance current of the power inductor is reduced to a first current, where N≥2 and N is an integer; The stacked switched-capacitor module is electrically connected to the series-parallel switched-capacitor current reduction module. The stacked switched-capacitor module includes M cascaded capacitor boosting units. The stacked switched-capacitor module is used to alternately control the charge and discharge states of the M capacitor boosting units based on the potential difference across the power inductor to boost the input voltage and output a target voltage. The M capacitor boosting units include a first capacitor boosting sub-unit and M-1 second capacitor boosting sub-units. The first capacitor boosting sub-unit includes a seventh switch, an eighth switch and a third capacitor. The second capacitor boosting sub-unit includes a ninth switch, a tenth switch, a fourth capacitor and a fifth capacitor. By controlling the charge and discharge states of the third capacitor, M-1 of the fourth capacitors and M-1 of the fifth capacitors, the voltage input to the stacked switched-capacitor module and the output voltage are evenly divided, so that the withstand voltage value of the switches in the M capacitor boosting units is reduced to a first withstand voltage value. The first withstand voltage value is as follows: V m =(V OM -V INM ) / M; Among them, V m represents the first withstand voltage value, V OM represents the voltage output by the stacked switched-capacitor module, V INM represents the voltage input to the stacked switched-capacitor module, M≥2, and M is an integer.

2. The DC voltage conversion circuit according to claim 1, wherein The cascaded N capacitor current reduction units include N-1 first capacitor shunt sub-units and a second capacitor shunt sub-unit; The first ends of the N-1 first capacitor shunt sub-units are electrically connected to the input power supply module, and the second ends of the N-1 first capacitor shunt sub-units are electrically connected to the first end of the second capacitor shunt sub-unit; The second end of the second capacitor shunt sub-unit is electrically connected to the first end of the power inductor, and the third end of the second capacitor shunt sub-unit is electrically connected to the stacked switched-capacitor module.

3. The DC voltage conversion circuit according to claim 2, wherein, The nth first capacitor shunt sub-unit among the N-1 first capacitor shunt sub-units includes a first switch, a second switch, a third switch and a first capacitor, where 1≤n≤N-1; The first end of the first switch of the nth first capacitor shunt sub-unit is electrically connected to the first end of the first capacitor of the (n + 1)th first capacitor shunt sub-unit, and the second end of the first switch is electrically connected to the second end of the first capacitor. Among them, the first end of the first switch of the (N-1)th first capacitor shunt sub-unit is electrically connected to the input power supply module; The first end of the second switch of the nth first capacitor shunt sub-unit is electrically connected to the input power supply module, and the second end of the second switch is electrically connected to the first end of the first capacitor; The first end of the third switch of the nth first capacitor shunt sub-unit is electrically connected to the second end of the first capacitor, and the second end of the third switch is grounded.

4. The DC voltage conversion circuit according to claim 3, characterized in that, The second capacitor shunting sub-unit includes a fourth switch, a fifth switch, a sixth switch, and a second capacitor; The first end of the fourth switch of the second capacitor shunting sub-unit is electrically connected to the first end of the first capacitor in the first one of the first capacitor shunting sub-units, and the second end of the fourth switch is electrically connected to the second end of the second capacitor; The first end of the fifth switch of the second capacitor shunting sub-unit is electrically connected to the input power supply module, and the second end of the fifth switch is electrically connected to the first end of the second capacitor; The first end of the sixth switch of the second capacitor shunting sub-unit is electrically connected to the first end of the second capacitor, and the second end of the sixth switch is electrically connected to the stacked switched capacitor module; The first end of the second capacitor of the second capacitor shunting sub-unit is electrically connected to the second end of the fifth switch, and the second end of the second capacitor is electrically connected to the first end of the power inductor.

5. The DC voltage conversion circuit according to claim 4, wherein The switching period of each switch includes a first time period and a second time period; During the first time period, N-1 of the first switches in N-1 of the first capacitor shunting sub-units are closed, N-1 of the second switches and N-1 of the third switches are open, the fourth switch and the sixth switch of the second capacitor shunting sub-unit are closed, and the fifth switch is open, so that N-1 of the first capacitors are connected in series, the second capacitor and the power inductor are connected in parallel. When N-1 of the first capacitors are connected in series and the second capacitor and the power inductor are connected in parallel, N-1 of the first capacitors are in a discharging state, and the voltage at the first end of the power inductor rises, so that the power inductor is in a magnetizing state and the potential difference across the power inductor is positive; During the second time period, N-1 of the first switches in N-1 of the first capacitor shunting sub-units are open, N-1 of the second switches and N-1 of the third switches are closed, the fourth switch and the sixth switch of the second capacitor shunting sub-unit are open, and the fifth switch is closed, so that N-1 of the first capacitors are connected in parallel, the second capacitor and the power inductor are connected in series. When N-1 of the first capacitors are connected in parallel and the second capacitor and the power inductor are connected in series, N-1 of the first capacitors are in a charging state, and the voltage at the first end of the power inductor drops, so that the power inductor is in a demagnetizing state and the potential difference across the power inductor is negative. Among them, through the first capacitors in N-1 of the first capacitor shunting sub-units, the switching of the charging and discharging states during the first time period and the second time period is used to reduce the average inductor current of the power inductor to the first current.

6. The DC voltage conversion circuit according to claim 1, wherein The first end of the first capacitor boosting unit is electrically connected to the series-parallel switched capacitor current reducing module, the second end of the first capacitor boosting unit is electrically connected to the first end of the (M-1)th second capacitor boosting sub-unit, and the third end of the first capacitor boosting unit is electrically connected to the power inductor; The first end of the m-th second capacitor boosting sub-unit is electrically connected to the second end of the (m + 1)-th second capacitor boosting sub-unit, the second end of the m-th second capacitor boosting sub-unit is electrically connected to the first end of the (m - 1)-th second capacitor boosting sub-unit, the third end of the m-th second capacitor boosting sub-unit is grounded, and the fourth end of the m-th second capacitor boosting sub-unit is electrically connected to the power inductor, where the first end of the (M - 1)-th second capacitor boosting sub-unit is electrically connected to the second end of the first capacitor boosting unit, and the second end of the first second capacitor boosting sub-unit is electrically connected to the output end, 1 ≤ m ≤ M - 1.

7. The DC voltage conversion circuit according to claim 6, wherein The first end of the seventh switch of the first capacitor boosting sub-unit is electrically connected to the series-parallel switched capacitor current reduction module, and the second end of the seventh switch is electrically connected to the first end of the third capacitor; The first end of the eighth switch of the first capacitor boosting sub-unit is electrically connected to the first end of the third capacitor, and the second end of the eighth switch is electrically connected to the fourth capacitor of the (M - 1)-th second capacitor boosting sub-unit; The second end of the third capacitor of the first capacitor boosting sub-unit is electrically connected to the power inductor; The first end of the ninth switch in the m-th second capacitor boosting sub-unit is electrically connected to the first end of the fourth capacitor, and the second end of the ninth switch is electrically connected to the first end of the tenth switch; The first end of the tenth switch in the m-th second capacitor boosting sub-unit is electrically connected to the first end of the fifth capacitor, and the second end of the tenth switch is electrically connected to the first end of the ninth switch in the (m - 1)-th second capacitor boosting sub-unit; The second end of the fourth capacitor in the m-th second capacitor boosting sub-unit is grounded, and the second end of the fifth capacitor is electrically connected to the power inductor.

8. The DC voltage conversion circuit according to claim 7, wherein The DC voltage conversion circuit includes: In the first time period, the seventh switch in the first capacitor boosting sub-unit is turned off, the eighth switch is turned on, the M - 1 ninth switches in the M - 1 second capacitor boosting sub-units are turned off, the M - 1 tenth switches are turned on, the third capacitor in the first capacitor boosting sub-unit is connected in series with the fourth capacitor in the (M - 1)-th second capacitor boosting sub-unit, and the fifth capacitor in the m-th second capacitor boosting sub-unit is connected in series with the fourth capacitor in the (m - 1)-th second capacitor boosting sub-unit. Based on the potential difference across the power inductor being positive, the third capacitor charges the fourth capacitor in the (M - 1)-th second capacitor boosting sub-unit, and the fifth capacitor in the m-th second capacitor boosting sub-unit charges the fourth capacitor in the (m - 1)-th second capacitor boosting sub-unit, so as to boost the input voltage and output the target voltage; During the second time period, the seventh switch in the first capacitor boosting sub-unit is closed, the eighth switch is opened, M - 1 ninth switches in M - 1 second capacitor boosting sub-units are closed, M - 1 tenth switches in M - 1 second capacitor boosting sub-units are opened, the third capacitor in the first capacitor boosting sub-unit is connected in parallel with the fourth capacitor and the fifth capacitor in the m-th second capacitor boosting sub-unit, the fourth capacitor in the m-th second capacitor boosting sub-unit is connected in series with the fifth capacitor in the m-th second capacitor boosting sub-unit. Based on the potential difference across the power inductor being negative, the fourth capacitor in the m-th second capacitor boosting sub-unit charges the fifth capacitor in the m-th second capacitor boosting sub-unit.

9. The DC voltage conversion circuit according to claim 1, wherein The DC voltage conversion circuit further includes a seventh capacitor; The first end of the seventh capacitor is electrically connected to the output terminal, the second end of the seventh capacitor is grounded. When the potential difference across the power inductor is positive, the fifth capacitor in the first second capacitor boosting sub-unit charges the seventh capacitor; when the potential difference across the power inductor is negative, the seventh capacitor discharges to the output terminal to facilitate maintaining the target voltage.

10. A DC voltage conversion method for the DC voltage conversion circuit according to any one of claims 1 to 9, characterized in that, The DC voltage conversion method includes: An input power supply module sends an input voltage to a series-parallel switched capacitor current reduction module; The series-parallel switched capacitor current reduction module boosts the input voltage to obtain a potential difference across the power inductor. Among them, during the first time period, the potential difference across the power inductor is positive, and during the second time period, the potential difference across the power inductor is negative; Based on the potential difference across the power inductor, a stacked switched capacitor module is used to boost the input voltage to output a target voltage.

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