Power converter with auxiliary inductor

Abstract

The invention relates to a power converter with an auxiliary inductor. The second transistor (M2) is coupled to the first transistor (M1) at a switching terminal. A third transistor (M3) is coupled to the auxiliary inductor terminal, and the third transistor (M3) is also coupled to the switch terminal. A logic circuit (140) has a switch terminal input, a first input, a second input, and a third input, and a first output and a second output. The first output is coupled to a control input of the third transistor (M3). The second output is coupled to the second transistor (M2). A configurable delay circuit (122) has a modulation input, a switch terminal input, and a voltage input, and a first output, a second output, and a third output. The switch terminal input is coupled to the switch terminal. A first output of the configurable delay circuit is coupled to a first input of a logic circuit (140). A second output of the configurable delay circuit (122) is coupled to a second input of the logic circuit (140). A third output of the configurable delay circuit (122) is coupled to a control input of the first transistor (M1).

Description

Technical Field

[0001] The present application relates to an electronic device, and in particular, to a power converter with an auxiliary inductor. Background Art

[0002] A power converter converts an input voltage into an output voltage. A switching power converter is a type of power converter that includes one or more transistors that are switched on and off according to a control signal, such as a pulse width modulation control signal. A buck converter is a type of switching power converter that produces an output voltage at a level lower than the input voltage. Other types of switching power converters include boost converters and buck-boost converters. Summary of the invention

[0003] In one example, a power converter includes a first transistor having a control input and a first terminal and a second terminal. A second transistor has a control input and a first terminal and a second terminal. The first terminal of the second transistor is coupled to the second terminal of the first transistor at a switch terminal. A third transistor has a control input and a first terminal and a second terminal. The first terminal of the third transistor is coupled to an auxiliary inductor terminal, and the second terminal of the third transistor is coupled to the switch terminal. A logic circuit has a switch terminal input, a first input, a second input, a third input, a first output, and a second output. The first output is coupled to the control input of the third transistor, and the second output is coupled to the control input of the second transistor. A configurable delay circuit has a modulation input, a switch terminal input, a voltage input, a first output, a second output, and a third output. The switch terminal input of the configurable delay circuit is coupled to the switch terminal. The first output of the configurable delay circuit is coupled to the first input of the logic circuit. The second output of the configurable delay circuit is coupled to the second input of the logic circuit, and the third output of the configurable delay circuit is coupled to the control input of the first transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram of an example power converter with an auxiliary inductor to partially charge a switch terminal.

[0005] Figure 2 is a timing diagram illustrating the operation of a power converter in one example.

[0006] Figure 3 is a graphic identifying suitable points for charging the switch terminals in one example.

[0007] Figure 4 is a flow chart of a method for partially charging switch terminals in one example.

[0008] Figure 5is a block diagram of a processing circuit for partially charging a switch terminal in one example. DETAILED DESCRIPTION

[0009] The same reference numbers or other reference designators are used in the drawings to designate the same or similar features (functionally and / or structurally).

[0010] A synchronous buck converter is a type of switching power converter in which two transistors are coupled in series between an input voltage terminal and a ground terminal. The connection between the transistors is referred to as a switch (SW) terminal, which is also coupled to an inductor. The transistor coupled to the input voltage terminal may be referred to as a "high side" (HS) transistor, and the transistor coupled to the ground terminal may be referred to as a "low side" (LS) transistor. According to a pulse width modulation (PWM) control signal, the control circuit turns on one of the transistors, and then turns on the other transistor after a "dead time". When the LS transistor is turned on, the voltage on the SW terminal is approximately 0V. For example, due to the on-resistance of the current flowing through the LS terminal, the SW terminal voltage may be a slightly negative voltage.

[0011] When the LS transistor is turned off, the control circuit waits for a dead time before turning on the HS transistor. During the dead time, current can continue to flow from ground through the body diode of the LS transistor to the SW terminal. The voltage drop across the body diode (e.g., 0.7V) forces the SW terminal voltage to an even more negative voltage. When the control circuit then begins to turn on the HS transistor, a voltage equal to the input voltage (Vin) plus the body diode voltage drop exists across the terminals (e.g., drain and source) of the HS transistor. Current begins to flow through the channel of the HS transistor, where the voltage drop across the transistor is relatively large. The current that begins to flow through the HS transistor when the HS transistor begins to turn on also charges the parasitic capacitance present at the SW terminal (e.g., the drain to source capacitance of the LS transistor). Therefore, significant power dissipation may occur whenever the HS transistor is turned on - power dissipation is referred to as "switching loss."

[0012] Switching losses are at least somewhat proportional to the square of the input voltage. Therefore, at higher input voltage levels, switching losses may be particularly problematic, especially for some applications. For example, a car may have a 12V battery, and therefore the input voltage of the power converter in the car is 12V. Cars are increasingly equipped with more and more electronic devices. The increase in power loads in cars means that, for the same 12V battery, the cables carry increased current levels. The increase in current carried by the car's cables results in an increase in the cross-sectional area of ​​the cables, which makes the cables heavier and more difficult to lay around narrow corners in the chassis of the car. One way to solve the problem of car wiring is to provide a higher voltage battery. For example, a car with a 48V battery can have thinner and lighter cables than a car with a 12V battery. However, a power converter with a 48V input voltage will have significantly higher switching losses than a power converter with a 12V input voltage.

[0013] One method of reducing the switching losses of the HS transistor includes using an auxiliary inductor. When the LS transistor is turned on, current flows through the LS transistor to the main inductor of the buck converter, and during this time, current may also be allowed to flow to the auxiliary inductor. Energy is thereby stored in the auxiliary inductor. During the subsequent dead time, when the LS transistor is turned off, the auxiliary inductor releases its energy to the SW terminal, causing the voltage on the SW terminal to increase until the SW terminal reaches the level of the input voltage Vin. Then, when the control circuit turns the HS transistor on, current begins to flow through the HS transistor with little, if any, voltage drop across the drain and source terminals of the transistor, thereby greatly reducing or eliminating the switching losses associated with the HS transistor.

[0014] However, using an auxiliary inductor as described above to charge the SW terminal before turning on the HS transistor causes losses associated with the auxiliary inductor. The resistance of the auxiliary inductor causes conduction losses in the auxiliary inductor. According to the example described below, the control circuit partially charges the SW terminal using the auxiliary inductor before turning on the HS transistor. In one example, the control circuit causes the SW terminal to be charged to approximately half of the input voltage (Vin / 2). Then, when the control circuit begins to turn on the HS transistor, the voltage drop across the HS transistor is approximately Vin / 2, which is significantly less than the voltage drop in the absence of the auxiliary inductor. Using an auxiliary inductor to charge the SW terminal to a fraction of Vin, Vin / K (e.g., K=2), and then using the HS transistor to complete charging the SW terminal to Vin results in a more efficient buck converter than not using an auxiliary inductor at all or using an auxiliary inductor to charge the SW terminal to the full Vin.

[0015] Figure 1is a block diagram of a power converter 100 in an example. The power converter 100 converts an input voltage Vin into an output voltage Vout to drive a load 190 . Figure 1 The power converter 100 in the example of is a synchronous buck converter, but the principles described herein are applicable to other types of power converters, including, for example, non-synchronous buck converters and boost converters and class D audio amplifiers. The power converter 100 includes a controller 102, a converter control circuit 120, and a power stage 170. The controller 102 includes a controller output 102a. The controller 102 generates a PWM signal 119 as described below. The controller 102 may include an analog circuit, a digital circuit, or a combination of analog and digital circuit components. In some examples, the controller 102 may include a processor that executes machine instructions. The power stage 170 has power stage terminals 170a, 170b, 170c, 170d, 170e, and 170f.

[0016] The converter control circuit 120 includes a voltage input 120a, a modulation input 120b, a switch terminal input 120c, an input terminal 120d, and outputs 120e, 120f, and 120g. The voltage input 120a receives an input voltage Vin scaled by a scaling factor K. In one example, the scaling factor K is 2, and therefore, the voltage input 122a receives Vin / 2. In another example, the value of the scaling factor K is between 1.8 and 2.2. The modulation input 120b is coupled to the controller output 102a. The switch terminal input 120c is coupled to the terminal 170d of the power stage 170. The input terminal 120d is coupled to the terminal 170b. The outputs 120e, 120f, and 120g of the converter control circuit 120 are coupled to the terminals 170a, 170e, and 170c of the power stage 170, respectively. The terminal 170f is the output terminal of the power converter 100 and can be coupled to the load 190.

[0017] exist Figure 1 In the example of , the converter control circuit 120 includes a configurable delay circuit 122 coupled to the logic circuit 140. The configurable delay circuit 122 has a voltage input 122a, a modulation input 122b, a switch terminal input 122c, and outputs 122d and 122e. The voltage input 122a and the modulation input 122b of the configurable delay circuit 122 are coupled to the voltage input 120a and the modulation input 120b of the converter control circuit 120, respectively. The switch terminal input 122c of the configurable delay circuit 122 is coupled to the switch terminal input 120c of the converter control circuit 120. The output 122e of the configurable delay circuit 122 is coupled to the output 120e of the converter control circuit 120.

[0018] Logic circuit 140 has inputs 140a, 140b, and 140c, a switch terminal input 140d, and outputs 140e and 140f. Input 140a of logic circuit 140 is coupled to modulation input 120b of converter control circuit 120. Input 140b of logic circuit 140 is coupled to output 122d of configurable delay circuit 122. Input 140c of logic circuit 140 is coupled to terminal 120d of converter control circuit 120. Switch terminal input 140d is coupled to switch terminal input 122c. Outputs 140e and 140f are coupled to outputs 120f and 120g, respectively.

[0019] The configurable delay circuit 122 includes a comparator 124, a counter 126, and delay elements 127 and 128. The comparator 124 may be a latched comparator having comparator inputs 124a and 124b, a latch input 124c, and a comparator output 124d. The counter 126 has a control input 126a, a clock input 126b, and a counter output 126c. The delay element 127 has an input 127a, a delay control input 127b, and a delay output 126c. The delay element 128 has an input 128a and a delay output 128b. The comparator inputs 124a and 124b are coupled to the voltage input 122a and the modulation input 122b, respectively. The latch input 124c and the clock input 126b are coupled to the delay output 128b. The delay output 128b is coupled to the output 122e of the configurable delay circuit 122.

[0020] Comparator output 124d is coupled to control input 126a. Control input 126a may be an up / down control input. In one example, a logic high at control input 126a causes the counter to increment its count value, and a logic low causes the counter to decrement its count value. Comparator output 126c is coupled to delay control input 127b. Modulation input 122b is coupled to input 127a of delay element 127 and to output 122d coupled to modulation input 122b. Delay output 127c is coupled to input 128a of delay element 128 and to output 122d of configurable delay circuit 122.

[0021] exist Figure 1In the example of , logic circuit 140 includes inverter 141, set-reset (SR) flip-flop 142, comparator 143 and latch 144. Latch 144 can be an edge-triggered latch. In other examples, a data (D) flip-flop can be used instead of latch 144. Input 140a of logic circuit 140 is coupled to the input of inverter 141 and to the clock input of latch 144. The SR flip-flop has a set (S) input, a reset (R) input and an output (Q). The output of inverter 141 is coupled to the S input of SR flip-flop 142. Input 140b of logic circuit 140 is coupled to the R input of SR flip-flop 142, and the Q output of the SR flip-flop is coupled to output 140e of logic circuit 140. The signal from the Q output of the SR flip-flop 142 is LS ON 182, and turns on transistor M2 when LS ON 182 is logic high (e.g., by forcing the gate-to-source voltage (Vgs) of transistor M2 to exceed its threshold voltage), and turns off transistor M2 when LS ON 182 is logic low (Vgs is below the threshold voltage). Comparator 143 has comparator inputs 143a and 143b and a comparator output 143c. Input terminal 120d is coupled to comparator input 143a. Power stage terminal 170d is coupled to comparator input 143b. In addition to the clock input, latch 144 has an R input and a Q output. Comparator output 143c is coupled to the R input of latch 144. The Q output of latch 144 is coupled to output 140f of logic circuit 140. The signal from the Q output of latch 144 is AUX ON 183, and when AUX ON 183 is logic high (e.g., by forcing the gate-to-source voltage (Vgs) of transistor M3 to exceed its threshold voltage), transistor M3 is turned on, and when AUX ON 183 is logic low (Vgs is below its threshold voltage), transistor M3 is turned off.

[0022] The power stage 170 includes transistors M1, M2 and M3, inductors L1 and L2, and capacitor C1. Figure 1 In the example of , transistors M1 to M3 are n-channel field effect transistors (NFETs), but may be implemented as other types of transistors in other examples. The drain of transistor M1 is coupled to input voltage terminal 175 (Vin), and the source of transistor M2 is coupled to ground terminal 177. The source of transistor M1 is coupled to the drain of transistor M2 at power stage terminal 170d, which is also referred to as switch (SW) terminal 170d. The voltage at SW terminal 170d is referred to herein as V SW. Inductor L1 is coupled between SW terminal 170d and capacitor C1. Capacitor C1 is coupled between output terminal 170f and ground. The gates of transistors M1 and M2 are coupled to terminals 170a and 170e, respectively. The signal from the delayed output 128b of delay element 128 is HS ON 181, and when HS ON 181 is a logic high (e.g., by forcing the gate-to-source voltage (Vgs) of transistor M1 to exceed its threshold voltage), transistor M1 is turned on, and when HS ON 181 is a logic low (Vgs is less than its threshold voltage), transistor M1 is turned off. Transistor M3 and inductor L2 are coupled in series between power stage output terminal 170f and SW terminal 170d. The gate of transistor M3 is coupled to power stage terminal 170c. In one example, when transistor M3 is "off", no current flows through transistor M3 in either direction. In one example, a diode can be coupled in series with transistor M3. In another example, transistor M3 may include two transistors coupled in series. In yet another example, the body connection of the transistor may be available and used to prevent current from flowing through the parasitic body diode. In some examples, inductor L1 may be referred to as the "main" inductor of the power converter, and inductor L2 may be referred to as the "auxiliary" inductor.

[0023] Figure 2 is a timing diagram illustrating the operation of power converter 100 . Figure 2 The PWM signal 119, the LS ON signal 182, the HS ON signal 181, the AUX ON signal 183, the switch terminal voltage V SW and example waveforms of the current Iaux through the auxiliary inductor L2. Figure 1 and 2 , the controller 102 starts the PWM cycle by forcing the PWM signal 119 to a logic high state as indicated by a rising edge 201. The rising edge 201 of the PWM signal 119 is received by the clock input of the latch 144, which causes a rising edge 202 of the AUX ON signal from the Q output of the latch 144. The logic high AUX ON turns on the transistor M3.

[0024] When transistor M3 is turned on, current flows from ground and through transistors M2 and M3 to inductor L2. The direction of current Iaux is Figure 3 is designated as from the drain of transistor M3 to the source of transistor M3. Therefore, current Iaux increases, as indicated by Figure 2 As indicated by 204 in FIG. 1 , energy is stored in the auxiliary inductor L2 .

[0025] The delay element 127 also receives the rising edge 201 of the PWM signal 119. The delay element 127 introduces a delay ( Figure 2142 ). In one example, the delay element 127 introduces an adjustable delay in response to a rising edge at its input 127a, but does not introduce a configurable delay in response to a falling edge at its input 127a. As described below, the length of the configurable delay is programmed into the delay element by the counter 126. The delayed output signal from the delay element 127 is provided to the R input of the SR flip-flop 142. The rising edge on the R input of the SR flip-flop 142 causes the LS ON signal 182 to be forced low at its Q output, as indicated by the falling edge 206. Therefore, after the DELAY1 period implemented by the delay element 127, the transistor M2 is turned off.

[0026] When transistor M2 turns off, auxiliary inductor L2 begins to release at least some of its energy to thereby charge the capacitance at SW terminal 170d. Current Iaux continues to flow from auxiliary inductor L2 through transistor M3 into SW terminal 170d but decreases, as indicated by reference numeral 210. In response, voltage V SW Increases, as indicated by reference numeral 208. After the rising edge of 212 of the HS ON signal, current Iaux continues to decrease. Current Iaux stops flowing due to transistor M3 turning off.

[0027] The delayed signal from delay element 127 is also provided to delay element 128, which introduces an additional delay (DELAY2). In some instances, the delay introduced by delay element 128 is a fixed delay (not configurable). In some instances, delay element 128 introduces a fixed delay in response to a rising edge at its input 128a, but does not introduce a fixed delay in response to a falling edge at its input 128a. The rising edge 212 of the HS ON signal at the gate of transistor M1 is a delayed version of the rising edge 201 of the PWM signal. The delay length of the rising edge 212 relative to the rising edge 201 is the sum of DELAY1 and DELAY2. Therefore, after the delay of DELAY1 plus DELAY2 starting from the rising edge 201 of the PWM signal, transistor M1 is turned on. After energy is stored in auxiliary inductor L2 and after transistor M2 is turned off, transistor M1 is turned on.

[0028] The configurable delay circuit 122 configures the delay DELAY1 into the delay element 127 so that when the transistor M1 is turned on, the SW terminal 170d is charged to a voltage of approximately Vin / 2. In one example, the configurable delay circuit 122 configures the delay DELAY1 so that the SW terminal 170d is charged to a voltage within 10% of half the voltage of the input voltage Vin. The rising edge 212 of HS ON is received by the latch input 124c of the comparator 124 and the clock input 126b of the counter 126. Whenever the transistor M1 is turned on, the comparator 124 compares Vin / K (e.g., K=2) with V SW is compared to determine V SW Is it indeed approximately equal to Vin / 2? If the voltage Vin / 2 is greater than V SW , then when transistor M1 is turned on, V SW Vin / 2 has not yet been reached. In this case, comparator 124 outputs a logic high signal to control input 126a of counter 126. In response to the logic high at input 126a, counter 126 increments its count value. The incremented count value is provided to delay control input 127b of delay element 127, which then increases the length of DELAY1.

[0029] However, if the voltage Vin / 2 is less than V SW , then when transistor M1, V SW is greater than Vin / 2. In this case, comparator 124 outputs a logic low signal to control input 126a of counter 126. In response to the logic low at input 126a, counter 126 decrements its count value. The decremented count value is provided to delay control input 127b of delay element 127, which in turn decreases the length of DELAY1. Configurable delay circuit 122 adjusts the length of DELAY1 to ensure that when V SW When the voltage is approximately equal to Vin / 2, transistor M1 is turned on.

[0030] As described above, some power converters do not include auxiliary inductor L2. Therefore, when the HS transistor (e.g., Figure 1 When the transistor M1 in the example of HS is turned on, the Vds of the HS transistor is Vin, and the HS transistor has relatively high switching losses. Other power converters include an auxiliary inductor that charges the switch terminal to Vin to minimize switching losses in the HS transistor, but causes conduction losses in the auxiliary inductor. Figure 1 In the example of , when transistor M1 is turned on, power converter 100 charges SW terminal 170d to approximately Vin / 2. Figure 3As explained, the combination of the switching losses of transistor M1 and the conduction losses of the auxiliary inductor L2 is lower than the losses of either of the two power conductors described above: (a) a power converter in which there is no auxiliary inductor and the SW terminal is not charged at all when the HS transistor is turned on; and (b) a power converter in which the auxiliary inductor charges the SW terminal to Vin before the HS transistor is turned on.

[0031] Figure 3 301 is a graph containing curves 301, 302, and 303. Power loss is on the y-axis and switch terminal voltage is on the x-axis. The data in this example is for a power converter with an input voltage Vin of 48V. Curve 301 is an example curve illustrating the losses due to transition and capacitive losses associated with turning on transistor M1. Transition losses represent the power dissipated by the current flowing through the channel of transistor M1 when the Vds of transistor M1 is greater than 0V. When transistor M1 is turned on and it is charged by parasitic capacitance (which is charged to Vin-V SW ) discharge, capacitive losses occur. The transition and capacitive losses associated with transistor M1 decrease as the voltage on SW terminal 170d increases. Curve 302 is an example curve illustrating the losses caused by auxiliary inductor L2. Such losses are proportional to the integral of the product of the inductor current and the on-resistance of transistor M3. The losses caused by the use of auxiliary inductor L2 increase as the voltage on SW terminal 170d increases. Curve 303 is the sum of curves 301 and 302, and therefore represents the transition and capacitive losses plus the losses caused by the use of auxiliary inductor current. Therefore, curve 303 represents the combined losses. Point 310 identifies the lowest point of curve 303, which occurs at approximately 24V, which in this example is approximately half of the input voltage of 48V.

[0032] Figure 4 Flowchart 400 is provided to illustrate a method implemented by power converter 100. In block 402, the method includes turning on transistor M2. At block 404, when transistor M2 is turned on, the method includes turning on transistor M3 to allow current to flow to auxiliary inductor L2 and to store energy in auxiliary inductor L2. At block 406, after a configurable time period (e.g., DELAY1), transistor M2 is turned off. By turning off transistor M2, the energy stored in auxiliary inductor L2 is used to charge SW terminal 170d. At block 408, transistor M1 is then turned on. At block 410, the method includes updating the configurable time period based on a comparison of a voltage proportional to the switch terminal voltage and a voltage proportional to the input voltage. In one example, the voltages proportional to the switch terminal voltage and the input voltage are V SWand Vin / K, where, for example, K=2. In another example, the voltages proportional to the switch terminal voltage and the input voltage are V SW * K and Vin.

[0033] Figure 5 1 is a block diagram of a converter control circuit 120 including a processing circuit 500. The processing circuit 500 may perform the operations described herein attributed to the converter control circuit 120 and its constituent circuits ( Figure 1 ). Processing circuit 500 includes one or more processors 502 coupled to non-transitory storage medium 504. Non-transitory storage medium 504 may include volatile memory (e.g., random access memory), non-volatile memory (e.g., read-only memory, flash memory, etc.), or a combination thereof. Non-traditional storage medium 504 stores machine-executable instructions (e.g., firmware) that may be executed by one or more processors 502 to perform the functionality attributed to converter control circuit 120 described herein.

[0034] In this description, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0035] Additionally, in this description, the recitation “based on” means “based at least in part on.” Thus, if X is based on Y, then X may depend on Y and any number of other factors.

[0036] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0037] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnections between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their ends.

[0038] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0039] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used in practice with little or no change to the rest of the circuitry. For example, field effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs—e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0040] In the claims reference may be made to the control input of a transistor and its current terminals. In the case of a FET, the control input is the gate, and the current terminals are the drain and the source. In the case of a BJT, the control input is the base, and the current terminals are the collector and the emitter.

[0041] Reference herein to a FET being "on" or "enabled" means that there is a conduction channel of the FET and drain current can flow through the FET. Reference herein to a FET being "off" or "disabled" means that there is no conduction channel, and therefore drain current cannot flow through the FET. However, an "off" FET can have current flowing through the body diode of the transistor.

[0042] The circuits described herein may be reconfigured to include additional or different components to provide functionality at least partially similar to functionality available before component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the displayed resistor. For example, a resistor or capacitor shown and described as a single component herein may actually be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described as a single component herein may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0043] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features described as external to the integrated circuit may be included in the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0044] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this description. In this description, unless otherwise stated, "about," "substantially," or "substantially" preceding a parameter means within + / - 10% of the parameter, or if the parameter is zero, within a reasonable range of values ​​about zero.

[0045] Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.

Claims

1. A power converter, comprising: a first transistor having a control input and a first terminal and a second terminal; a second transistor having a control input and a first terminal and a second terminal, the first terminal of the second transistor being coupled to the second terminal of the first transistor at a switch terminal; a third transistor having a control input and a first terminal and a second terminal, the first terminal of the third transistor being coupled to the auxiliary inductor terminal and the second terminal of the third transistor being coupled to the switch terminal; a logic circuit having a switch terminal input, a first input, a second input, a third input, a first output, and a second output, the first output being coupled to a control input of the third transistor and the second output being coupled to the control input of the second transistor; and A configurable delay circuit having a modulation input, a switch terminal input, a voltage input, a first output, a second output, and a third output, wherein the switch terminal input of the configurable delay circuit is coupled to the switch terminal, the first output of the configurable delay circuit is coupled to the first input of the logic circuit, the second output of the configurable delay circuit is coupled to the second input of the logic circuit, and the third output of the configurable delay circuit is coupled to the control input of the first transistor.

2. The power converter of claim 1 , wherein the configurable delay circuit comprises: a counter having a control input and a counter output; and A delay element having a signal input coupled to the modulation input, a delay control input coupled to the counter output, and a delay output coupled to the second output of the configurable delay circuit.

3. The power converter of claim 2 , further comprising a comparator having a first comparator input and a second comparator input and a comparator output, the first comparator input being coupled to the voltage input, the second comparator input being coupled to the switch terminal input of the configurable delay circuit, and the comparator output being coupled to the control input of the counter.

4. The power converter of claim 3 , wherein the delay element is a first delay element, and the comparator includes a latch input, and the configurable delay circuit includes a second delay element, the second delay element having an input and a delayed output, the input of the second delay element being coupled to the delayed output of the first delay element, and the delayed output of the second delay element being coupled to the third output of the configurable delay circuit and to the latch input.

5. The power converter of claim 4 , wherein in response to assertion of a signal at the latch input, the counter is configured to: responsive to the signal at the control input of the counter being in a first logic state, incrementing a count value at an output of the counter; and In response to the signal at the control input of the counter being in a second logic state, the count value at the counter output is decremented.

6. The power converter of claim 1 , wherein the logic circuit comprises: a latch having a clock input coupled to the first input of the logic circuit and a latch output coupled to the first output of the logic circuit; an inverter having an input and an output, the input being coupled to the first input of the logic circuit; and A set-reset SR flip-flop having a set S input, a reset R input and an output, wherein the S input is coupled to the output of the inverter, the R input is coupled to the second input of the logic circuit, and the output of the SR flip-flop is coupled to the control input of the second transistor.

7. A power converter according to claim 6, wherein the latch has an R input, and the logic circuit further includes a comparator having a first comparator input and a second comparator input and a comparator output, the first comparator input is coupled to the third input of the logic circuit, the second comparator input is coupled to the switch terminal input of the logic circuit, and the comparator output is coupled to the R input of the latch.

8. The power converter of claim 7, wherein the configurable delay circuit comprises: a first delay element having a delay input and a delay output, the delay input of the first delay element being coupled to the first output of the configurable delay circuit and the delay output of the first delay element being coupled to the second output of the configurable delay circuit; and A second delay element having a delay input and a delay output, the delay input of the second delay element being coupled to the second output of the configurable delay circuit, and the delay output of the second delay element being coupled to the third output of the configurable delay circuit.

9. The power converter of claim 8, wherein the time delay of the first delay element is adjustable.

10. A power converter comprising: a first transistor having a control input and a first terminal and a second terminal; a second transistor having a control input and a first terminal and a second terminal, the first terminal of the second transistor being coupled to the second terminal of the first transistor at a switch terminal; a third transistor having a control input and a first terminal and a second terminal, the first terminal of the third transistor being coupled to the auxiliary inductor terminal and the second terminal of the third transistor being coupled to the switch terminal; and A converter control circuit having a voltage input, a switch terminal input coupled to the switch terminal, and a first output, a second output, and a third output, the switch terminal input being coupled to the control input of the first transistor, the second output being coupled to the control input of the second transistor, and the third output being coupled to the control input of the third transistor, wherein the converter control circuit is configured to: turning on the second transistor; When the second transistor is turned on, turning on the third transistor for a configurable delay period; upon expiration of the configurable delay period, turning off the second transistor; and After the second transistor is turned off, the first transistor is turned on and the configurable delay period is updated based on a comparison of a voltage proportional to a voltage at the switch terminal input and a voltage proportional to a voltage at the voltage input.

11. The power converter of claim 10, wherein the converter control circuit is configured to: increasing the configurable delay period based on the voltage proportional to the voltage at the switch terminal being less than the voltage proportional to the voltage at the voltage input; and Based on the voltage proportional to the voltage at the switch terminal being greater than the voltage proportional to the voltage at the voltage input, the configurable delay period is reduced.

12. The power converter of claim 10 wherein the converter control circuit has a modulation input and the converter control circuit includes an adjustable delay element between the modulation input and the first output.

13. The power converter of claim 12, wherein the adjustable delay element has an input and a delayed output, wherein the converter control circuit comprises: a second delay element having a delay input and a delay output, the delay input of the second delay element being coupled to the delay output of the adjustable delay element and the delay output of the second delay element being coupled to the first output; a comparator having a first comparator input coupled to the voltage input and a second comparator input coupled to the switch terminal input and a comparator output; and A counter having a control input coupled to the comparator output, a clock input coupled to the delayed output of the second delay element, and a counter output coupled to the adjustable delay element.

14. The power converter of claim 13, wherein the comparator is a latching comparator and includes a latch input coupled to the delayed output of the second delay element.

15. The power converter of claim 10, wherein the converter control circuit has a modulation input, and the converter control circuit comprises: a latch having a clock input and an output, the clock input being coupled to the modulation input and the output of the latch being coupled to the control terminal of the third transistor; an inverter having an inverter input and an inverter output, the inverter input being coupled to the modulation input; and A set-reset SR flip-flop having a set S input, a reset R input and an output, wherein the S input is coupled to the inverter output, the R input is coupled to the delayed output of the adjustable delay element, and the output of the SR flip-flop is coupled to the control input of the second transistor.

16. The power converter of claim 10, wherein the converter control circuit comprises a processor configured to: turning on the second transistor; When the second transistor is turned on, turning on the third transistor for a configurable delay period; upon expiration of the configurable delay period, turning off the second transistor; and After the second transistor is turned off, the first transistor is turned on and the configurable delay period is updated.

17. A system comprising: load; and A switching power converter comprising: a first transistor having a control input and a first terminal and a second terminal, the first terminal being coupled to an input voltage terminal; a second transistor having a control input and a first terminal and a second terminal, the first terminal of the second transistor being coupled to the second terminal of the first transistor at a switch terminal; a third transistor having a control input and a first terminal and a second terminal, the first terminal of the third transistor being coupled to the auxiliary inductor terminal and the second terminal of the third transistor being coupled to the switch terminal; a first inductor coupled between the switch terminal and the load; a second inductor coupled between the load and the first terminal of the third transistor; a controller having a controller output; and A converter control circuit having a voltage input, a switch terminal input coupled to the switch terminal, a modulation input coupled to the controller output, a first output coupled to the control input of the first transistor, a second output coupled to the control input of the second transistor, and a third output coupled to the control input of the third transistor, wherein the converter control circuit is configured to: turning on the second transistor; When the second transistor is turned on, turning on the third transistor for a certain period of time to store energy in the second inductor; upon expiration of the time period, increasing the voltage at the switch terminal to a voltage within 10% of half the voltage at the input voltage terminal by turning off the second transistor for a certain time period; and After the second transistor is turned off, the first transistor is turned on.

18. The system of claim 17, wherein the converter control circuit is configured to adjust the time period.

19. The system of claim 17, wherein the converter control circuit is configured to adjust the time period by comparing a voltage proportional to the voltage at the switch terminal and a voltage proportional to the voltage at the input voltage terminal.

20. The system of claim 19, wherein the converter control circuit comprises: a comparator having a first input and a second input and a comparator output, the first input of the comparator being coupled to the voltage input and the second input of the comparator being coupled to the switch terminal input; a counter having a control input and a counter output, the control input being coupled to the comparator output; and an adjustable delay element having an input and a delayed output, the input of the adjustable delay element being coupled to the modulation input; and A second delay element has an input and a delayed output, the input of the second delay element being coupled to the delayed output of the adjustable delay element and the delayed output of the second delay element being coupled to the first output.

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