Primary-secondary double-DSP (Digital Signal Processor) real-time multiplex loop control circuit

Abstract

The invention discloses a primary-secondary double-DSP (Digital Signal Processor) real-time multiplex loop control circuit in the field of switching power supplies, which comprises a secondary side DSP, a primary side DSP, a relay switch circuit, a BUCK / full-bridge power conversion circuit, an input voltage sampling circuit and an output voltage sampling circuit, the input end of the input voltage sampling circuit and the input end of the relay switch circuit are both connected with input voltage, and the primary side DSP is connected with the control end of the relay switch circuit, the control end of the BUCK / full-bridge power conversion circuit and the output end of the input voltage sampling circuit. The output end of the BUCK / full-bridge power conversion circuit and the input end of the output voltage sampling circuit are both connected with output voltage, and the secondary side DSP is connected with the output end of the primary side DSP and the output end of the output voltage sampling circuit. The problem that an existing primary side DSP is low in response speed is solved, input feedforward of the primary side DSP is achieved through the input voltage sampling circuit, and the response speed is increased.

Description

Technical Field

[0001] The invention relates to the technical field of switch power supply, in particular to a primary-secondary dual DSP real-time multiplexing loop control circuit. Background Art

[0002] With the development of science and technology, the application of switching power supplies is becoming more and more extensive, and the power density and efficiency requirements of power supplies are also getting higher and higher. Since the control method of the BUCK+ open-loop full-bridge topology can achieve soft switching and has higher efficiency than the traditional topology, it is widely used in the field of switching power supplies.

[0003] The primary and secondary of the existing BUCK+ open-loop full-bridge topology are both controlled by DSP (digital signal processor), including the primary DSP and the secondary DSP. The primary current loop detects the buck inductor current, and the secondary voltage loop detects the output voltage. The two DSPs work together to process. When the input voltage increases, the output voltage also increases. The secondary DSP detects that the output voltage has increased, and the drive duty cycle sent by the secondary DSP to the primary DSP decreases, thereby reducing the output voltage. However, the above-mentioned reduction in output voltage requires a complete loop control to be achieved, that is, after the primary DSP receives the adjustment instruction from the secondary DSP, it takes a certain processing time to respond and adjust its drive duty cycle. The primary DSP cannot quickly adjust the drive duty cycle, and the response speed is slow, which easily leads to large current stress, increasing the risk of MOS tube breakdown and damage, thereby affecting the stability and reliability of the switching power supply.

[0004] The above defects need to be solved urgently. Summary of the invention

[0005] In order to solve the problem of slow response speed of primary-side DSP in the existing BUCK+ open-loop full-bridge topology control method, the present invention provides a primary-secondary dual DSP real-time multiplexing loop control circuit.

[0006] The technical solution of the present invention is as follows:

[0007] A primary-secondary dual DSP real-time multiplex loop control circuit comprises a secondary DSP, a primary DSP, a relay switch circuit, a BUCK / full-bridge power conversion circuit, an input voltage sampling circuit and an output voltage sampling circuit, wherein the input end of the input voltage sampling circuit and the input end of the relay switch circuit are both connected to the input voltage, the primary DSP is respectively connected to the control end of the relay switch circuit, the control end of the BUCK / full-bridge power conversion circuit and the output end of the input voltage sampling circuit, the output end of the BUCK / full-bridge power conversion circuit and the input end of the output voltage sampling circuit are both connected to the output voltage, and the secondary DSP is respectively connected to the output end of the primary DSP and the output voltage sampling circuit;

[0008] The primary-side DSP receives the duty cycle signal output by the secondary-side DSP, and switches the switching power supply between the off state and the on state through the relay switch circuit.

[0009] According to the present invention of the above scheme, when the input voltage sampling circuit detects that the voltage value of the input voltage exceeds the preset voltage value, a control signal is sent to the primary DSP, and the primary DSP reduces the driving duty cycle of the MOS tube that drives the BUCK / full-bridge power conversion circuit to avoid damage to the MOS tube of the BUCK / full-bridge power conversion circuit.

[0010] According to the present invention of the above scheme, when the primary DSP receives a duty cycle signal of 3% or less from the secondary DSP, the primary DSP controls the relay switch circuit to disconnect;

[0011] When the primary-side DSP receives the 5% duty cycle signal sent by the secondary-side DSP, the primary-side DSP controls the relay switch circuit to be turned on.

[0012] According to the above scheme of the present invention, when the primary DSP receives a duty cycle signal of 10% to 90% sent by the secondary DSP, the primary DSP sends a driving signal to the MOS tube of the BUCK / full-bridge power conversion circuit.

[0013] According to the above scheme of the present invention, the input voltage sampling circuit includes a voltage-dividing resistor group, one end of the voltage-dividing resistor group is connected to the sampling point of the input voltage, the other end of the voltage-dividing resistor group is respectively connected to one end of a resistor R138, one end of a resistor R43, and one end of a capacitor C35, the other end of the resistor R138 is respectively connected to the primary DSP and one end of a capacitor C107, the other end of the resistor R43, the other end of the capacitor C35, and the other end of the capacitor C107 are all grounded.

[0014] According to the above scheme of the present invention, the output voltage sampling circuit includes a resistor R315, the resistor R315 is connected to one end of the resistor R311, the other end of the resistor R311 is respectively connected to one end of the resistor R309, one end of the resistor R308, and one end of the resistor R31, the other end of the resistor R309 and the other end of the resistor R308 are both grounded, the other end of the resistor R31 is respectively connected to one end of the capacitor C20 and the secondary side DSP, and the other end of the capacitor C20 is grounded.

[0015] According to the above scheme of the present invention, the relay switch circuit includes an inductor L5 and an inductor L1. The inductor L5 is respectively connected to the input voltage, one end of the capacitor C38, the capacitor C51, the capacitor C79, the capacitor C83, the capacitor C225, and one end of the inductor L1. The other end of the inductor L1 is respectively connected to one end of the relay RLY3, and the other end of the relay RLY3 is connected to the other end of the capacitor C225.

[0016] The present invention according to the above scheme further comprises an isolation IC circuit, wherein the input end of the isolation IC circuit is connected to the secondary DSP, and the output end of the isolation IC circuit is connected to the primary DSP.

[0017] According to the above scheme of the present invention, the isolation IC circuit includes a chip U5, and the chip U5 is respectively connected to one end of the resistor R61, the resistor R163, the primary DSP, and the capacitor C39, and the other end of the resistor R61 is connected to the secondary DSP.

[0018] The present invention according to the above scheme further comprises a Buck current sampling circuit, the input end of the Buck current sampling circuit is connected to the BUCK / full-bridge power conversion circuit, and the output end of the Buck current sampling circuit is connected to the primary side DSP.

[0019] According to the present invention of the above scheme, the Buck current sampling circuit includes an operational amplifier U23, the positive power input terminal of the operational amplifier U23 is connected to one end of the resistor R215, the other end of the resistor R215 is respectively connected to the BUCK / full-bridge power conversion circuit, one end of the capacitor C345, and one end of the capacitor C236, the other end of the capacitor C345 is grounded, the negative power input terminal of the operational amplifier U23 is connected to one end of the resistor R160, the other end of the resistor R160 is respectively connected to the other end of the capacitor C236 and one end of the capacitor C344, the other end of the capacitor C344 is grounded, the positive power terminal of the operational amplifier U23 is connected to one end of the capacitor C348, the other end of the capacitor C348 and the negative power terminal of the operational amplifier U23 are both grounded, and the output end of the operational amplifier U23 is connected to the primary side DSP.

[0020] According to the present invention of the above scheme, the BUCK / full-bridge power conversion circuit includes a BUCK topology buck circuit and a full-bridge topology buck circuit, the input end of the BUCK topology buck circuit is connected to the relay switch circuit, the output end of the BUCK topology buck circuit is respectively connected to the input end of the Buck current sampling circuit and the input end of the full-bridge topology buck circuit, and the output end of the full-bridge topology buck circuit is connected to the input end of the output voltage sampling circuit.

[0021] According to the present invention of the above scheme, the BUCK topology buck circuit includes a MOS tube Q1, the S pole of the MOS tube Q1 is connected to the resistor RS1 and the Buck current sampling circuit, the G pole of the MOS tube Q1 is connected to the drive IC circuit, the D pole of the MOS tube Q1 is respectively connected to one end of the diode D6, one end of the diode D1, and one end of the inductor L2, the other end of the inductor L2 is respectively connected to one end of the capacitor C101 and one end of the capacitor C99, the other end of the diode D6, the other end of the diode D1, the other end of the capacitor C101, and the other end of the capacitor C99 are respectively connected to the relay switch circuit and the full-bridge topology buck circuit.

[0022] According to the above-mentioned solution of the present invention, the driving IC circuit includes a chip U27, and the chip U27 is connected to the S pole of the primary DSP and the MOS tube Q1 respectively.

[0023] According to the above scheme of the present invention, the full-bridge topology buck circuit includes MOS tube Q120, MOS tube Q122, MOS tube Q125, MOS tube Q124, transformer T6, MOS tube Q10, MOS tube Q129, MOS tube Q126, and MOS tube Q127.

[0024] The present invention according to the above scheme has the following beneficial effects:

[0025] In the primary-secondary dual DSP real-time multiplex loop control circuit, the input end of the input voltage sampling circuit is connected to the input voltage, and the primary DSP is connected to the output end of the input voltage sampling circuit. When the input voltage sampling circuit detects that the voltage value of the input voltage exceeds the preset voltage value, a control signal is sent to the primary DSP, and the primary DSP reduces the driving duty cycle of the MOS tube driving the BUCK / full-bridge power conversion circuit to avoid damage to the MOS tube of the BUCK / full-bridge power conversion circuit. The present invention implements input feedforward of the primary DSP through the input voltage sampling circuit, so that the primary DSP can quickly adjust the driving duty cycle and improve the response speed. After adding the input feedforward of the primary DSP, the primary DSP can limit the size of the duty cycle, thereby preventing the MOS tube from being broken down and damaged due to large current stress, thereby making the loop of the switching power supply more stably controlled and improving the stability and reliability of the switching power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 One of the connection block diagrams of the present invention;

[0027] Figure 2 This is the second connection block diagram of the present invention;

[0028] Figure 3 is a circuit diagram of an input voltage sampling circuit;

[0029] Figure 4 is a circuit diagram of a relay switch circuit;

[0030] Figure 5 This is the circuit diagram of the Buck current sampling circuit;

[0031] Figure 6 The circuit diagram of the BUCK / full-bridge power conversion circuit;

[0032] Figure 7 The circuit diagram of the BUCK topology step-down circuit;

[0033] Figure 8 The circuit diagram of the full-bridge topology buck circuit;

[0034] Fig. 9 is a circuit diagram of an output voltage sampling circuit;

[0035] Fig.10 A circuit diagram for isolating an IC circuit;

[0036] Fig.11 One of the circuit diagrams of the driver IC circuit;

[0037] Fig.12 This is the second circuit diagram of the driver IC circuit. DETAILED DESCRIPTION

[0038] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0039] like Figure 1 , Figure 2 As shown, the present invention provides a primary-secondary dual DSP real-time multiplex loop control circuit, including a secondary DSP, a primary DSP, a relay switch circuit, a BUCK / full-bridge power conversion circuit, an input voltage sampling circuit and an output voltage sampling circuit. The input end of the input voltage sampling circuit and the input end of the relay switch circuit are both connected to the input voltage. The primary DSP is respectively connected to the control end of the relay switch circuit, the control end of the BUCK / full-bridge power conversion circuit, and the output end of the input voltage sampling circuit. The output end of the BUCK / full-bridge power conversion circuit and the input end of the output voltage sampling circuit are both connected to the output voltage. The secondary DSP is respectively connected to the primary DSP and the output end of the output voltage sampling circuit. The primary DSP receives the duty cycle signal output by the secondary DSP, and switches the switch power supply between the off state and the on state through the relay switch circuit.

[0040] In this embodiment, the input end of the input voltage sampling circuit is connected to the input voltage, and the primary DSP is connected to the output end of the input voltage sampling circuit. When the input voltage sampling circuit detects that the voltage value of the input voltage exceeds the preset voltage value, a control signal is sent to the primary DSP, and the primary DSP reduces the driving duty cycle of the MOS tube driving the buck / full-bridge power conversion circuit to avoid damage to the MOS tube of the buck / full-bridge power conversion circuit. The present invention implements input feedforward of the primary DSP through the input voltage sampling circuit, so that the primary DSP can quickly adjust the driving duty cycle and improve the response speed. After adding the input feedforward of the primary DSP, the primary DSP can limit the size of the duty cycle, thereby preventing the MOS tube from being broken down and damaged due to large current stress, thereby making the loop of the switching power supply more stably controlled, and improving the stability and reliability of the switching power supply.

[0041] For example, when the input voltage sampling circuit detects that the input voltage suddenly increases by 20%, the secondary DSP sends a duty cycle reduction signal to the primary DSP. Due to the input feedforward of the primary DSP, the primary DSP can limit the duty cycle in advance. The primary DSP then controls the MOS tube by reducing the original duty cycle by 20%.

[0042] In this embodiment, when the primary DSP receives a duty cycle signal of 3% or less from the secondary DSP, the primary DSP controls the relay switch circuit to be disconnected; when the primary DSP receives a duty cycle signal of 5% from the secondary DSP, the primary DSP controls the relay switch circuit to be connected. Specifically, when an abnormality occurs in the circuit, the secondary DSP sends a duty cycle signal of 3% or less to the primary DSP, and the primary DSP controls the relay switch circuit to be disconnected, so that the switching power supply is in a shutdown state, effectively cutting off the power supply, preventing the abnormal current or voltage from further damaging the circuit components, thereby protecting the entire circuit. When the circuit is running normally and no abnormality is reported, the secondary DSP sends a duty cycle signal of 5% to the primary DSP, and the primary DSP controls the relay switch circuit to be connected, so that the switching power supply is in a power-on state, ensuring that the power supply is allowed only when the circuit state is normal, further enhancing the safety and reliability of the system.

[0043] In this embodiment, when the primary DSP receives a 10% to 90% duty cycle signal from the secondary DSP, the primary DSP sends a driving signal to the MOS tube of the BUCK / full-bridge power conversion circuit. Specifically, when the switching power supply is in the on state, the secondary DSP sends a 10% to 90% duty cycle signal to the primary DSP, and the duty cycle signal is sent to the primary DSP as a voltage loop. At the same time, the primary DSP detects the Buck inductor current through the Buck current sampling circuit as feedback of the current inner loop. The voltage outer loop is compared with the current inner loop, and the primary DSP adjusts the driving duty cycle sent to the MOS tube of the BUCK / full-bridge power conversion circuit, so that the switching power supply is in a working state. This control method enables the output voltage and current of the switching power supply to respond quickly to load changes while maintaining small fluctuations, thereby improving the output quality and efficiency of the power supply.

[0044] like Figure 1 , Figure 3 As shown, in this embodiment, the input voltage sampling circuit includes a voltage-dividing resistor group, one end of the voltage-dividing resistor group is connected to the sampling point HV1+ of the input voltage, and the other end of the voltage-dividing resistor group is respectively connected to one end of the resistor R138, one end of the resistor R43, and one end of the capacitor C35, the other end of the resistor R138 is respectively connected to the primary DSP and one end of the capacitor C107, and the other end of the resistor R43, the other end of the capacitor C35, and the other end of the capacitor C107 are all grounded. Specifically, the voltage-dividing resistor group includes resistors R104, R82, R83, R133, R131, R130, R132, R88, R69, and R110 connected in series in sequence, the resistor R104 is connected to the sampling point HV1+ of the input voltage, and the resistor R110 is respectively connected to the resistor R138, the resistor R43, and the capacitor C35. The input voltage is accurately divided by the voltage-dividing resistor group and the signal transmitted to the primary DSP is "VIN_MK". The input voltage sampling circuit can detect the change of the input voltage in real time and transmit the changed voltage signal to the primary DSP in time. The primary DSP can respond quickly according to the received voltage signal and adjust the driving duty cycle of the MOS tube of the BUCK / full-bridge power conversion circuit, thereby achieving stable control of the output voltage, which helps to improve the stability and efficiency of the system. In addition, the voltage-dividing resistor group is composed of multiple resistors connected in series in sequence, which ensures that the input voltage can be divided according to a predetermined ratio, so as to obtain a voltage signal suitable for processing by the primary DSP, which can reduce the direct impact of the input voltage on the primary DSP and protect the DSP from damage by high voltage.

[0045] like Figure 1 , Figure 4As shown, in the present embodiment, the relay switch circuit comprises an inductor L5 and an inductor L1, and the inductor L5 is connected with one end of the input voltage, capacitor C38, capacitor C51, capacitor C79, capacitor C83, capacitor C225, and one end of the inductor L1 respectively, and the other end of the inductor L1 is connected with one end of the relay RLY3 respectively, and the other end of the relay RLY3 is connected with the other end of the capacitor C225. Inductor L5 plays the role of filtering and energy storage in the circuit, helps to stabilize the input voltage and reduce current fluctuations. The primary DSP chip output signal controls the switch state of relay RLY3, thereby realizing the accurate control of the circuit power.

[0046] like Figure 1 , Figure 5 As shown, in this embodiment, the input end of the Buck current sampling circuit is connected to the BUCK / full-bridge power conversion circuit, and the output end of the Buck current sampling circuit is connected to the primary DSP. Specifically, the Buck current sampling circuit includes an operational amplifier U23, the positive power input end of the operational amplifier U23 is connected to one end of the resistor R215, the other end of the resistor R215 is respectively connected to the BUCK / full-bridge power conversion circuit, one end of the capacitor C345, and one end of the capacitor C236, the other end of the capacitor C345 is grounded, the negative power input end of the operational amplifier U23 is connected to one end of the resistor R160, the other end of the resistor R160 is respectively connected to the other end of the capacitor C236 and one end of the capacitor C344, the other end of the capacitor C344 is grounded, the positive power terminal of the operational amplifier U23 is connected to one end of the capacitor C348, the other end of the capacitor C348 and the negative power terminal of the operational amplifier U23 are both grounded, and the output end of the operational amplifier U23 is connected to the primary DSP. By connecting with the BUCK / full-bridge power conversion circuit, the Buck current sampling circuit can accurately sample the current signal on the MOS tube, providing basic data for subsequent current control and protection. In the circuit diagram, the IS-A signal is the current sampling signal on the MOS tube through the BUCK / full-bridge power conversion circuit. The operational amplifier U23 amplifies the signal and generates the IS1 signal to be transmitted to the primary DSP. The operational amplifier U23 amplifies the sampled current signal to reach the level range that the primary DSP can recognize, ensuring the accuracy and reliability of the signal.

[0047] like Figure 2 , Figure 6 As shown, in this embodiment, the BUCK / full-bridge power conversion circuit includes a BUCK topology buck circuit and a full-bridge topology buck circuit. The input end of the BUCK topology buck circuit is connected to the relay switch circuit, the output end of the BUCK topology buck circuit is respectively connected to the input end of the Buck current sampling circuit and the input end of the full-bridge topology buck circuit, and the output end of the full-bridge topology buck circuit is connected to the input end of the output voltage sampling circuit.

[0048] like Figure 2 , Figure 7 As shown, specifically, the BUCK topology buck circuit includes a MOS tube Q1, the S pole of the MOS tube Q1 is connected to the resistor RS1 and the Buck current sampling circuit, the G pole of the MOS tube Q1 is connected to the drive IC circuit, the D pole of the MOS tube Q1 is respectively connected to one end of the diode D6, one end of the diode D1, and one end of the inductor L2, the other end of the inductor L2 is respectively connected to one end of the capacitor C101 and one end of the capacitor C99, the other end of the diode D6, the other end of the diode D1, the other end of the capacitor C101, and the other end of the capacitor C99 are respectively connected to the relay switch circuit and the full-bridge topology buck circuit.

[0049] like Figure 2 , Figure 8 As shown, in this embodiment, the full-bridge topology buck circuit includes a MOS tube Q120, a MOS tube Q122, a MOS tube Q125, a MOS tube Q124, a transformer T6, a MOS tube Q10, a MOS tube Q129, a MOS tube Q126, and a MOS tube Q127. The G pole of the MOS tube Q120 is respectively connected to one end of the resistor R464 and the resistor R103, the S pole of the MOS tube Q120 is respectively connected to the other end of the resistor R103, one end of the resistor R460, one end of the capacitor C306, and the D pole of the MOS tube Q125, the other end of the resistor R460 and the other end of the capacitor C306 are both connected to the transformer T6, the D pole of the MOS tube Q120 is respectively connected to the D pole of the diode D6, the diode D1, the capacitor C101, the capacitor C99, and the MOS tube Q122, the G pole of the MOS tube Q122 is respectively connected to one end of the resistor R464 and the resistor R104, the S pole of the MOS tube Q122 is respectively connected to the other end of the resistor R103, the one end of the resistor R460, the one end of the capacitor C306, and the D pole of the MOS tube Q125. The electrodes are respectively connected to the other end of the resistor R104, the transformer T6, and the D electrode of the MOS tube Q124. The G electrode of the MOS tube Q124 is respectively connected to the resistor R463 and one end of the resistor R105. The S electrode of the MOS tube Q124 is respectively connected to the other end of the resistor R105, the S electrode of the MOS tube Q125, and one end of the resistor R107. The other end of the resistor R107 is respectively connected to the G electrode of the MOS tube Q125 and the resistor R462. The transformer T6 is also respectively connected to the D electrode of the MOS tube Q10, the D electrode of the MOS tube Q129, the D electrode of the MOS tube Q126, and the D electrode of the MOS tube Q127. The S electrode of the MOS tube Q10, the S electrode of the MOS tube Q129, the S electrode of the MOS tube Q126, and the S electrode of the MOS tube Q127 are all connected to one end of the capacitor C44 and one end of the capacitor C156. The other end of the capacitor C44 and the other end of the capacitor C156 are respectively connected to the transformer T6 and the output voltage sampling circuit.

[0050] Working principle of BUCK / full-bridge power conversion circuit: high voltage input VIN+, VIN- is filtered by inductor and capacitor, and opened by relay closure, and then stepped down by BUCK topology MOS tube Q1, diode D1, diode D6, and inductor L2, and then isolated and stepped down by full-bridge topology MOS tube Q120, MOS tube Q122, MOS tube Q125, MOS tube Q124, transformer T6, MOS tube Q10, MOS tube Q129, MOS tube Q126, and MOS tube Q127 to produce low voltage output VOUT. BUCK / full-bridge power conversion circuit realizes the conversion from high voltage to low voltage, provides the required stable power supply for various electronic devices, and through the coordinated work of BUCK topology buck circuit and full-bridge topology buck circuit, the circuit has high efficiency and stability. In addition, multiple MOS tubes and transformers are used to form a complex topology structure, which improves the reliability and flexibility of the circuit.

[0051] like Figure 2 , Fig. 9 As shown, in this embodiment, the output voltage sampling circuit includes a resistor R315, the resistor R315 is connected to one end of the resistor R311, the other end of the resistor R311 is respectively connected to one end of the resistor R309, one end of the resistor R308, and one end of the resistor R31, the other end of the resistor R309 and the other end of the resistor R308 are both grounded, the other end of the resistor R31 is respectively connected to one end of the capacitor C20 and the secondary DSP, and the other end of the capacitor C20 is grounded. The output voltage is divided by the resistor R315, the resistor R311, the resistor R308, and the resistor R309 to transmit the signal VV to the secondary DSP, avoiding the risk of damaging the secondary DSP due to excessive voltage.

[0052] like Figure 2 , Fig.10 As shown, in this embodiment, the primary-secondary dual DSP real-time multiplexing loop control circuit also includes an isolation IC circuit, the input end of the isolation IC circuit is connected to the secondary DSP, and the output end of the isolation IC circuit is connected to the primary DSP. Specifically, the isolation IC circuit includes a chip U5, and the chip U5 is respectively connected to one end of the resistor R61, the resistor R163, the primary DSP, and the capacitor C39, and the other end of the resistor R61 is connected to the secondary DSP. In the circuit, the AGND-P signal is the ground terminal of the primary DSP, the AGND-S is the ground terminal of the secondary DSP, and the SPWM is the pulse duty cycle signal transmitted by the secondary DSP, which is isolated by the chip U5 and transmitted to the primary DSP through SPWM-OUT. The isolation IC circuit can maintain the integrity of the signal. The isolation IC isolates the noise through its internal mechanism to ensure that when the SPWM signal is transmitted from the secondary DSP to the primary DSP, its duty cycle and waveform remain the same without external interference.

[0053] like Figure 2 , Fig.11 , Fig.12 As shown, in this embodiment, the driver IC circuit includes a chip U27, and the chip U27 is connected to the S pole of the primary DSP and the MOS tube Q1 respectively. In the circuit diagram, the chip U22 is the chip of the primary DSP, and the chip U22 sends a driving signal "A-DRV" to drive the MOS tube Q1 through the chip U27. Through the drive of the chip U27, the switching state of the MOS tube Q1 can be more accurately controlled, thereby optimizing the working performance of the circuit, helping to reduce the fluctuation and noise of the circuit, and improving the stability of the entire system.

[0054] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the appended claims of the present invention.

[0055] The above is an exemplary description of the present invention in conjunction with the accompanying drawings. It is obvious that the implementation of the present invention is not limited to the above-mentioned method. As long as various improvements are made by adopting the method concept and technical solution of the present invention, or the concept and technical solution of the present invention are directly applied to other occasions without improvement, they are all within the protection scope of the present invention.

Claims

1. A primary and secondary dual DSP real-time multiplexing loop control circuit, characterized in that: It includes a secondary DSP, a primary DSP, a relay switch circuit, a BUCK / full-bridge power conversion circuit, an input voltage sampling circuit and an output voltage sampling circuit, wherein the input end of the input voltage sampling circuit and the input end of the relay switch circuit are both connected to the input voltage, the primary DSP is respectively connected to the control end of the relay switch circuit, the control end of the BUCK / full-bridge power conversion circuit, and the output end of the input voltage sampling circuit, the output end of the BUCK / full-bridge power conversion circuit and the input end of the output voltage sampling circuit are both connected to the output voltage, and the secondary DSP is respectively connected to the output end of the primary DSP and the output voltage sampling circuit; The primary-side DSP receives the duty cycle signal output by the secondary-side DSP, and switches the switching power supply between the shutdown state and the startup state through the relay switch circuit.

2. The primary-secondary dual DSP real-time multiplexing loop control circuit according to claim 1, characterized in that: When the input voltage sampling circuit detects that the voltage value of the input voltage exceeds the preset voltage value, a control signal is sent to the primary DSP, and the primary DSP reduces the driving duty cycle of the MOS tube driving the BUCK / full-bridge power conversion circuit to avoid damage to the MOS tube of the BUCK / full-bridge power conversion circuit.

3. The primary-secondary dual DSP real-time multiplexing loop control circuit according to claim 1, characterized in that: When the primary DSP receives a duty cycle signal of 3% or less from the secondary DSP, the primary DSP controls the relay switch circuit to disconnect; When the primary-side DSP receives the 5% duty cycle signal sent by the secondary-side DSP, the primary-side DSP controls the relay switch circuit to be turned on.

4. The primary and secondary dual DSP real-time multiplexing loop control circuit according to claim 1, characterized in that: When the primary-side DSP receives a duty cycle signal of 10% to 90% sent by the secondary-side DSP, the primary-side DSP sends a driving signal to the MOS tube of the BUCK / full-bridge power conversion circuit.

5. The primary and secondary dual DSP real-time multiplexing loop control circuit according to claim 1, characterized in that: The input voltage sampling circuit includes a voltage-dividing resistor group, one end of which is connected to the sampling point of the input voltage, and the other end of which is respectively connected to one end of a resistor R138, one end of a resistor R43, and one end of a capacitor C35, the other end of the resistor R138 is respectively connected to the primary DSP and one end of a capacitor C107, and the other end of the resistor R43, the other end of the capacitor C35, and the other end of the capacitor C107 are all grounded.

6. The primary and secondary dual DSP real-time multiplexing loop control circuit according to claim 1, characterized in that: The output voltage sampling circuit includes a resistor R315, and the resistor R315 is connected to one end of a resistor R311. The other end of the resistor R311 is respectively connected to one end of a resistor R309, one end of a resistor R308, and one end of a resistor R31. The other end of the resistor R309 and the other end of the resistor R308 are both grounded. The other end of the resistor R31 is respectively connected to one end of a capacitor C20 and the secondary side DSP. The other end of the capacitor C20 is grounded.

7. The primary and secondary dual DSP real-time multiplexing loop control circuit according to claim 1, characterized in that: The relay switch circuit includes an inductor L5 and an inductor L1. The inductor L5 is respectively connected to the input voltage, capacitor C38, capacitor C51, capacitor C79, capacitor C83, one end of capacitor C225, and one end of the inductor L1. The other end of the inductor L1 is respectively connected to one end of the relay RLY3, and the other end of the relay RLY3 is connected to the other end of the capacitor C225.

8. The primary and secondary dual DSP real-time multiplexing loop control circuit according to claim 1, characterized in that: It also includes an isolation IC circuit, the input end of the isolation IC circuit is connected to the secondary side DSP, and the output end of the isolation IC circuit is connected to the primary side DSP.

9. The primary and secondary dual DSP real-time multiplexing loop control circuit according to claim 1, characterized in that: It also includes a Buck current sampling circuit, the input end of the Buck current sampling circuit is connected to the BUCK / full-bridge power conversion circuit, and the output end of the Buck current sampling circuit is connected to the primary side DSP.

10. The primary and secondary dual DSP real-time multiplexing loop control circuit according to claim 9, characterized in that: The BUCK / full-bridge power conversion circuit includes a BUCK topology buck circuit and a full-bridge topology buck circuit. The input end of the BUCK topology buck circuit is connected to the relay switch circuit. The output end of the BUCK topology buck circuit is respectively connected to the input end of the Buck current sampling circuit and the input end of the full-bridge topology buck circuit. The output end of the full-bridge topology buck circuit is connected to the input end of the output voltage sampling circuit.

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