Mutual inductance elimination system for X-type multi-level converter

Abstract

A multi-phase power inverter for an electric propulsion system includes a plurality of X-type multi-level power converters arranged between a high voltage direct current (DC) power source and an electric machine. Each of the plurality of X-type multi-level power converters is a solid state integrated circuit (IC) including a positive DC power bus, a negative DC power bus, a neutral bus, and a plurality of semiconductor switches disposed in a stacked arrangement. The plurality of semiconductor switches are interconnected via the positive DC power bus, the negative DC power bus, and the neutral bus.

Description

[0001] introduction Concepts described herein generally relate to vehicles that employ an electrified powertrain or propulsion system consisting of a direct current (DC) power source that provides alternating current (AC) electrical power to a multi-phase power inverter to control the operation of one or more electric machines.

[0002] As the trend of transportation electrification rapidly expands toward large-capacity public transportation systems such as electric airplanes, trains, and ships, high-voltage and high-power multilevel inverters (MLI) have attracted attention. MLI inverters such as neutral point clamped (NPC) and T-type inverters provide high voltage and high power operating capabilities, but include stacked DC link capacitors with a neutral point connection with a zero voltage vector. Such a neutral point connection with the stacked DC link capacitors may generate a neutral current oscillating at three times the fundamental frequency, which may cause capacitor voltage unbalance and overvoltage stress on the capacitors and switching devices.

[0003] The multi-phase inverter circuit can generate an inherent power loop in which a high current flows from the DC link capacitor to the high side of the multi-level power inverter, then to the low side of the multi-level power inverter and back. This power loop can generate a magnetic field that forms a parasitic inductance.

[0004] Since multi-phase power inverters operate at higher switching frequencies, even small levels of parasitic inductance may cause problems such as, but not limited to, ringing and / or electromagnetic interference (EMI).

[0005] The current flow path determines the size of the power loop, which determines the size of the generated magnetic field and therefore the size of the parasitic inductance. The current flow path is defined by the topology of the circuit, and therefore the topology of the circuit can affect the size of the parasitic inductance. Summary of the invention

[0006] In view of the above discussion, it is useful to develop a system and method for mutual inductance cancellation of a multi-phase power inverter, which includes a plurality of X-type multilevel power converters, the topology of which reduces parasitic inductance within the multi-phase power inverter and / or within each X-type multilevel power converter.

[0007] Concepts disclosed herein relate to a system for a multiphase power inverter including a plurality of X-type multilevel power converters that achieve mutual inductance cancellation. Such a system can be used in a vehicle with an electrified propulsion system to reduce parasitic inductance within the multiphase power inverter, such as, but not limited to, a motor vehicle with an electrified powertrain or propulsion system, such as an electric vehicle (EV) or a plug-in hybrid electric vehicle (PHEV), or another mobile platform that can be powered by an electric propulsion system.

[0008] Each multiphase power inverter may include a plurality of X-type multilevel power converters disposed between a high voltage direct current (DC) power source and an electric machine. The number of X-type multilevel power converters required is application specific.

[0009] Each X-type multilevel power converter may be configured as a solid-state integrated circuit (IC) comprising a plurality of circuit components, such as but not limited to semiconductor switches and busbars, connected to form an interconnected network through which current may flow. The form of such an interconnected circuit network is referred to as a circuit topology.

[0010] The concepts described herein provide a multiphase power inverter that is advantageously arranged to minimize stray inductance and loop inductance using magnetic field elimination. This includes using magnetic field elimination by arranging a positive bus, a neutral bus, and a negative bus and a plurality of X-type multilevel power converters arranged with solid-state integrated circuits having stacked or layered elements. The arrangement of the X-type multilevel power converter with stacked or layered elements enables single-sided or double-sided cooling to reduce thermal impedance. This configuration can be used to reduce stray inductance, resulting in lower switching losses, less ringing, less electromagnetic interference (EMI), and lower device thermal stress.

[0011] One aspect of the present disclosure may include a multiphase power inverter for an electric drive train, wherein the multiphase power inverter converts high voltage DC electric power into multiphase alternating current (AC) power that is delivered to the electric drive train. The multiphase power inverter includes a plurality of X-type multilevel power converters arranged between a high voltage DC power source and an electric motor. Each of the plurality of X-type multilevel power converters is a solid-state IC, the solid-state IC including: a positive DC power bus; a negative DC power bus; a first neutral bus; a second neutral bus; a first AC bus; a second AC bus; a plurality of semiconductor switches, including a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, a fourth semiconductor switch, a fifth semiconductor switch, a sixth semiconductor switch, a seventh semiconductor switch, and an eighth semiconductor switch; a first power diode and a second power diode; a first heat sink, which is adjacent to the positive DC power bus of the solid-state IC via a first direct bond copper (DBC) substrate; and a second heat sink, which is adjacent to the negative DC power bus of the solid-state IC via a second DBC substrate.

[0012] The first semiconductor switch, the second semiconductor switch, the third semiconductor switch and the fourth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus. The fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch and the eighth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus. The first semiconductor switch is connected to the second semiconductor switch at a first node, the second semiconductor switch is connected to the third semiconductor switch at a second node, the third semiconductor switch is connected to the fourth semiconductor switch at a third node, the fifth semiconductor switch is connected to the sixth semiconductor switch at a fourth node, the sixth semiconductor switch is connected to the seventh semiconductor switch at a fifth node, and the seventh semiconductor switch is connected to the eighth semiconductor switch at a sixth node. The first power diode is connected between the third node and the fourth node, and the second power diode is connected between the first node and the sixth node. The second node is connected to the first AC bus, and the fifth node is connected to the second AC bus.

[0013] Another aspect of the present disclosure may include multiple semiconductor switches, a positive DC power bus, a negative DC power bus, a first AC bus, a second AC bus, a first power diode, and a second power diode arranged into multiple layers, including: a first layer, consisting of a first semiconductor switch arranged coplanarly with a second semiconductor switch, the second semiconductor switch arranged coplanarly with a third semiconductor switch, and the third semiconductor switch arranged coplanarly with a fourth semiconductor switch; a second layer, consisting of a first power diode, a second power diode, a positive DC power bus arranged coplanarly with the first AC bus, and a negative DC power bus arranged coplanarly with the negative AC bus; and a third layer, consisting of a second semiconductor switch arranged coplanarly with the third semiconductor switch, the third semiconductor switch arranged coplanarly with a sixth semiconductor switch, and the sixth semiconductor switch arranged coplanarly with a seventh semiconductor switch; wherein the first layer is arranged in parallel with the second layer, and the second layer is arranged in parallel with the third layer.

[0014] Another aspect of the present disclosure may include the first AC bus being arranged in parallel with the second AC bus.

[0015] Another aspect of the present disclosure may include a positive DC power bus being arranged in parallel with a negative DC power bus.

[0016] Another aspect of the present disclosure may include the positive DC power bus and the negative DC power bus being arranged at a first end of the X-type multilevel power converter, and the first AC bus and the second AC bus being arranged at a second end of the X-type multilevel power converter.

[0017] Another aspect of the present disclosure may include a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, and a fourth semiconductor switch adjacent to a first side of a first DBC substrate, and a first heat sink adjacent to a second side of the first DBC substrate; and a fifth semiconductor switch, a sixth semiconductor switch, a seventh semiconductor switch, and an eighth semiconductor switch adjacent to a first side of a second DBC substrate, and a second heat sink adjacent to a second side of the second DBC substrate.

[0018] Another aspect of the present disclosure may include multiple semiconductor switches, a positive DC power bus, a negative DC power bus, a first AC bus, a second AC bus, a first power diode, and a second power diode arranged into multiple layers, including: a first layer, consisting of the first semiconductor switch, the positive DC power bus, and the first AC bus arranged coplanarly with the second semiconductor switch, the second semiconductor switch is arranged coplanarly with the third semiconductor switch, and the third semiconductor switch is arranged coplanarly with the fourth semiconductor switch; a second layer, consisting of the first power diode and the second power diode; and a third layer, consisting of the second semiconductor switch, the negative DC power bus, and the second AC bus arranged coplanarly with the third semiconductor switch, the third semiconductor switch is arranged coplanarly with the sixth semiconductor switch, and the sixth semiconductor switch is arranged coplanarly with the seventh semiconductor switch; wherein the first layer is arranged in parallel with the second layer, and the second layer is arranged in parallel with the third layer.

[0019] Another aspect of the present disclosure may include the first AC bus being arranged in parallel with the second AC bus.

[0020] Another aspect of the present disclosure may include a positive DC power bus being arranged in parallel with a negative DC power bus.

[0021] Another aspect of the present disclosure may include a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, and a fourth semiconductor switch adjacent to a first side of a first DBC substrate, and a first heat sink adjacent to a second side of the first DBC substrate; and a fifth semiconductor switch, a sixth semiconductor switch, a seventh semiconductor switch, and an eighth semiconductor switch adjacent to a first side of a second DBC substrate, and a second heat sink adjacent to a second side of the second DBC substrate.

[0022] Another aspect of the present disclosure may include an X-type multilevel power converter for a multi-phase electric power inverter, the X-type multilevel power converter being a solid-state integrated circuit (IC), the solid-state IC comprising: a positive DC power bus; a negative DC power bus; a first neutral bus; a second neutral bus; a first AC bus; a second AC bus; a plurality of semiconductor switches, including a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, a fourth semiconductor switch, a fifth semiconductor switch, a sixth semiconductor switch, a seventh semiconductor switch, and an eighth semiconductor switch; a first power diode and a second power diode; a first heat sink adjacent to the positive DC power bus of the solid-state IC via a first direct bond copper (DBC) substrate; and a second heat sink adjacent to the negative DC power bus of the solid-state IC via a second DBC substrate.

[0023] The first semiconductor switch, the second semiconductor switch, the third semiconductor switch and the fourth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus. The fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch and the eighth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus. The first semiconductor switch is connected to the second semiconductor switch at a first node, the second semiconductor switch is connected to the third semiconductor switch at a second node, the third semiconductor switch is connected to the fourth semiconductor switch at a third node, the fifth semiconductor switch is connected to the sixth semiconductor switch at a fourth node, the sixth semiconductor switch is connected to the seventh semiconductor switch at a fifth node, and the seventh semiconductor switch is connected to the eighth semiconductor switch at a sixth node. The first power diode is connected between the third node and the fourth node, and the second power diode is connected between the first node and the sixth node. The second node is connected to the first AC bus, and the fifth node is connected to the second AC bus.

[0024] Another aspect of the present disclosure may include an electrified vehicle having an electric propulsion system, the electric propulsion system including an electric motor configured to provide power to the electric propulsion system, and a multi-phase inverter, the multi-phase inverter including a plurality of X-type multi-level power converters arranged between a high voltage DC power source and the electric machine, wherein each of the plurality of X-type multi-level power converters is a solid-state IC.

[0025] Another aspect of the present disclosure may include a method for performing inductance elimination in a multi-phase power inverter, comprising: arranging a plurality of semiconductor switches into an X-type multi-level stack; assembling the plurality of semiconductor switches arranged into the X-type multi-level stack into a solid-state integrated circuit (IC), the solid-state IC having: a positive DC power bus; a negative DC power bus; and a neutral bus; and interconnecting the plurality of semiconductor switches via the positive DC power bus, the negative DC power bus, and the neutral bus.

[0026] The present disclosure provides the following embodiments.

[0027] 1. A multiphase power inverter for an electric propulsion system, the multiphase power inverter comprising: A plurality of X-type multilevel power converters arranged to transfer electric power between a high voltage direct current (DC) power source and an electric machine, wherein each of the plurality of X-type multilevel power converters is a solid-state integrated circuit (IC), the solid-state IC comprising: Positive DC power bus; Negative DC power bus; First neutral bus; Second neutral bus; a first alternating current (AC) bus; a second AC bus; a plurality of semiconductor switches, including a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, a fourth semiconductor switch, a fifth semiconductor switch, a sixth semiconductor switch, a seventh semiconductor switch, and an eighth semiconductor switch; a first power diode and a second power diode; a first heat sink abutting the positive DC power bus of the solid-state IC via a first direct bond copper (DBC) substrate; and a second heat sink abutting the negative DC power bus of the solid-state IC via a second DBC substrate; and wherein a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, and a fourth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus; wherein a fifth semiconductor switch, a sixth semiconductor switch, a seventh semiconductor switch and an eighth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus; wherein the first semiconductor switch is connected to the second semiconductor switch at a first node, wherein the second semiconductor switch is connected to the third semiconductor switch at a second node, and wherein the third semiconductor switch is connected to the fourth semiconductor switch at a third node; wherein the fifth semiconductor switch is connected to the sixth semiconductor switch at a fourth node, wherein the sixth semiconductor switch is connected to the seventh semiconductor switch at a fifth node, and wherein the seventh semiconductor switch is connected to the eighth semiconductor switch at a sixth node; wherein the first power diode is connected between the third node and the fourth node; wherein the second power diode is connected between the first node and the sixth node; wherein the second node is connected to the first AC bus; and The fifth node is connected to the second AC bus.

[0028] 2. The multiphase power inverter of embodiment 1, wherein the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first AC bus, the second AC bus, the first power diode, and the second power diode are arranged in a plurality of layers, comprising: A first layer, consisting of a first semiconductor switch arranged coplanarly with a second semiconductor switch, the second semiconductor switch arranged coplanarly with a third semiconductor switch, and the third semiconductor switch arranged coplanarly with a fourth semiconductor switch; a second layer consisting of a first power diode, a second power diode, the positive DC power bus arranged coplanar with the first AC bus, and the negative DC power bus arranged coplanar with the negative AC bus; and The third layer is composed of the second semiconductor switch arranged coplanarly with the third semiconductor switch, the third semiconductor switch is arranged coplanarly with the sixth semiconductor switch, and the sixth semiconductor switch is arranged coplanarly with the seventh semiconductor switch; wherein the first layer is arranged parallel to the second layer, and the second layer is arranged parallel to the third layer.

[0029] 3. The multiphase power inverter of embodiment 2, wherein the first AC bus is arranged in parallel with the second AC bus.

[0030] 4. The multiphase power inverter of embodiment 3, wherein the positive DC power bus is arranged in parallel with the negative DC power bus.

[0031] 5. The multiphase power inverter of embodiment 4, wherein the positive DC power bus and the negative DC power bus are arranged at a first end of the X-type multilevel power converter, and wherein a first AC bus and a second AC bus are arranged at a second end of the X-type multilevel power converter.

[0032] 6. The multiphase power inverter of embodiment 2, wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are adjacent to a first side of the first DBC substrate, and the first heat sink is adjacent to a second side of the first DBC substrate; and The fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch and the eighth semiconductor switch are adjacent to the first side of the second DBC substrate, and the second heat sink is adjacent to the second side of the second DBC substrate.

[0033] 7. The multiphase power inverter of embodiment 1, wherein the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first AC bus, the second AC bus, the first power diode, and the second power diode are arranged in a plurality of layers, comprising: a first layer consisting of a first semiconductor switch arranged coplanarly with a second semiconductor switch, the positive DC power bus and a first AC bus, the second semiconductor switch being arranged coplanarly with a third semiconductor switch, the third semiconductor switch being arranged coplanarly with a fourth semiconductor switch; A second layer, consisting of a first power diode and a second power diode; and a third layer, consisting of a second semiconductor switch arranged coplanarly with the third semiconductor switch, the negative DC power bus and a second AC bus, the third semiconductor switch being arranged coplanarly with the sixth semiconductor switch, the sixth semiconductor switch being arranged coplanarly with the seventh semiconductor switch, and The first layer is arranged in parallel with the second layer, and the second layer is arranged in parallel with the third layer.

[0034] 8. The multiphase power inverter of embodiment 7, wherein the first AC bus is arranged in parallel with the second AC bus.

[0035] 9. The multiphase power inverter of embodiment 7, wherein the positive DC power bus is arranged in parallel with the negative DC power bus.

[0036] 10. The multiphase power inverter of embodiment 1, wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are adjacent to a first side of the first DBC substrate, and the first heat sink is adjacent to a second side of the first DBC substrate; and The fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch and the eighth semiconductor switch are adjacent to the first side of the second DBC substrate, and the second heat sink is adjacent to the second side of the second DBC substrate.

[0037] 11. An X-type multilevel power converter for a multiphase electric power inverter, the X-type multilevel power converter comprising: A solid-state integrated circuit (IC) having: positive direct current (DC) power bus; Negative DC power bus; First neutral bus; Second neutral bus; a first alternating current (AC) bus; a second AC bus; a plurality of semiconductor switches interconnected via the positive DC power bus, the negative DC power bus, a first neutral bus, and a second neutral bus, the plurality of semiconductor switches comprising: a first semiconductor switch connected at a first node; a second semiconductor switch connected to the first semiconductor switch at a first node, the first semiconductor switch and the second semiconductor switch being arranged in series between a first AC bus and the positive DC power bus, wherein the first AC bus is connected at the second node; a third semiconductor switch connected at a third node, wherein the second semiconductor switch is connected to the third semiconductor switch at the second node, the second semiconductor switch being arranged in series with the third semiconductor switch between the positive DC power bus and the negative DC power bus; a fourth semiconductor switch connected to the third semiconductor switch at a third node, wherein the third semiconductor switch is arranged in series with the fourth semiconductor switch between the first AC bus and the negative DC power bus; a fifth semiconductor switch connected at the fourth node; a sixth semiconductor switch connected to the fifth semiconductor switch at a fourth node, wherein the fifth semiconductor switch and the sixth semiconductor switch are arranged in series between a second AC bus and the positive DC power bus, wherein the second AC bus is connected to the fifth node; a seventh semiconductor switch connected to the sixth node, wherein the sixth semiconductor switch is connected to the seventh semiconductor switch at the fifth node, the sixth semiconductor switch being arranged in series with the seventh semiconductor switch between the positive DC power bus and the negative DC power bus; an eighth semiconductor switch connected to the seventh semiconductor switch at a sixth node, wherein the seventh semiconductor switch is arranged in series with the eighth semiconductor switch between the second AC bus and the negative DC power bus; a first power diode having a first end connected at the first node, and the first power diode having a second end connected at a sixth node via the first neutral bus; A second power diode has a first end connected to the third node, and the second power diode has a a second end connected at a fourth node by a second neutral bus; a first heat sink abutting the positive DC power bus of the solid-state IC via a first direct bond copper (DBC) substrate; and A second heat sink is adjacent to the negative DC power bus of the solid-state IC via a second DBC substrate.

[0038] 12. The X-type multilevel power converter of embodiment 11, wherein the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first AC bus, the second AC bus, the first power diode, and the second power diode are arranged in a plurality of layers, comprising: A first layer, consisting of a first semiconductor switch arranged coplanarly with a second semiconductor switch, the second semiconductor switch arranged coplanarly with a third semiconductor switch, and the third semiconductor switch arranged coplanarly with a fourth semiconductor switch; a second layer consisting of a first power diode, a second power diode, the positive DC power bus arranged coplanar with the first AC bus, and the negative DC power bus arranged coplanar with the negative AC bus; and The third layer is composed of the second semiconductor switch arranged coplanarly with the third semiconductor switch, the third semiconductor switch is arranged coplanarly with the sixth semiconductor switch, and the sixth semiconductor switch is arranged coplanarly with the seventh semiconductor switch, wherein the first layer is arranged parallel to the second layer, and the second layer is arranged parallel to the third layer.

[0039] 13. The X-type multilevel power converter according to embodiment 12, wherein the first AC bus is arranged in parallel with the second AC bus.

[0040] 14. The X-type multi-level power converter according to embodiment 13, wherein the positive DC power bus is arranged in parallel with the negative DC power bus.

[0041] 15. An X-type multilevel power converter according to embodiment 14, wherein the positive DC power bus and the negative DC power bus are arranged at a first end of the X-type multilevel power converter, and wherein a first AC bus and a second AC bus are arranged at a second end of the X-type multilevel power converter.

[0042] 16. The X-type multilevel power converter of embodiment 12, wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are adjacent to a first side of the first DBC substrate, and the first heat sink is adjacent to a second side of the first DBC substrate; and The fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch and the eighth semiconductor switch are adjacent to the first side of the second DBC substrate, and the second heat sink is adjacent to the second side of the second DBC substrate.

[0043] 17. The X-type multilevel power converter of embodiment 11, wherein the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first AC bus, the second AC bus, the first power diode, and the second power diode are arranged in a plurality of layers, comprising: a first layer consisting of a first semiconductor switch arranged coplanarly with a second semiconductor switch, the positive DC power bus and a first AC bus, the second semiconductor switch being arranged coplanarly with a third semiconductor switch, the third semiconductor switch being arranged coplanarly with a fourth semiconductor switch; A second layer, consisting of a first power diode and a second power diode; and The third layer is composed of the second semiconductor switch arranged coplanarly with the third semiconductor switch, the negative DC power bus and the second AC bus, the third semiconductor switch is arranged coplanarly with the sixth semiconductor switch, and the sixth semiconductor switch is arranged coplanarly with the seventh semiconductor switch, wherein the first layer is arranged parallel to the second layer, and the second layer is arranged parallel to the third layer.

[0044] 18. The X-type multilevel power converter according to embodiment 17, wherein the first AC bus is arranged in parallel with the second AC bus.

[0045] 19. The X-type multi-level power converter according to embodiment 17, wherein the positive DC power bus is arranged in parallel with the negative DC power bus.

[0046] 20. An electric vehicle, comprising: Electric propulsion system, including: an electric motor configured to provide power to the electric propulsion system; A multiphase inverter comprising a plurality of X-type multilevel power converters arranged between a high voltage direct current (DC) power source and a motor, wherein each of the plurality of X-type multilevel power converters is a solid-state integrated circuit (IC), the solid-state IC comprising: Positive DC power bus; Negative DC power bus; First neutral bus; Second neutral bus; a first alternating current (AC) bus; a second AC bus; a plurality of semiconductor switches interconnected via the positive DC power bus, the negative DC power bus, a first neutral bus, and a second neutral bus, the plurality of semiconductor switches comprising: a first semiconductor switch connected at a first node; a second semiconductor switch connected to the first semiconductor switch at a first node, the first semiconductor switch and the second semiconductor switch being arranged in series between a first AC bus and the positive DC power bus, wherein the first AC bus is connected at the second node; a third semiconductor switch connected at a third node, wherein the second semiconductor switch is connected to the third semiconductor switch at the second node, the second semiconductor switch being arranged in series with the third semiconductor switch between the positive DC power bus and the negative DC power bus; a fourth semiconductor switch connected to the third semiconductor switch at a third node, wherein the third semiconductor switch is arranged in series with the fourth semiconductor switch between the first AC bus and the negative DC power bus; a fifth semiconductor switch connected at the fourth node; a sixth semiconductor switch connected to the fifth semiconductor switch at a fourth node, wherein the fifth semiconductor switch and the sixth semiconductor switch are arranged in series between a second AC bus and the positive DC power bus, wherein the second AC bus is connected to the fifth node; a seventh semiconductor switch connected to the sixth node, wherein the sixth semiconductor switch is connected to the seventh semiconductor switch at the fifth node, the sixth semiconductor switch being arranged in series with the seventh semiconductor switch between the positive DC power bus and the negative DC power bus; an eighth semiconductor switch connected to the seventh semiconductor switch at a sixth node, wherein the seventh semiconductor switch is arranged in series with the eighth semiconductor switch between the second AC bus and the negative DC power bus; a first power diode having a first end connected at the first node, and the first power diode having a second end connected at a sixth node via the first neutral bus; a second power diode having a first end connected at the third node, and the second power diode having a second end connected at a fourth node via a second neutral bus; a first heat sink abutting the positive DC power bus of the solid-state IC via a first direct bond copper (DBC) substrate; and A second heat sink is adjacent to the negative DC power bus of the solid-state IC via a second DBC substrate.

[0047] The above-mentioned features and advantages of the present disclosure and other features and attendant advantages will become apparent from the following detailed description of illustrative examples and modes for implementing the present disclosure in conjunction with the accompanying drawings and the appended claims. Moreover, the present disclosure explicitly includes combinations and sub-combinations of the elements and features presented above and below. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate implementations of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0049] Figure 1 An electric powertrain system including a multi-phase power inverter arranged between a high voltage direct current (DC) power source and an electric machine according to the present disclosure is schematically illustrated.

[0050] Figure 2 An electric powertrain system including a multi-phase power inverter including a plurality of X-type multi-level power converters arranged between a high voltage DC power source and an electric machine according to the present disclosure is schematically illustrated.

[0051] Figure 3 A circuit diagram of an X-type multi-level power converter according to one aspect of the present disclosure is schematically illustrated.

[0052] Figure 4A A cross-sectional front view of an X-type multi-level power converter according to one aspect of the present disclosure is schematically illustrated.

[0053] Figure 4B Schematically illustrated is a cross-sectional end view of an X-type multi-level power converter according to one aspect of the present disclosure.

[0054] Figure 4C Schematically illustrated is a cross-sectional rear view of an X-type multi-level power converter according to one aspect of the present disclosure.

[0055] Figure 5AA cross-sectional front view of an X-type multi-level power converter according to another aspect of the present disclosure is schematically illustrated.

[0056] Figure 5B Schematically illustrated is a cross-sectional end view of an X-type multi-level power converter according to another aspect of the present disclosure.

[0057] Figure 5C Schematically illustrated is a cross-sectional rear view of an X-type multi-level power converter according to another aspect of the present disclosure.

[0058] The accompanying drawings are not necessarily drawn to scale and may present somewhat simplified representations of various preferred features of the present disclosure as disclosed herein, including, for example, specific dimensions, orientations, locations, and shapes. The details associated with such features will be determined in part by the specific intended application and use environment. DETAILED DESCRIPTION

[0059] As described and illustrated herein, the components of each aspect of the present disclosure can be arranged and designed in various different configurations. Therefore, the following detailed description is not intended to limit the scope of the present disclosure claimed for protection, but is merely to represent possible aspects of the present disclosure. In addition, although numerous specific details are set forth in the following description in order to provide a thorough understanding of each aspect of the present disclosure disclosed herein, some aspects of the present disclosure can be practiced without some of these details. Moreover, for the sake of clarity, some technical materials understood in the relevant art are not described in detail to avoid unnecessarily obscuring the present disclosure. In addition, as illustrated and described herein, the present disclosure can be practiced in the absence of elements not specifically disclosed herein.

[0060] The present disclosure allows for embodiments in many different forms. Representative examples of the present disclosure are shown in the accompanying drawings and are described in detail herein as non-limiting examples of the disclosed principles. For this reason, elements and limitations described herein but not explicitly set forth in the claims shall not be incorporated into the claims individually or collectively by implication, inference or otherwise.

[0061] For the purposes of this description, unless expressly disclaimed, the use of the singular includes the plural, and vice versa, the terms "and" and "or" shall be both conjunctive and disjunctive, and the words "including", "containing", "comprising", "having", etc. shall mean "including but not limited to". Moreover, approximate words (such as "about", "almost", "substantially", "substantially", "approximately", etc.) may be used herein in the sense of "at, close to, or nearly at", or "within 0%-5% of...", or "within an acceptable manufacturing tolerance", or their logical combinations.

[0062] As used herein, the term "system" refers to separate or combined mechanical and electrical hardware, software, firmware, electronic control component parts, processing logic and / or processor devices, including but not limited to: application-specific integrated circuits (ASICs), electronic circuits, processors (shared, dedicated or groups) that execute one or more software or firmware programs, (one or more) memory devices that electrically store software or firmware instructions, combinational logic circuits and / or other components that provide the described functionality.

[0063] As used herein, terms such as "vertical", "horizontal", "left", "right", "upper", "lower", "top", "bottom" and similar expressions are non-limiting terms that merely describe the various elements as illustrated in the accompanying drawings and are not intended to limit the scope of the present disclosure.

[0064] As used herein, the term “electric machine” refers to an electric motor / generator device including a rotor and a stator that is capable of converting electrical power to mechanical power and / or converting mechanical power to electrical power through electromagnetic effort.

[0065] Referring to the drawings, wherein like reference numerals refer to the same or similar components throughout the several views, Figure 1 and 2 An electric drive train 100 is schematically illustrated, and is composed of a direct current (DC) power source 101, a multi-phase power inverter 104, a multi-phase rotary electric motor, generator or motor generator (motor) 10, and a torque actuator 120, the operation of which is monitored and controlled by a controller 30. In one aspect of the present disclosure, the electric drive train 100 is arranged to generate torque and transmit the torque to the torque actuator 120 in the form of one or more drive wheels to perform work. The controller 30 executes a control routine to control and manage the operation of the multi-phase power inverter 104. In one aspect of the present disclosure, the electric drive train 100 is provided on an electrified vehicle (schematically illustrated as 20) and is capable of generating traction torque for vehicle propulsion. When disposed on the electric vehicle 20, the electric vehicle 20 may include, but is not limited to, a mobile platform in the form of a commercial vehicle, an industrial vehicle, an agricultural vehicle, a passenger vehicle, an aircraft, a boat, a train, an all-terrain vehicle, a personal mobility device, a robot, etc., to achieve the purposes of the present disclosure. Alternatively, the electric drive train 100 may be an element of a stationary system.

[0066] The controller 30 may be embodied as one or more digital computing devices and may include one or more processors 34 and memory 32. The control routine 36 may be stored as an executable instruction set in the memory 32 and executed by one of the processors 34 of the controller 30. The controller 30 communicates with the multi-phase power inverter 104 to control the operation of the multi-phase power inverter 104 in response to the execution of the control routine 36 to operate the motor 10. The multi-phase power inverter 104 exchanges or delivers electrical power to the motor 10 via a plurality of first AC buses 121 and second AC buses 122.

[0067] The term "controller" and related terms (such as microcontroller, control module, module, control device, control unit, processor and similar terms) refer to one or more combinations of application specific integrated circuit(s) (ASIC), field programmable gate array (FPGA), electronic circuit(s), central processing unit(s), such as microprocessor(s) and associated memory components(s) in the form of temporary and / or non-temporary memory components and storage devices (read-only, programmable read-only, random access, hard drive, etc.). The non-temporary memory components are capable of storing machine-readable instructions in the form of one or more software or firmware programs or routines, combinational logic circuit(s), input / output circuit(s) and devices, signal conditioning and buffer circuits, and other components accessible by one or more processors to provide the described functionality. The input / output circuit(s) and devices include analog / digital inverters and related devices that monitor inputs from sensors, where such inputs are monitored at a preset sampling frequency or in response to a triggering event. Software, firmware, programs, instructions, control routines, code, algorithms and similar terms mean sets of instructions executable by the controller, including calibration and lookup tables.

[0068] The electric machine 10 includes a cylindrical rotor assembly arranged on a rotor shaft and disposed within an annular stator, wherein the rotor assembly is coaxial with a rotor opening formed in the stator. Other elements of the electric machine 10 (e.g., end caps, bearings, electrical connections, etc.) are included but not shown. The electrical windings of the stator are arranged with a certain number of electrical phases and a certain number of electrical turns per phase. Depending on the specific arrangement, the number of electrical phases can be between 3 and 6, and the number of conductor layers can be between 4 and 12.

[0069] The multi-phase power inverter 104 includes a plurality of semiconductor switches (refer to Figure 310 and the following figures are illustrated), these semiconductor switches are arranged and controllable to convert direct current (DC) electric power into alternating current (AC) electric power, and convert AC electric power into DC electric power using a pulse width modulation signal 108 or another control technique. The multiphase power inverter 104 is arranged and controllable to convert DC electric power originating from a high voltage DC power supply 101 into AC electric power to actuate the motor 10 via electromagnetic force. The motor 10 can be controlled to rotate and generate mechanical torque, which is transmitted to the torque actuator 120 via the rotatable member 12 and the gear train 114 when operating in the torque generation mode. The motor 10 can be controlled to generate AC electric power from the mechanical torque originating from the torque actuator 120 via electromagnetic force, which is converted into DC electric power by the multiphase power inverter 104 to be stored in the high voltage DC power supply 101 when operating in the electric power generation mode. In one aspect of the present disclosure, the torque actuator 120 comprises a vehicle wheel that transmits torque to the ground surface to achieve forward motion as part of a traction propulsion system. The high voltage DC power source 101 may be in the form of a rechargeable electrochemical battery device, a fuel cell, a supercapacitor, and / or another electrical energy storage / generation technology.

[0070] The high voltage DC power source 101 may be a rechargeable electrochemical battery device, a fuel cell, a supercapacitor, and / or another electrical energy storage / generation technology. The high voltage DC power source 101 is connected to a multi-phase power inverter 104 via a high voltage DC bus having a positive link 102 and a negative link 103, and the multi-phase power inverter 104 is connected to the motor 10 via a plurality of first AC buses 121 and a second AC bus 122 to deliver a pulse width modulation signal 108.

[0071] As reference Figure 2 As illustrated, the multiphase power inverter 104 of the electric drive train 100 is composed of a plurality of X-type multilevel power converters 150 disposed between the high voltage DC power source 101 and the motor 10, a DC link capacitor 105 between the multiphase power inverter 104 of the electric drive train 100 and the high voltage DC power source 101, and a respective first AC bus 121 and a second AC bus 122. As illustrated, and in one non-limiting aspect of the present disclosure, the multiphase power inverter 104 of the electric drive train 100 is composed of three X-type multilevel power converters 150.

[0072] Figure 3One of the X-type multilevel power converters 150 is schematically illustrated, which is arranged as a solid-state integrated circuit (IC) having a plurality of semiconductor switches arranged in a stacked or layered arrangement. In one aspect of the present disclosure and as shown, the plurality of semiconductor switches include a first semiconductor switch S1 151, a second semiconductor switch S2 152, a third semiconductor switch S3 153, a fourth semiconductor switch S4 154, a fifth semiconductor switch S5 155, a sixth semiconductor switch S6 156, a seventh semiconductor switch S7 157, and an eighth semiconductor switch S8 158. In one aspect of the present disclosure, at least a portion of the semiconductor switches are field effect transistors (FETs). In one aspect of the present disclosure, the FETs are gallium nitride (GaN) transistors. In one aspect of the present disclosure, at least a portion of the semiconductor switches are insulated gate bipolar transistors (IGBTs).

[0073] Other constituent elements of the X-type multilevel power converter 150 include a positive DC power bus 110, a neutral bus 111, and a negative DC power bus 112. The positive DC power bus 110 is connected to a positive link 102 of a high voltage DC bus, while the negative DC power bus 112 is connected to a negative link 103 of the high voltage DC bus.

[0074] The first semiconductor switch S1 151, the second semiconductor switch S2 152, the third semiconductor switch S3 153 and the fourth semiconductor switch S4 154 are arranged in series between the positive DC power bus 110 and the negative DC power bus 112. This includes: the first semiconductor switch S1 151 is connected to the second semiconductor switch S2 152 at a first node 161; the second semiconductor switch S2 152 is connected to the third semiconductor switch S3 153 at a second node 162; the third semiconductor switch S3 153 is connected to the fourth semiconductor switch S4 154 at a third node 163.

[0075] The fifth semiconductor switch S5 155, the sixth semiconductor switch S6 156, the seventh semiconductor switch S7 157 and the eighth semiconductor switch S8 158 are arranged in series between the positive DC power bus 110 and the negative DC power bus 112. This includes: the fifth semiconductor switch S5 155 is connected to the sixth semiconductor switch S6 156 at the fourth node 164; the sixth semiconductor switch S6 156 is connected to the seventh semiconductor switch S7 157 at the fifth node 165; and the seventh semiconductor switch S7 157 is connected to the eighth semiconductor switch S8 158 at the sixth node 166.

[0076] The first power diode 171 is arranged between the fourth node 164 and the third node 163 , wherein an anode of the first power diode 171 is connected to the fourth node 164 , and a cathode of the first power diode 171 is connected to the third node 163 .

[0077] The second power diode 172 is arranged between the first node 161 and the sixth node 166 , wherein an anode of the second power diode 172 is connected to the sixth node 166 , and a cathode of the second power diode 172 is connected to the first node 161 .

[0078] The first node 161 is connected to the first AC bus 121 to transfer power to the motor 10 (refer to Figure 2 shown).

[0079] The second node 162 is connected to the second AC bus 122 to transfer power to the motor 10 (refer to Figure 2 shown).

[0080] A positive DC power bus 110 , a neutral power bus 111 , and a negative DC power bus 112 are schematically illustrated.

[0081] By configuring the topology within each of the X-type multilevel converters 150 such that both the positive DC power bus 110 and the negative DC power bus 112 are parallel to the neutral bus 111, mutual inductance cancellation minimizes parasitic inductance by coupling the positive mutual inductance and the negative mutual inductance of the commutation loop current within each of the X-type multilevel converters 150.

[0082] According to one aspect of the present disclosure, illustrated as (I), the buses are configured from top 33 to bottom 34 such that the positive DC power bus 110 is parallel to the neutral bus 111 , which is then parallel to the negative DC power bus 112 .

[0083] According to another aspect of the present disclosure, illustrated as (II), the buses are configured from top 33 to bottom 34 such that positive DC power bus 110 is parallel to negative DC power bus 112 , which is then parallel to neutral bus 111 .

[0084] According to another aspect of the present disclosure, illustrated as (III), the buses are configured from top 33 to bottom 34 such that neutral bus 111 is parallel to positive DC power bus 110 , which is then parallel to negative DC power bus 112 .

[0085] According to another aspect of the present disclosure, illustrated as (IV), the positive DC power bus 110 is coplanar with the negative DC power bus 112 , while both the positive DC power bus 110 and the negative DC power bus 112 are parallel to the neutral bus 111 .

[0086] Although several topologies are discussed above, they are merely exemplary and non-limiting aspects of the present disclosure. Therefore, it should be understood that within each of the X-type multilevel converters 150, mutual inductance cancellation minimizes parasitic inductance by coupling the positive mutual inductance and the negative mutual inductance of the commutation loop current within each of the X-type multilevel converters 150, i.e., by configuring the topology of the X-type multilevel inverter 150 so that both the positive DC power bus 110 and the negative DC power bus 112 are parallel to the neutral bus 111.

[0087] Reference now Figure 4A , 4B 4C, the topology of one of the X-type multilevel power converters 150 according to one aspect of the present disclosure is shown and arranged as a multilevel inverter (MLI). In one aspect of the present disclosure, and as described herein, each of the X-type multilevel power converters 150 adopts a neutral-point-less (NPL) MLI topology. Topology refers to the physical arrangement of constituent elements, which include network bus interconnections, dielectrics, semiconductor switches, and other elements.

[0088] The X-type multilevel power converter 150 is arranged as a solid-state integrated circuit (IC) having a plurality of semiconductor switches arranged in a stacked or layered arrangement. According to one aspect of the present disclosure, the plurality of semiconductor switches include a first semiconductor switch S1 151, a second semiconductor switch S2 152, a third semiconductor switch S3 153, a fourth semiconductor switch S4 154, a fifth semiconductor switch S5 155, a sixth semiconductor switch S6 156, a seventh semiconductor switch S7 157, an eighth semiconductor switch S8 158, a first power diode 171, and a second power diode 172.

[0089] According to one aspect of the present disclosure, each semiconductor switch S1-S8 151-158 includes three dies D arranged in parallel with each other. S However, it should be appreciated that each semiconductor switch S1-S8 151-158 may include multiple dies arranged in parallel with each other other than the three dies illustrated, as dictated by each application.

[0090] According to one aspect of the present disclosure, at least a portion of the semiconductor switch is a field effect transistor (FET). According to another aspect of the present disclosure, the FET is a gallium nitride (GaN) transistor. According to another aspect of the present disclosure, at least a portion of the semiconductor switch is an insulated gate bipolar transistor (IGBT).

[0091] According to one aspect of the present disclosure, each power diode 171, 172 includes two dies D arranged in parallel with each other. D However, it should be appreciated that each power diode 171 , 172 may include multiple dies arranged in parallel with each other other than the two dies shown, as determined by each application.

[0092] Other elements of the X-type multilevel power converter 150 include a positive DC power bus 110, a neutral bus 111, a negative DC power bus 112, a first AC bus 121, and a second AC bus 122. The positive DC power bus 110 and the negative DC power bus 112 are arranged at a first end 131 of the X-type multilevel power converter 150. The first AC bus 121 and the second AC bus 122 are arranged at a second end 132 of the X-type multilevel power converter 150, and the second end 132 is opposite to the first end 131.

[0093] The first semiconductor switch S1 151, the second semiconductor switch S2 152, the third semiconductor switch S3 153, the fourth semiconductor switch S4 154, the fifth semiconductor switch S5 155, the sixth semiconductor switch S6 156, the seventh semiconductor switch S7 157, the eighth semiconductor switch S8 158, the first power diode 171 and the second power diode 172 are arranged in a stacked or multi-layer configuration including a first layer 135, a second layer 136 and a third layer 137.

[0094] The first layer 135 includes a first semiconductor switch S1 151 , a second semiconductor switch S2 152 , a third semiconductor switch S3 153 , a fourth semiconductor switch S4 154 , a first heat sink 141 , and a first DBC plate 143 .

[0095] The second layer 136 includes first and second power diodes 171 and 172 , a conductive spacer 146 , a positive DC power bus 110 , a neutral bus 111 , a negative DC power bus, and first and second AC buses 121 and 122 .

[0096] The third layer 137 includes a fifth semiconductor switch S5 155 , a sixth semiconductor switch S6 156 , a seventh semiconductor switch S7 157 , an eighth semiconductor switch S8 158 , a second DBC plate 144 , and a second heat sink 142 .

[0097] Other elements of the X-type multilevel power converter 150 include a positive DC power bus 110, a neutral bus 111, a negative DC power bus, a first AC bus 121, and a second AC bus 122. The positive DC power bus 110 and the negative DC power bus 112 are arranged at a first end 131 of the X-type multilevel power converter 150. The first AC bus 121 and the second AC bus 122 are arranged at a second end 132 of the X-type multilevel power converter 150, and the second end 132 is opposite to the first end 131.

[0098] Reference now Figure 5A , 5B 5C, the topology of one of the X-type multilevel power converters 250 according to another aspect of the present disclosure is shown and arranged as a multilevel inverter (MLI). In another aspect of the present disclosure, and as described herein, each of the X-type multilevel power converters 250 employs a no-neutral-point (NPL) MLI topology.

[0099] The X-type multilevel power converter 250 is arranged as a solid-state integrated circuit (IC) having a plurality of semiconductor switches arranged in a stacked or layered arrangement. According to one aspect of the present disclosure, the plurality of semiconductor switches include a first semiconductor switch S1 251, a second semiconductor switch S2 252, a third semiconductor switch S3 253, a fourth semiconductor switch S4 254, a fifth semiconductor switch S5 255, a sixth semiconductor switch S6 256, a seventh semiconductor switch S7 257, an eighth semiconductor switch S8 258, a first power diode 271, and a second power diode 272. According to one aspect of the present disclosure, at least a portion of the semiconductor switches are field effect transistors (FETs). According to another aspect of the present disclosure, the FETs are gallium nitride (GaN) transistors. According to another aspect of the present disclosure, at least a portion of the semiconductor switches are insulated gate bipolar transistors (IGBTs).

[0100] Other elements of the X-type multilevel power converter 250 include a positive DC power bus 110, a neutral bus 111, a negative DC power bus, a first AC bus 121, and a second AC bus 122. The positive DC power bus 110 and the negative DC power bus 112 are arranged at a first end 231 of the X-type multilevel power converter 250. The first AC bus 121 and the second AC bus 122 are arranged at a second end 232 of the X-type multilevel power converter 250, and the second end 132 is opposite to the first end 231.

[0101] The first semiconductor switch S1 251, the second semiconductor switch S2 252, the third semiconductor switch S3 253, the fourth semiconductor switch S4 254, the fifth semiconductor switch S5 255, the sixth semiconductor switch S6 256, the seventh semiconductor switch S7 257, the eighth semiconductor switch S8 258, the first power diode 271 and the second power diode 272 are arranged in a stacked or multi-layer configuration, which includes a first layer 235, a second layer 236 and a third layer 237.

[0102] The first layer 235 includes a first semiconductor switch S1 251 , a second semiconductor switch S2 252 , a third semiconductor switch S3 253 , a fourth semiconductor switch S4 254 , a first heat sink 241 , and a first DBC plate 243 .

[0103] The second layer 236 includes first and second power diodes 271 and 272 , the positive DC power bus 110 , the neutral bus 111 , the negative DC power bus 112 , the first and second AC buses 121 and 122 .

[0104] The third layer 237 includes a fifth semiconductor switch S5 255 , a sixth semiconductor switch S6 256 , a seventh semiconductor switch S7 257 , an eighth semiconductor switch S8 258 , a second DBC plate 244 , and a second heat sink 242 .

[0105] The illustrated aspects of the present disclosure of an X-type multi-level power converter provide an overlap of the positive DC power bus 110, the neutral bus 111, and the negative DC power bus 112 to reduce mutual inductance. This arrangement includes overlaying the first AC bus 121 on the second AC bus 122 to cancel dV / dt and reduce or eliminate electromagnetic interference, and achieve magnetic field cancellation via P, 0, and N currents to minimize parasitic loops and stray inductance.

[0106] The disclosed concepts and aspects described herein facilitate optimal design of the positive DC power bus 110 , the negative DC power bus 112 , the neutral bus 111 , and the DC link capacitor 105 to achieve mutual inductance cancellation.

[0107] The disclosed concepts and aspects described herein facilitate various heat transfer and cooling systems, including direct cooling, indirect cooling, immersion cooling, single-sided or double-sided cooling.

[0108] The disclosed concepts and aspects described herein facilitate voltage / current overshoot reduction of device stress including die / power modules, bus bars, and DC link capacitors.

[0109] The disclosed concepts and aspects described herein facilitate size reduction and power density increase compared to current systems.

[0110] The disclosed concepts and aspects described herein facilitate the use of lower voltage rated semiconductor switch dies to achieve lower conduction losses and increased EV range compared to current systems.

[0111] The disclosed concepts and aspects described herein facilitate reducing ringing and radiated / conducted electromagnetic interference to other subsystems.

[0112] The disclosed concepts and aspects described herein facilitate higher switching speeds, which can reduce losses and thereby increase vehicle range and current capability.

[0113] These and other benefits of the present disclosure will be appreciated by those skilled in the art in view of the foregoing disclosure.

[0114] The specific implementation and the accompanying drawings are support and description of the present teaching, but the scope of the present teaching is limited only by the claims. Although some best modes and other examples for implementing the present teaching have been described in detail, there are various alternative designs and aspects of the present disclosure to practice the present teaching defined in the appended claims.

Claims

1. A multiphase power inverter for an electric propulsion system, the multiphase power inverter comprising: A plurality of X-type multilevel power converters arranged to transfer electric power between a high voltage direct current (DC) power source and an electric machine, wherein each of the plurality of X-type multilevel power converters is a solid-state integrated circuit (IC), the solid-state IC comprising: Positive DC power bus; Negative DC power bus; First neutral bus; Second neutral bus; a first alternating current (AC) bus; a second AC bus; a plurality of semiconductor switches, including a first semiconductor switch, a second semiconductor switch, a third semiconductor switch, a fourth semiconductor switch, a fifth semiconductor switch, a sixth semiconductor switch, a seventh semiconductor switch, and an eighth semiconductor switch; a first power diode and a second power diode; a first heat sink abutting the positive DC power bus of the solid-state IC via a first direct bond copper (DBC) substrate; and a second heat sink abutting the negative DC power bus of the solid-state IC via a second DBC substrate; and wherein a first semiconductor switch, a second semiconductor switch, a third semiconductor switch and a fourth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus; wherein a fifth semiconductor switch, a sixth semiconductor switch, a seventh semiconductor switch and an eighth semiconductor switch are connected in series between the positive DC power bus and the negative DC power bus; wherein the first semiconductor switch is connected to the second semiconductor switch at a first node, wherein the second semiconductor switch is connected to the third semiconductor switch at a second node, and wherein the third semiconductor switch is connected to the fourth semiconductor switch at a third node; wherein the fifth semiconductor switch is connected to the sixth semiconductor switch at the fourth node, wherein the sixth semiconductor switch is connected to the seventh semiconductor switch at the fifth node, and wherein the seventh semiconductor switch is connected to the eighth semiconductor switch at the sixth node; wherein the first power diode is connected between the third node and the fourth node; wherein the second power diode is connected between the first node and the sixth node; wherein the second node is connected to the first AC bus; and The fifth node is connected to the second AC bus.

2. The multiphase power inverter of claim 1 , wherein the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first AC bus, the second AC bus, the first power diode, and the second power diode are arranged in a plurality of layers, comprising: A first layer, consisting of a first semiconductor switch arranged coplanarly with a second semiconductor switch, the second semiconductor switch arranged coplanarly with a third semiconductor switch, and the third semiconductor switch arranged coplanarly with a fourth semiconductor switch; a second layer consisting of a first power diode, a second power diode, the positive DC power bus arranged coplanarly with the first AC bus, and the negative DC power bus arranged coplanarly with the negative AC bus; as well as A third layer, consisting of a second semiconductor switch arranged coplanarly with a third semiconductor switch, the third semiconductor switch and a sixth semiconductor switch arranged coplanarly, and the sixth semiconductor switch and a seventh semiconductor switch arranged coplanarly; The first layer is arranged in parallel with the second layer, and the second layer is arranged in parallel with the third layer. 3 . The multiphase power inverter of claim 2 , wherein the first AC bus is arranged in parallel with the second AC bus. 4 . The multiphase power inverter of claim 3 , wherein the positive DC power bus is arranged in parallel with the negative DC power bus.

5. The multiphase power inverter of claim 4, wherein the positive DC power bus and the negative DC power bus are arranged at a first end of the X-type multilevel power converter, and wherein a first AC bus and a second AC bus are arranged at a second end of the X-type multilevel power converter.

6. The multiphase power inverter of claim 2, wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are adjacent to a first side of the first DBC substrate, and the first heat sink is adjacent to a second side of the first DBC substrate; and The fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch and the eighth semiconductor switch are adjacent to the first side of the second DBC substrate, and the second heat sink is adjacent to the second side of the second DBC substrate.

7. The multiphase power inverter of claim 1, wherein the plurality of semiconductor switches, the positive DC power bus, the negative DC power bus, the first AC bus, the second AC bus, the first power diode, and the second power diode are arranged in a plurality of layers, comprising: a first layer consisting of a first semiconductor switch arranged coplanarly with a second semiconductor switch, the positive DC power bus and a first AC bus, the second semiconductor switch being arranged coplanarly with a third semiconductor switch, the third semiconductor switch being arranged coplanarly with a fourth semiconductor switch; A second layer, consisting of a first power diode and a second power diode; and a third layer, consisting of a second semiconductor switch arranged coplanarly with a third semiconductor switch, the negative DC power bus and a second AC bus, the third semiconductor switch being arranged coplanarly with a sixth semiconductor switch, the sixth semiconductor switch being arranged coplanarly with a seventh semiconductor switch, and The first layer is arranged in parallel with the second layer, and the second layer is arranged in parallel with the third layer.

8. The multiphase power inverter of claim 7, wherein the first AC bus is arranged in parallel with the second AC bus.

9. The multiphase power inverter of claim 7, wherein the positive DC power bus is arranged in parallel with the negative DC power bus.

10. The multiphase power inverter of claim 1, wherein the first semiconductor switch, the second semiconductor switch, the third semiconductor switch, and the fourth semiconductor switch are adjacent to a first side of the first DBC substrate, and the first heat sink is adjacent to a second side of the first DBC substrate; and The fifth semiconductor switch, the sixth semiconductor switch, the seventh semiconductor switch and the eighth semiconductor switch are adjacent to the first side of the second DBC substrate, and the second heat sink is adjacent to the second side of the second DBC substrate.

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