A topological circuit for photovoltaic inverter matching and control method thereof

Abstract

The present invention discloses a topological circuit for matching a photovoltaic inverter and a control method thereof. The topological circuit comprises a plurality of operational amplifiers, a plurality of MOS transistors, a plurality of resistors, a plurality of connectors, a plurality of capacitors, and a plurality of diodes. Among the plurality of operational amplifiers, an operational amplifier U1 is connected to one end of a resistor R2 and a source of a MOS transistor Q2 in the same phase, to one end of a resistor R3 and a source of a MOS transistor Q1 in the opposite phase, and to the other end of the resistor R3 in the output phase; an operational amplifier U5 is connected to the cathode of a diode D4 in the same phase, to the cathode of a diode D2 in the opposite phase, and to the anode of a diode D2 in the opposite phase; an operational amplifier U6 is connected to the output end and one end of the resistor R1 in the opposite phase; a gate of the MOS transistor Q1 is connected to the gate of the MOS transistor Q2, and a drain is connected to one end of the resistor R4; a drain of the MOS transistor Q2 is connected to the other end of the resistor R1; an anode of the diode D4 is connected to an end of a connector P1; the other end of the resistor R4 is connected to an end of a connector P2; and the other end of the capacitor C1 and the other end of the resistor R2 are grounded.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a topology circuit for photovoltaic inverter matching and a control method thereof. Background Art

[0002] Publication No. CN118100292A discloses a photovoltaic inverter topology circuit, identification method, control system and control method. By arranging multiple DC conversion modules on the input side of the inverter module, when the number of photovoltaic strings is greater than the number of DC conversion modules, the excess photovoltaic strings are connected in parallel, and the input current of the multiple DC conversion modules is balanced through MPPT loop control. Although this method can enable the inverter input end to obtain the required current and voltage, its overall cost and volume are too high, and the photovoltaic components will cause parameter deviation due to light and loss aging, which in turn leads to differences in output current / voltage between each photovoltaic component, increasing the workload of the entire circuit. Summary of the Invention

[0003] In view of the above technical problems, the present invention aims to provide a topological circuit for photovoltaic inverter matching, comprising a plurality of operational amplifiers, a plurality of MOS tubes, a plurality of resistors, a plurality of connectors, a plurality of capacitors, and a plurality of diodes. The operational amplifier U1 in the plurality of operational amplifiers is connected to one end of the resistor R2 and the source of the MOS tube Q2 in the same phase, to one end of the resistor R3 and the source of the MOS tube Q1 in the opposite phase, and to the other end of the resistor R3 in the output phase; the operational amplifier U5 is connected to the cathode of the diode D4 in the same phase, to the cathode of the diode D2 and one end of the capacitor C1 in the opposite phase, and to the anode of the diode D2 in the output phase; the operational amplifier U6 is connected to the output end and the resistor R1 in the opposite phase. One end; the gate of MOS tube Q1 is connected to the gate of MOS tube Q2, and the drain is connected to one end of resistor R4; the drain of MOS tube Q2 is connected to the other end of resistor R1; the anode of diode D4 is connected to the end of connector P1; the other end of resistor R4 is connected to the end of connector P2; the other end of capacitor C1 and the other end of resistor R2 are grounded; the non-inverting end of op amp U3 is connected to the output end of op amp U1, the inverting end is connected to the non-inverting end of op amp U4, the cathode of diode D1, one end of capacitor C4, the drain of MOS tube Q3, and the output end is connected to the anode of diode D1; the inverting end of op amp U4 is connected to the output end and the anode of diode D3; the cathode of diode D3 is connected to the cathode of diode D4; the other end of capacitor C4 is grounded.

[0004] Furthermore, it also includes an AND gate, wherein the operational amplifier U9 among the plurality of operational amplifiers is connected to one end of the resistor R1 in the same phase, to one end of the resistor R16 and the resistor R17 in the opposite phase, and the output end is connected to the first input end of the AND gate U2 and the other end of the resistor R16; the second input end of the AND gate U2 is connected to the connector P3 end, and the output end is connected to the gate of the MOS tube Q1; the other end of the resistor R17 is grounded.

[0005] Furthermore, the source of the MOS transistor Q7 among the plurality of MOS transistors is connected to one end of the resistor R11, the gate is connected to the gate of the MOS transistor Q8 and the end of the connector P3, and the drain is connected to the drain of the MOS transistor Q8, one end of the capacitor C3, and one end of the resistor R12; the source of the MOS transistor Q8 is connected to one end of the resistor R14; the other end of the resistor R11 is connected to the power supply; the other end of the capacitor C3, the resistor R12, and the other end of the resistor R14 are grounded.

[0006] Furthermore, the operational amplifier U8 among the plurality of operational amplifiers is connected to the source of the MOS tube Q8 at the same phase terminal, to the resistor R9 and one end of the resistor R10 at the opposite phase terminal, and to the gate of the MOS tube Q3 at the output terminal; one end of the resistor R15 is connected to the power supply, and the other end is connected to the other end of the resistor R19R19; the other end of the resistor R10 and the source of the MOS tube Q3 are grounded.

[0007] Furthermore, it also includes a triode, wherein the operational amplifier U7 among the plurality of operational amplifiers is connected to the drain of the MOS tube Q6 and one end of the resistor R8 at the same phase terminal, to the other end of the resistor R9 at the opposite phase terminal, and to the gate of the MOS tube Q4 at the output terminal; the drain of the MOS tube Q4 is connected to one end of the capacitor C1; the collector of the triode Q5 is connected to the power supply, the base is connected to the gate of the MOS tube Q6, one end of the resistor R13, and the end of the connector P3, and the emitter is connected to the source of the MOS tube Q6 and one end of the capacitor C2; the other end of the capacitor C2, the source of the MOS tube Q4, the resistor R8, and the other end of the resistor R13 are grounded.

[0008] Furthermore, one end of the resistor R5 among the plurality of resistors is connected to the gate of the MOS transistor Q1 , and the other end is grounded.

[0009] Furthermore, one end of the resistor R6 among the plurality of resistors is connected to the gate of the MOS transistor Q3 , and the other end is grounded.

[0010] Furthermore, one end of the resistor R7 among the plurality of resistors is connected to the gate of the MOS transistor Q4 , and the other end is grounded.

[0011] Furthermore, a control method for photovoltaic inverter matching is provided, the control method comprising the following steps:

[0012] S1. Obtaining initial demand signals and matching signals based on transformer parameters and PV module parameters;

[0013] S2 obtains a matching start signal, and the topology circuit calculates and memorizes the remaining matching signal based on the initial demand memory signal amplitude and the initial matching signal amplitude;

[0014] S3. Get a matching start signal again. If the matching is successful, the topology circuit is automatically reset. If the matching is not successful, the matching signal is recalculated and memorized based on the matching parameters.

[0015] S4. Repeat the matching and repeatedly calculate and memorize the remaining required matching signals until the matching is successful.

[0016] The beneficial effects of the present invention compared with the prior art are:

[0017] The present invention can automatically match and assemble the photovoltaic units in the photovoltaic module based on the required current of the inverter input end and the output current of each photovoltaic component, and can automatically match and assemble the photovoltaic module based on the required voltage of the inverter input end and the output voltage of each photovoltaic unit after matching and assembling, so as to prevent the increase in the workload of the entire circuit caused by the difference in output current / voltage between each photovoltaic component when the photovoltaic component causes parameter deviation due to light and loss aging. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, a brief introduction is given below to the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 This is a circuit structure diagram provided by the present invention. DETAILED DESCRIPTION

[0020] In order to make the objects and advantages of the present invention more clearly understood, the present invention is described in detail below with reference to the embodiments. It should be understood that the following text is only used to describe one or several specific implementation methods of the present invention and does not strictly limit the scope of protection specifically requested by the present invention.

[0021] The present invention discloses a topological circuit for photovoltaic inverter matching, comprising a plurality of operational amplifiers, a plurality of MOS tubes, a plurality of resistors, a plurality of connectors, a plurality of capacitors, and a plurality of diodes. The operational amplifier U1 in the plurality of operational amplifiers is connected to one end of the resistor R2 and the source of the MOS tube Q2 in the same phase, to one end of the resistor R3 and the source of the MOS tube Q1 in the opposite phase, and to the other end of the resistor R3 in the output phase; the operational amplifier U5 is connected to the cathode of the diode D4 in the same phase, to the cathode of the diode D2 and one end of the capacitor C1 in the opposite phase, and to the anode of the diode D2 in the output phase; the operational amplifier U6 is connected to the output end and one end of the resistor R1 in the opposite phase; the MOS tube Q2 is connected to the output end and one end of the resistor R1 in the opposite phase; the MOS tube Q2 is connected to the output end and one end of the resistor R1 in the opposite phase; the MOS tube Q2 is connected to the output end and one end of the resistor R1 in the opposite phase; the MOS tube Q2 is connected to the output end and the source of the resistor R3 ... The gate of tube Q1 is connected to the gate of MOS tube Q2, and the drain is connected to one end of resistor R4; the drain of MOS tube Q2 is connected to the other end of resistor R1; the anode of diode D4 is connected to the end of connector P1; the other end of resistor R4 is connected to the end of connector P2; the other end of capacitor C1 and the other end of resistor R2 are grounded; the non-inverting end of op amp U3 is connected to the output end of op amp U1, the inverting end is connected to the non-inverting end of op amp U4, the cathode of diode D1, one end of capacitor C4, and the drain of MOS tube Q3, and the output end is connected to the anode of diode D1; the inverting end of op amp U4 is connected to the output end and the anode of diode D3; the cathode of diode D3 is connected to the cathode of diode D4; the other end of capacitor C4 is grounded.

[0022] Specifically, it also includes an AND gate. The operational amplifier U9 among the several operational amplifiers is connected to one end of the resistor R1 in the same phase, and is connected to one end of the resistor R16 and the resistor R17 in the opposite phase. The output end is connected to the first input end of the AND gate U2 and the other end of the resistor R16; the second input end of the AND gate U2 is connected to the connector P3, and the output end is connected to the gate of the MOS tube Q1; the other end of the resistor R17 is grounded.

[0023] Specifically, the source of the MOS transistor Q7 among the plurality of MOS transistors is connected to one end of the resistor R11, the gate is connected to the gate of the MOS transistor Q8 and the end of the connector P3, and the drain is connected to the drain of the MOS transistor Q8, one end of the capacitor C3, and one end of the resistor R12; the source of the MOS transistor Q8 is connected to one end of the resistor R14; the other end of the resistor R11 is connected to the power supply; the other end of the capacitor C3, the resistor R12, and the other end of the resistor R14 are grounded.

[0024] Specifically, the operational amplifier U8 among the plurality of operational amplifiers is connected to the source of the MOS tube Q8 in the same phase, connected to the resistor R9 and one end of the resistor R10 in the opposite phase, and connected to the gate of the MOS tube Q3 at the output end; one end of the resistor R15 is connected to the power supply, and the other end is connected to the other end of the resistor R19R19; the other end of the resistor R10 and the source of the MOS tube Q3 are grounded.

[0025] Specifically, it also includes a triode. The operational amplifier U7 among the several operational amplifiers is connected to the drain of the MOS tube Q6 and one end of the resistor R8 at the same phase terminal, to the other end of the resistor R9 at the opposite phase terminal, and to the gate of the MOS tube Q4 at the output terminal; the drain of the MOS tube Q4 is connected to one end of the capacitor C1; the collector of the triode Q5 is connected to the power supply, the base is connected to the gate of the MOS tube Q6, one end of the resistor R13, and the end of the connector P3, and the emitter is connected to the source of the MOS tube Q6 and one end of the capacitor C2; the other end of the capacitor C2, the source of the MOS tube Q4, the resistor R8, and the other end of the resistor R13 are grounded.

[0026] Specifically, one end of the resistor R5 among the plurality of resistors is connected to the gate of the MOS transistor Q1 , and the other end is grounded.

[0027] Specifically, one end of the resistor R6 among the plurality of resistors is connected to the gate of the MOS transistor Q3 , and the other end is grounded.

[0028] Specifically, one end of the resistor R7 among the plurality of resistors is connected to the gate of the MOS transistor Q4 , and the other end is grounded.

[0029] Specifically, a control method for photovoltaic inverter matching includes the following steps:

[0030] S1. Obtaining initial demand signals and matching signals based on transformer parameters and PV module parameters;

[0031] S2 obtains a matching start signal, and the topology circuit calculates and memorizes the remaining matching signal based on the initial demand memory signal amplitude and the initial matching signal amplitude;

[0032] S3. Get a matching start signal again. If the matching is successful, the topology circuit is automatically reset. If the matching is not successful, the matching signal is recalculated and memorized based on the matching parameters.

[0033] S4. Repeat the matching and repeatedly calculate and memorize the remaining required matching signals until the matching is successful.

[0034] The photovoltaic unit is composed of several photovoltaic components connected in parallel. The number of parallel connections is determined by the output current of each photovoltaic component and the required input current of the inverter. The photovoltaic module is composed of several photovoltaic units connected in series. The number of photovoltaic units in series is determined by the output voltage of each photovoltaic unit and the required input voltage of the inverter. Before the matching and assembly of the photovoltaic modules, the photovoltaic units are matched and assembled first. A matching module is set in the topology circuit. When the photovoltaic units / photovoltaic modules are initially matched and assembled, the matching module feeds back an initial demand signal to the connector P1 on the topology circuit based on the demand current / demand voltage at the inverter input end. The amplitude of the initial demand signal is the middle value of the allowable deviation range of the demand current / demand voltage at the inverter input end. Connector P1 on the topology circuit Obtain the demand signal, and the connector P2 obtains the matching signal. If the photovoltaic unit is assembled, when the topology circuit obtains the signal feedback from the connector P1 end once, the first memory end on the topology circuit automatically memorizes the signal, and then the matching module selects the photovoltaic component with the largest output current among all photovoltaic components and feeds back the corresponding matching signal to the connector P2 on the topology circuit based on its output current. This signal is the initial matching current signal. If the photovoltaic module is assembled, the signal obtained by the connector P1 end is the demand voltage signal of the inverter input end. When the topology circuit obtains the signal feedback from the connector P1 end once, the first memory end on the topology circuit automatically memorizes the signal, and then the matching module selects the photovoltaic unit with the largest output voltage among all photovoltaic units and feeds back the corresponding matching signal to the connector P2 on the topology circuit. Based on its output voltage, the corresponding matching signal is fed back to the connector P2 on the topology circuit. The matching signal is the initial matching voltage signal. After the connector P2 end obtains the feedback, the matching module feeds back the matching start signal to the connector P3 on the topology circuit. When the topology circuit obtains the matching start signal, the topology circuit calculates the remaining required matching signals based on the initial required memory signal amplitude and the initial matching signal amplitude. After the calculation is completed, the second memory end of the topology circuit automatically memorizes the signal. When the topology circuit loses the matching start signal, the topology circuit prioritizes clearing the first memory end signal and records the second memory end signal after clearing. After the first matching is completed, the matching module obtains the signal of the first memory end after the first matching is completed. Then the matching module compares the signal amplitudes of the current / voltage output by the remaining photovoltaic modules / photovoltaic units based on the signal amplitude of the first memory end. If there is no photovoltaic module / photovoltaic unit that can be directly matched, the photovoltaic module / photovoltaic unit with the largest output current / voltage is selected again and the corresponding matching signal is fed back to the connector P2 on the topology circuit based on its output current / voltage. When the matching module feeds back a new matching start signal again, the topology circuit gives priority to clearing the second memory end signal. At the same time, the topology circuit calculates the difference between the remaining required matching signals based on the signal amplitude of the first memory end after the first matching and the matching signal amplitude fed back for the second time. After the calculation is completed, the second memory end of the topology circuit automatically memorizes the signal again.When the matching module finishes feeding back the matching signal again, it clears the first memory-end signal and records the second memory-end signal. Successfully matched photovoltaic modules are connected in parallel, and successfully matched photovoltaic units are connected in series. This process is repeated multiple times to complete the formation of photovoltaic units / modules. If the current / voltage amplitude output by the currently matched photovoltaic module / module is consistent with the amplitude of the first memory-end signal after the previous matching, the topology circuit automatically returns to its initial state after the current matching is completed. If, after the last matching, the output current / voltage of the photovoltaic unit / module is within the allowable deviation range of the required current / voltage at the inverter input, the matching unit feedback is higher than the amplitude of the first memory-end signal during the previous matching, resetting the topology circuit. Regularly rematching and forming photovoltaic modules prevents parameter drift due to aging caused by light exposure and wear and tear, and increases in the workload of the entire circuit caused by differences in output current / voltage between photovoltaic modules.

[0035] VCC is the power supply terminal, GND is the ground terminal, and the signal at the connector P1 terminal is fed back to the in-phase terminal of the operational amplifier U5 after passing through the diode D4. When the connector P1 terminal obtains the signal, the output terminal signal of the operational amplifier U5 causes the potential of the capacitor C1 to rise after passing through the diode D2. The signal at the capacitor C1 terminal rises to the same amplitude as the signal at the connector P1 terminal. When the connector P1 terminal loses the signal feedback, the diode D2 prevents reverse flow, and the signal at the capacitor C1 terminal is the first memory terminal signal. The signal at the capacitor C1 terminal is fed back to the in-phase terminal of the operational amplifier U6, and the operational amplifier U6 follows the output capacitor C1 terminal signal. At this time, the first memory terminal signal is the initial required voltage. The first memory signal is fed through resistor R1, the drain and source of MOS transistor Q2, and resistor R2 to the ground terminal. The signal at the resistor R2 terminal is fed back to the non-inverting terminal of the operational amplifier U1. The initial matching current / voltage signal is fed back to the inverting terminal of the operational amplifier U1 through the drain and source of MOS transistor Q1. The output terminal of the operational amplifier U1 is negatively feedback connected to the inverting terminal of the operational amplifier U1 through resistor R3. At this time, the operational amplifier U1 outputs the remaining required matching current / voltage signal, which is the difference between the amplitude of the initial required current / voltage memory signal and the initial matching current / voltage signal.

[0036] The output signal of the operational amplifier U6 is fed back to the non-inverting terminal of the operational amplifier U9. The output signal of the operational amplifier U9 is fed back to the ground terminal through the resistors R16 and R17. The signal at the resistor R17 terminal is fed back to the inverting terminal of the operational amplifier U9 so that the operational amplifier U9 amplifies and outputs the amplitude of the initial memory signal. The output signal of the operational amplifier U9 is fed back to the first input terminal of the AND gate U2. The connector P3 is used to obtain the matching start signal. After the matching module feeds back the initial demand current / demand voltage signal and the matching current signal to the topology circuit, the matching start signal is fed back to the topology circuit again. The signal is fed back to the second input terminal of the AND gate U2 through the connector P3. The AND gate U2 outputs the signal from the output of the AND gate U2, and the signal is fed back to the gates of the MOS tubes Q1 and Q2. The resistor R5 is used to discharge the parasitic capacitance of the gates of the MOS tubes Q1 and Q2. When the AND gate U2 outputs, the voltage difference between the gate of the MOS tube Q1 and the source of the MOS tube Q1 is higher than the conduction threshold, and the MOS tube Q1 is turned on. The voltage difference between the gate of the MOS tube Q2 and the source of the MOS tube Q2 is higher than the conduction threshold, and the MOS tube Q2 is turned on. In this way, the topology circuit enables the op amp U1 to output the remaining required matching current / voltage signal only after obtaining the matching start signal.

[0037] The matching start signal is synchronously fed back to the gate of MOS tube Q7 and the gate of MOS tube Q8. When the connector P3 end does not receive the matching start signal feedback, the power signal passes through the resistor R11, the source of MOS tube Q7, the drain of MOS tube Q7, and the resistor R12 to the ground end. The capacitor C3 end has an initial potential. The power signal passes through the resistor R15, the resistor R9, and the resistor R10 to the ground end. The signal at the resistor R10 end is fed back to the inverting end of the operational amplifier U8. The operational amplifier U8 is cut off. When the connector P3 end receives the matching start signal feedback, the power signal passes through the resistor R11, the source of MOS tube Q7, the drain of MOS tube Q7, and the resistor R12 to the ground end. The capacitor C3 end has an initial potential. The power signal passes through the resistor R15, the resistor R9, and the resistor R10 end to the ground end. The signal at the resistor R10 end is fed back to the inverting end of the operational amplifier U8. The operational amplifier U8 is cut off. When the voltage difference between the gate of MOS tube Q7 and the source of MOS tube Q7 is higher than the conduction threshold, MOS tube Q7 is cut off, the voltage difference between the gate of MOS tube Q8 and the source of MOS tube Q8 is higher than the conduction threshold, MOS tube Q8 is turned on, the potential of capacitor C3 drops, and the signal at the end of capacitor C3 passes through the drain of MOS tube Q8, the source of MOS tube Q8, and resistor R14 to the ground end. The signal at the end of resistor R14 is fed back to the non-inverting end of op amp U8, and op amp U8 outputs. When the amplitude of the signal at the end of capacitor C3 is lower than the amplitude of the signal at the end of resistor R10, Op amp U8 is turned off again, and the output signal of op amp U8 is fed back to the gate of MOS transistor Q3. Resistor R6 is used to discharge the parasitic capacitance of the gate of MOS transistor Q3. When op amp U8 is outputting, the voltage difference between the gate and source of MOS transistor Q3 exceeds the turn-on threshold, MOS transistor Q3 is turned on, and the signal at capacitor C4 reaches the ground terminal through the drain and source of MOS transistor Q3, and then capacitor C4 reaches the ground potential. When op amp U8 is turned off, MOS transistor Q3 is turned off, and the amplitude of the signal at capacitor C4 rises to the amplitude of the signal at the output of op amp U1. The signal at capacitor C4 becomes the second memory terminal signal, which is fed back to the non-inverting terminal of op amp U4. The output of op amp U4 is negatively feedback connected to the inverting terminal of op amp U4. Op amp U4 follows the output signal at capacitor C4. At this time, the second memory terminal signal is the memory signal of the remaining required matching current / voltage signal. Therefore, each time the matching module feeds back a matching start signal, the signal at the second memory terminal is cleared first, and then the remaining required matching current / voltage signal is memorized.

[0038] The output signal of the operational amplifier U4 is fed back to the non-inverting terminal of the operational amplifier U5 through the diode D3. When the signal feedback is obtained at the connector P3, the signal passes through the base of the transistor Q5 and the emitter of the transistor Q5 to increase the potential of the capacitor C2. At the same time, the base of the transistor Q5 and the emitter of the transistor Q5 are forward biased, and the transistor Q5 is turned on. The signal at the connector P3 is synchronously fed back to the gate of the MOS tube Q6. The resistor R13 is used to discharge the parasitic capacitance of the gates of the MOS tubes Q6, Q7, and Q8. When the connector When the P3 terminal loses signal feedback, the voltage difference between the gate of the MOS tube Q6 and the source of the MOS tube Q6 is higher than the conduction threshold, the MOS tube Q6 is turned on, and the signal at the capacitor C2 terminal passes through the source of the MOS tube Q6, the drain of the MOS tube Q6, and the resistor R8 to the ground terminal. The signal at the resistor R8 terminal is fed back to the non-inverting terminal of the operational amplifier U7, and the signal at the resistor R9 terminal is fed back to the inverting terminal of the operational amplifier U7. The operational amplifier U7 outputs. When the signal amplitude at the capacitor C2 terminal is lower than the signal amplitude at the resistor R9 terminal, the operational amplifier U7 is cut off, and the signal at the output terminal of the operational amplifier U7 is fed back to the MOS tube The gate of Q4 and resistor R7 are used to discharge the parasitic capacitance of the gate of MOS transistor Q4. When op amp U7 outputs, the voltage difference between the gate and source of MOS transistor Q4 exceeds the conduction threshold, MOS transistor Q4 is turned on, and the signal at capacitor C1 passes through the drain and source of MOS transistor Q4 to the ground terminal, and then capacitor C1 reaches the ground potential. At this time, the memory signal at the first memory terminal is cleared. When op amp U7 is turned off, the potential at capacitor C1 rises and rises to the potential at capacitor C4. At this time, the memory signal at the first memory terminal is the memory signal of the remaining required matching current / voltage signal. Therefore, after the matching module first feeds back the matching start signal, the initial required current / voltage memory signal memorized at the first memory terminal is cleared, and then the signal amplitude at the second memory terminal is memorized. When the matching module feeds back the matching signal again, the remaining required matching current / voltage signal output by op amp U1 is the difference between the amplitude of the remaining required matching current signal calculated first and the matching current signal fed back second.

[0039] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be encompassed therein. Any reference in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A topology circuit for photovoltaic inverter matching, characterized in that: The present invention comprises a plurality of operational amplifiers, a plurality of MOS tubes, a plurality of resistors, a plurality of connectors, a plurality of capacitors, a plurality of diodes, and an AND gate. The operational amplifier U1 in the plurality of operational amplifiers is connected to one end of the resistor R2 and the source of the MOS tube Q2 in the same phase, and is connected to one end of the resistor R3 and the source of the MOS tube Q1 in the opposite phase, and the output terminal is connected to the other end of the resistor R3; the operational amplifier U5 is connected to the cathode of the diode D4 in the same phase, and is connected to the cathode of the diode D2 and the drain of the MOS tube Q4 in the opposite phase, and the output terminal is connected to the anode of the diode D2; the output terminal of the operational amplifier U6 is connected to the cathode of the diode D2 and the drain of the capacitor C1 and the drain of the MOS tube Q4 in the opposite phase. One end of R1; the gate of MOS transistor Q1 is connected to the gate of MOS transistor Q2, and the drain is connected to one end of resistor R4; the drain of MOS transistor Q2 is connected to the other end of resistor R1; the anode of diode D4 is connected to the end of connector P1; the other end of resistor R4 is connected to the end of connector P2; the other end of capacitor C1 and the other end of resistor R2 are grounded; the non-inverting end of op amp U3 is connected to the output end of op amp U1, the inverting end is connected to the non-inverting end of op amp U4, the cathode of diode D1, one end of capacitor C4, the drain of MOS transistor Q3, and the output end is connected to the anode of diode D1; the inverting end of op amp U4 is connected to the output end and the anode of diode D3; The cathode of diode D3 is connected to the cathode of diode D4; the op amp U9 is connected to one end of resistor R1 in the same phase, and to one end of resistor R16 and resistor R17 in the opposite phase. The output end is connected to the first input end of AND gate U2 and the other end of resistor R16; the second input end of AND gate U2 is connected to the end of connector P3, and the output end is connected to the gate of MOS tube Q1; the other end of resistor R17, the other end of capacitor C4, the source of MOS tube Q4, and the source of MOS tube Q3 are grounded.

2. The topology circuit for photovoltaic inverter matching according to claim 1, characterized in that: Among the plurality of MOS transistors, the source of the MOS transistor Q7 is connected to one end of the resistor R11, the gate is connected to the gate of the MOS transistor Q8 and the end of the connector P3, and the drain is connected to the drain of the MOS transistor Q8, one end of the capacitor C3, and one end of the resistor R12; the source of the MOS transistor Q8 is connected to one end of the resistor R14; the other end of the resistor R11 is connected to the power supply; the other end of the capacitor C3, the resistor R12, and the other end of the resistor R14 are grounded.

3. The topology circuit for photovoltaic inverter matching according to claim 2, characterized in that: The operational amplifier U8 among the plurality of operational amplifiers is connected to the source of the MOS tube Q8 in the same phase terminal, to one end of the resistor R9 and the resistor R10 in the opposite phase terminal, and to the gate of the MOS tube Q3 in the output terminal; one end of the resistor R15 is connected to the power supply, and the other end is connected to the other end of the resistor R19; the other end of the resistor R10 is grounded.

4. The topology circuit for photovoltaic inverter matching according to claim 1, characterized in that: It also includes a triode, wherein the operational amplifier U7 among the plurality of operational amplifiers is connected at the same phase to the drain of the MOS transistor Q6 and one end of the resistor R8, at the opposite phase to the other end of the resistor R9, and at the output end to the gate of the MOS transistor Q4; the drain of the MOS transistor Q4 is connected to one end of the capacitor C1; the collector of the triode Q5 is connected to the power supply, the base is connected to the gate of the MOS transistor Q6, one end of the resistor R13, and the end of the connector P3, and the emitter is connected to the source of the MOS transistor Q6 and one end of the capacitor C2; the other end of the capacitor C2, the source of the MOS transistor Q4, the resistor R8, and the other end of the resistor R13 are grounded.

5. The topology circuit for photovoltaic inverter matching according to claim 1, characterized in that: One end of the resistor R5 among the plurality of resistors is connected to the gate of the MOS transistor Q1 , and the other end is grounded.

6. The topology circuit for photovoltaic inverter matching according to claim 3, characterized in that: One end of the resistor R6 among the plurality of resistors is connected to the gate of the MOS transistor Q3 , and the other end is grounded.

7. The topology circuit for photovoltaic inverter matching according to claim 4, characterized in that: One end of the resistor R7 among the plurality of resistors is connected to the gate of the MOS transistor Q4 , and the other end is grounded.

8. A control method for photovoltaic inverter matching, characterized in that: The control method has the topology circuit described in any one of claims 1 to 7, and the control method comprises the following steps: S1. Obtaining initial demand signals and matching signals based on transformer parameters and PV module parameters; S2 obtains a matching start signal, and the topology circuit calculates and memorizes the remaining matching signal based on the initial demand memory signal amplitude and the initial matching signal amplitude; S3. Get a matching start signal again. If the matching is successful, the topology circuit is automatically reset. If the matching is not successful, the matching signal is recalculated and memorized based on the matching parameters. S4. Repeat the matching and repeatedly calculate and memorize the remaining required matching signals until the matching is successful.

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