Demand-oriented dynamic high-gain amplification circuit and Pipeline SAR ADC (Synthetic Aperture Radar Analog to Digital Converter)

Abstract

The invention belongs to the field of analog circuits, and particularly relates to a demand-oriented dynamic high-gain amplification circuit and a Pipeline SAR ADC (Synthetic Aperture Radar Analog to Digital Converter). The circuit comprises a front-end dynamic amplifier with adjustable output gain and a CR-CLS circuit, wherein the CR-CLS circuit is composed of CLS capacitors C7 and C8, trimming capacitors C9 and C10, and CMOS switches K25-K38. The topological structures of a CLS capacitor and a trimming capacitor in the front-end dynamic amplifier and the CR-CLS circuit in the circuit can be dynamically adjusted and matched with each other in the mode switching process of integral-estimation and integral-level shift, and then the gain and the amplitude of the final output of the circuit are optimized. The gain matching of the front-end dynamic amplifier optimizes the open-loop gain performance and the closed-loop gain precision of the circuit under an advanced process; the trimming capacitor introduced by the CR-CLS effectively reduces non-ideal factors in the switched capacitor integrating circuit, and the integrating error is reduced.

Description

Technical Field

[0001] The invention belongs to the field of analog circuits, and in particular relates to a demand-oriented dynamic high-gain amplifier circuit and a Pipeline SAR ADC. Background Art

[0002] Pipeline SAR ADC requires the design of high-gain and high-bandwidth op amps to amplify the residual output voltage of the front-end SAR ADC to match the quantization range of the back-end SAR ADC. However, with advanced processes, it is becoming increasingly challenging to implement op amps with high gain and high bandwidth. To adapt to advanced processes, various new op amp structures have been proposed to achieve the required performance. However, these new structures require power consumption or stability, which is not conducive to stable operation.

[0003] CLS technology is a general technology that can reduce the error of the op amp caused by limited gain and increase the distortion-free swing. The traditional CLS technology isolates the output node of the op amp from the output node of the switched capacitor circuit through the CLS capacitor, so that the output voltage of the op amp is close to the common-mode voltage; thus, the equivalent input voltage is close to the common-mode voltage, and the open-loop gain is increased to its square. However, due to the charge sharing and actual sampling loss of the CLS capacitor, there is an error between the op amp output voltage and the common-mode voltage after the level shift, resulting in the gain improvement effect not being as expected. Summary of the invention

[0004] In order to solve the problem that the performances such as gain and bandwidth of the existing residual amplifier cannot meet the requirements of Pipeline SAR ADC, the present invention provides a demand-oriented dynamic high-gain amplifier circuit and Pipeline SAR ADC.

[0005] The technical solution provided by the present invention is:

[0006] A demand-oriented dynamic high-gain amplifier circuit includes a front-end dynamic amplifier and a CR-CLS circuit. The front-end dynamic amplifier has an adjustable gain and is used to adjust the input signal IN P , IN N The sampling and reset amplification operations are performed. Among them, the output end of the front-end dynamic amplifier is recorded as OUT2 P OUT2 N ;

[0007] The CR-CLS circuit includes two CLS capacitors C7 and C8, two trimming capacitors C9 and C10, and 14 CMOS switches K25-K38. The circuit connection relationship is: the upper plates of C7 and C9 are connected to OUT2 through K25. P The connection point between the two also serves as the final positive phase output terminal OUT of the dynamic high gain amplifier circuit.P The lower plates of C8 and C10 are connected to OUT2 through K26. N The connection point between the two also serves as the final negative output terminal OUT of the dynamic high-gain amplifier circuit. N The lower board of C7 is connected to OUT through K29, K31, K35 respectively. N OUT2 P , and the common-mode signal input terminal V CM The upper plate of C8 is connected to OUT through K30, K33, and K36 respectively. P OUT2 N 、V CM The lower board of C9 is connected to OUT through K27 and K32 respectively. P and OUT2 P ; The upper plate of C10 is connected to OUT through K28 and K34 respectively N and OUT2 N OUT P and OUT N Connect V through K37 and K38 respectively. CM .

[0008] By synchronously adjusting the switching states of K31-K34 and K25-K30 for the inverted clock signals S7 and S8, the circuit topology of the CR-CLS circuit is switched between "integration-estimation" and "integration-level shift"; and the gain and swing of the final output of the CR-CLS circuit are optimized in combination with the front-end dynamic amplifier gain matching.

[0009] In the demand-oriented dynamic high-gain amplifier circuit provided by the present invention, when K25-K30 is closed and K31-K34 is open, the CR-CLS circuit is used to perform the integration-estimation operation. At this time, the CLS capacitor is connected across the two output nodes of the CR-CLS circuit, and the upper and lower plates of the trimming capacitor are short-circuited, thereby transferring the charge on the sampling capacitor in the front-end dynamic amplifier to the feedback integration capacitor.

[0010] On the contrary, when K25-K30 is disconnected and K31-K34 is closed, the CR-CLS circuit is used to perform integration-level shifting operation. At this time, the residual charge on the sampling capacitor in the front-end dynamic amplifier is further transferred to the feedback integration capacitor, and the trimming capacitor is connected in parallel with the CLS capacitor to correct the capacitance value of the CLS capacitor, compensate for the charge loss of the CLS capacitor due to non-ideal factors, and thus make the closed-loop gain approach the ideal value.

[0011] As a further improvement of the present invention, the trimming capacitor C9 or C10 is composed of a fixed capacitor C trim , 5 controllable capacitors C trim1 ~C trim5; and 5 pairs of CMOS switches K trim1-1 ~K trim5-1 , K trim1-2 ~K trim5-2 The circuit connection relationship of the trimming capacitor is:

[0012] C trim1 ~C trim5 The lower board and C trim The lower board is connected; C trim1 ~C trim5 The upper board is respectively K trim1-1 ~K trim5-1 With C trim Connected to the upper board; C trim1 ~C trim5 The upper and lower boards are also connected by K trim1-2 ~K trim5-2 Directly connected; among them, C trim1 ~C trim5 The ratio of the capacitance value is 1:2:4:8:16. The five-bit adjustment control code controls K trim1-1 ~K trim5-1 and K trim1-2 ~K trim5-2 The switching state of the two CMOS switches connected to the same controllable capacitor is changed, and the switching states of the two CMOS switches connected to the same controllable capacitor are made opposite, thereby adjusting the capacitance value of the trimming capacitor.

[0013] As a further improvement of the present invention, the front-end dynamic amplifier adopts a cascade residual amplifier including a first-stage FIA ​​circuit and a second-stage FIA ​​circuit. Two inverters composed of components with different parameters are used in both the positive-phase path and the negative-phase path in the second-stage FIA ​​circuit. The circuit topology of the positive-phase path and the negative-phase path in the second-stage FIA ​​circuit is synchronously adjusted by the clock signal S8 to achieve matching of the output gain of the second-stage FIA ​​circuit with the input requirements of the CR-CLS circuit in different modes.

[0014] As a further improvement of the present invention, the second-stage FIA ​​circuit is composed of 4 PMOS tubes PM3-PM6, 4 NMOS tubes NM3-NM6, 10 CMOS switches K17-K22, K23-1, K23-2, K24-1, K24-2, and 1 bias capacitor C6; the circuit connection relationship is:

[0015] The upper plate of C6 is connected to VDD through K17, and the lower plate is connected to GND through K18. The sources of PM3 and PM4 are connected to the upper plate of C6 through K19; the sources of NM3 and NM4 are connected to the lower plate of C6 through K20. The gates of PM3, PM5, NM3, and NM5 are connected and serve as the first-stage inverting output terminal OUT1 of the front-end dynamic amplifier. NThe gates of PM4, PM6, NM4, and NM6 are connected and serve as the first-stage positive-phase output terminal OUT1 of the front-end dynamic amplifier. P The drains of PM5 and NM5 are connected and serve as the second-stage positive-phase output terminal OUT2 of the front-end dynamic amplifier. P ; The drains of PM6 and NM6 are connected and serve as the second stage inverting output terminal OUT2 of the front-end dynamic amplifier N ; The drain of PM3 and the source of PM5 are connected to OUT2 through K23-1 P ; The source of NM5 and the drain of NM3 are connected to OUT2 through K23-2 P The drain of PM4 and the source of PM6 are connected to OUT2 through K24-1. N ; The source of NM6 and the drain of NM4 are connected to OUT2 through K24-2 N OUT2 P and OUT2 N Connect V through K21 and K22 respectively. CM Among them, the switch states of K23-1, K23-2, K24-1, and K24-2 are synchronously adjusted by the clock signal S8.

[0016] As a further improvement of the present invention, the first-stage FIA ​​circuit is composed of two PMOS transistors PM0-PM1, two NMOS transistors NM0-NM1, six CMOS switches K11-K16, and one bias capacitor C5. The circuit connection relationship is:

[0017] The upper plate of C5 is connected to VDD through K11, and the lower plate is connected to GND through K12. The sources of PM0 and PM1 are connected to the upper plate of C5 through K13; the sources of NM0 and NM1 are connected to the lower plate of C5 through K14. The gates of PM0 and NM0 are connected and serve as the first stage positive input terminal IN1 of the front-end dynamic amplifier. P The gates of PM1 and NM1 are connected and serve as the first stage inverting input terminal IN1 of the front-end dynamic amplifier. N The drain of PM0 and NM0 is connected to OUT1 N connected; the drain of PM1 and NM0 is connected to OUT1 P Connected to OUT1 N and OUT1 P Also connect V through K15 and K16 respectively CM .

[0018] As a further improvement of the present invention, the front-end dynamic amplifier also includes a sampling and holding circuit. The sampling and holding circuit is composed of two gate voltage bootstrap switches K3 and K4, eight CMOS switches K1, K2, K5-K10, two input sampling capacitors C1 and C2, and two feedback integration capacitors C3 and C4. The circuit connection is:

[0019] The upper plate of C1 is connected to IN through K3 and K9 respectively. P and V CM ; The upper plate of C2 is connected to IN through K4 and K10 respectively N and V CM ; The lower plate of C1 is connected to IN1 through K7 and K1 respectively P and V CM ; The lower plate of C2 is connected to IN1 through K2 and K8 respectively N and V CM ;IN1 P and IN1 N Connect V through K5 and K6 respectively. CM ; C3 is connected to IN1 P and OUT N between; C4 is connected to IN1 N and OUT P between.

[0020] As a further improvement of the present invention, the demand-oriented dynamic high-gain amplifier circuit further includes or is connected to a clock control circuit. The clock control circuit is used to generate clock signals S1, S1D, S2-S8 for controlling the switching states of each CMOS switch or gate voltage bootstrap switch in the front-end comparator and the CR-CLS circuit.

[0021] Among them, S1 is used to control K1 and K2; S1D is used to control K3~K6; S2 is used to control K9 and K10; S3 is used to control K7 and K8; S4 is used to control K11, K12, K15~K18, K21, K22; S5 is used to control K13, K14, K19, K20; S6 is used to control K35~K38.

[0022] The present invention also includes a Pipeline SAR ADC, which adopts the demand-oriented dynamic high-gain amplifier circuit as described above.

[0023] The technical solution provided by the present invention has the following beneficial effects:

[0024] The present invention uses a front-end dynamic amplifier with adjustable output gain and a CR-CLS circuit with a trimming capacitor to design a demand-oriented high-gain discharge circuit, which can adjust and match the front-end dynamic amplifier performance and the circuit topology of the CR-CLS circuit in different working modes, thereby stably maintaining a higher gain within a wider amplitude range. Therefore, it is very suitable for use in circuits such as Pipeline SAR ADC, and has outstanding performance.

[0025] Compared with the residual amplifier used in the traditional Pipeline SAR ADC, the dynamic high-gain amplifier circuit of the present invention introduces the FIA ​​dynamic amplifier, optimizes the open-loop gain performance and closed-loop gain accuracy of the residual amplifier under advanced technology, and introduces a trimming capacitor into the traditional CLS technology, which effectively reduces the non-ideal factors in the switched capacitor integration circuit and reduces the integration error. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a circuit schematic diagram of a demand-oriented dynamic high-gain amplifier circuit provided in Example 1 of the present invention.

[0027] Figure 2 This is the circuit diagram of the trimming capacitor used in the CR-CLS circuit in the dynamic high-gain amplifier circuit.

[0028] Figure 3 The circuit diagram of the second-stage FIA ​​circuit with adjustable gain used in the front-end dynamic amplifier.

[0029] Figure 4 The circuit diagram of the fixed gain first-stage FIA ​​circuit used in the front-end dynamic amplifier.

[0030] Figure 5 This is a circuit diagram of a CMOS switch used in the demand-oriented dynamic high-gain amplifier circuit provided in Example 1 of the present invention.

[0031] Figure 6 This is a circuit diagram of a gate voltage bootstrap switch used in a demand-oriented dynamic high-gain amplifier circuit provided in Embodiment 1 of the present invention.

[0032] Figure 7 It is a circuit diagram of the demand-oriented dynamic high-gain amplifier circuit in the integration-estimation mode provided in Embodiment 1 of the present invention.

[0033] Figure 8 It is a circuit diagram of the demand-oriented dynamic high-gain amplifier circuit provided in Embodiment 1 of the present invention in the integration-level shift mode.

[0034] Fig. 9This is a circuit schematic diagram of a clock control circuit required for the high-gain amplifier of Example 1 of the present invention.

[0035] Fig.10 The signal flow diagram of the high-gain amplifier designed by the present invention in the performance test experiment.

[0036] Fig.11 This is a curve showing the change of the open-loop gain of the high-gain amplifier designed by the present invention with the output amplitude under different PVT changes based on the CR-CLSFIA structure in the performance test experiment. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0038] Example 1

[0039] This embodiment provides a demand-oriented dynamic high-gain amplifier circuit, which includes a front-end dynamic amplifier and a CR-CLS (charge-redistribution correlated level shifting) circuit. The front-end dynamic amplifier uses an amplifier with adjustable gain, and the front-end dynamic amplifier is used to adjust the input signal IN P , IN N Perform sampling and reset amplification operations; the output OUT2 of the front-end dynamic amplifier P OUT2 N As the input of the CR-CLS circuit. The CR-CLS circuit in this embodiment is a CLS circuit that introduces a trimming capacitor and has an adjustable circuit topology. Among them, the circuit topology of the CR-CLS circuit is switched between the "integration-estimation" mode and the "integration-level shift" mode through a specific clock signal; and while the CR-CLS circuit is switching the mode, the output gain and swing of the front-end dynamic amplifier are adjusted, so that the output performance of the front-end dynamic amplifier matches the performance requirements of the input of the back-end CR-CLS circuit for the signal; and then the final output of the CR-CLS circuit (i.e., OUT P and OUT N ) gain and swing. The output of the dynamic high-gain amplifier circuit can meet the performance requirements of the amplifier circuit in a specific scenario.

[0040] Specifically, Figure 1As shown, in the demand-oriented dynamic high-gain amplifier circuit provided in this embodiment, the designed CR-CLS circuit that introduces trimming capacitors and supports circuit topology adjustment is composed of two CLS capacitors C7 and C8, two trimming capacitors C9 and C10, and 14 CMOS switches K25-K38. The circuit connection relationship is: the upper plates of C7 and C9 are connected to OUT2 through K25. P The connection point between the two also serves as the final positive phase output terminal OUT of the dynamic high gain amplifier circuit. P The lower plates of C8 and C10 are connected to OUT2 through K26. N The connection point between the two also serves as the final negative output terminal OUT of the dynamic high-gain amplifier circuit. N The lower board of C7 is connected to OUT through K29, K31, K35 respectively. N OUT2 P , and the common-mode signal input terminal V CM The upper plate of C8 is connected to OUT through K30, K33, and K36 respectively. P OUT2 N 、V CM The lower board of C9 is connected to OUT through K27 and K32 respectively. P and OUT2 P ; The upper plate of C10 is connected to OUT through K28 and K34 respectively N and OUT2 N OUT P and OUT N Connect V through K37 and K38 respectively. CM .

[0041] in, Figure 1 The CMOS switches K31 to K34 in the CR-CLS circuit are switched by the same timing control signal, and the switch states of the four switches are switched synchronously. In this embodiment, the timing control signal for controlling K31 to K34 is recorded as S8. In addition, in the CR-CLS circuit, the switch states of the CMOS switches K35 to K38 are also switched synchronously by the same clock signal, which is recorded as S6; the switch states of the CMOS switches K25 to K30 are also switched synchronously by the same clock signal, which is recorded as S7.

[0042] Specifically, for the CR-CLS circuit, the clock signal S6 is a reset signal. Before the CR-CLS circuit enters the integration phase, the CLS capacitors C7 and C8 are restored to the common mode level by controlling the CMOS switches K35-K38 to close. The clock signals S7 and S8 are inversely phased to each other, and together they constitute a mode switching signal for switching the working mode of the CR-CLS circuit between the integration-estimation mode and the integration-level shifting mode.

[0043] When S7 is high and S8 is low, K25-K30 are closed and K31-K34 are open. In this state, the trimming capacitors C9 and C10 are short-circuited; while the CLS capacitors C7 and CLS capacitors C8 are connected across the positive and negative output terminals of the front-end dynamic amplifier. At this time, the CR-CLS circuit is in the integration-estimation mode.

[0044] On the contrary, when S7 is low level and S8 is high level, K25-K30 are opened and K31-K34 are closed. In this state, CLS capacitors C7 and CLS capacitors C8 are flipped, trimming capacitor C9 is connected in parallel with CLS capacitor C7, trimming capacitor C10 is connected in parallel with CLS capacitor C8, and the CR-CLS circuit is in integration-level shifting mode.

[0045] exist Figure 1 In the circuit, the trimming capacitor C9 or C10 is a special capacitor whose capacitance value can be adjusted as needed. In this embodiment, by modifying the capacitance values ​​of the trimming capacitors C9 and C10, the amplifier circuit can effectively cope with the capacitance deviation of the CLS capacitors C7 and C8 caused by different environments, thereby reducing the closed-loop gain error of the discharge circuit. Specifically, in practical applications, the trimming capacitors C9 and C10 can be used as follows Figure 2 Specific scheme shown.

[0046] Figure 2 Each trimming capacitor provided consists of a fixed capacitor C trim , 5 controllable capacitors C trim1 ~C trim5 ; and 5 pairs of CMOS switches K trim1-1 ~K trim5-1 , K trim1-2 ~K trim5-2 The circuit connection relationship of the trimming capacitor is:

[0047] C trim1 ~C trim5 The lower board and C trim The lower board is connected; C trim1 ~C trim5 The upper board is respectively K trim1-1 ~K trim5-1 With C trim Connected to the upper board; C trim1 ~C trim5 The upper and lower boards are also connected by K trim1-2 ~K trim5-2 Directly connected; among them, C trim1 ~C trim5 The ratio of the capacitance values ​​is 1:2:4:8:16.

[0048] In the trimming capacitor of this embodiment, K trim1-1 With K trim1-2 , K trim2-1 With K trim2-2 , K trim3-1 With K trim3-2 , K trim4-1 With K trim4-2 , K trim4-1 With K trim4-2 are inversely proportional to each other, that is, each controllable capacitor C trim1 ~C trim5 Either keep it short or connect it with fixed capacitor C trim In this state, only a five-bit adjustment control code is needed to control K trim1-1 ~K trim5-1 and K trim1-2 ~K trim5-2 The switching states of a total of 10 CMOS switches enable a specified number of controllable capacitors among the 5 controllable capacitors to be connected in parallel with the fixed capacitor, thereby adjusting the overall capacitance value of the trimming capacitor.

[0049] In order to more clearly explain the principle of optimizing the gain and swing of the final output by using different topological structures for the CR-CLS circuit in the dynamic high-gain amplifier circuit provided in this embodiment, the basic circuit function of the front-end dynamic amplifier part is first explained below.

[0050] In combination with the foregoing content, it can be seen that the dynamic high-gain amplifier circuit provided in this embodiment has the following requirements for the front-end dynamic amplifier: the front-end dynamic amplifier should match the gain of the signal input to the CR-CLS circuit when the rear-end CR-CLS circuit switches modes. That is, when the CR-CLS circuit is in the integration-estimation mode, the output of the front-end dynamic amplifier is in a low-gain high-swing state; and when the CR-CLS circuit is in the integration-level shifting mode, the output of the front-end dynamic amplifier is in a high-gain low-swing state.

[0051] In practical applications, there are many types of amplifiers with gain adjustment functions, including single-stage amplifiers and cascaded multi-pole amplifiers, etc. This embodiment can use any of the above-mentioned gain-adjustable amplifiers. However, in a more optimized solution of this embodiment, the front-end dynamic amplifier can be as follows: Figure 1The cascade residual amplifier shown includes a first FIA (Dynamic Floating Inverter Amplifier) ​​circuit and a second-stage FIA ​​circuit. In this two-stage amplifier, a gain adjustment mechanism can be introduced in the post-stage amplifier. For example, two inverters composed of components with different parameters are used in the positive phase path and the negative phase path in the second-stage FIA ​​circuit of this embodiment. In this case, a clock signal capable of switching the CR-CLS mode can be used to synchronously adjust the circuit topology of the positive phase path and the negative phase path in the second-stage FIA ​​circuit, thereby adjusting the output gain and swing of the second-stage FIA ​​circuit, so that the output gain and swing of the front-end cascade residual amplifier match the input requirements of the back-end CR-CLS circuit in different modes.

[0052] Specifically, in a specific solution provided in this embodiment, Figure 3 As shown, the second-stage FIA ​​circuit can be composed of a circuit including 4 PMOS transistors PM3-PM6, 4 NMOS transistors NM3-NM6, 10 CMOS switches K17-K22, K23-1, K23-2, K24-1, K24-2, and 1 bias capacitor C6. The connection relationship of the circuit is:

[0053] The upper plate of C6 is connected to VDD through K17, and the lower plate is connected to GND through K18. The sources of PM3 and PM4 are connected to the upper plate of C6 through K19; the sources of NM3 and NM4 are connected to the lower plate of C6 through K20. The gates of PM3, PM5, NM3, and NM5 are connected and serve as the first-stage inverting output terminal OUT1 of the front-end dynamic amplifier. N The gates of PM4, PM6, NM4, and NM6 are connected and serve as the first-stage positive-phase output terminal OUT1 of the front-end dynamic amplifier. P The drains of PM5 and NM5 are connected and serve as the second-stage positive-phase output terminal OUT2 of the front-end dynamic amplifier. P ; The drains of PM6 and NM6 are connected and serve as the second stage inverting output terminal OUT2 of the front-end dynamic amplifier N ; The drain of PM3 and the source of PM5 are connected to OUT2 through K23-1 P ; The source of NM5 and the drain of NM3 are connected to OUT2 through K23-2 P The drain of PM4 and the source of PM6 are connected to OUT2 through K24-1. N ; The source of NM6 and the drain of NM4 are connected to OUT2 through K24-2 N OUT2 P and OUT2 N Connect V through K21 and K22 respectively. CM .

[0054] In the second-stage FIA ​​circuit, the switch states of K23-1, K23-2, K24-1, and K24-2 are synchronously adjusted by the clock signal S8. The adjustment of the output gain is mainly achieved by adjusting the switch states of the above four CMOS switches by this signal. Specifically, when S8 is at a high level, K23-1, K23-2, K24-1, and K24-2 are disconnected. At this time, the second-stage FIA ​​circuit is in a high-gain, low-swing output mode. On the contrary, when S8 is at a low level, K23-1, K23-2, K24-1, and K24-2 are closed. At this time, the second-stage FIA ​​circuit is in a low-gain, high-swing output mode.

[0055] In the cascaded residual amplifier used in this embodiment, the first stage FIA ​​circuit is an amplifier circuit with fixed performance. This embodiment does not make any requirements on the component composition and circuit structure of this part of the circuit. For example, in a typical solution, Figure 4 As shown, the first-stage FIA ​​circuit can be composed of two PMOS transistors PM0-PM1, two NMOS transistors NM0-NM1, six CMOS switches K11-K16, and one bias capacitor C5. The circuit connection relationship of the circuit is:

[0056] The upper plate of C5 is connected to VDD through K11, and the lower plate is connected to GND through K12. The sources of PM0 and PM1 are connected to the upper plate of C5 through K13; the sources of NM0 and NM1 are connected to the lower plate of C5 through K14. The gates of PM0 and NM0 are connected and serve as the first stage positive input terminal IN1 of the front-end dynamic amplifier. P The gates of PM1 and NM1 are connected and serve as the first stage inverting input terminal IN1 of the front-end dynamic amplifier. N The drain of PM0 and NM0 is connected to OUT1 N connected; the drain of PM1 and NM0 is connected to OUT1 P Connected to OUT1 N and OUT1 P Also connect V through K15 and K16 respectively CM .

[0057] It should be noted that: Figure 1 , Figure 3 and Figure 4 In the cascaded residual amplifier shown in the figure, the two input terminals of the first stage FIA ​​circuit are denoted as IN1 P and IN1 N ; The two output terminals are marked as OUT1 P and OUT1 N ; The two input terminals of the second-stage FIA ​​circuit are OUT1 P and OUT1N ; The two output terminals are marked as OUT2 P and OUT2 N .

[0058] Generally speaking, in order to sample the input signal and reset the amplifier circuit, the front-end dynamic amplifier part of the dynamic high-gain amplifier circuit provided in this embodiment should also include or be connected to a sample-and-hold circuit. Figure 1 As shown, in the typical solution provided by this embodiment, the sampling and holding circuit can be composed of two gate voltage bootstrap switches K3 and K4, eight CMOS switches K1, K2, K5-K10, two input sampling capacitors C1 and C2, and two feedback integration capacitors C3 and C4. Among them, the three input ports of the sampling and holding circuit include the input signal IN P , IN N and a common-mode voltage signal V CM The output of the sample and hold circuit is connected to the input of the first stage FIA ​​circuit, namely: IN1 P and IN1 N . Its circuit connection relationship is:

[0059] The upper plate of C1 is connected to IN through K3 and K9 respectively. P and V CM ; The upper plate of C2 is connected to IN through K4 and K10 respectively N and V CM ; The lower plate of C1 is connected to IN1 through K7 and K1 respectively P and V CM ; The lower plate of C2 is connected to IN1 through K2 and K8 respectively N and V CM ;IN1 P and IN1 N Connect V through K5 and K6 respectively. CM ; C3 is connected to IN1 P and OUT N between; C4 is connected to IN1 N and OUT P between.

[0060] In this embodiment, the circuit diagram of the CMOS switch used is as follows: Figure 5 As shown, the circuit diagram of the gate voltage bootstrap switch used is as follows Figure 6 shown.

[0061] In the front-end dynamic amplifier of this embodiment, the switch states of K1 and K2 are controlled by S1; the switch states of K3 to K6 are controlled by S1D; the switch states of K7 and K8 are controlled by S3; the switch states of K9 and K10 are controlled by S2;

[0062] The switch states of K11, K12, K15-K18, K21, and K22 are controlled by S4. The switch states of K13, K14, K19, and K20 are controlled by S5.

[0063] For the sampling and holding circuit in the front-end dynamic amplifier, when the clock signal S1 and its corresponding delayed clock signal S1D are both at high levels, the inverted delayed clock signal S2 corresponding to the clock signal S1 and the delayed clock signal S3 of S2 are at low levels. At this time, the switches K1, K2, K3, K4, K5, and K6 in the sampling and holding circuit are closed, and the switches K7, K8, K9, and K10 are open. C1 and C2 are sensitive to the input signal IN. P , IN N Sampling is performed to obtain a sampling signal, and a common-mode signal V is input to the first-stage FIA ​​circuit. CM .

[0064] On the contrary, when the clock signal S1 and its corresponding delayed clock signal S1D are both at low levels, the inverted delayed clock signal S2 corresponding to the clock signal S1 and the delayed clock signal S3 corresponding to the clock signal S2 are at high levels. At this time, the switches K7, K8, K9, and K10 in the sample-and-hold circuit are closed, and the switches K1, K2, K3, K4, K5, and K6 are open. The sample-and-hold circuit enters the holding state, and inputs the sampling signal to the first-stage FIA ​​circuit and the second-stage FIA ​​circuit of the subsequent stage.

[0065] Furthermore, combined with the sampling capacitors C1 and C2 in the sampling and holding circuit of the front-end dynamic amplifier, the feedback integration capacitors C3 and C4, the cascade residual amplifier composed of the first-stage FIA ​​circuit and the second-stage FIA ​​circuit, and the CLS capacitors C7 and C8 and the trimming capacitors C9 and C10 in the CR-CLS circuit, it can be known that:

[0066] In the integration-estimation mode, the circuit topology is as follows Figure 7 As shown. At this time, the trimming capacitors C9 and C10 are short-circuited; while the CLS capacitors C7 and C8 are connected across the positive and negative output terminals of the front-end dynamic amplifier. Therefore, the circuit can preliminarily transfer the charges on the sampling capacitors C1 and C22 to the feedback integration capacitors C3 and C4, respectively.

[0067] In the integration-level shifting mode, the circuit topology is as follows Figure 8As shown. At this time, CLS capacitor C7 and CLS capacitor C8 are reversed, trimming capacitor C9 is connected in parallel with CLS capacitor C7, and trimming capacitor C10 is connected in parallel with CLS capacitor C8. Therefore, the circuit can further transfer the residual charge on sampling capacitor C1 and sampling capacitor C2 to feedback integration capacitor C3 and feedback integration capacitor C4 respectively, and compensate for the non-ideal charge loss of CLS in the level shifting stage through the trimming capacitor, thereby making the closed-loop gain of the circuit approach the ideal value and obtaining better amplifier performance.

[0068] Further summarizing the working mode of the high-gain amplifier including the front-end dynamic amplifier and the CR-CLS circuit, it can be found that: the circuit requires a total of 9 clock signals in practical applications, namely S1, S1D, S2, S3, S4, S5, S6, S7 and S8. Among them, the clock signals S1, S1D, and S2 constitute the control signals for switching the two working states of signal sampling and phase holding of the sampling and holding circuit. Among them, the clock signal S1D is a delayed signal of the clock signal S1, and the clock signal S2 and the clock signal S1 satisfy the two-phase non-overlapping relationship. The clock signal S3 is a delayed signal of the clock signal S2. When the clock signal is pulled high, the circuit enters the integration state.

[0069] The clock signals S4 and S5 are control signals acting on the first-stage FIA ​​circuit and the second-stage FIA ​​circuit. The group of signals is used to switch the cascade residual amplifier composed of the first-stage FIA ​​circuit and the second-stage FIA ​​circuit between the reset mode and the amplification mode. Specifically, the clock signal S4 is a reset signal, which is kept at a low level in the sampling stage. After the sampling is completed and before entering the integration stage, the clock signal S4 is pulled high to reset the first-stage FIA ​​circuit and the second-stage FIA ​​circuit. In addition, when the CR-CLS circuit at the back end is in a critical state between the integration-estimation mode and the integration-level shifting mode, the clock signal S4 will also be pulled high, thereby resetting the first-stage FIA ​​circuit and the second-stage FIA ​​circuit. Correspondingly, the clock signal S5 is an amplification signal. When the CR-CLS circuit is in the integration-estimation mode and the integration-level shifting mode, S5 will be pulled high, and the cascade residual amplifier will realize the amplification operation of the input signal.

[0070] Finally, the clock signals S6, S7, and S8 together constitute the control signal for adjusting the working mode of the CR-CLS circuit. Among them, the clock signal S6 is the reset signal of the CR-CLS circuit. After the sampling is completed and before entering the integration stage, the clock signal S6 is pulled high to reset the CR-CLS circuit. S7 and S8 constitute the control signal for switching the integration-estimation and integration-level shift modes of the CR-CLS circuit. When the S7 signal is pulled high and the S8 signal is at a low level, the CR-CLS circuit enters the integration-estimation mode to perform the integration-estimation operation. Conversely, when the S7 signal is at a low level and the S8 signal is pulled high, the clock signal S8 enters the integration-level shift mode to perform the integration-level shift operation.

[0071] In order to provide the 9 control signals required for the circuit operation, the dynamic high-gain amplifier of this embodiment is also designed with a corresponding clock control circuit, which can be used as a part of the dynamic high-gain amplifier circuit provided by this embodiment, or as a peripheral circuit that cooperates with the dynamic high-gain amplifier circuit provided by this embodiment. Among them, considering the phase relationship and delay characteristics between the 9 clock signals output by the clock control circuit, the designed clock control circuit is as follows: Fig. 9 As shown, the circuit includes at least four parts: a delay signal chain circuit, a pulse generation circuit, a two-term non-overlap circuit, and a combinational logic circuit. Finally, the timing control circuit can generate the clock signals S1, S1D, S2, S3, S4, S5, S6, S7, and S8 required for the operation of the sampling and holding circuit, the first-stage FIA ​​circuit, the second-stage FIA ​​circuit, and the CR-CLS circuit according to the input external timing.

[0072] In view of the stable high gain of the dynamic high-gain amplifier provided in this embodiment, this embodiment also provides a Pipeline SAR ADC, which adopts the demand-oriented dynamic high-gain amplifier circuit as described above.

[0073] Performance Testing

[0074] In order to verify the performance of the demand-oriented dynamic high-gain amplifier circuit provided by the present invention, technicians conducted circuit simulation and performance testing. The complete signal flow diagram of the circuit in actual operation is as follows: Fig.10 As shown, Fig.10 The signal flow in the circuit can clearly reflect the phase relationship between the clock signals in different parts of the circuit at different stages of the signal amplification process.

[0075] Furthermore, this experiment also tests the change of the open-loop gain of the circuit based on the CR-CLS FIA structure with the output amplitude under different PVT changes, and compares it with the performance of the traditional CLS-FIA residual amplifier. The experimental data obtained are as follows Fig.11 Analysis Fig.11 It can be found from the data that the circuit provided by the present invention maintains the required worst open-loop gain above 80dB within the required output range (-500mV, 500mV), which is much higher than the performance of the traditional CLS-FIA residual amplifier of about 60dB. This shows that the demand-oriented dynamic high-gain amplifier circuit provided by the present invention can fully meet the requirements of Pipeline SAR ADC circuits for the amplifier to stably maintain high-gain performance.

[0076] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A demand-oriented dynamic high-gain amplifier circuit, characterized in that: It includes a front-end dynamic amplifier with adjustable gain and a CR-CLS circuit; the front-end dynamic amplifier is used to adjust the input signal IN P , IN N Perform sampling and reset amplification operations, and its output terminal is recorded as OUT2 P OUT2 N ; The CR-CLS circuit includes two CLS capacitors C7 and C8, two trimming capacitors C9 and C10, and 14 CMOS switches K25-K38. The circuit connection is as follows: the upper plates of C7 and C9 are connected to OUT2 through K25. P connected and serves as the final positive-phase output terminal OUT P ; The lower plates of C8 and C10 are connected to OUT2 through K26 N connected and serves as the final negative phase output terminal OUT N ; The lower board of C7 is connected to OUT through K29, K31, K35 respectively N OUT2 P , and the common-mode signal input terminal V CM The upper plate of C8 is connected to OUT through K30, K33, K36 respectively. P OUT2 N 、V CM The lower board of C9 is connected to OUT through K27 and K32 respectively. P and OUT2 P ; The upper plate of C10 is connected to OUT through K28 and K34 respectively N and OUT2 N OUT P and OUT N Connect V through K37 and K38 respectively. CM ; By synchronously adjusting the switch states of K31-K34 and K25-K30 for the inverted clock signals S7 and S8, the circuit topology of the CR-CLS circuit is switched between "integration-estimation" and "integration-level shifting"; and the gain and swing of the final output of the CR-CLS circuit are optimized in combination with the front-end dynamic amplifier gain matching.

2. The demand-oriented dynamic high-gain amplifier circuit according to claim 1, characterized in that: When K25-K30 are closed and K31-K34 are open, the CR-CLS circuit is used to perform integration-estimation operations; at this time, the CLS capacitor is connected across the two output nodes of the CR-CLS circuit, and the upper and lower plates of the trimming capacitor are short-circuited, thereby transferring the charge on the sampling capacitor in the front-end dynamic amplifier to the feedback integration capacitor.

3. The demand-oriented dynamic high-gain amplifier circuit according to claim 2, characterized in that: When K25-K30 are disconnected and K31-K34 are closed, the CR-CLS circuit is used to perform an integration-level shift operation; at this time, the residual charge on the sampling capacitor in the front-end dynamic amplifier is further transferred to the feedback integration capacitor, and the trimming capacitor is connected in parallel with the CLS capacitor to correct the capacitance value of the CLS capacitor, compensate for the charge lost by the CLS capacitor due to non-ideal factors, and thereby make the closed-loop gain approach the ideal value.

4. The demand-oriented dynamic high-gain amplifier circuit according to claim 1, characterized in that: The trimming capacitor C9 or C10 consists of a fixed capacitor C trim , 5 controllable capacitors C trim1 ~C trim5 , and 5 pairs of CMOS switches K trim1-1 ~K trim5-1 , K trim1-2 ~K trim5-2 Composition; circuit connection is: C trim1 ~C trim5 The lower board and C trim The lower board is connected; C trim1 ~C trim5 The upper board is respectively K trim1-1 ~K trim5-1 With C trim Connected to the upper board; C trim1 ~C trim5 The upper and lower boards are also connected by K trim1-2 ~K trim5-2 Directly connected; among them, C trim1 ~C trim5 The ratio of the capacitance values ​​is 1:2:4:8:16; Control K through the five-bit adjustment control code trim1-1 ~K trim5-1 and K trim1-2 ~K trim5-2 The switching state of the two CMOS switches connected to the same controllable capacitor is reversed, thereby adjusting the capacitance value of the trimming capacitor.

5. The demand-oriented dynamic high-gain amplifier circuit according to claim 4, characterized in that: The front-end dynamic amplifier adopts a cascade residual amplifier including a first-stage FIA ​​circuit and a second-stage FIA ​​circuit; two inverters composed of components with different parameters are used in the positive-phase path and the negative-phase path in the second-stage FIA ​​circuit; the circuit topology of the positive-phase path and the negative-phase path in the second-stage FIA ​​circuit is synchronously adjusted through the clock signal S8 to achieve matching of the output gain of the second-stage FIA ​​circuit with the input requirements of the CR-CLS circuit in different modes.

6. The demand-oriented dynamic high-gain amplifier circuit according to claim 5, characterized in that: The second-stage FIA ​​circuit is composed of 4 PMOS transistors PM3-PM6, 4 NMOS transistors NM3-NM6, 10 CMOS switches K17-K22, K23-1, K23-2, K24-1, K24-2, and 1 bias capacitor C6; the circuit connection is: The upper plate of C6 is connected to VDD through K17, and the lower plate is connected to GND through K18; the sources of PM3 and PM4 are connected to the upper plate of C6 through K19; the sources of NM3 and NM4 are connected to the lower plate of C6 through K20; the gates of PM3, PM5, NM3, and NM5 are connected and serve as the first-stage inverting output terminal OUT1 of the front-end dynamic amplifier N The gates of PM4, PM6, NM4, and NM6 are connected and serve as the first-stage positive-phase output terminal OUT1 of the front-end dynamic amplifier. P ; The drains of PM5 and NM5 are connected and serve as the second-stage positive-phase output terminal OUT2 of the front-end dynamic amplifier P ; The drains of PM6 and NM6 are connected and serve as the second stage inverting output terminal OUT2 of the front-end dynamic amplifier N ; The drain of PM3 and the source of PM5 are connected to OUT2 through K23-1 P ; The source of NM5 and the drain of NM3 are connected to OUT2 through K23-2 P ; The drain of PM4 and the source of PM6 are connected to OUT2 through K24-1 N ; The source of NM6 and the drain of NM4 are connected to OUT2 through K24-2 N OUT2 P and OUT2 N Connect V through K21 and K22 respectively. CM ; Among them, the switching states of K23-1, K23-2, K24-1, and K24-2 are synchronously adjusted by the clock signal S8.

7. The demand-oriented dynamic high-gain amplifier circuit according to claim 6, characterized in that: The first-stage FIA ​​circuit is composed of two PMOS transistors PM0-PM1, two NMOS transistors NM0-NM1, six CMOS switches K11-K16, and one bias capacitor C5; the circuit connection is: The upper plate of C5 is connected to VDD through K11, and the lower plate is connected to GND through K12; the sources of PM0 and PM1 are connected to the upper plate of C5 through K13; the sources of NM0 and NM1 are connected to the lower plate of C5 through K14; the gates of PM0 and NM0 are connected and serve as the first-stage positive input terminal IN1 of the front-end dynamic amplifier P The gates of PM1 and NM1 are connected and serve as the first stage inverting input terminal IN1 of the front-end dynamic amplifier. N ; The drain of PM0 and NM0 and OUT1 N connected; the drain of PM1 and NM0 is connected to OUT1 P Connected to OUT1 N and OUT1 P Also connect V through K15 and K16 respectively CM .

8. The demand-oriented dynamic high-gain amplifier circuit according to claim 7, characterized in that: The front-end dynamic amplifier also includes a sample-and-hold circuit; the sample-and-hold circuit is composed of two gate voltage bootstrap switches K3 and K4, eight CMOS switches K1, K2, K5-K10, two input sampling capacitors C1 and C2, and two feedback integration capacitors C3 and C4; the circuit connection is: The upper plate of C1 is connected to IN through K3 and K9 respectively. P and V CM ; The upper plate of C2 is connected to IN through K4 and K10 respectively N and V CM ; The lower plate of C1 is connected to IN1 through K7 and K1 respectively P and V CM ; The lower plate of C2 is connected to IN1 through K2 and K8 respectively N and V CM ;IN1 P and IN1 N Connect V through K5 and K6 respectively. CM ; C3 is connected to IN1 P and OUT N between; C4 is connected to IN1 N and OUT P between.

9. The demand-oriented dynamic high-gain amplifier circuit according to claim 8, characterized in that: It also includes or is connected to a clock control circuit, which is used to generate clock signals S1, S1D, S2-S8 for controlling the switching states of various CMOS switches and gate voltage bootstrap switches in the front-end comparator and the CR-CLS circuit; Among them, S1 is used to control K1 and K2; S1D is used to control K3~K6; S2 is used to control K9 and K10; S3 is used to control K7 and K8; S4 is used to control K11, K12, K15~K18, K21, K22; S5 is used to control K13, K14, K19, K20; S6 is used to control K35~K38.

10. A Pipeline SAR ADC, characterized in that: It adopts the demand-oriented dynamic high-gain amplifier circuit as described in any one of claims 1-9.

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