Delay-adjustable clock burr filtering circuit, chip and electronic equipment

Abstract

The invention provides a delay-adjustable clock burr filtering circuit, a chip and electronic equipment, and relates to the technical field of integrated circuits. The delay adjustable unit is connected with the logic gate unit; the logic gate unit is connected with the trigger unit. The delay adjustable unit is used for generating delay time based on the target clock signal and different delay selection signals, correspondingly adjusting the pulse width for filtering burrs of the target clock signal, and obtaining and outputting a corresponding delay output signal; the logic gate unit is used for performing logic operation based on the target clock signal and the delay output signal to obtain two level signals; the trigger unit is used for processing the two level signals and a target clock signal, and the output end outputs a stable clock signal. According to the invention, the application range is wider, the delay is more suitable for the working environment, and the performance index of the clock module is improved. The circuit structure is simple, area overhead and power consumption are reduced, low power consumption and miniaturization of the chip are facilitated, and the trend of future development of the chip is met.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a delay-adjustable clock glitch filtering circuit, a chip and an electronic device. Background Art

[0002] With the continuous development of science and technology, the use of chips is increasing. Chips have become indispensable in daily life, and the normal operation of most chips is inseparable from the clock. However, due to different working environments, the generation of the clock will be mixed with a lot of noise or glitches, which will affect the normal operation of the chip.

[0003] In the current circuit structure, many technical solutions have been proposed to filter glitches to obtain relatively clean clock signals, but these technical solutions are all for a clock signal of a fixed frequency, that is, the glitch width of the clock signal is basically fixed. This is because the delay time in these technical solutions is fixed, and it cannot be adjusted appropriately according to different glitch widths. For a chip, there are many types of clock signals that may be used, so it is necessary to have multiple sets of circuit structures for filtering glitches. More glitch filtering circuit structures not only make the circuit structure of the chip complex, but also cause higher area overhead and power consumption, which is obviously not conducive to the low power consumption and miniaturization of the chip, and is even more inconsistent with the future development trend of the chip. Summary of the invention

[0004] In view of the above problems, the present invention is proposed to provide a delay-adjustable clock glitch filtering circuit, chip and electronic device that solve the above problems or partially solve the above problems.

[0005] A first aspect of an embodiment of the present invention provides a delay-adjustable clock glitch filtering circuit, the delay-adjustable clock glitch filtering circuit comprising: a delay-adjustable unit, a logic gate unit, and a trigger unit; The output end of the adjustable delay unit is connected to the input end of the logic gate unit; The output end of the logic gate unit is connected to the second and third input ends of the trigger unit respectively, and the first input end thereof receives the target clock signal; The adjustable delay unit is used to generate a delay time based on the received target clock signal and different delay selection signals, and correspondingly adjust the pulse width of the target clock signal burr to obtain and output a corresponding delayed output signal to the logic gate unit, wherein the target clock signal is a clock signal of any frequency; The logic gate unit is used to perform a logic operation based on the target clock signal and the delayed output signal to obtain two level signals which are respectively transmitted to the second and third input terminals of the trigger unit; The trigger unit is used to process the two level signals and the target clock signal, and the output end outputs a stable clock signal, which is a target clock signal with glitches filtered out.

[0006] Optionally, the adjustable delay unit comprises: a plurality of delay units, a plurality of switches and a decoder; A plurality of the delay units are sequentially connected in series to form a series delay structure, wherein the input end of the first delay unit receives the target clock signal, and the output end of the last delay unit is connected to the input end of the logic gate unit; In the series delay structure, the two delay units in the middle are the first group, the first switch in the multiple switches is connected in parallel with the first group, the four delay units in the middle are the second group, the second switch in the multiple switches is connected in parallel with the second group, ... all delay units except the first delay unit and the last delay unit are the Nth group, the Nth switch in the multiple switches is connected in parallel with the Nth group; or, In the series delay structure, a delay unit located in the middle is a first group, a first switch among multiple switches is connected in parallel with the first group, three delay units located in the middle are a second group, a second switch among multiple switches is connected in parallel with the second group, ... all delay units except the first delay unit and the last delay unit are an Nth group, and an Nth switch among multiple switches is connected in parallel with the Nth group; The input end of the decoder receives the different delayed signals, and the output end is connected to the plurality of switches.

[0007] Optionally, the decoder is used to generate corresponding control signals based on the different delayed signals and transmit the control signals to corresponding switches; Each of the plurality of switches is used to be opened when not receiving the control signal, and closed when receiving the control signal; The plurality of delay units are used to adjust the pulse width of the target clock signal glitches in accordance with the closed or open state of each of the plurality of switches, and obtain and output the delayed output signal to the logic gate unit.

[0008] Optionally, the logic gate unit includes: an AND gate and an OR gate; The first input terminal of the AND gate receives the delayed output signal; The second input terminal of the AND gate receives the target clock signal; The output end of the AND gate is connected to the second input end of the trigger unit; The first input terminal of the OR gate receives the delayed output signal; The second input terminal of the OR gate receives the target clock signal; The output terminal of the OR gate is connected to the third input terminal of the trigger unit.

[0009] Optionally, the AND gate is used to perform an AND operation on the delayed output signal and the target clock signal, and output a first level signal of the two level signals to the trigger unit; The OR gate is used to perform an OR operation on the delayed output signal and the target clock signal, and output the second level signal of the two level signals to the trigger unit.

[0010] Optionally, the trigger unit includes: a D trigger; The first input terminal of the D flip-flop receives the target clock signal; The clock terminal of the D flip-flop is used as its second input terminal and connected to the output terminal of the AND gate; The reset terminal of the D flip-flop is used as its third input terminal and connected to the output terminal of the OR gate; The output end of the D flip-flop outputs the stable clock signal.

[0011] Optionally, the D flip-flop is used to filter the glitches of the target clock signal based on the high and low level states of the first level signal and the second level signal, respectively, to obtain and output the target clock signal with the glitches filtered out.

[0012] Optionally, the number of the plurality of delay units is determined according to the delay time of a single delay unit in combination with preset requirements; The number of the plurality of switches is determined according to the number of the delay units; The preset requirement is the pulse width of all glitches contained in clock signals of different frequencies; The different delay times obtained by combining the multiple delay units with the closed or open state of each switch in the multiple switches must satisfy the following requirement: each delay time corresponds to a pulse width of a glitch. Optionally, each of the delay units comprises: an inverter; A plurality of the inverters are sequentially connected in series to form a series delay structure, wherein the input end of the first inverter receives the target clock signal, and the output end of the last inverter is connected to the input end of the logic gate unit.

[0013] A second aspect of an embodiment of the present invention provides a chip, the chip comprising: a plurality of clock units, a multiplexer unit, a digital circuit, a level conversion unit, and a delay-adjustable clock glitch filtering circuit as claimed in any one of claims 1 to 9; The output ends of the plurality of clock units are all connected to the input end of the multi-way selection unit; The output end of the multiplexer unit is connected to the adjustable delay unit and the logic gate unit in the adjustable delay clock glitch filtering circuit; The output end of the trigger unit in the delay adjustable clock glitch filtering circuit is connected to the detection end of the digital circuit; The digital end of the level conversion unit is connected to the register in the digital circuit; The analog terminal of the level conversion unit is connected to the delay adjustable unit.

[0014] Optionally, the plurality of clock units are used to generate respective clock signals, and the frequencies of the clock signals generated by different clock units are the same or different; The multiplexer selection unit is used for, based on the situation that any clock unit among the multiple clock units generates a clock signal, using the clock signal generated by the clock unit as the target clock signal and transmitting it to the delay adjustable clock glitch filtering circuit; The digital circuit is used to detect whether the burrs in the stable clock signal are filtered through the detection end, and send different adjustment signals to the level conversion unit through the register based on whether the burrs are filtered; The level conversion unit is used to perform level conversion on the different adjustment signals to convert them into corresponding different analog signals, and the different analog signals are the different delay selection signals.

[0015] A third aspect of an embodiment of the present invention provides an electronic device, wherein the electronic device includes the chip as described in the second aspect.

[0016] The delay adjustable clock glitch filtering circuit provided by the present invention comprises: a delay adjustable unit, a logic gate unit and a trigger unit. The output end of the delay adjustable unit is connected to the input end of the logic gate unit; the output end of the logic gate unit is connected to the second and third input ends of the trigger unit respectively, and the first input end receives the target clock signal.

[0017] The delay adjustable unit is used to generate a delay time based on the received target clock signal and different delay selection signals, and correspondingly adjust the pulse width of the filtered target clock signal glitches to obtain and output the corresponding delayed output signal to the logic gate unit, and the target clock signal is a clock signal of any frequency; the logic gate unit is used to perform logical operations based on the target clock signal and the delayed output signal, and obtain two level signals that are transmitted to the second and third input terminals of the trigger unit respectively; the trigger unit is used to process the two level signals and the target clock signal, and the output terminal outputs a stable clock signal, which is the target clock signal with the glitches filtered.

[0018] The delay-adjustable clock glitch filtering circuit proposed in the present invention creatively proposes a delay-adjustable glitch filtering circuit structure, and utilizes the delay-adjustable unit in the circuit structure to generate different delay times for clock signals of different frequencies and different delay selection signals, and correspondingly adjusts the pulse width of the target clock signal glitch to be filtered, and then through the operation of the logic gate unit and the processing of the trigger unit, it is extremely well adjusted according to the different glitch widths, so that only one glitch filtering circuit structure is needed to filter the glitch of clock signals of different frequencies. It has a wider range of use and a delay that is more suitable for the working environment, so that the clock module that generates the clock signal has a faster setup time, thereby better filtering the clock glitch and also improving the performance indicators of the clock module. The entire circuit structure is simple, reduces area overhead and power consumption, is very conducive to low power consumption and miniaturization of the chip, and is more in line with the future development trend of the chip, and has a high practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0020] Figure 1 is a modular schematic diagram of a delay adjustable clock glitch filtering circuit according to an embodiment of the present invention; Figure 2 Schematic diagram of a circuit structure of a preferred delay adjustable unit in an embodiment of the present invention; Figure 3 It is a structural schematic diagram of a preferred delay-adjustable clock glitch filtering circuit in an embodiment of the present invention; Figure 4 is a modular schematic diagram of a chip according to an embodiment of the present invention; Figure 5 It is a waveform diagram of a frequency clock signal CLK_IN carrying 100mV overshoot and undershoot burrs as an input clock signal in an embodiment of the present invention, and the burr filtering result is a stable clock signal CLK_OUT. DETAILED DESCRIPTION

[0021] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, are only part of the embodiments of the present invention, not all of the embodiments, and are not used to limit the present invention.

[0022] The inventors found that in order to solve the problem of clock signal glitch filtering, the current technical solutions basically adopt the method of generating delay time to achieve glitch filtering. However, this technical solution is only for a clock signal with a fixed frequency, that is, the glitch width of this clock signal is basically fixed, and it cannot be properly adjusted according to different glitch widths.

[0023] For example, most chips may use at least two clock signals. The first is the internal high-speed clock signal generated by the chip's internal high-speed clock HIRC (Highspeed Internal RC Oscillator), and the second is the internal low-speed clock signal generated by the chip's internal low-speed clock LIRC (Low-speed Internal RC Oscillator). The clock units that generate high-speed and low-speed clock signals are not as accurate as external quartz crystals, but they can save costs in applications that do not require high accuracy.

[0024] Since the accuracy of the clock signals generated by the above-mentioned embedded high-speed RC oscillator and embedded low-speed RC oscillator may not meet the application requirements, in the scenario of high-precision application, especially in the scenario of both high and low precision application requirements, the chip also needs to use the clock signals generated by two other methods: the third is the external high-speed clock signal generated by the high-speed clock HOSC (Highspeed Crystal Oscillator, external high-speed crystal oscillator), and the fourth is the external low-speed clock signal generated by the low-speed clock LOSC (Low-speed Crystal Oscillator, external low-speed crystal oscillator). The clock units that generate high and low-speed clock signals have relatively high accuracy in generating clock signals, but also increase some hardware costs.

[0025] Among the four clock signals listed above, the frequency of each clock signal may be the same as or different from the frequencies of other clock signals. If the frequencies of the four clock signals are all different (which is the case in most cases), then in the traditional technical solution, one chip needs to be equipped with four sets of glitch filtering circuit structures to filter the glitches of the four clock signals with different frequencies. More glitch filtering circuit structures not only make the circuit structure of the chip complex, but also cause higher area overhead and power consumption, which is obviously not conducive to the low power consumption and miniaturization of the chip, and is even more inconsistent with the future development trend of the chip.

[0026] Based on the above problems, the inventor creatively proposed a delay adjustable clock glitch filtering circuit, chip and electronic device of the present invention. The technical solution of the present invention is explained and illustrated in detail below.

[0027] A delay-adjustable clock glitch filtering circuit according to an embodiment of the present invention comprises: a delay-adjustable unit, a logic gate unit and a trigger unit. The delay-adjustable clock glitch filtering circuit of the present invention is particularly suitable for the circuit structure of a chip, but can also be expanded to be applied to any structure that has a glitch filtering requirement for the clock signal, such as the astronomical clock structure of a time-controlled street lamp, etc. The so-called chip (Integrated Circuit, abbreviated as IC), generally referred to as a microcircuit, microchip, wafer / chip in electronics, is a way to miniaturize circuits (mainly including semiconductor devices, but also passive components, etc.), and is often manufactured on the surface of a semiconductor wafer.

[0028] Today, the most advanced integrated circuits are at the heart of microprocessors or multi-core processors that control everything from computers to cell phones to the vast majority of smart devices. Although the cost of designing and developing a complex chip is very high, when spread across products that typically number in the millions, the cost of each chip is minimized. The performance of the chips is high because the small size results in short paths, allowing low-power logic circuits to be used at fast switching speeds.

[0029] Over the years, chips have continued to move toward smaller form factors, allowing more circuits to be packed into each chip. This increases the capacity per unit area, which can reduce costs and increase functionality. In short, as the form factor shrinks, almost all indicators improve, with unit costs and switching power consumption decreasing and speed increasing. However, ICs that integrate nanometer-level devices also have problems, mainly leakage current. Therefore, the increase in speed and power consumption is very obvious to end users, and manufacturers face the acute challenge of improving chip structures.

[0030] Only half a century after the development of integrated circuits, chips have become ubiquitous, and intelligent devices such as computers, mobile phones and other digital appliances have become an indispensable part of the social structure. This is because modern computing, communication, manufacturing and transportation systems, including the Internet, the Internet of Things, etc., all rely on the existence of chips. The digital revolution brought about by chips is the most important event in human history. The maturity of chips will bring about a great leap in technology, not only in design technology, but also in semiconductor process breakthroughs, both of which are necessary.

[0031] There are many factors that restrict the development of chips, including but not limited to: how to integrate more electronic components in a smaller area to achieve more and better functions; how to drive the various electronic components in the chip to work with less power consumption; how to generate more stable and better quality clock signals, voltages, currents, etc. In order to obtain more stable and better quality clock signals, it is also necessary to reduce area overhead and power consumption as much as possible.

[0032] The present invention proposes a delay adjustable clock glitch filtering circuit, referring to Figure 1 The modular schematic diagram of the adjustable delay clock glitch filtering circuit shown in the figure, the output end of the adjustable delay unit is connected to the input end of the logic gate unit; the output end of the logic gate unit is connected to the second and third input ends of the trigger unit respectively, and its first input end receives the target clock signal.

[0033] The adjustable delay unit is used to generate a delay time based on the received target clock signal and different delay selection signals, and to adjust the pulse width of the target clock signal glitches to obtain and output the corresponding delayed output signal to the logic gate unit. The target clock signal is a clock signal of any frequency. That is, the adjustable delay unit can receive a clock signal of any frequency, and is no longer limited to a clock signal of a fixed frequency.

[0034] The logic gate unit is used to perform logic operations based on the target clock signal and the delayed output signal to obtain two level signals which are respectively transmitted to the second and third input terminals of the trigger unit; the trigger unit is used to process the two level signals and the target clock signal, and the output terminal outputs a stable clock signal, which is the target clock signal with glitches filtered out.

[0035] Since the adjustable delay unit of the present invention can generate different delay times corresponding to clock signals of different frequencies, the pulse width for filtering glitches of clock signals of different frequencies can be adjusted accordingly. Combined with subsequent logic gate unit and trigger unit processing, filtering of glitches of clock signals of different frequencies can be achieved, and there is no need to set up a glitch filtering circuit structure corresponding to each frequency clock signal.

[0036] In one embodiment of the present invention, the delay adjustable unit generates delay times corresponding to different frequency clock signals based on different frequency clock signals and different delay selection signals received. There are many implementation methods, which are not described one by one. One preferred structure of the delay adjustable unit includes: multiple delay units, multiple switches and a decoder.

[0037] Reference Figure 2The circuit structure diagram of a preferred delay adjustable unit in the embodiment of the present invention is shown, wherein a plurality of delay units T1, T2, ... Tn-1, Tn-m, ... Tn-1, Tn are sequentially connected in series to form a series delay structure, wherein the first delay unit (i.e. Figure 2 The input end of the leftmost delay unit T1 in the series delay unit receives the target clock signal ( Figure 2 CLK_IN), the tail delay unit (i.e. Figure 2 The output terminal of the rightmost delay unit Tn in the series delay unit is connected to the logic gate unit ( Figure 2 The input terminal of the circuit is connected to the circuit breaker (not shown).

[0038] In the series delay structure, the two delay units in the middle (i.e. Figure 2 The delay units Tn-1 and Tn-m are exemplarily shown in the series delay unit as the first group, the first switch of the plurality of switches is connected in parallel with the first group, and the four delay units ( Figure 2 The delay unit Tn-1 and the delay unit Tn-m, and Figure 2 The delay unit adjacent to the left of the delay unit Tn-1 not shown in the figure, the delay unit adjacent to the right of the delay unit Tn-m not shown in the figure, a total of four delay units) is the second group, the second switch in the plurality of switches is connected in parallel with the second group, ... all delay units except the first delay unit T1 and the last delay unit Tn are the Nth group, and the Nth switch in the plurality of switches is connected in parallel with the Nth group. It can be seen that there are a total of an even number of delay units in this series delay structure.

[0039] Naturally, it is understandable that there may be an odd number of delay units in the series delay structure. When there are an odd number of delay units in the series delay structure, the delay unit located in the middle of the series delay structure is the first group, and the first switch among the multiple switches is connected in parallel with the first group, the three delay units located in the middle are the second group, and the second switch among the multiple switches is connected in parallel with the second group, ... all delay units except the first delay unit and the last delay unit are the Nth group, and the Nth switch among the multiple switches is connected in parallel with the Nth group.

[0040] In one embodiment of the present invention, the input end of the decoder DEC receives different delayed signals (i.e. Figure 2 The output end is connected to a plurality of switches. The decoder is used to generate corresponding control signals (i.e. Figure 2 D1, D2, ...DN) and transmit it to the corresponding switch; for example: Figure 2In the example, marking the control signal D1 below the first switch indicates that the control signal D1 controls the closing or opening of the first switch, and marking the control signal DN below the Nth switch indicates that the control signal DN controls the closing or opening of the Nth switch.

[0041] Each of the multiple switches is used to open when no control signal is received, and close when a control signal is received; for example, the first switch is opened when no control signal D1 is received, and closed when the control signal D1 is received.

[0042] In one embodiment of the present invention, a plurality of delay units are used to adjust the pulse width of the target clock signal glitch in accordance with the closed or open state of each switch in the plurality of switches, and obtain and output the delayed output signal DELAY_OUT to the logic gate unit. For example, when the first switch is closed upon receiving the control signal D1, the input clock signal CLK_IN needs to be delayed by all delay units except the delay units Tn-1 and Tn-m to obtain a delayed output signal DELAY_OUT1, and when the Nth switch is closed upon receiving the control signal DN, the input clock signal CLK_IN only needs to be delayed by the delay units T1 and Tn to obtain the delayed output signal DELAY_OUT2. It is naturally known that the delay time corresponding to the delayed output signal DELAY_OUT2 is less than the delay time corresponding to the delayed output signal DELAY_OUT1. In the above manner, the adjustable delay unit can generate different delay times corresponding to the pulse width of each different clock signal glitch.

[0043] In one embodiment of the present invention, the number of delay units in the series delay structure is as follows: the number of multiple delay units is determined according to the delay time of a single delay unit in combination with preset requirements. When the number of delay units is determined, the number of multiple switches can be determined according to the number of delay units. Among them, the preset requirement is the pulse width of all glitches contained in clock signals of different frequencies. The different delay times obtained by combining the closed or open state of each switch in the multiple switches must satisfy: each delay time corresponds to the pulse width of a glitch.

[0044] In one embodiment of the present invention, the delay unit may be implemented in a variety of ways, for example, using a MOS tube (Metal-Oxide-Semiconductor Field-Effect Transistor, abbreviated as MOSFET, Chinese name: Metal-Oxide Semiconductor Field-Effect Transistor, abbreviated as MOSFET), etc. A preferred option is that each delay unit includes an inverter.

[0045] The inverter is a structure that can reverse the phase of the input signal by 180 degrees. Most of them are used in analog circuits, such as audio amplifiers, clock oscillators, etc. With the continuous development and innovation of microelectronics technology and processes, various digital electronic products represented by computers are becoming more and more widely used, and at the same time they are also facing a more complex electromagnetic environment. The types of inverters are roughly divided into: TTL NOT gate inverter and CMOS inverter. Among them, CMOS inverters have the advantages of large noise tolerance, extremely high input resistance, extremely low static power consumption, and insensitivity to noise and interference, so they are widely used in digital integrated circuits.

[0046] Therefore, a plurality of inverters connected in series in sequence can also form a series delay structure, wherein the input end of the first inverter receives the target clock signal, and the output end of the last inverter is connected to the input end of the logic gate unit.

[0047] In one embodiment of the present invention, for the logic gate unit, it performs logic operations based on clock signals of different frequencies and corresponding different delayed output signals, and obtains two level signals which are respectively transmitted to the second and third input terminals of the trigger unit. There are many ways to implement the logic gate unit, which will not be described one by one. One of the preferred structures of the logic gate unit includes: an AND gate and an OR gate.

[0048] The so-called AND gate, also known as "AND circuit", logical "product", and logical "AND" circuit. It is a basic logic gate circuit that performs "AND" operations. It has multiple input terminals and one output terminal. When all inputs are high level (logic 1) at the same time, the output of the AND gate is high level, otherwise the output of the AND gate is low level (logic 0). The implementation methods of the AND gate include using CMOS logic, NMOS logic, PMOS logic, and diode implementation, etc.

[0049] The so-called OR gate is also called "OR circuit" or logical "and" circuit. If an event will occur as long as one of several conditions is met, this relationship is called an "OR" logic relationship. A circuit with an "OR" logic relationship is called an OR gate. The OR gate has multiple input terminals and one output terminal. As long as one of the inputs is at a high level (logic 1), the output of the OR gate is high (logic 1); only when all inputs are at a low level (logic 0), the output of the OR gate is low (logic 0). The OR gate can be implemented in different ways, including diode implementation, switch implementation, CMOS logic implementation, and so on.

[0050] Based on the above AND gate, the first input terminal of the AND gate receives the delayed output signal DELAY_OUT; the second input terminal of the AND gate receives the clock signal CLK_IN of different frequency; and the output terminal of the AND gate is connected to the second input terminal of the trigger unit.

[0051] Based on the above OR gate, the first input terminal of the OR gate receives the delayed output signal DELAY_OUT; the second input terminal of the OR gate receives the clock signal CLK_IN of different frequency; and the output terminal of the OR gate is connected to the third input terminal of the trigger unit.

[0052] Among them, the AND gate is used to perform AND operations on different delayed output signals and different frequency clock signals, and output the first level signal of the two level signals to the trigger unit; the OR gate is used to perform OR operations on different delayed output signals and different frequency clock signals, and output the second level signal of the two level signals to the trigger unit. Based on the logical operations of the AND gate and the OR gate, it can be known that: only when both the delayed output signal and the clock signal are at a high level, the signal output by the AND gate to the trigger unit is a high level, as long as either one is not at a high level, the signal output by the AND gate to the trigger unit is a low level; and as long as one of the delayed output signal or the clock signal is at a high level, the signal output by the OR gate to the trigger unit is a high level, and only when both are at a low level, the signal output by the OR gate to the trigger unit is a low level.

[0053] In one embodiment of the present invention, the trigger unit processes two level signals and clock signals of different frequencies, and the output terminal outputs a stable clock signal. There are many ways to implement the trigger unit, which will not be described one by one. One preferred structure of the trigger unit includes: a D flip-flop.

[0054] The D flip-flop is an information storage device with memory function and two stable states. It is the most basic logic unit that constitutes a variety of sequential circuits and an important unit circuit in digital logic circuits. The D flip-flop has two stable states, namely 0 and 1. Under the action of certain external signals, it can flip from one stable state to another. The D flip-flop has a trigger composed of an integrated flip-flop and a gate circuit. There are two triggering modes: level triggering and edge triggering. The former can be triggered when the clock pulse = 1 (that is, the clock signal is high level), and the latter is mostly triggered at the leading edge of the clock pulse (positive transition 0→1, that is, the rising edge of the clock signal).

[0055] The next state of the D flip-flop depends on the state of the first input terminal before the trigger. Therefore, it has two functions: set to 0 and set to 1. For the edge D flip-flop, since the circuit has a maintenance blocking effect during the clock pulse = 1, the data state change of the first input terminal during the clock pulse = 1 will not affect the output state of the D flip-flop. The D flip-flop (data flip-flop or delay flip-flop) is composed of 4 NAND gates. When the level-triggered master-slave flip-flop works, the input signal must be added before the positive jump edge. For the synchronous flip-flop, if an interference signal appears at the first input terminal during the high level of the clock signal, it is possible to make the state of the D flip-flop wrong. For the edge flip-flop, it allows the input signal to be added at the moment before the clock signal trigger edge arrives. In this way, the time for the first input terminal to be interfered is greatly shortened, and the possibility of interference is reduced. The edge D flip-flop is also called a maintain-block edge D flip-flop. The edge D flip-flop can be composed of two D flip-flops in series, but the clock signal of the first D flip-flop needs to be inverted by a NOT gate.

[0056] Based on the above-mentioned D flip-flop, the first input terminal of the D flip-flop receives a clock signal CLK_IN of different frequencies; the clock terminal of the D flip-flop serves as its second input terminal, which is directly connected to the output terminal of the AND gate; the clear terminal of the D flip-flop serves as its third input terminal, which is directly connected to the output terminal of the OR gate; and the output terminal of the D flip-flop outputs a stable clock signal CLK_OUT.

[0057] In one embodiment of the present invention, a D flip-flop is used to filter the glitches of clock signals of different frequencies based on the high and low level states of a first level signal (i.e., the output signal of an AND gate) and a second level signal (i.e., the output signal of an OR gate), to obtain clock signals of different frequencies with the glitches filtered out, i.e., a stable clock signal, and output it.

[0058] In order to better understand the structure of the above delay adjustable clock glitch filtering circuit, refer to Figure 3 A schematic structural diagram of a preferred clock glitch filtering circuit with adjustable delay is shown. Figure 3 In the figure, the AND gate AND, the OR gate OR and the D flip-flop DTR are used to represent the logic gate unit and the trigger unit respectively. For the sake of simplicity, the delay adjustable unit DAU is not specifically shown. Figure 2 shown.

[0059] Figure 3The adjustable delay unit DAU receives different frequency clock signals CLK_IN and different delay selection signals DELAY_SEL respectively, and the delayed output signal DELAY_OUT output by the adjustable delay unit DAU is used as one input signal of the AND gate AND and the OR gate OR respectively, and the different frequency clock signal CLK_IN is used as the other input signal of the AND gate AND and the OR gate OR respectively. At the same time, the different frequency clock signals are also used as the input signal of the first input terminal D of the D flip-flop DTR, and the output signal of the AND gate AND is used as the input signal of the clock terminal Clk (that is, the second input terminal of the D flip-flop) of the D flip-flop DTR, and the output signal of the OR gate OR is used as the input signal of the reset terminal Reset (that is, the third input terminal of the D flip-flop) of the D flip-flop DTR, and the output terminal Q of the D flip-flop DTR outputs a stable clock signal CLK_OUT. If the negative signal of the stable clock signal CLK_OUT is required, the other output terminal of the D flip-flop Outputs a negative signal of the stable clock signal CLK_OUT.

[0060] Its working principle is: when a clock signal of any frequency changes from a low level to a high level in the current stage, and then changes to a low level after maintaining a high level for a period of time, assuming that it carries glitches, upshoots and undershoots, then when it changes from a low level to a high level, due to the delay time of the glitch upshoot pulse width generated by the delay adjustable unit DAU, the signals received by the two input ends of the AND gate AND and the OR gate OR are both high levels, and the output signals of the AND gate AND and the OR gate OR are both high levels. At this time, the D end, Clk end, and Reset end of the D flip-flop DTR all receive high levels, and the output signal of the Q end of the D flip-flop DTR maintains the level of the previous stage, that is, the Q end output continues to be a low level, and will not change to a high level with the glitch upshoot.

[0061] Afterwards, as the delay time ends, the AND gate AND and the OR gate OR each receive a delayed output signal DELAY_OUT that becomes low, and the output signal of the AND gate AND becomes low. Since the clock signal received by the other input end of the OR gate OR is high, the output signal of the OR gate OR remains high. At this time, the D and Reset ends of the D flip-flop DTR both receive high levels, and the Clk end receives a low-level signal. The output signal of the Q end of the D flip-flop DTR becomes the same level as the D input signal, and no longer maintains the level of the previous stage, that is, the Q end output becomes high. At this time, the glitch overshoot ends, the Q end output becomes high, and the glitch overshoot is filtered out.

[0062] Similarly, it can be analyzed that after the high level of the clock signal ends, the glitch undershoots. Since the delay time of the glitch undershoot pulse width generated by the delay adjustable unit DAU, the signals received by the two input ends of the AND gate AND and the OR gate OR are both high level, and the output signals of the AND gate AND and the OR gate OR are both high level. At this time, the D end, Clk end, and Reset end of the D flip-flop DTR all receive high level, and the output signal of the Q end of the D flip-flop DTR maintains the level of the previous stage, that is, the Q end output continues to be high level, and will not change to low level with the glitch undershoot until the glitch undershoot ends.

[0063] After the glitch undershoot ends, the clock signal becomes low level, and the AND gate AND and the OR gate OR each receive a delayed output signal DELAY_OUT that becomes low level. The clock signal received at the other input end of the AND gate AND is low level, so the output signal of the AND gate AND becomes low level, and the output end of the OR gate OR receives low level signals at both input ends, so the output signal of the OR gate OR also becomes low level. At this time, the D end, Clk end, and Reset end of the D flip-flop DTR all receive low-high levels, so the output signal of the Q end of the D flip-flop DTR becomes low level. At this time, the glitch undershoot ends, and the Q end output becomes low level, filtering out the glitch undershoot. The above process can be repeated to filter out the glitch overshoot and undershoot for the frequency clock signal, and obtain a clock signal of the corresponding frequency with the glitch filtered.

[0064] Based on the above delay adjustable clock glitch filtering circuit, the embodiment of the present invention further provides a chip, referring to Figure 4 The modular schematic diagram of a chip shown in the figure comprises: a plurality of clock units 1, 2, ... n, a multiplexer unit, a digital circuit, a level conversion unit and a delay-adjustable clock glitch filtering circuit as described above.

[0065] The output ends of the multiple clock units 1, 2, ...n are all connected to the input end of the multiplexer unit; the output end of the multiplexer unit is connected to the adjustable delay unit and the logic gate unit in the adjustable delay clock glitch filter circuit. The output end of the trigger unit in the adjustable delay clock glitch filter circuit is connected to the detection end of the digital circuit; the digital end of the level conversion unit is connected to the register in the digital circuit; and the analog end of the level conversion unit is connected to the adjustable delay unit.

[0066] Multiple clock units are used to generate respective clock signals, and the frequencies of clock signals generated by different clock units are the same or different; that is, the frequency of clock signal 1 generated by clock unit 1 is the same or different from the frequencies of clock signals 2, ...n generated by clock unit 2, ... clock unit n.

[0067] The multi-way selection unit is used to use the clock signal generated by any clock unit among the multiple clock units as the target clock signal and transmit it to the delay adjustable clock glitch filtering circuit. That is, when clock unit 1 generates clock signal 1, the multi-way selection unit uses the clock signal 1 generated by clock unit 1 as the target clock signal CLK_IN and transmits it to the delay adjustable clock glitch filtering circuit; when clock unit n generates clock signal n, the multi-way selection unit uses the clock signal n generated by clock unit n as the target clock signal CLK_IN and transmits it to the delay adjustable clock glitch filtering circuit.

[0068] The digital circuit is used to detect whether the glitches in the stable clock signal CLK_OUT are filtered through the detection end, and based on whether the glitches are filtered, send different adjustment signals (the adjustment signals are digital quantities) to the level conversion unit through the register; the level conversion unit is used to perform level conversion on different adjustment signals and convert them into corresponding different analog signals (which are analog quantities), and the different analog signals are different delay selection signals DELAY_SEL.

[0069] In addition, the adjustment signal sent by the digital circuit through the register can also be defined as a delay selection signal of different gears. The delay selection signals of different gears correspond to the closing and opening conditions of different switches in the delay adjustable unit. After the digital circuit determines that the burr is filtered, the target adjustment signal corresponding to the burr filtering is determined as the adjustment signal corresponding to the target clock unit, so that the target adjustment signal can be directly sent when the target clock unit generates the corresponding clock signal next time.

[0070] For example: assuming that the default gear is the lowest gear, the corresponding delay time is the smallest, which corresponds to the situation that the Nth group of switches in the adjustable delay unit is closed and the remaining switches are disconnected, and the delay time corresponding to the highest gear is the largest, which corresponds to the situation that the first group of switches in the adjustable delay unit is closed and the remaining switches are disconnected.

[0071] When the clock unit 1 starts to work and generate a clock signal, since the pulse width of the glitch is unknown, the adjustment signal can be sent in the default gear first, so that the delay adjustable clock glitch filter circuit works at the delay time corresponding to the default gear and outputs the processed clock signal, and then the digital circuit detects it. If it is detected that the glitch is filtered, the delay adjustable clock glitch filter circuit continues to work at the default gear; if it is detected that the glitch still exists, the digital circuit adjusts the gear to a higher gear and sends the adjustment signal of other gears to the level conversion unit, so that the delay adjustable clock glitch filter circuit works at the delay time corresponding to the latest gear and outputs the processed clock signal, and then the digital circuit detects it. The above process continues until the digital circuit detects that the glitch is filtered, determines the gear corresponding to the clock unit 1, and records it as the adjustment signal corresponding to the clock unit 1. When the clock unit 1 stops working and works again, it can directly send its corresponding adjustment signal to the level conversion unit.

[0072] In order to prove the effectiveness of the delay adjustable clock glitch filtering circuit proposed by the present invention, it was tested and the results were obtained. Figure 5 The frequency clock signal CLK_IN shown carries 100mV overshoot and undershoot burrs as the input clock signal, and the burr filtering result is a waveform diagram of a stable clock signal CLK_OUT. Figure 5 The horizontal axis is time, in units of ns (nanoseconds), and the vertical axis is voltage v, in units of V (volts). The upper part is a waveform of the frequency clock signal CLK_IN, which carries 100mV overshoot and undershoot glitches, and the lower part is a stable clock signal CLK_OUT. It can be seen that the glitches are filtered and a stable clock signal is obtained, indicating the effectiveness of the delay adjustable clock glitch filtering circuit proposed in the present invention.

[0073] Based on the above-mentioned delay-adjustable clock glitch filtering circuit, an embodiment of the present invention further provides an electronic device, and the electronic device includes the above-mentioned chip.

[0074] In summary, the delay adjustable clock glitch filtering circuit provided by the present invention includes: a delay adjustable unit, a logic gate unit and a trigger unit. The output end of the delay adjustable unit is connected to the input end of the logic gate unit; the output end of the logic gate unit is connected to the second and third input ends of the trigger unit respectively, and the first input end receives the target clock signal.

[0075] The delay adjustable unit is used to generate a delay time based on the received target clock signal and different delay selection signals, and correspondingly adjust the pulse width of the filtered target clock signal glitches to obtain and output the corresponding delayed output signal to the logic gate unit, and the target clock signal is a clock signal of any frequency; the logic gate unit is used to perform logical operations based on the target clock signal and the delayed output signal, and obtain two level signals that are transmitted to the second and third input terminals of the trigger unit respectively; the trigger unit is used to process the two level signals and the target clock signal, and the output terminal outputs a stable clock signal, which is the target clock signal with the glitches filtered.

[0076] The delay-adjustable clock glitch filtering circuit proposed in the present invention creatively proposes a delay-adjustable glitch filtering circuit structure, and utilizes the delay-adjustable unit in the circuit structure to generate different delay times for clock signals of different frequencies and different delay selection signals, and correspondingly adjusts the pulse width of the target clock signal glitch to be filtered, and then through the operation of the logic gate unit and the processing of the trigger unit, it is extremely well adjusted according to the different glitch widths, so that only one glitch filtering circuit structure is needed to filter the glitch of clock signals of different frequencies. It has a wider range of use and a delay that is more suitable for the working environment, so that the clock module that generates the clock signal has a faster setup time, thereby better filtering the clock glitch and also improving the performance indicators of the clock module. The entire circuit structure is simple, reduces area overhead and power consumption, is very conducive to low power consumption and miniaturization of the chip, and is more in line with the future development trend of the chip, and has a high practical value.

[0077] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0078] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0079] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A delay adjustable clock glitch filtering circuit, characterized in that: The adjustable-delay clock glitch filtering circuit comprises: an adjustable-delay unit, a logic gate unit and a trigger unit; The output end of the adjustable delay unit is connected to the input end of the logic gate unit; The output end of the logic gate unit is connected to the second and third input ends of the trigger unit respectively, and the first input end thereof receives the target clock signal; The adjustable delay unit is used to generate a delay time based on the received target clock signal and different delay selection signals, and correspondingly adjust the pulse width of the target clock signal burr to obtain and output a corresponding delayed output signal to the logic gate unit, wherein the target clock signal is a clock signal of any frequency; The logic gate unit is used to perform a logic operation based on the target clock signal and the delayed output signal to obtain two level signals which are respectively transmitted to the second and third input terminals of the trigger unit; The trigger unit is used to process the two level signals and the target clock signal, and the output end outputs a stable clock signal, which is a target clock signal with glitches filtered out.

2. The delay adjustable clock glitch filtering circuit according to claim 1, characterized in that: The adjustable delay unit comprises: a plurality of delay units, a plurality of switches and a decoder; A plurality of the delay units are sequentially connected in series to form a series delay structure, wherein the input end of the first delay unit receives the target clock signal, and the output end of the last delay unit is connected to the input end of the logic gate unit; In the series delay structure, the two delay units in the middle are the first group, the first switch in the multiple switches is connected in parallel with the first group, the four delay units in the middle are the second group, the second switch in the multiple switches is connected in parallel with the second group, ... all delay units except the first delay unit and the last delay unit are the Nth group, the Nth switch in the multiple switches is connected in parallel with the Nth group; or, In the series delay structure, a delay unit located in the middle is a first group, a first switch among multiple switches is connected in parallel with the first group, three delay units located in the middle are a second group, a second switch among multiple switches is connected in parallel with the second group, ... all delay units except the first delay unit and the last delay unit are an Nth group, and an Nth switch among multiple switches is connected in parallel with the Nth group; The input end of the decoder receives the different delayed signals, and the output end is connected to the plurality of switches.

3. The delay adjustable clock glitch filtering circuit according to claim 2, characterized in that: The decoder is used to generate corresponding control signals based on the different delayed signals and transmit the control signals to corresponding switches; Each of the plurality of switches is used to be opened when not receiving the control signal, and closed when receiving the control signal; The plurality of delay units are used to adjust the pulse width of the target clock signal glitches in accordance with the closed or open state of each of the plurality of switches, and obtain and output the delayed output signal to the logic gate unit.

4. The delay adjustable clock glitch filtering circuit according to claim 1, characterized in that: The logic gate unit includes: an AND gate and an OR gate; The first input terminal of the AND gate receives the delayed output signal; The second input terminal of the AND gate receives the target clock signal; The output end of the AND gate is connected to the second input end of the trigger unit; The first input terminal of the OR gate receives the delayed output signal; The second input terminal of the OR gate receives the target clock signal; The output terminal of the OR gate is connected to the third input terminal of the trigger unit.

5. The delay adjustable clock glitch filtering circuit according to claim 4, characterized in that: The AND gate is used to perform an AND operation on the delayed output signal and the target clock signal, and output a first level signal of the two level signals to the trigger unit; The OR gate is used to perform an OR operation on the delayed output signal and the target clock signal, and output the second level signal of the two level signals to the trigger unit.

6. The delay adjustable clock glitch filtering circuit according to claim 4, characterized in that: The trigger unit comprises: a D trigger; The first input terminal of the D flip-flop receives the target clock signal; The clock terminal of the D flip-flop is used as its second input terminal and connected to the output terminal of the AND gate; The reset terminal of the D flip-flop is used as its third input terminal and connected to the output terminal of the OR gate; The output end of the D flip-flop outputs the stable clock signal.

7. The delay adjustable clock glitch filtering circuit according to claim 6, characterized in that: The D flip-flop is used to filter the glitches of the target clock signal based on the high and low level states of the first level signal and the second level signal, to obtain and output the target clock signal with the glitches filtered out.

8. The delay adjustable clock glitch filtering circuit according to claim 2, characterized in that: The number of the plurality of delay units is determined according to the delay time of a single delay unit in combination with preset requirements; The number of the plurality of switches is determined according to the number of the delay units; The preset requirement is the pulse width of all glitches contained in clock signals of different frequencies; The different delay times obtained by combining the multiple delay units with the closed or open state of each switch in the multiple switches must satisfy the following requirement: each delay time corresponds to a pulse width of a glitch.

9. The delay adjustable clock glitch filtering circuit according to any one of claims 1 to 3 or 8, characterized in that: Each of the delay units comprises: an inverter; A plurality of the inverters are sequentially connected in series to form a series delay structure, wherein the input end of the first inverter receives the target clock signal, and the output end of the last inverter is connected to the input end of the logic gate unit.

10. A chip, characterized in that: The chip comprises: a plurality of clock units, a multiplexer unit, a digital circuit, a level conversion unit and a delay-adjustable clock glitch filtering circuit as claimed in any one of claims 1 to 9; The output ends of the plurality of clock units are all connected to the input end of the multi-way selection unit; The output end of the multiplexer unit is connected to the adjustable delay unit and the logic gate unit in the adjustable delay clock glitch filtering circuit; The output end of the trigger unit in the delay adjustable clock glitch filtering circuit is connected to the detection end of the digital circuit; The digital end of the level conversion unit is connected to the register in the digital circuit; The analog terminal of the level conversion unit is connected to the delay adjustable unit.

11. The chip according to claim 10, characterized in that: The multiple clock units are used to generate respective clock signals, and the frequencies of the clock signals generated by different clock units are the same or different; The multiplexer selection unit is used for, based on the situation that any clock unit among the multiple clock units generates a clock signal, using the clock signal generated by the clock unit as the target clock signal and transmitting it to the delay adjustable clock glitch filtering circuit; The digital circuit is used to detect whether the burrs in the stable clock signal are filtered through the detection end, and send different adjustment signals to the level conversion unit through the register based on whether the burrs are filtered; The level conversion unit is used to perform level conversion on the different adjustment signals to convert them into corresponding different analog signals, and the different analog signals are the different delay selection signals.

12. An electronic device, characterized in that: The electronic device comprises the chip as described in any one of claims 10-11.

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