Low-power-consumption high-voltage switching circuit suitable for thin gate oxide process

Abstract

The invention relates to a low-power-consumption high-voltage switching circuit suitable for a thin gate oxide process, which belongs to the field of high-voltage domain analog integrated circuits and comprises a charge pump, a delay self-locking switch and a high-voltage switch. The charge pump, the delay self-locking switch and the high-voltage switch are connected in sequence; the charge pump is used for sampling the source end voltage of the high-voltage switch and generating a corresponding boost control signal; the delay self-locking switch is used for outputting a grid end control signal according to the boost control signal so as to control on and off of the high-voltage switch; the delay self-locking switch is provided with a short-circuit switch module; and the short-circuit switch module is used for short-circuiting the gate end and the source end of the high-voltage switch to turn off the high-voltage switch and discharging after the high-voltage switch is turned off. When the high-voltage switch is turned off, the gate end and the source end of the high-voltage switch are quickly short-circuited through the short-circuit switch module arranged in the delay self-locking switch, and then slow discharging is performed, so that the problem of voltage resistance of a pure charge pump structure in the high-voltage switch turn-off action is solved, and quick turn-off of the high-voltage switch is realized.

Description

Technical Field

[0001] The invention belongs to the field of high-voltage domain analog integrated circuits, and in particular relates to a low-power high-voltage switch circuit suitable for a thin gate oxide layer process. Background Art

[0002] In the design of high-voltage analog integrated circuits, we often encounter the need to design clocked high-voltage switches, such as high-voltage signal sampling switches or periodic power drive switches. The use of high-voltage switches can avoid the complex processing flow of high-voltage domain signal buck-transmission-boost, thereby greatly improving the performance and efficiency of the circuit.

[0003] Traditional high-voltage switch implementation schemes are mainly divided into two categories: the first category is the ordinary switch connection method based on the thick gate oxide process, and the second category is the high-voltage switch design scheme using the thin gate oxide process. For the thick gate oxide process, the disadvantages of high process manufacturing cost, high switch threshold voltage, and poor switch transmission performance lead to low market acceptance. The traditional high-voltage switch design scheme based on the thin gate oxide process also has technical defects. On the one hand, the gate-source withstand voltage of the high-voltage transistor of the thin gate oxide process is only 5V, so it cannot be used according to the design scheme of the traditional switch, and a complex boost clamp circuit needs to be designed; on the other hand, the level shift circuit in the traditional high-voltage switch unit, the operational amplifier in the floating clamp circuit and other structures make the circuit scale large and the power consumption high, and the delay of the switching process is also high, making it difficult to achieve fast shutdown. Therefore, a new type of high-voltage switch suitable for the thin gate oxide process is needed. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a low-power high-voltage switch circuit suitable for thin gate oxide layer technology. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] The present invention provides a low-power high-voltage switch circuit suitable for a thin gate oxide process, comprising: a charge pump, a time-delay self-locking switch and a high-voltage switch; wherein the charge pump, the time-delay self-locking switch and the high-voltage switch are connected in sequence; the charge pump is used to sample the source voltage of the high-voltage switch and obtain a boost control signal according to the source voltage of the high-voltage switch; the time-delay self-locking switch is used to output a gate control signal according to the boost control signal to control the on and off of the high-voltage switch; the time-delay self-locking switch is provided with a short-circuit switch module; the short-circuit switch module is used to short-circuit the gate and source ends of the high-voltage switch to turn off the high-voltage switch and discharge after the high-voltage switch is turned off.

[0006] In one embodiment of the present invention, the charge pump comprises: an inverter INV1, an N-type field effect transistor MN3, an N-type field effect transistor MN4, an N-type field effect transistor MN5, an N-type field effect transistor MN6, a diode D1, a diode D2, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2 and a capacitor C3; wherein the input end of the inverter INV1 inputs a clock control signal, and the output end is respectively connected to the gate end of the N-type field effect transistor MN3, the lower plate of the capacitor C1 and the lower plate of the capacitor C3; the source end of the N-type field effect transistor MN3 is connected to the ground end, and the drain end is respectively connected to the source end of the N-type field effect transistor MN4 and the lower plate of the capacitor C2; the source end of the N-type field effect transistor MN5, the source end of the N-type field effect transistor MN6 and the diode The input end of D2 is connected to the power supply voltage end; the gate end of the N-type field effect transistor MN5, the gate end of the N-type field effect transistor MN6 and the output end of the diode D2 are all connected to the upper plate of the capacitor C1; the drain end of the N-type field effect transistor MN5 is connected to the first end of the resistor R1; the drain end of the N-type field effect transistor MN6 is respectively connected to the first end of the resistor R2 and the input end of the diode D1; the second end of the resistor R1 is respectively connected to the second end of the resistor R2, the first end of the resistor R3 and the output end of the diode D1; the input end and the output end of the diode D1 are both connected to the delayed self-locking switch; the upper plate of the capacitor C3 is connected to the second end of the resistor R3; the drain end of the N-type field effect transistor MN4 is connected to the source end of the high-voltage switch, and the gate end is connected to the gate end of the high-voltage switch.

[0007] In one embodiment of the present invention, the delayed self-locking switch includes: a P-type field effect transistor MP1 and a short-circuit switch module; wherein the source end of the P-type field effect transistor MP1 is connected to the input end of the diode D1, the gate end is connected to the output end of the diode D1, and the drain end is connected to the short-circuit switch module; the short-circuit switch module is respectively connected to the gate end and the source end of the high-voltage switch.

[0008] In one embodiment of the present invention, the short-circuit switch module includes: an inverter INV2, an N-type field effect transistor MN7, an N-type field effect transistor MN8, an N-type field effect transistor MN9, a resistor R4, a resistor R5, a resistor R6 and a P-type field effect transistor MP2; wherein the input end of the inverter INV2 inputs a clock control signal, and the output end is respectively connected to the gate ends of the N-type field effect transistor MN7 and the N-type field effect transistor MN9; the source ends of the N-type field effect transistor MN7 and the N-type field effect transistor MN9 are both connected to the ground end; the drain end of the N-type field effect transistor MN7 is connected to the second end of the resistor R5; The first end of the resistor R5 is respectively connected to the second end of the resistor R4 and the gate end of the P-type field effect transistor MP2; the source end of the P-type field effect transistor MP2 is respectively connected to the first end of the resistor R4 and the drain end of the N-type field effect transistor MN8; the drain end of the P-type field effect transistor MP2 is respectively connected to the gate end of the N-type field effect transistor MN8 and the first end of the resistor R6; the second end of the resistor R6 is respectively connected to the source end of the N-type field effect transistor MN8 and the drain end of the N-type field effect transistor MN9; the drain end of the N-type field effect transistor MN8 is connected to the gate end of the high-voltage switch, and the source end is connected to the source end of the high-voltage switch.

[0009] In one embodiment of the present invention, the high-voltage switch includes: an N-type field effect transistor MN1 and an N-type field effect transistor MN2; the gate terminal of the N-type field effect transistor MN1 is connected to the gate terminal of the N-type field effect transistor MN2 and serves as the gate terminal of the high-voltage switch; the source terminal of the N-type field effect transistor MN1 is connected to the source terminal of the N-type field effect transistor MN2 and serves as the source terminal of the high-voltage switch.

[0010] In one embodiment of the present invention, the drain terminal of the N-type field effect transistor MN1 serves as the input terminal of a low-power high-voltage switching circuit suitable for a thin gate oxide process, and the drain terminal of the N-type field effect transistor MN2 serves as the output terminal of the low-power high-voltage switching circuit suitable for a thin gate oxide process.

[0011] In one embodiment of the present invention, the high-voltage switch further includes: a clamping protection module, which is connected in series between the gate terminal and the source terminal of the N-type field effect transistor MN1 and the N-type field effect transistor MN2 to form a discharge path to prevent the N-type field effect transistor MN1 and the N-type field effect transistor MN2 from breaking down.

[0012] In one embodiment of the present invention, the clamping protection module includes: a Zener diode Z1; wherein the first end of the Zener diode Z1 is respectively connected to the source end of the N-type field effect transistor MN1 and the source end of the N-type field effect transistor MN2, and the second end is respectively connected to the gate end of the N-type field effect transistor MN1 and the gate end of the N-type field effect transistor MN2.

[0013] In one embodiment of the present invention, the charge pump and the delayed self-locking switch are both controlled by a clock control signal.

[0014] In one embodiment of the present invention, when the clock control signal turns high, the short-circuit switch module is turned off, the charge pump samples the source voltage of the high-voltage switch, and after boosting, inputs it to the gate of the high-voltage switch through the delayed self-locking switch to turn on the high-voltage switch; when the clock control signal turns low, the short-circuit switch module is turned on to short-circuit the gate and source terminals of the high-voltage switch to turn off the high-voltage switch.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] The low-power high-voltage switch circuit suitable for thin gate oxide layer technology of the present invention ensures the feasibility of the sampling structure based on the charge pump in the high-voltage switch circuit through the delayed self-locking switch. When the high-voltage switch is turned off, compared with the solution in the traditional high-voltage switch circuit that the high-voltage switch is turned off only after the gate terminal is discharged to the conduction threshold voltage, the gate terminal and the source terminal of the high-voltage switch are quickly short-circuited through the short-circuit switch module built into the delayed self-locking switch, and then the discharge is performed slowly, which solves the voltage resistance problem of the pure charge pump structure in the high-voltage switch turn-off action and realizes the rapid turn-off of the high-voltage switch.

[0017] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following specifically cites a preferred embodiment and describes it in detail with the accompanying drawings as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural schematic diagram of a low-power high-voltage switch circuit suitable for a thin gate oxide layer process provided by an embodiment of the present invention;

[0019] Figure 2 It is a schematic diagram of the structure of a charge pump and a delayed self-locking switch provided in an embodiment of the present invention;

[0020] Figure 3 is a structural schematic diagram of a short-circuit switch module in a time-delay self-locking switch provided in an embodiment of the present invention;

[0021] Figure 4 is a structural schematic diagram of a high voltage switch provided by an embodiment of the present invention;

[0022] Figure 5 It is a turn-on timing diagram of a low-power high-voltage switch circuit suitable for a thin gate oxide layer process provided by an embodiment of the present invention.

[0023] Icon: 100-charge pump; 200-delay self-locking switch; 210-short-circuit switch module; 300-high-voltage switch; 310-clamp protection module. DETAILED DESCRIPTION

[0024] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following is a detailed description of a low-power high-voltage switching circuit suitable for a thin gate oxide layer process proposed in accordance with the present invention in combination with the accompanying drawings and specific implementation methods.

[0025] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0026] Embodiment 1

[0027] In view of the disadvantages of high power consumption and large size of the traditional high voltage switch, and the disadvantage that the gate source of the high voltage transistor of the thin gate oxide layer process cannot withstand high voltage, this embodiment provides a low power consumption high voltage switch circuit suitable for the thin gate oxide layer process, such as Figure 1 As shown, Figure 1 It is a structural schematic diagram of a low-power high-voltage switch circuit suitable for a thin gate oxide layer process provided by an embodiment of the present invention.

[0028] In the present embodiment, a low-power high-voltage switch circuit suitable for a thin gate oxide process includes: a charge pump 100, a delayed self-locking switch 200 and a high-voltage switch 300; wherein the charge pump 100, the delayed self-locking switch 200 and the high-voltage switch 300 are connected in sequence; the charge pump 100 is used to sample the source voltage of the high-voltage switch 300, and obtain a boost control signal according to the source voltage of the high-voltage switch; the delayed self-locking switch 200 is used to output a gate control signal VG according to the boost control signal to control the opening and closing of the high-voltage switch 300; the delayed self-locking switch 200 is provided with a short-circuit switch module 210; the short-circuit switch module 210 is used to short-circuit the gate terminal and the source terminal of the high-voltage switch 300 to turn off the high-voltage switch 300, and discharge after the high-voltage switch 300 is turned off.

[0029] It is worth noting that the charge pump 100 and the delayed self-locking switch 200 are both controlled by a clock control signal, and their turn-on timing is as follows: Figure 5 As shown, Figure 5 It is a turn-on timing diagram of a low-power high-voltage switch circuit suitable for a thin gate oxide layer process provided by an embodiment of the present invention.

[0030] Specifically, when the clock control signal turns high, the short-circuit switch module 210 is turned off, the charge pump 100 samples the source voltage of the high-voltage switch 300, and after boosting, inputs it to the gate of the high-voltage switch 300 through the delayed self-locking switch 200 to turn on the high-voltage switch 300; when the clock control signal turns low, the short-circuit switch module 210 is turned on to short-circuit the gate and source ends of the high-voltage switch 300 to turn off the high-voltage switch 300.

[0031] The working principle of the low-power high-voltage switch circuit suitable for thin gate oxide process of this embodiment is as follows: when the clock control signal VC turns high, the charge pump 100 samples the source voltage VS of the high-voltage switch 300 and boosts it to VS+VCC (source voltage+power supply voltage), and then transmits it to the gate of the high-voltage switch 300 through the delay self-locking switch 200; at the same time, the N-type field effect transistor MN1 and the N-type field effect transistor MN2 in the high-voltage switch 300 are both turned on, completing the conduction action of the high-voltage switch 300. When the clock control signal VC turns low, the delay self-locking switch 200 short-circuits the gate and source of the high-voltage switch 300 through the gate control signal VG, thereby completing the shutdown action of the high-voltage switch 300.

[0032] like Figure 2 As shown, Figure 2 It is a schematic diagram of the structure of a charge pump and a delayed self-locking switch provided in an embodiment of the present invention.

[0033] In this embodiment, the charge pump 100 includes: an inverter INV1, an N-type field effect transistor MN3, an N-type field effect transistor MN4, an N-type field effect transistor MN5, an N-type field effect transistor MN6, a diode D1, a diode D2, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2 and a capacitor C3; wherein the input end of the inverter INV1 inputs a clock control signal VC, and the output end is respectively connected to the gate end of the N-type field effect transistor MN3, the lower plate of the capacitor C1 and the lower plate of the capacitor C3; the source end of the N-type field effect transistor MN3 is connected to the ground end, and the drain end is respectively connected to the source end of the N-type field effect transistor MN4 and the lower plate of the capacitor C2; the source end of the N-type field effect transistor MN5 and the source end of the N-type field effect transistor MN6 are connected to the ground end. and the input end of the diode D2 are all connected to the power supply voltage end; the gate end of the N-type field effect transistor MN5, the gate end of the N-type field effect transistor MN6 and the output end of the diode D2 are all connected to the upper plate of the capacitor C1; the drain end of the N-type field effect transistor MN5 is connected to the first end of the resistor R1; the drain end of the N-type field effect transistor MN6 is respectively connected to the first end of the resistor R2 and the input end of the diode D1; the second end of the resistor R1 is respectively connected to the second end of the resistor R2, the first end of the resistor R3 and the output end of the diode D1; the input end and the output end of the diode D1 are both connected to the delayed self-locking switch 200; the upper plate of the capacitor C3 is connected to the second end of the resistor R3; the drain end of the N-type field effect transistor MN4 is connected to the source end of the high-voltage switch 300, and the gate end is connected to the gate end of the high-voltage switch 300.

[0034] In this embodiment, the delayed self-locking switch 200 includes: a P-type field effect transistor MP1 and a short-circuit switch module 210; wherein the source end of the P-type field effect transistor MP1 is connected to the input end of the diode D1, the gate end is connected to the output end of the diode D1, and the drain end is connected to the short-circuit switch module 210; the short-circuit switch module 210 is respectively connected to the gate end and the source end of the high-voltage switch 300.

[0035] like Figure 2 As shown, the working principle of the charge pump 100 and the delayed self-locking switch 200 of this embodiment is that:

[0036] When the clock control signal VC turns high, the short-circuit switch module 210 turns off, and the output signal V1 of the inverter INV1 turns low; the upper plate voltage of the capacitor C1 is charged to the source voltage VCC by the diode D2, and the N-type field effect transistors MN3, MN5 and MN6 are all turned off; because the capacitor has the characteristic that the voltage at both ends cannot change suddenly, the upper plate voltage of the capacitor C3 is pulled down to the ground voltage GND, and the gate voltage V3 of the P-type field effect transistor MP1 is also pulled down to close to the ground voltage GND. Further, by setting the resistance values ​​of the resistors R1, R2 and R3, the P-type field effect transistor MP1 can be turned on in the above situation, and the gate control signal VG is pulled up to the power supply voltage VCC by the capacitor C2; the N-type field effect transistor MN4 is turned on, and the source end of the high-voltage switch 300 is connected to the lower plate of the capacitor C2, and the gate control signal VG is VS+VCC at this time, so that the high-voltage switch 300 is turned on.

[0037] After the high-voltage switch 300 is turned on, the high-voltage signals at the input port A and the output port B of the high-voltage switch 300 are transmitted to its source end. Due to the bootstrap effect of the capacitor C2, the gate control signal VG is always maintained at VS+VCC, so that the high-voltage switch 300 remains turned on.

[0038] When the clock control signal VC turns low, the short-circuit switch module 210 turns on to short-circuit the source and gate of the high-voltage switch 300 and discharges to the ground voltage GND, and the N-type field effect transistor MN4 turns off; the output signal V1 of the inverter INV1 turns high, the N-type field effect transistor MN3 turns on, and the lower plate voltage of the capacitor C2 is pulled down to the ground voltage GND. At the same time, the upper plate voltage of the capacitor C1 is bootstrapped to 2 times the power supply voltage VCC, the N-type field effect transistor MN5 and the N-type field effect transistor MN6 are both turned on, and the upper plate voltage of the capacitor C2 is also pulled up and charged to the power supply voltage VCC; the upper plate voltage of the capacitor C3 is bootstrapped to the power supply voltage VCC, thereby quickly turning off the P-type field effect transistor MP1.

[0039] It is worth noting that the diode D1 is provided to prevent the P-type field effect transistor MP1 from breaking down due to excessive gate-source voltage during the operation of the charge pump 100 .

[0040] like Figure 3 As shown, Figure 3 It is a structural schematic diagram of a short-circuit switch module in a delayed self-locking switch provided in an embodiment of the present invention.

[0041] In this embodiment, the short-circuit switch module 210 includes: an inverter INV2, an N-type field effect transistor MN7, an N-type field effect transistor MN8, an N-type field effect transistor MN9, a resistor R4, a resistor R5, a resistor R6 and a P-type field effect transistor MP2; wherein the input end of the inverter INV2 inputs a clock control signal, and the output end is respectively connected to the gate end of the N-type field effect transistor MN7 and the N-type field effect transistor MN9; the source end of the N-type field effect transistor MN7 and the N-type field effect transistor MN9 are both connected to the ground end; the drain end of the N-type field effect transistor MN7 is connected to the second end of the resistor R5 ; The first end of the resistor R5 is respectively connected to the second end of the resistor R4 and the gate end of the P-type field effect transistor MP2; the source end of the P-type field effect transistor MP2 is respectively connected to the first end of the resistor R4 and the drain end of the N-type field effect transistor MN8; the drain end of the P-type field effect transistor MP2 is respectively connected to the gate end of the N-type field effect transistor MN8 and the first end of the resistor R6; the second end of the resistor R6 is respectively connected to the source end of the N-type field effect transistor MN8 and the drain end of the N-type field effect transistor MN9; the drain end of the N-type field effect transistor MN8 is connected to the gate end of the high-voltage switch 300, and the source end is connected to the source end of the high-voltage switch 300.

[0042] like Figure 3 As shown, the working principle of the short-circuit switch module 210 of this embodiment is:

[0043] When the clock control signal VC turns high, the output signal of the inverter INV2 turns low. When the high-voltage switch 300 needs to be turned on, the N-type field effect transistors MN7, MN8 and MN9 are all turned off, and the P-type field effect transistor MP2 is also turned off.

[0044] During the high-voltage switch conduction operation of the charge pump 100 and the delayed self-locking switch 200, the gate control signal VG is always higher than the source voltage VS of the high-voltage switch 300, and the short-circuit switch module 210 always disconnects the gate and source ends of the high-voltage switch 300 to avoid interfering with the high-voltage signal transmitted thereto.

[0045] When the clock control signal VC turns low, the output of the inverter INV2 turns high, and when the high-voltage switch 300 needs to be turned off, the N-type field effect transistor MN7 is turned on, and the resistors R4 and R5 discharge the gate terminal of the high-voltage switch 300; the voltage drop generated on the resistor R4 turns on the P-type field effect transistor MP2, and the discharge current generated by the P-type field effect transistor MP2 and the N-type field effect transistor MN9 forms a voltage difference at both ends of the resistor R6 to turn on the N-type field effect transistor MN8, thereby quickly short-circuiting the gate terminal and the source terminal of the high-voltage switch 300, thereby turning off the high-voltage switch 300; finally, the N-type field effect transistor MN7 and the N-type field effect transistor MN9 discharge the gate terminal control signal VG and the source terminal voltage VS of the high-voltage switch 300 to the ground voltage GND.

[0046] It is worth noting that the feasibility of applying the charge pump 100 to the high-voltage switch circuit is ensured by the delayed self-locking switch 200. When the high-voltage switch 300 is turned off, the short-circuit switch module 210 built into the delayed self-locking switch 200 first quickly short-circuits the gate control signal VG and the source voltage VS of the high-voltage switch 300 and then slowly discharges. This can perfectly solve the voltage resistance problem in the shutdown action of applying the pure charge pump structure to the high-voltage switch, and also realize the rapid shutdown of the high-voltage switch.

[0047] In this embodiment, the high-voltage switch 300 includes: an N-type field effect transistor MN1 and an N-type field effect transistor MN2; the gate terminal of the N-type field effect transistor MN1 is connected to the gate terminal of the N-type field effect transistor MN2 and serves as the gate terminal of the high-voltage switch 300; the source terminal of the N-type field effect transistor MN1 is connected to the source terminal of the N-type field effect transistor MN2 and serves as the source terminal of the high-voltage switch 300.

[0048] Specifically, the drain end of the N-type field effect transistor MN1 serves as the input end or output end of the low-power high-voltage switching circuit suitable for the thin gate oxide layer process; correspondingly, the drain end of the N-type field effect transistor MN2 serves as the output end or input end of the low-power high-voltage switching circuit suitable for the thin gate oxide layer process.

[0049] In an optional embodiment, the high-voltage switch 300 further includes: a clamping protection module 310, which is connected in series between the gate terminal and the source terminal of the N-type field effect transistor MN1 and the N-type field effect transistor MN2 to form a discharge path to prevent the N-type field effect transistor MN1 and the N-type field effect transistor MN2 from breaking down.

[0050] like Figure 4 As shown, Figure 4 It is a structural schematic diagram of a high voltage switch provided by an embodiment of the present invention.

[0051] Specifically, the clamp protection module 310 includes: a Zener diode Z1; wherein the first end of the Zener diode Z1 is respectively connected to the source end of the N-type field effect transistor MN1 and the N-type field effect transistor MN2, and the second end is respectively connected to the gate end of the N-type field effect transistor MN1 and the N-type field effect transistor MN2.

[0052] The principle is that the clamp protection module 310 detects the voltage difference between the gate control signal VG and the source voltage VS of the high-voltage switch 300. When VG-VS is greater than the gate-source safety withstand voltage of the N-type field effect transistor MN1 and the N-type field effect transistor MN2, it is turned on to form a discharge path from the gate end of the high-voltage switch 300 to its source end to protect the functions of the N-type field effect transistor MN1 and the N-type field effect transistor MN2. Taking the Zener diode Z1 as an example, when VG-VS is greater than 5.5V, the Zener diode Z1 is reversely turned on, generating a current discharge from the gate end of the high-voltage switch 300 to its source end, thereby clamping VG-VS to 5.5V.

[0053] The low-power high-voltage switch circuit suitable for thin gate oxide layer technology of the present invention ensures the feasibility of the sampling structure based on the charge pump in the high-voltage switch circuit through the delayed self-locking switch. When the high-voltage switch is turned off, compared with the solution in the traditional high-voltage switch circuit that the high-voltage switch is turned off only after the gate terminal is discharged to the conduction threshold voltage, the gate terminal and the source terminal of the high-voltage switch are quickly short-circuited through the short-circuit switch module built into the delayed self-locking switch, and then the discharge is performed slowly, which solves the voltage resistance problem of the pure charge pump structure in the high-voltage switch turn-off action and realizes the rapid turn-off of the high-voltage switch.

[0054] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0055] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A low-power high-voltage switching circuit suitable for thin gate oxide process, characterized in that: include: A charge pump (100), a time-delay self-locking switch (200) and a high-voltage switch (300); Wherein, the charge pump (100), the delayed self-locking switch (200) and the high-voltage switch (300) are connected in sequence; The charge pump (100) is used to sample the source terminal voltage of the high-voltage switch (300) and obtain a boost control signal according to the source terminal voltage of the high-voltage switch (300); The delayed self-locking switch (200) is used to output a gate control signal according to the boost control signal to control the opening and closing of the high-voltage switch (300); The delayed self-locking switch (200) is provided with a short-circuit switch module (210); the short-circuit switch module (210) is used to short-circuit the gate end and the source end of the high-voltage switch (300) to turn off the high-voltage switch (300), and to discharge after the high-voltage switch (300) is turned off.

2. The low-power high-voltage switch circuit suitable for thin gate oxide process according to claim 1, characterized in that: The charge pump (100) comprises: an inverter INV1, an N-type field effect transistor MN3, an N-type field effect transistor MN4, an N-type field effect transistor MN5, an N-type field effect transistor MN6, a diode D1, a diode D2, a resistor R1, a resistor R2, a resistor R3, a capacitor C1, a capacitor C2 and a capacitor C3; The input end of the inverter INV1 inputs a clock control signal, and the output end is respectively connected to the gate end of the N-type field effect transistor MN3, the lower plate of the capacitor C1 and the lower plate of the capacitor C3; The source end of the N-type field effect transistor MN3 is connected to the ground end, and the drain end is respectively connected to the source end of the N-type field effect transistor MN4 and the lower plate of the capacitor C2; the source end of the N-type field effect transistor MN5, the source end of the N-type field effect transistor MN6 and the input end of the diode D2 are all connected to the power supply voltage end; the gate end of the N-type field effect transistor MN5, the gate end of the N-type field effect transistor MN6 and the output end of the diode D2 are all connected to the upper plate of the capacitor C1; The drain end of the N-type field effect transistor MN5 is connected to the first end of the resistor R1; the drain end of the N-type field effect transistor MN6 is respectively connected to the first end of the resistor R2 and the input end of the diode D1; the second end of the resistor R1 is respectively connected to the second end of the resistor R2, the first end of the resistor R3 and the output end of the diode D1; The input end and the output end of the diode D1 are both connected to the delayed self-locking switch (200); The upper plate of the capacitor C3 is connected to the second end of the resistor R3; The drain terminal of the N-type field effect transistor MN4 is connected to the source terminal of the high-voltage switch (300), and the gate terminal is connected to the gate terminal of the high-voltage switch (300).

3. The low-power high-voltage switch circuit suitable for thin gate oxide process according to claim 2, characterized in that: The delayed self-locking switch (200) comprises: a P-type field effect transistor MP1 and a short-circuit switch module (210); wherein the source end of the P-type field effect transistor MP1 is connected to the input end of the diode D1, the gate end is connected to the output end of the diode D1, and the drain end is connected to the short-circuit switch module (210); The short-circuit switch module (210) is respectively connected to the gate terminal and the source terminal of the high-voltage switch (300).

4. The low-power high-voltage switch circuit suitable for thin gate oxide process according to claim 3, characterized in that: The short-circuit switch module (210) comprises: an inverter INV2, an N-type field effect transistor MN7, an N-type field effect transistor MN8, an N-type field effect transistor MN9, a resistor R4, a resistor R5, a resistor R6 and a P-type field effect transistor MP2; The input end of the inverter INV2 inputs a clock control signal, and the output end is respectively connected to the gate end of the N-type field effect transistor MN7 and the gate end of the N-type field effect transistor MN9; the source end of the N-type field effect transistor MN7 and the source end of the N-type field effect transistor MN9 are both connected to the ground end; the drain end of the N-type field effect transistor MN7 is connected to the second end of the resistor R5; the first end of the resistor R5 is respectively connected to the second end of the resistor R4 and the gate end of the P-type field effect transistor MP2; The source end of the P-type field effect transistor MP2 is respectively connected to the first end of the resistor R4 and the drain end of the N-type field effect transistor MN8; the drain end of the P-type field effect transistor MP2 is respectively connected to the gate end of the N-type field effect transistor MN8 and the first end of the resistor R6; The second end of the resistor R6 is connected to the source end of the N-type field effect transistor MN8 and the drain end of the N-type field effect transistor MN9 respectively; The drain terminal of the N-type field effect transistor MN8 is connected to the gate terminal of the high-voltage switch (300), and the source terminal is connected to the source terminal of the high-voltage switch (300).

5. The low-power high-voltage switch circuit suitable for thin gate oxide process according to claim 1, characterized in that: The high voltage switch (300) comprises: an N-type field effect transistor MN1 and an N-type field effect transistor MN2; The gate terminal of the N-type field effect transistor MN1 is connected to the gate terminal of the N-type field effect transistor MN2 and serves as the gate terminal of the high-voltage switch (300); The source end of the N-type field effect transistor MN1 is connected to the source end of the N-type field effect transistor MN2 and serves as the source end of the high voltage switch (300).

6. The low-power high-voltage switch circuit suitable for thin gate oxide process according to claim 4, characterized in that: The drain end of the N-type field effect transistor MN1 serves as the input end of the low-power high-voltage switch circuit suitable for thin gate oxide layer technology, and the drain end of the N-type field effect transistor MN2 serves as the output end of the low-power high-voltage switch circuit suitable for thin gate oxide layer technology.

7. The low-power high-voltage switch circuit suitable for thin gate oxide process according to claim 5, characterized in that: The high-voltage switch (300) further comprises: a clamping protection module (310), the clamping protection module (310) being connected in series between the gate terminal and the source terminal of the N-type field effect transistor MN1 and the N-type field effect transistor MN2, and being used to form a discharge path to prevent the N-type field effect transistor MN1 and the N-type field effect transistor MN2 from breaking down.

8. The low-power high-voltage switch circuit suitable for thin gate oxide process according to claim 7, characterized in that: The clamping protection module (310) comprises: a Zener diode Z1; wherein the first end of the Zener diode Z1 is respectively connected to the source end of the N-type field effect transistor MN1 and the source end of the N-type field effect transistor MN2, and the second end is respectively connected to the gate end of the N-type field effect transistor MN1 and the gate end of the N-type field effect transistor MN2.

9. The low-power high-voltage switch circuit suitable for thin gate oxide process according to claim 4, characterized in that: The charge pump (100) and the delayed self-locking switch (200) are both controlled by a clock control signal.

10. The low-power high-voltage switch circuit suitable for thin gate oxide process according to claim 9, characterized in that: When the clock control signal turns high, the short-circuit switch module (210) is turned off, the charge pump (100) samples the source voltage of the high-voltage switch (300), and after voltage boosting, inputs the voltage to the gate of the high-voltage switch (300) through the delayed self-locking switch (200) to turn on the high-voltage switch (300); When the clock control signal turns low, the short-circuit switch module (210) is turned on to short-circuit the gate terminal and the source terminal of the high-voltage switch (300), so that the high-voltage switch (300) is turned off.

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