Control protection circuit for analog multiplexer

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a control protection circuit for an analog multiplexer. The circuit comprises a decoder, a multi-path driving control circuit, a substrate protection circuit and a switching power tube, the output of the decoder is connected with the multi-path driving control circuit; each driving control circuit is connected with the corresponding substrate protection circuit and the corresponding switching power tube; the substrate protection circuit corresponding to each driving control circuit is connected with the switching power tube; two-path common-state conduction of the multiplexer can be effectively avoided, the circuit can be protected from being burnt down when transmission signals have super power supply voltage burrs, and the stability and the reliability of the circuit are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a control protection circuit for an analog multiplexer. Background Art

[0002] Analog multiplexers are a type of analog switch, mainly used in integrated circuits, especially in signal acquisition systems and signal transmission systems, to achieve the transmission of analog signals. In current signal transmission systems, the acquisition accuracy and reliability of multiplexers are very high. Especially for multi-channel signal acquisition systems, the acquisition accuracy and authenticity of each signal are very high. If the control signal timing of each switch power tube is inaccurate and the driving ability is not strong enough, the switch power tube will not be turned on and off in time, resulting in the common conduction of the switch power tube, which will increase the power consumption of the chip and cause the signal transmission to short-circuit, or even burn the circuit. This will affect the authenticity of the signal and cause the system to misjudge the signal.

[0003] The current commonly used multiplexer control circuit is usually driven by an inverter (such as Figure 1 As shown in the figure, the switch power tube is composed of parallel MOS tubes, the substrate is fixed, and the front-stage driver is controlled by a two-stage inverter to generate a drive signal for the switch tube. Although this structure is simple, it also limits the control dead zone capability of the drive circuit and the protection capability of the switch power tube. At present, many analog signals that need to be transmitted may have burrs that exceed the power supply voltage. If the substrate of the power tube is not controlled and the dead zone time of the control signal is not strictly controlled, the circuit may burn out and fail when the circuit signal is frequently switched.

[0004] In summary, there is an urgent need for a control protection circuit for an analog multiplexer, which can effectively improve the driving capability of the control signal while avoiding the risk of burning the circuit when the transmission signal exceeds the supply voltage burr, thereby effectively protecting the circuit. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention proposes a control protection circuit for an analog multiplexer, which circuit includes: a decoder, a multi-channel drive control circuit, a substrate protection circuit and a switch power tube; the decoder output is connected to the multi-channel drive control circuit; each drive control circuit is connected to the corresponding substrate protection circuit and the switch power tube; the substrate protection circuit and the switch power tube corresponding to each drive control circuit are interconnected.

[0006] Preferably, the drive control circuit includes 10 PMOS tubes P6 to P15, 10 NMOS tubes N6 to N15, a resistor R1 and a capacitor C1; the gate of the PMOS tube P6, the gate of the NMOS tube N6, the gate of the PMOS tube P9 and the gate of the NMOS tube N9 are all connected to the control signal CL; the source and substrate of all PMOS tubes except the PMOS tube P11 are connected to the power supply VDD; The sources and substrates of all NMOS tubes except 9 are connected to the power supply VSS; the drain of PMOS tube P6 is connected to the drain of NMOS tube N6, the gate of PMOS tube P7, the gate of NMOS tube N7, the gate of PMOS tube P11 and the gate of NMOS tube N11; the drain of PMOS tube P7 is connected to one end of resistor R1, the drain of NMOS tube N7 is connected to the other end of resistor R1, the gate of PMOS tube P8, the gate of NMOS tube N8, the gate of NMOS tube N10 and one end of capacitor C1, and the other end of capacitor C1 is connected to the power supply VSS; the drain of PMOS tube P8 is connected to the drain of NMOS tube N8 and the gate of PMOS tube P10; the substrate of PMOS tube P11 is connected to the power supply VDD, the drain of PMOS tube P11 is connected to the drain of NMOS tube N11, the drain of PMOS tube P11 and the gate of NMOS tube N10. The gate of the PMOS tube P3 and the gate of the NMOS tube N13 are connected; the drain of the PMOS tube P13 is connected to the drain of the NMOS tube N13, the gate of the PMOS tube P15 and the gate of the NMOS tube N15; the drain of the PMOS tube P15 and the drain of the NMOS tube N15 are connected to the substrate protection circuit and the switch power tube; the drain of the NMOS tube N10 is connected to the source of the NMOS tube N9; the substrate of the NMOS tube N9 is connected to the power supply VSS, the drain of the NMOS tube N9 is connected to the drain of the PMOS tube P9, the gate of the PMOS tube P12 and the gate of the NMOS tube N12; the drain of the PMOS tube P12 is connected to the drain of the NMOS tube N12, the gate of the PMOS tube P14 and the gate of the NMOS tube N14, and the drain of the PMOS tube P14 and the drain of the NMOS tube N14 are connected to the substrate protection circuit and the switch power tube.

[0007] Preferably, the substrate protection circuit includes four PMOS tubes P2 to P5, four NMOS tubes N2 to N5 and two resistors R2 to R3; the gate of the PMOS tube P2, the gate of the PMOS tube P4, the gate of the NMOS tube N3 and the gate of the NMOS tube N5 are all connected to the drain of the PMOS tube P14 and the drain of the NMOS tube N14 in the drive control circuit; the gate of the PMOS tube P3, the gate of the PMOS tube P5, the gate of the NMOS tube N2 and the gate of the NMOS tube N4 are all connected to the drain of the PMOS tube P15 and the drain of the NMOS tube N15 in the drive control circuit; the drain of the PMOS tube P2, the source of the NMOS tube N2, the source of the PMOS tube P4 and the drain of the NMOS tube N4 are all connected to the input signal VIN; the source of the PMOS tube P2 is connected to the PMOS tube P14; the drain of the PMOS tube P15 is connected to the PMOS tube P15 ... is connected to the PMOS tube P15; the drain of the PMOS tube P2 is connected to the PMOS tube P15; the drain of the PMOS tube P2 is connected to the PMOS tube P15; the drain of the PMOS tube P2 is connected to the PMOS tube P15; the drain of the PMOS tube P2 is connected to the PMOS tube P15; the drain of the PMOS tube P2 is connected to the PMOS tube P15; the drain of the PMOS tube P2 is connected to the PMOS tube P15; the drain of the PMOS tube P2 is connected to the The substrate of the MOS tube P2, the drain of the NMOS tube N2, one end of the resistor R2 and the switch power tube; the other end of the resistor R2 is connected to the source of the NMOS tube N3 and the drain of the PMOS tube P3; the drain of the NMOS tube N3, the source of the PMOS tube P3, the substrate of the PMOS tube P3, the substrate of the PMOS tube P4 and the substrate of the PMOS tube P5 are all connected to the power supply VDD; the drain of the PMOS tube P4 is connected to the substrate of the NMOS tube N4, the source of the NMOS tube N4, one end of the resistor R3 and the switch power tube; the other end of the resistor R3 is connected to the drain of the NMOS tube N5 and the source of the PMOS tube P5; the substrate of the NMOS tube N2, the substrate of the NMOS tube N3, the substrate of the NMOS tube N5, the source of the NMOS tube N5 and the drain of the PMOS tube P5 are all connected to the power supply VSS.

[0008] Preferably, the switching power tube includes an NMOS tube N1 and a PMOS tube P1; the source of the NMOS tube N1 and the source of the PMOS tube P1 are both connected to the input signal VIN; the drain of the NMOS tube N1 and the drain of the PMOS tube P1 are connected as the output of the switching power tube; the gate of the NMOS tube N1 is connected to the drain of the PMOS tube P15 and the drain of the NMOS tube N15 in the drive control circuit, and the gate of the PMOS tube P1 is connected to the drain of the PMOS tube P14 and the drain of the NMOS tube N14 in the drive control circuit; the substrate of the NMOS tube N1 is connected to the drain of the PMOS tube P4 in the substrate protection circuit, and the substrate of the PMOS tube P1 is connected to the drain of the NMOS tube N2 in the substrate protection circuit.

[0009] The beneficial effects of the present invention are as follows: the control protection circuit designed for the analog multiplexer of the present invention can effectively improve the driving capability of the control signal through reasonable drive control circuit design and substrate protection circuit design, while avoiding the common-state conduction and increased power consumption of the multiplexer, and the influence of the protection circuit on the circuit when there is a power supply glitch exceeding the power supply voltage, thereby effectively avoiding the risk of burning the circuit when the transmission signal exceeds the power supply voltage glitch; compared with the prior art, the present invention can more effectively protect the circuit and improve the accuracy and reliability of the multiplexer in the signal transmission system. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a conventional multiplexer driving circuit diagram;

[0011] Figure 2 This is a structural diagram of a control protection circuit for an analog multiplexer in the present invention;

[0012] Figure 3 This is a driving protection circuit diagram of the present invention;

[0013] Figure 4 It is a timing diagram of the control signals and substrate signals of the first and nth paths of the driving protection circuit in the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] The present invention proposes a control protection circuit for an analog multiplexer, such as Figure 2 As shown, the circuit includes: a decoder, a multi-channel drive control circuit, a substrate protection circuit and a switch power tube; the decoder output is connected to the multi-channel drive control circuit; each drive control circuit is connected to the corresponding substrate protection circuit and switch power tube; the substrate protection circuit and the switch power tube corresponding to each drive control circuit are interconnected.

[0016] The control protection circuit of the present invention is composed of a decoder and a multi-channel drive protection circuit. The decoder structure is determined according to the number of channels of the multiplexer, and can effectively translate the address signal into the corresponding multiplexer control signal according to its original meaning, so as to realize the logical function. A drive control circuit, a substrate protection circuit and a switch power tube form a drive protection circuit. The drive protection circuit is implemented as follows. Figure 3 shown.

[0017] The drive control circuit includes 10 PMOS tubes P6 to P15, 10 NMOS tubes N6 to N15, a resistor R1 and a capacitor C1; the gate of the PMOS tube P6, the gate of the NMOS tube N6, the gate of the PMOS tube P9 and the gate of the NMOS tube N9 are all connected to the control signal CL; the source and substrate of all PMOS tubes except the PMOS tube P11 are connected to the power supply VDD; except the NMOS tube N The sources and substrates of all NMOS tubes except 9 are connected to the power supply VSS; the drain of PMOS tube P6 is connected to the drain of NMOS tube N6, the gate of PMOS tube P7, the gate of NMOS tube N7, the gate of PMOS tube P11 and the gate of NMOS tube N11; the drain of PMOS tube P7 is connected to one end of resistor R1, the drain of NMOS tube N7 is connected to the other end of resistor R1, the gate of PMOS tube P8, the gate of NMOS tube N8, the gate of NMOS tube N10 and one end of capacitor C1, and the other end of capacitor C1 is connected to the power supply VSS; the drain of PMOS tube P8 is connected to the drain of NMOS tube N8 and the gate of PMOS tube P10; the substrate of PMOS tube P11 is connected to the power supply VDD, the drain of PMOS tube P11 is connected to the drain of NMOS tube N11, the drain of PMOS tube P11 and the gate of NMOS tube N10. The gate of the PMOS tube P3 and the gate of the NMOS tube N13 are connected; the drain of the PMOS tube P13 is connected to the drain of the NMOS tube N13, the gate of the PMOS tube P15 and the gate of the NMOS tube N15; the drain of the PMOS tube P15 and the drain of the NMOS tube N15 are connected to the substrate protection circuit and the switch power tube; the drain of the NMOS tube N10 is connected to the source of the NMOS tube N9; the substrate of the NMOS tube N9 is connected to the power supply VSS, the drain of the NMOS tube N9 is connected to the drain of the PMOS tube P9, the gate of the PMOS tube P12 and the gate of the NMOS tube N12; the drain of the PMOS tube P12 is connected to the drain of the NMOS tube N12, the gate of the PMOS tube P14 and the gate of the NMOS tube N14, and the drain of the PMOS tube P14 and the drain of the NMOS tube N14 are connected to the substrate protection circuit and the switch power tube.

[0018] The substrate protection circuit includes four PMOS tubes P2-P5, four NMOS tubes N2-N5 and two resistors R2-R3; the gate of the PMOS tube P2, the gate of the PMOS tube P4, the gate of the NMOS tube N3 and the gate of the NMOS tube N5 are all connected to the drain of the PMOS tube P14 and the drain of the NMOS tube N14 in the drive control circuit; the gate of the PMOS tube P3, the gate of the PMOS tube P5, the gate of the NMOS tube N2 and the gate of the NMOS tube N4 are all connected to the drain of the PMOS tube P15 and the drain of the NMOS tube N15 in the drive control circuit; the drain of the PMOS tube P2, the source of the NMOS tube N2, the source of the PMOS tube P4 and the drain of the NMOS tube N4 are all connected to the input signal VIN; the source of the PMOS tube P2 is connected to the PMOS The substrate of the S tube P2, the drain of the NMOS tube N2, one end of the resistor R2 and the switch power tube; the other end of the resistor R2 is connected to the source of the NMOS tube N3 and the drain of the PMOS tube P3; the drain of the NMOS tube N3, the source of the PMOS tube P3, the substrate of the PMOS tube P3, the substrate of the PMOS tube P4 and the substrate of the PMOS tube P5 are all connected to the power supply VDD; the drain of the PMOS tube P4 is connected to the substrate of the NMOS tube N4, the source of the NMOS tube N4, one end of the resistor R3 and the switch power tube; the other end of the resistor R3 is connected to the drain of the NMOS tube N5 and the source of the PMOS tube P5; the substrate of the NMOS tube N2, the substrate of the NMOS tube N3, the substrate of the NMOS tube N5, the source of the NMOS tube N5 and the drain of the PMOS tube P5 are all connected to the power supply VSS.

[0019] The switch power tube includes an NMOS tube N1 and a PMOS tube P1; the source of the NMOS tube N1 and the source of the PMOS tube P1 are both connected to the input signal VIN; the gate of the NMOS tube N1 is connected to the drain of the PMOS tube P15 and the drain of the NMOS tube N15 in the drive control circuit, and the gate of the PMOS tube P1 is connected to the drain of the PMOS tube P14 and the drain of the NMOS tube N14 in the drive control circuit; the substrate of the NMOS tube N1 is connected to the drain of the PMOS tube P4 in the substrate protection circuit, and the substrate of the PMOS tube P1 is connected to the drain of the NMOS tube N2 in the substrate protection circuit; the drain of the NMOS tube N1 and the drain of the PMOS tube P1 are connected as the output of the switch power tube.

[0020] The implementation principle of the present invention is:

[0021] The multiplexer includes multiple channels, which can be 2 channels, 4 channels, 8 channels, 16 channels, 32 channels, or even more. A1~An are address signals, which serve as input signals of the decoder. The decoder generates n control signals CL1~CLn, and the selected control signal CL is an inverse complementary signal to the control signals of other channels. The CL signal generates a CN signal and a CP signal through the drive control circuit, wherein the signal CN and the signal CP are inverse, the CN signal generated by the multiplexer selected channel drive control is inverse to the CN signal generated by the remaining shut-down channel drive control circuit, and the CP signal generated by the multiplexer selected channel drive control is inverse to the CP signal generated by the remaining shut-down channel drive control circuit. The control drive circuit can effectively enhance the control signal driving capability of the multiplexer, and stabilize the control timing of each control signal; avoid the common conduction of multiple channels, and select only one channel to output the input signal VIN to VOUT, so that the transmitted signal is stably transmitted to the output. The CN signal and the CP signal are simultaneously used as input signals for the switch power tube and the substrate protection circuit to control the on or off of the switch power tube and the switching state of the substrate protection circuit. The substrate protection circuit receives the CN signal and the CP signal, generates substrate signals NB and PB for the switch power tube, so that the substrate is at the correct potential when the switch power tube is turned on or off, and can protect the multiplexer from being burned when the transmission signal has overshoot.

[0022] like Figure 3 As shown in , CL is the control signal translated by the decoder. For the multiplexer, the CL signal generated by the decoder, the control signal CL for opening the channel is opposite to the control signal generated by the decoder for closing other channels. Here, the first channel is used as an example to open the channel, and the nth channel is used as an example to close the channel. That is, the CL signal and CLn signal generated by the decoder are a pair of opposite complementary signals.

[0023] The CL signal generates a CM signal through P6 and N6, which can shape the CL signal generated by the decoder. The CM signal is opposite to the CL signal. The CM signal generates a CQ signal through P7 and N7, and generates a unilateral delay through R1 and C1, delaying the rise time of its rising edge. The CL and CQ signals generate a CS signal through P9, N9 and N10. The CL signal and the CQ signal are in the same direction. Due to the delay in the rise time of the CQ signal, N10 will be turned on after N9 is turned on, which will delay the fall time of the CS signal, but will not affect the rise time of CS. The CS signal generates a CP signal through P12, N12, P14, and N14, which enhances the signal driving capability of CP, thereby driving the switch power tube P1 to turn on and off, and can achieve fast shutdown of P1. The CQ signal passes through P8 and N8 to generate the CR signal. The CR signal and the CM signal pass through P10, P11, and N11 to generate the CT signal. Due to the delay in the rise time of the CQ signal, P10 will be turned on after P11 is turned on, which delays the rise time of the CT signal, but does not affect the fall time of CT. The CT signal passes through P13, N13, P15, and N15 to generate the CN signal, which enhances the driving ability of the CN signal, thereby driving the switch power tube N1 to turn on and off, and realizing the rapid shutdown of N1.

[0024] At the same time, the CP signal is used as the driving signal of P2, N3, P4, and N5, and the CN signal is used as the driving signal of N2, P3, N4, and P5. P2 and N2 adopt a parallel structure, which can quickly turn on P2 and N2 when the switch tube P1 is turned on, and follow the substrate signal PB of the P1 tube to the input signal VIN, eliminating the substrate bias effect of the P1 tube when it is turned on, and protecting the circuit from damage caused by long-term input signal glitches. N3 and P3 adopt a parallel structure, which can quickly turn on N3 and P3 when the switch tube P1 is turned off, and embed the substrate signal PB of the P1 tube to the highest power supply potential VDD. R2 is used as a protective resistor to protect the tube from burning due to the dynamic large current caused by the injected charge and port capacitance of the switch tube when the control signal is constantly switched. P4 and N4 adopt a parallel structure, which can quickly turn on P4 and N4 when the switch tube N1 is turned on, and follow the substrate signal NB of the N1 tube to the input signal VIN, eliminating the substrate bias effect of the N1 tube when it is turned on, and protecting the circuit from damage caused by long-term input signal glitches. N5 and P5 adopt a parallel structure, which can quickly turn on N5 and P5 when the switch tube N1 is turned off, and embed the substrate signal NB of the N1 tube to the lowest power supply potential VSS. R3 is used as a protection resistor to protect the tube from burning due to the dynamic large current caused by the injected charge of the switch tube and the port capacitance when the control signal is constantly switched.

[0025] The first channel is the open channel, and the nth channel is the closed channel. Their same control signals are reversed, such as Figure 4 As shown, by reasonably setting the drive control circuit and the substrate protection circuit, the on and off states of the multiplexer can be effectively controlled to avoid common-state conduction. At the same time, the substrate potential of the switching power tube can be effectively controlled to eliminate the substrate bias effect and effectively avoid the risk of circuit damage caused by transmission signal glitches and overshoots.

[0026] In summary, the present invention proposes a control protection circuit for an analog multiplexer, which can effectively avoid the two channels of the multiplexer from being turned on in the same state through reasonable drive control circuit design and substrate protection circuit design, and can protect the circuit from being burned when the transmission signal has an over-supply voltage glitch, thereby improving the stability and reliability of the circuit.

[0027] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A control protection circuit for an analog multiplexer, characterized in that: include: Decoder, multi-channel drive control circuit, substrate protection circuit and switch power tube; The decoder output is connected to a multi-channel drive control circuit; Each driving control circuit is connected to a corresponding substrate protection circuit and a switching power tube; and the substrate protection circuit and the switching power tube corresponding to each driving control circuit are connected to each other.

2. A control protection circuit for an analog multiplexer according to claim 1, characterized in that: The driving control circuit includes 10 PMOS tubes P6-P15, 10 NMOS tubes N6-N15, a resistor R1 and a capacitor C1; the gate of the PMOS tube P6, the gate of the NMOS tube N6, the gate of the PMOS tube P9 and the gate of the NMOS tube N9 are all connected to the control signal CL; the source and substrate of all PMOS tubes except the PMOS tube P11 are connected to the power supply VDD; The sources and substrates of all NMOS tubes except 9 are connected to the power supply VSS; the drain of PMOS tube P6 is connected to the drain of NMOS tube N6, the gate of PMOS tube P7, the gate of NMOS tube N7, the gate of PMOS tube P11 and the gate of NMOS tube N11; the drain of PMOS tube P7 is connected to one end of resistor R1, the drain of NMOS tube N7 is connected to the other end of resistor R1, the gate of PMOS tube P8, the gate of NMOS tube N8, the gate of NMOS tube N10 and one end of capacitor C1, and the other end of capacitor C1 is connected to the power supply VSS; the drain of PMOS tube P8 is connected to the drain of NMOS tube N8 and the gate of PMOS tube P10; the substrate of PMOS tube P11 is connected to the power supply VDD, the drain of PMOS tube P11 is connected to the drain of NMOS tube N11, the drain of PMOS tube P11 and the gate of NMOS tube N10. The gate of the PMOS tube P3 and the gate of the NMOS tube N13 are connected; the drain of the PMOS tube P13 is connected to the drain of the NMOS tube N13, the gate of the PMOS tube P15 and the gate of the NMOS tube N15; the drain of the PMOS tube P15 and the drain of the NMOS tube N15 are connected to the substrate protection circuit and the switch power tube; the drain of the NMOS tube N10 is connected to the source of the NMOS tube N9; the substrate of the NMOS tube N9 is connected to the power supply VSS, the drain of the NMOS tube N9 is connected to the drain of the PMOS tube P9, the gate of the PMOS tube P12 and the gate of the NMOS tube N12; the drain of the PMOS tube P12 is connected to the drain of the NMOS tube N12, the gate of the PMOS tube P14 and the gate of the NMOS tube N14, and the drain of the PMOS tube P14 and the drain of the NMOS tube N14 are connected to the substrate protection circuit and the switch power tube.

3. The control protection circuit for an analog multiplexer according to claim 1, characterized in that: The substrate protection circuit includes four PMOS tubes P2-P5, four NMOS tubes N2-N5 and two resistors R2-R3; the gate of the PMOS tube P2, the gate of the PMOS tube P4, the gate of the NMOS tube N3 and the gate of the NMOS tube N5 are all connected to the drain of the PMOS tube P14 and the drain of the NMOS tube N14 in the drive control circuit; the gate of the PMOS tube P3, the gate of the PMOS tube P5, the gate of the NMOS tube N2 and the gate of the NMOS tube N4 are all connected to the drain of the PMOS tube P15 and the drain of the NMOS tube N15 in the drive control circuit; the drain of the PMOS tube P2, the source of the NMOS tube N2, the source of the PMOS tube P4 and the drain of the NMOS tube N4 are all connected to the input signal VIN; the source of the PMOS tube P2 is connected to the PM The substrate of the OS transistor P2, the drain of the NMOS transistor N2, one end of the resistor R2 and the switch power transistor; the other end of the resistor R2 is connected to the source of the NMOS transistor N3 and the drain of the PMOS transistor P3; the drain of the NMOS transistor N3, the source of the PMOS transistor P3, the substrate of the PMOS transistor P3, the substrate of the PMOS transistor P4 and the substrate of the PMOS transistor P5 are all connected to the power supply VDD; the drain of the PMOS transistor P4 is connected to the substrate of the NMOS transistor N4, the source of the NMOS transistor N4, one end of the resistor R3 and the switch power transistor; the other end of the resistor R3 is connected to the drain of the NMOS transistor N5 and the source of the PMOS transistor P5; the substrate of the NMOS transistor N2, the substrate of the NMOS transistor N3, the substrate of the NMOS transistor N5, the source of the NMOS transistor N5 and the drain of the PMOS transistor P5 are all connected to the power supply VSS.

4. The control protection circuit for an analog multiplexer according to claim 1, characterized in that: The switch power tube includes an NMOS tube N1 and a PMOS tube P1; the source of the NMOS tube N1 and the source of the PMOS tube P1 are both connected to the input signal VIN; the drain of the NMOS tube N1 and the drain of the PMOS tube P1 are connected as the output of the switch power tube; the gate of the NMOS tube N1 is connected to the drain of the PMOS tube P15 and the drain of the NMOS tube N15 in the drive control circuit, and the gate of the PMOS tube P1 is connected to the drain of the PMOS tube P14 and the drain of the NMOS tube N14 in the drive control circuit; the substrate of the NMOS tube N1 is connected to the drain of the PMOS tube P4 in the substrate protection circuit, and the substrate of the PMOS tube P1 is connected to the drain of the NMOS tube N2 in the substrate protection circuit.

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