Ringing elimination circuit of driving chip, ringing elimination method and electronic equipment

Abstract

The embodiment of the invention provides a ringing elimination circuit and a ringing elimination method of a driving chip, and the ringing elimination circuit comprises a first logic control circuit and a second logic control circuit which are connected to a first-stage driver and a second-stage driver; the first logic control circuit comprises a first time delay module, a first phase inverter and an NAND gate; the second logic control circuit comprises a second delay module, a second phase inverter and a NOR gate; the first time delay module and the second time delay module are configured to prolong the rising time and the falling time of the output signal according to the time delay parameter; the NAND gate is configured to skip the first delay module when the driving tube of the driving chip is closed, and the NOR gate is configured to skip the second delay module when the driving tube of the driving chip is closed.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of electronic circuits, and in particular, to a ringing elimination circuit of a driver chip, a ringing elimination method, and an electronic device. Background Art

[0002] High-speed circuits refer to digital logic circuits with operating frequencies reaching or exceeding 50MHz. Rapid changes in signals in high-speed circuits can cause various problems in signal transmission. For example, when the PMOS and NMOS of the push-pull structure are switched at the same time, the resistance and inductance of the common ground line cause a ground bounce effect, which may lead to false triggering, signal distortion or jitter; since parasitic inductance, capacitance and parasitic impedance will cause ringing when the switching device is switched, this ringing will cause the output signal to exceed the expected range, thereby affecting the reliability of the circuit and the quality of signal transmission. At present, the methods to reduce ringing include increasing transmission delay and optimizing PCB board wiring. These methods cannot suppress the ringing phenomenon from the source while ensuring the high-speed signal requirements. Summary of the invention

[0003] In order to solve the ringing problem, the embodiments described in this article provide a ringing elimination circuit, a ringing elimination method and an electronic device for a driver chip, which suppress the ringing phenomenon by reducing the output impedance change speed.

[0004] According to a first aspect of the present disclosure, a ringing elimination circuit of a driver chip is provided. The driver chip includes a first-stage driver and a second-stage driver, and the first-stage driver and the second-stage driver jointly provide an output voltage. The ringing elimination circuit includes: a first logic control circuit and a second logic control circuit, both of which are connected to the first-stage driver and the second-stage driver; the first logic control circuit includes a first delay module, a first inverter and a NAND gate, the second logic control circuit includes a second delay module, a second inverter and a NOR gate, the first delay module and the second delay module are configured to extend the rise time and the fall time of the output signal according to the delay parameter, the NAND gate is configured to skip the first delay module when the driver tube of the driver chip is turned off, and the NOR gate is configured to skip the second delay module when the driver tube of the driver chip is turned off.

[0005] In some embodiments of the present disclosure, the signal input terminal is connected to the first input terminal of the NAND gate via the first delay module, the second input terminal of the NAND gate and the input terminal of the first inverter are directly connected to the signal input terminal, the first input terminal of the NOR gate and the input terminal of the second inverter are directly connected to the signal input terminal, and the signal input terminal is connected to the second input terminal of the NOR gate via the second delay module.

[0006] In some embodiments of the present disclosure, the first-stage driver is a push-pull structure consisting of a first PMOS tube and a first NMOS tube, the source of the first PMOS tube is connected to a voltage source, the drain of the first PMOS tube is connected to the drain of the first NMOS tube and is led to a voltage output end, the gate of the first PMOS tube is connected to the output end of the first inverter, the gate of the first NMOS tube is connected to the output end of the second inverter, and the source of the first NMOS tube is grounded.

[0007] In some embodiments of the present disclosure, the second-stage driver is a push-pull structure composed of a second PMOS tube and a second NMOS tube, the source of the second PMOS tube is connected to a voltage source, the drain of the second PMOS tube is connected to the drain of the second NMOS tube and is led to the voltage output end, the gate of the second PMOS tube is connected to the output end of the NAND gate, the gate of the second NMOS tube is connected to the output end of the NOR gate, and the source of the second NMOS tube is grounded.

[0008] In some embodiments of the present disclosure, the first delay module includes an RC circuit and a MOS switch circuit, the MOS switch circuit includes a third PMOS tube, a fourth PMOS tube, a third NMOS tube, and a fourth NMOS tube, the source of the third PMOS tube and the fourth PMOS tube are connected to a voltage source, the drain of the third PMOS tube is connected to the drain of the third NMOS tube, the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube, the source of the third NMOS tube and the fourth NMOS tube is grounded, one end of the RC circuit is connected to the drain common end of the third PMOS tube and the third NMOS tube, and the other end is connected to the gate common end of the fourth PMOS tube and the fourth NMOS tube, the gates of the third PMOS tube and the third NMOS tube are connected to the signal input end, and the drain common end of the fourth PMOS tube and the fourth NMOS tube is connected to the first input end of the NAND gate.

[0009] In some embodiments of the present disclosure, the second delay module includes an RC circuit and a MOS switching circuit, the MOS switching circuit includes a fifth PMOS tube, a sixth PMOS tube, a fifth NMOS tube, and a sixth NMOS tube, the source of the fifth PMOS tube and the sixth PMOS tube are connected to a voltage source, the drain of the fifth PMOS tube is connected to the drain of the fifth NMOS tube, the drain of the sixth PMOS tube is connected to the drain of the sixth NMOS tube, the source of the fifth NMOS tube and the sixth NMOS tube is grounded, one end of the RC circuit is connected to the common drain end of the fifth PMOS tube and the fifth NMOS tube, and the other end is connected to the common gate end of the sixth PMOS tube and the sixth NMOS tube, the gates of the fifth PMOS tube and the fifth NMOS tube are connected to the signal input end, and the drain common end of the sixth PMOS tube and the sixth NMOS tube is connected to the second input end of the NOR gate.

[0010] In some embodiments of the present disclosure, the resistance value and the capacitance value of the RC circuit are determined according to the calculated transmission delay time.

[0011] In some embodiments of the present disclosure, a high-level control signal is input to the signal input terminal, the first delay module is used to extend the rising time of the output voltage signal, and the second delay module is used to extend the falling time of the output voltage signal.

[0012] According to a second aspect of the present disclosure, a method for eliminating ringing of a driver chip is provided, wherein the driver chip includes a first-stage driver and a second-stage driver, and the first-stage driver and the second-stage driver jointly provide an output voltage, and the method includes:

[0013] A first logic control circuit and a second logic control circuit are provided to connect a first-level driver and a second-level driver, the first logic control circuit includes a first delay module, a first inverter and a NAND gate, and the second logic control circuit includes a second delay module, a second inverter and a NOR gate; the transmission delay time of the wiring is calculated by measuring the electrical length and characteristic impedance of the circuit wiring, and the transmission delay time of the wiring is used as the delay parameter of the first delay module and the second delay module, and the transmission delay time of the wiring is calculated by measuring the electrical length and characteristic impedance of the circuit wiring; when the MOS tube of the driver chip is turned on, the first delay module is used to extend the rise time of the output voltage signal, and the second delay module is used to extend the fall time of the output voltage signal; when the MOS tube of the driver chip is turned off, the first delay module is skipped through the NAND gate, and the second delay module is skipped through the NOR gate.

[0014] According to a third aspect of the present disclosure, an electronic device is provided, comprising a driver chip and a ringing elimination circuit of the driver chip according to the first aspect of the present disclosure.

[0015] According to the ringing elimination circuit and ringing elimination method of the driver chip of the embodiment of the present disclosure, by adding a delay module in the hierarchical drive of the push-pull structure, it is possible to effectively control the rise time and fall time of the output signal and reduce the ringing caused by rapid changes. The introduction of the delay module not only helps to smooth the changes in the output signal, but also makes the output impedance change speed more controllable through hierarchical drive and reasonable delay design, thereby improving the stability of the system. In the closing direction, skipping the delay module through the logic gate will not affect the closing speed and response time of the circuit, thereby ensuring that the speed and response time of the circuit when it is closed remain within the expected range. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0017] Figure 11 is a schematic diagram of a circuit principle of a ringing elimination circuit 100 of a driver chip according to an embodiment of the present disclosure;

[0018] Figure 2 Schematic diagram of the circuit structure of a ringing elimination circuit of a driver chip according to an embodiment of the present disclosure;

[0019] Figure 3 is a schematic diagram of the internal structure of the first delay module according to an embodiment of the present disclosure;

[0020] Figure 4 is a schematic diagram of the internal structure of the second delay module according to an embodiment of the present disclosure;

[0021] Figure 5 A schematic diagram of the output voltage rising edge and the PMOS tube gate pull-down potential change according to an embodiment of the present disclosure;

[0022] Figure 6 Schematic diagram of the falling edge of the output voltage and the change of the NMOS tube gate pull-up potential according to an embodiment of the present disclosure.

[0023] It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0026] The embodiments of the present disclosure provide a ringing elimination circuit and a ringing elimination method for a driver chip, which suppress the ringing phenomenon by controlling the change speed of the output impedance through hierarchical driving and adding a delay module.

[0027] Figure 1FIG. 1 is a schematic diagram of a circuit principle of a ringing elimination circuit 100 of a driver chip according to an embodiment of the present disclosure. Figure 1 As shown, the driver chip includes a first-stage driver and a second-stage driver, and the first-stage driver and the second-stage driver jointly provide an output voltage. The output stage can respond to input signal changes more smoothly through the hierarchical driver.

[0028] The ringing elimination circuit includes a first logic control circuit and a second logic control circuit, both of which are connected to the first stage driver and the second stage driver. The first logic control circuit includes a first delay module, a first inverter and a NAND gate, and the second logic control circuit includes a second delay module, a second inverter and a NOR gate. The first delay module and the second delay module are configured to extend the output signal rise time and fall time according to the delay parameter, wherein the delay parameter can be determined according to the circuit wiring transmission delay time.

[0029] The purpose of the first delay module and the second delay module is to adjust the rise and fall time of the output voltage signal. Especially in the push-pull drive structure, the speed of signal change needs to be finely controlled to avoid ringing caused by too fast changes. Since there is no high-frequency signal switching during the shutdown of the driver tube, the signal decline is usually smoother and does not require a delay module to control. Therefore, the NAND gate is configured to skip the first delay module when the driver tube of the driver chip is turned off, and the NOR gate is configured to skip the second delay module when the driver tube of the driver chip is turned off. This design effectively reduces unnecessary delays while ensuring the stability of the signal during the rise process and avoiding ringing.

[0030] Figure 2 FIG. 1 is a schematic diagram of a circuit structure of a ringing elimination circuit of a driver chip according to an embodiment of the present disclosure. Figure 2 As shown, the signal input terminal is connected to the first input terminal of the NAND gate via the first delay module, the second input terminal of the NAND gate and the input terminal of the first inverter N1 are directly connected to the signal input terminal, the first input terminal of the NOR gate and the input terminal of the second inverter N2 are directly connected to the signal input terminal, and the signal input terminal is connected to the second input terminal of the NOR gate NOR via the second delay module.

[0031] The first-stage driver is a push-pull structure composed of a first PMOS tube Mp1 and a first NMOS tube Mn1. The source of the first PMOS tube Mp1 is connected to a voltage source, the drain of the first PMOS tube Mp1 is connected to the drain of the first NMOS tube Mn1 and is led to the voltage output terminal Vout, the gate of the first PMOS tube Mp1 is connected to the output terminal of the first inverter N1, the gate of the first NMOS tube Mn1 is connected to the output terminal of the second inverter N2, and the source of the first NMOS tube Mn1 is grounded.

[0032] The second-stage driver is a push-pull structure composed of a second PMOS tube Mp2 and a second NMOS tube Mn2. The source of the second PMOS tube Mp2 is connected to a voltage source, the drain of the second PMOS tube Mp2 is connected to the drain of the second NMOS tube Mn2 and is led to the voltage output terminal Vout, the gate of the second PMOS tube Mp2 is connected to the output terminal of the NAND gate, the gate of the second NMOS tube Mn2 is connected to the output terminal of the NOR gate, and the source of the second NMOS tube Mn2 is grounded.

[0033] The signal input terminal inputs a high level control signal, the first delay module is used to extend the rising time of the output voltage signal, and the second delay module is used to extend the falling time of the output voltage signal.

[0034] Figure 3 The first delay module includes an RC circuit (R1, C1) and a MOS switch circuit. Figure 3 As shown, the MOS switch circuit includes a third PMOS tube Mp3, a fourth PMOS tube Mp4, a third NMOS tube Mn3, and a fourth NMOS tube Mn4. The sources of the third PMOS tube Mp3 and the fourth PMOS tube Mp4 are connected to the voltage source VCC, the drain of the third PMOS tube Mp3 is connected to the drain of the third NMOS tube Mn3, the drain of the fourth PMOS tube Mp4 is connected to the drain of the fourth NMOS tube Mn4, the sources of the third NMOS tube Mn3 and the fourth NMOS tube Mn4 are grounded, one end of the RC circuit is connected to the common end of the drains of the third PMOS tube Mp3 and the third NMOS tube Mn3, and the other end is connected to the common end of the gates of the fourth PMOS tube Mp4 and the fourth NMOS tube Mn4, the gates of the third PMOS tube Mp3 and the third NMOS tube Mn3 are connected to the signal input end, and the common end of the drains of the fourth PMOS tube Mp4 and the fourth NMOS tube Mn4 is connected to the first input end of the NAND gate NAND.

[0035] Figure 4 Schematic diagram of the internal structure of the second delay module of the embodiment of the present disclosure. Similarly, the second delay module includes an RC circuit (R2, C2) and a MOS switch circuit. Figure 4As shown, the MOS switch circuit includes a fifth PMOS tube Mp5, a sixth PMOS tube Mp6, a fifth NMOS tube Mn5, and a sixth NMOS tube Mn6. The sources of the fifth PMOS tube Mp5 and the sixth PMOS tube Mp6 are connected to the voltage source VCC, the drain of the fifth PMOS tube Mp5 is connected to the drain of the fifth NMOS tube Mn5, the drain of the sixth PMOS tube Mp6 is connected to the drain of the sixth NMOS tube Mn6, the sources of the fifth NMOS tube Mn5 and the sixth NMOS tube Mn6 are grounded, one end of the RC circuit is connected to the common end of the drains of the fifth PMOS tube Mp5 and the fifth NMOS tube Mn5, and the other end is connected to the common end of the gates of the sixth PMOS tube Mp6 and the sixth NMOS tube Mn6, the gates of the fifth PMOS tube Mp5 and the fifth NMOS tube Mn5 are connected to the signal input end, and the common end of the drains of the sixth PMOS tube Mp6 and the sixth NMOS tube Mn6 is connected to the second input end of the NOR gate NOR.

[0036] Among them, the time constant (τ) of the RC circuit is the product of the resistance (R) and the capacitance (C), and the resistance and capacitance values ​​of the RC circuit are determined according to the calculated transmission delay time. The parameters of the RC circuit can be adjusted according to the actual use environment. By simulating and analyzing the transmission delay time caused by the parasitic inductance of the PCB board, chip packaging, etc., the RC parameters of the delay module are greater than or equal to the signal transmission delay time.

[0037] According to an embodiment of the present disclosure, a method for eliminating ringing of a driver chip is also provided. The driver chip includes a first-stage driver and a second-stage driver. The first-stage driver and the second-stage driver jointly provide an output voltage Vout. Through hierarchical driving, the signal change speed is suppressed, especially the rise time and the fall time. By smoothing the signal change step by step, the output signal will not fluctuate violently, thereby reducing problems such as signal reflection and ringing.

[0038] In this method, a first logic control circuit and a second logic control circuit are provided, both connected to the first-stage driver and the second-stage driver, the first logic control circuit includes a first delay module, a first inverter and a NAND gate, and the second logic control circuit includes a second delay module, a second inverter and a NOR gate.

[0039] The transmission delay time of the wiring is calculated by measuring the electrical length and characteristic impedance of the circuit wiring, and the transmission delay time is used as the delay parameter of the first delay module and the second delay module.

[0040] The wiring delay of high-frequency circuits is usually determined by the following factors: wiring length, capacitance and impedance characteristics of the trace, and different semiconductor process and material characteristics. The transmission delay time of the wiring in the circuit can be calculated based on these factors. For example, the transmission delay time of the wiring is Where L is the length of the signal line, v propis the speed at which the signal propagates in the signal line, Where c is the speed of light, ∈ r is the dielectric constant. In a push-pull structure, the rise and fall time of the drive current is determined by the response speed of the driver stage. In order to effectively control the rise and fall time of the signal and avoid ringing or overshoot caused by too fast signal changes, a delay module needs to be added. The delay module is designed to allow the signal to be transmitted to the output stage after a delay, thereby slowing down the change speed of the signal and avoiding the generation of high-frequency noise or ringing. Once the wiring delay time is calculated, the delay module can be designed so that its time delay matches the wiring transmission delay. The delay module is composed of resistors and capacitors, and can also be implemented with a dedicated digital delay circuit.

[0041] When the MOS tube of the driver chip is turned on, the first delay module is used to extend the rise time of the output voltage signal, and the second delay module is used to extend the fall time of the output voltage signal. For example, when the signal is transmitted from the driver stage to the output stage, the delay module controls the change speed of the signal by delaying the transmission of the signal. For example, when the signal is transmitted from the driver stage to the output stage, the delay module can suppress the steepness of the rising or falling edge. By accurately designing the delay amount of the delay module, the ringing can be significantly suppressed without affecting the circuit function, ensuring a smoother signal and reducing unnecessary electromagnetic interference.

[0042] When the MOS tube of the driver chip is turned off, the first delay module is skipped through the NAND gate, and the second delay module is skipped through the NOR gate, which can avoid unnecessary delay in the MOS tube closing process and make the shutdown process faster.

[0043] Figure 5 Schematic diagram of the output voltage rising edge and the PMOS tube gate pull-down potential change according to the embodiment of the present disclosure. Figure 5 As shown, the pull-down potentials of the first PMOS transistor Mp1 and the second PMOS transistor Mp2 extend the output voltage rise time.

[0044] Figure 6 Schematic diagram of the output voltage falling edge and the NMOS gate pull-up potential change according to the embodiment of the present disclosure. Figure 6 As shown, the pull-up potentials of the first NMOS transistor Mn1 and the second NMOS transistor Mn2 prolong the output voltage falling time.

[0045] The embodiment of the present disclosure further provides a driver chip, which includes a ringing elimination circuit of the driver chip according to the embodiment of the present disclosure.

[0046] The embodiment of the present disclosure also provides an electronic device. The electronic device includes a driver chip and a ringing elimination circuit according to the embodiment of the present disclosure. The electronic device is, for example, a computer system, a communication device, a digital signal processor, a video and image processor, etc.

[0047] In summary, according to the ringing elimination circuit and ringing elimination method of the driver chip of the embodiment of the present disclosure, by adding a delay module in the hierarchical drive of the push-pull structure, it is possible to effectively control the rise time and fall time of the output signal and reduce the ringing caused by rapid changes. The introduction of the delay module not only helps to smooth the changes in the output signal, but also makes the output impedance change speed more controllable through hierarchical drive and reasonable delay design, thereby improving the stability of the system. In the closing direction, skipping the delay module through the logic gate will not affect the closing speed and response time of the circuit, thereby ensuring that the speed and response time of the circuit when it is closed remain within the expected range.

[0048] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0049] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0050] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A ringing elimination circuit for a driver chip, characterized in that: The driver chip provides an output voltage through a first-stage driver and a second-stage driver. The ringing elimination circuit includes: a first logic control circuit and a second logic control circuit, both connected to the first-stage driver and the second-stage driver; the first logic control circuit includes a first delay module, a first inverter and a NAND gate; the second logic control circuit includes a second delay module, a second inverter and a NOR gate; The first delay module and the second delay module are configured to: extend the rise time and fall time of the output signal according to the delay parameters; the NAND gate is configured to skip the first delay module when the driver tube of the driver chip is turned off; the NOR gate is configured to skip the second delay module when the driver tube of the driver chip is turned off.

2. The ringing elimination circuit of the driver chip according to claim 1, characterized in that: The signal input end is connected to the first input end of the NAND gate via the first delay module, the second input end of the NAND gate and the input end of the first inverter are directly connected to the signal input end, the first input end of the NOR gate and the input end of the second inverter are directly connected to the signal input end, and the signal input end is connected to the second input end of the NOR gate via the second delay module.

3. The ringing elimination circuit of the driver chip according to claim 1, characterized in that: The first-stage driver is a push-pull structure composed of a first PMOS tube and a first NMOS tube, the source of the first PMOS tube is connected to a voltage source, the drain of the first PMOS tube is connected to the drain of the first NMOS tube and is led to a voltage output end, the gate of the first PMOS tube is connected to the output end of the first inverter, the gate of the first NMOS tube is connected to the output end of the second inverter, and the source of the first NMOS tube is grounded.

4. The ringing elimination circuit of the driver chip according to claim 1, characterized in that: The second-stage driver is a push-pull structure composed of a second PMOS tube and a second NMOS tube, the source of the second PMOS tube is connected to a voltage source, the drain of the second PMOS tube is connected to the drain of the second NMOS tube and is led to a voltage output end, the gate of the second PMOS tube is connected to the output end of the NAND gate, the gate of the second NMOS tube is connected to the output end of the NOR gate, and the source of the second NMOS tube is grounded.

5. The ringing elimination circuit of the driver chip according to claim 1, characterized in that: The first delay module includes an RC circuit and a MOS switch circuit, and the MOS switch circuit includes a third PMOS tube, a fourth PMOS tube, a third NMOS tube, and a fourth NMOS tube; The sources of the third PMOS tube and the fourth PMOS tube are connected to a voltage source, the drain of the third PMOS tube is connected to the drain of the third NMOS tube, the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube, the sources of the third NMOS tube and the fourth NMOS tube are grounded, one end of the RC circuit is connected to the common end of the drains of the third PMOS tube and the third NMOS tube, and the other end is connected to the common end of the gates of the fourth PMOS tube and the fourth NMOS tube, the gates of the third PMOS tube and the third NMOS tube are connected to the signal input end, and the common end of the drains of the fourth PMOS tube and the fourth NMOS tube is connected to the first input end of the NAND gate.

6. The ringing elimination circuit of the driver chip according to claim 1, characterized in that: The second delay module includes an RC circuit and a MOS switch circuit, and the MOS switch circuit includes a fifth PMOS tube, a sixth PMOS tube, a fifth NMOS tube, and a sixth NMOS tube; The sources of the fifth PMOS tube and the sixth PMOS tube are connected to a voltage source, the drain of the fifth PMOS tube is connected to the drain of the fifth NMOS tube, the drain of the sixth PMOS tube is connected to the drain of the sixth NMOS tube, the sources of the fifth NMOS tube and the sixth NMOS tube are grounded, one end of the RC circuit is connected to the common end of the drains of the fifth PMOS tube and the fifth NMOS tube, and the other end is connected to the common end of the gates of the sixth PMOS tube and the sixth NMOS tube, the gates of the fifth PMOS tube and the fifth NMOS tube are connected to the signal input end, and the common end of the drains of the sixth PMOS tube and the sixth NMOS tube is connected to the second input end of the NOR gate.

7. The ringing elimination circuit of the driver chip according to claim 5 or 6, characterized in that: The resistance value and the capacitance value of the RC circuit are determined according to the calculated transmission delay time.

8. The ringing elimination circuit of the driver chip according to claim 1, characterized in that: The signal input terminal inputs a high-level control signal, the first delay module is used to extend the rising time of the output voltage signal, and the second delay module is used to extend the falling time of the output voltage signal.

9. A method for eliminating ringing of a driver chip, wherein the driver chip provides an output voltage through a first-stage driver and a second-stage driver, characterized in that: The method comprises: Providing a first logic control circuit and a second logic control circuit connected to the first-stage driver and the second-stage driver, the first logic control circuit comprising a first delay module, a first inverter and a NAND gate, and the second logic control circuit comprising a second delay module, a second inverter and a NOR gate; Using the transmission delay time of the wiring as the delay parameter of the first delay module and the second delay module, the transmission delay time of the wiring is calculated by measuring the electrical length and characteristic impedance of the circuit wiring; When the MOS tube of the driving chip is turned on, the first delay module is used to extend the rising time of the output voltage signal, and the second delay module is used to extend the falling time of the output voltage signal; When the MOS tube of the driving chip is turned off, the first delay module is skipped through the NAND gate, and the second delay module is skipped through the NOR gate.

10. An electronic device, characterized in that: The invention comprises a driving chip and a ringing elimination circuit of the driving chip according to any one of claims 1 to 9.

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