BUCK self-turn-off circuit, power supply circuit and electronic equipment

Abstract

The embodiment of the invention provides a BUCK self-turn-off circuit, a power supply circuit and electronic equipment, and the circuit comprises an inductive current sampling module which obtains the sampling current in a sampling clock period, and determines the sampling voltage of the inductive current according to the sampling current; the comparison module outputs a first comparison voltage signal according to the relationship between the inductive current sampling voltage and the ramp voltage in the sampling clock period; the logic control module outputs a control signal to the power tube according to the clock control signal, the first comparison voltage signal and the maximum conduction time control signal; the maximum on-time generation module is used for determining whether to generate a maximum on-time control signal or not according to the relationship between the time corresponding to the change of a first comparison voltage signal into a high level in a sampling clock period and the time corresponding to the fact that the sampling voltage is greater than the first reference voltage; and the counting module is used for outputting an enable signal to the BUCK circuit when the maximum on-time control signal is received in the continuous target number of sampling clock periods. And the automatic turn-off of the BUCK circuit is realized.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technology and related technical fields, and in particular, to a BUCK self-shutdown circuit, a power supply circuit, and an electronic device. Background Art

[0002] PMIC (Power Management Integrated Circuit) is a highly integrated power supply circuit, which is mainly used to manage and regulate the power supply of electronic systems. Its main functions include voltage conversion, current control, multiple power rails and power management. PMIC integrates multi-channel DCDC converters, linear regulators LDO, high-side / low-side switches, charging controllers, etc., which can provide multi-channel power supplies to meet the power needs of different subsystems. PMIC has the advantages of high integration, small size, low cost and high efficiency, and is increasingly widely used in terminal equipment in many fields such as automobiles, communications, electronics, radar, etc.

[0003] However, for a multi-channel PMIC, in actual applications, it is possible to encounter situations where not all BUCK channels are used up, and for unused BUCK channels, the BUCK circuit of the channel is usually turned off to save power. In the prior art, there are several solutions for turning off idle BUCK circuits: one is to add external pins, configure the pin voltage or timing to control the turning off of the BUCK circuit corresponding to the idle BUCK channel, which will significantly increase the chip area; the second is to use the MCU to control the enable signal of the idle BUCK to achieve the purpose of turning off the idle BUCK channel, which increases the peripheral configuration devices and costs; the third is to add register configuration, and use the register configuration to turn off the enable signal of the idle BUCK channel after each startup, which will increase the complexity and area of ​​chip design. Summary of the invention

[0004] The embodiments described herein provide a BUCK self-shutdown circuit, a power supply circuit, and an electronic device to solve the problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, there is provided a BUCK self-shutdown circuit, comprising: an inductor current sampling module, a comparison module, a logic control module, a maximum on-time generation module and a counting module;

[0006] The inductor current sampling module is configured to obtain a sampled current within a sampling clock period, and determine an inductor current sampling voltage according to the sampled current;

[0007] The comparison module is configured to output a first comparison voltage signal to the logic control module according to the relationship between the inductor current sampling voltage and the ramp voltage within the sampling clock period;

[0008] The logic control module is configured to output a control signal to the power tube according to the clock control signal, the first comparison voltage signal and the maximum on-time control signal;

[0009] The maximum on-time generating module is configured to determine whether to generate a maximum on-time control signal according to the relationship between the time corresponding to when the first comparison voltage signal becomes high level and the time corresponding to when the sampling voltage is greater than the first reference voltage within the sampling clock period;

[0010] The counting module is configured to output an enable signal to the BUCK circuit when the maximum on-time control signal is received in a target number of consecutive sampling clock cycles.

[0011] In some embodiments of the present disclosure, the comparison module includes a first comparison unit and a second comparison unit;

[0012] The first comparison unit is configured to output a second comparison voltage signal to the second comparison unit according to the feedback voltage and the second reference voltage;

[0013] The second comparison unit is configured to output a first comparison voltage signal to the maximum on-time generation module according to the second comparison voltage signal, the inductor current sampling voltage and the sawtooth wave voltage.

[0014] In some embodiments of the present disclosure, the first comparison unit includes a first comparator, and the second comparison unit includes a second comparator. The positive input terminal of the first comparator receives a feedback voltage, the reverse input terminal of the first comparator receives a second reference voltage, the output terminal of the first comparator outputs a second comparison voltage signal to the reverse input terminal of the second comparator, the positive input terminal of the second comparator receives the inductor current sampling voltage and the sawtooth wave voltage respectively, and the output terminal of the second comparator outputs the first comparison voltage signal.

[0015] In some embodiments of the present disclosure, the logic control module includes a logic control unit and a main control unit;

[0016] The logic control unit is configured to output a logic control signal according to the clock control signal, the feedback voltage and the maximum on-time control signal;

[0017] The main control unit is configured to control the on and off of the power tube according to the first comparison voltage signal and the logic control signal, and to generate a feedback voltage to the logic control unit according to the collected on and off states of the power tube.

[0018] In some embodiments of the present disclosure, the logic control unit includes a first inverter, a second inverter, a third inverter, a first NAND gate and a second NAND gate, the input end of the first inverter receives a clock control signal, the output end of the first inverter is electrically connected to the first input end of the first NAND gate, the second input end of the first NAND gate is electrically connected to the output end of the second NAND gate, the output end of the first NAND gate is electrically connected to the first input end of the second NAND gate and outputs a control signal, the input end of the second inverter receives the feedback voltage, the output end of the second inverter is electrically connected to the second input end of the second NAND gate, the input end of the third inverter receives a maximum on-time control signal, and the output end of the third inverter is electrically connected to the third input end of the second NAND gate.

[0019] In some embodiments of the present disclosure, the maximum on-time generating module includes a fourth inverter, a transistor, a current source, a capacitor and a third comparator, the input end of the fourth inverter receives a logic control signal, the output end of the fourth inverter is electrically connected to the control end of the transistor, the first end of the current source receives a power supply voltage signal, the second end of the current source, the first end of the capacitor and the first end of the transistor are respectively electrically connected to the positive input end of the third comparator, the second end of the capacitor and the second end of the transistor are electrically connected to the ground node, the reverse input end of the third comparator receives a second reference voltage, and the output end of the third comparator outputs a maximum on-time control signal.

[0020] In some embodiments of the present disclosure, the transistor is an NMOS transistor.

[0021] In some embodiments of the present disclosure, the counting module includes a counter, which receives a maximum on-time control signal and a clock control signal, and outputs an enable signal to the BUCK circuit when the number of maximum on-time control signals meets a target number.

[0022] In some embodiments of the present disclosure, the BUCK self-shutdown circuit further includes a control module, and the control module is configured to control the on and off of the power tube according to the control signal.

[0023] According to a second aspect of the present disclosure, a power supply circuit is provided, comprising the BUCK self-shutdown circuit described in any one of the first aspects.

[0024] According to a third aspect of the present disclosure, an electronic device is provided, comprising the power supply circuit described in the second aspect.

[0025] In the buck self-shutdown circuit, power supply circuit and electronic device provided by the embodiments of the present disclosure, the inductor current sampling module obtains the sampling current within the sampling clock cycle, and determines the inductor current sampling voltage within the clock cycle according to the sampling current; the comparison module outputs the first comparison voltage signal to the logic control module according to the relationship between the inductor current sampling voltage and the ramp voltage within the sampling clock cycle; the logic control module is configured to output the control signal to the power tube according to the clock control signal, the first comparison voltage signal and the maximum on-time control signal; the maximum on-time generation module determines whether to generate the maximum on-time control signal according to the relationship between the time corresponding to the first comparison voltage signal becoming a high level within the sampling clock cycle and the time corresponding to the sampling voltage being greater than the first reference voltage; and the counting module outputs an enable signal to the buck circuit when the maximum on-time control signal is received in a continuous target number of sampling clock cycles. The maximum on-time control signal generated by the maximum on-time generating module is collected in each BUCK circuit of the power supply circuit, and the number of maximum on-time control signals received in multiple consecutive clock cycles is counted by the counting module. When the counting module receives the maximum on-time control signal in the sampling clock cycles of the target number of consecutive times, the counting module outputs an enable signal to the BUCK circuit to shut down the BUCK circuit. That is, there is no need to configure additional pins on the power supply circuit. The non-working BUCK circuit in the power supply circuit is shut down through timing control, and there is no need to add additional modules such as MCU and registers to realize the shutdown of the non-working BUCK circuit. The non-working BUCK circuit can be shut down only by collecting the number of maximum on-time control signals appearing in the BUCK circuit, thereby reducing the design complexity and circuit area of ​​the power supply circuit.

[0026] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0028] Figure 1 is a structural schematic diagram of a structural schematic diagram of a power supply circuit provided by an embodiment of the present disclosure;

[0029] Figure 2 It is a structural schematic diagram of a BUCK self-shutdown circuit provided by an embodiment of the present disclosure;

[0030] Figure 3 is a structural schematic diagram of another BUCK self-shutdown circuit provided by an embodiment of the present disclosure;

[0031] Figure 4 It is a structural schematic diagram of another BUCK self-shutdown circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0034] In all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a part of a component) from another component (or another part of a component).

[0035] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0036] Based on the problems existing in the prior art, the present disclosure provides a BUCK self-shutdown circuit. Figure 1 is a schematic diagram of a power supply circuit provided by an embodiment of the present disclosure, Figure 2is a schematic diagram of a BUCK self-shutdown circuit provided by an embodiment of the present disclosure, combined with Figure 1 and Figure 2 The power supply circuit includes a plurality of BUCK circuits, and any BUCK circuit includes an inductor current sampling module 10, a comparison module 20, a logic control module 30, a maximum on-time generation module 40 and a counting module 50, wherein the inductor current sampling module 10 in the BUCK circuit is configured to obtain a sampling current within a sampling clock cycle, and determine an inductor current sampling voltage according to the sampling current; the comparison module 20 is configured to output a first comparison voltage signal to the logic control module 30 according to a relationship between the inductor current sampling voltage and the ramp voltage within the sampling clock cycle; the logic control module 30 is configured to output a control signal to the power tube according to the clock control signal, the first comparison voltage signal and the maximum on-time control signal; the maximum on-time generation module 40 is configured to determine whether to generate a maximum on-time control signal according to a relationship between a time corresponding to a first comparison voltage signal becoming a high level within a sampling clock cycle and a time corresponding to a sampling voltage being greater than a first reference voltage; the counting module 50 is configured to output an enable signal to the BUCK circuit when the maximum on-time control signal is received in a continuous target number of sampling clock cycles.

[0037] It should be noted that Figure 1 The exemplary embodiment shows that the power supply circuit includes three BUCK circuits, and the output channels of the BUCK circuits are connected to the load via output inductors. In other possible implementation modes, the number of BUCK circuits in the power supply circuit is not specifically limited in the embodiments of the present disclosure.

[0038] In a specific implementation, when the power supply circuit includes multiple BUCK circuits, there will be one or more BUCK circuits in a non-working state. In order to reduce the overall power consumption of the power supply circuit, it is necessary to shut down the BUCK circuits in the power supply circuit that are in a non-working state. However, the methods for shutting down the non-working BUCK circuits in the power supply circuit in the prior art all require the addition of additional modules to realize the shutdown of the non-working BUCK circuits, making the chip design complicated. Based on the problems existing in the prior art, the embodiments of the present disclosure provide a BUCK self-shutdown circuit in the power supply circuit, which can realize the shutdown of the non-working BUCK circuits in the power supply circuit without adding additional pins or functional modules in the power supply circuit.

[0039] The following embodiments will be specifically described by taking the implementation logic of a BUCK self-shutdown circuit in a power supply circuit as an example.

[0040] In a specific implementation, the inductor current sampling module 10 collects the sampled current of the switch node in each sampling clock cycle, and generates the inductor current sampling voltage according to the sampled current. Specifically, when the clock control signal of the BUCK circuit changes from a low level to a high level, the lower power tube is controlled to be turned off and the upper power tube is controlled to be turned on. At this time, the sampled current collected by the inductor current sampling module gradually increases.

[0041] Specifically, the comparison module 20 compares the relationship between the inductor current sampling voltage and the ramp voltage, and outputs a first comparison voltage signal to the logic control module 30 . Exemplarily, within a sampling clock cycle, when the clock control signal changes from a low level to a high level, the logic control module 30 outputs a first control signal to control the lower power tube to be turned off and the upper power tube to be turned on. When the BUCK circuit is in a normal working state (that is, the BUCK circuit in the power supply circuit is connected to the output inductor through the BUCK channel), as the upper power tube is turned on, the inductor current sampling voltage gradually increases. When the inductor current sampling voltage gradually increases to be greater than the ramp voltage, the first comparison voltage signal output by the comparison module 20 changes from a low level to a high level. At this time, the logic control module 30 outputs a second control signal according to the first comparison voltage signal to control the upper power tube to be turned off and the lower power tube to be turned on. When the BUCK circuit is in an abnormal working state (that is, the BUCK circuit in the power supply circuit is not connected to the output inductor through the BUCK channel), at this time, the inductor current sampling voltage is 0, the inductor current sampling voltage is always less than the ramp voltage, and the first comparison voltage signal output by the comparison module 20 is always kept at a low level. At this time, the maximum on-time generation module 40 determines whether to generate a maximum on-time control signal according to the first comparison voltage signal received by the logic control module 30.

[0042] Specifically, the maximum on-time generation module 40 determines whether to generate the maximum on-time control signal according to the relationship between the time corresponding to the first comparison voltage signal becoming high level within the sampling clock cycle and the time corresponding to the sampling voltage being greater than the first reference voltage. Exemplarily, at the rising edge of a sampling clock cycle, the logic control module 30 outputs the first control signal to control the lower power to be turned off, the upper power tube to be turned on, the sampling current collected by the inductor current sampling module gradually increases, and the inductor current sampling voltage gradually increases. As the inductor current sampling voltage gradually increases to be greater than the ramp voltage, the first comparison voltage signal output by the comparison module changes from a low level to a high level. At this time, the logic control module 30 outputs the second control signal to control the upper power tube to be turned off and the lower power tube to be turned on, until the rising edge of the next sampling clock cycle arrives, and the logic control module 30 outputs the first control signal again to control the lower power tube to be turned off and the upper power tube to be turned on, and this cycle is repeated. When the BUCK circuit is in a normal working state (that is, the BUCK circuit in the power supply circuit is connected to the output inductor through the BUCK channel), the time corresponding to the first comparison voltage signal output by the comparison module 20 changing from a low level to a high level will be located before the time corresponding to the sampling voltage being greater than the first reference voltage. However, when a certain BUCK circuit in the power supply circuit is not connected to the output inductor, the inductor current sampling module 10 does not collect the sampling current, the inductor current sampling voltage is 0, and the inductor current sampling voltage will always be less than the ramp voltage. The first comparison voltage signal output by the comparison module 20 will always be a low level, and there will be a time corresponding to the sampling voltage being greater than the first reference voltage that is located before the time corresponding to the first comparison voltage signal changing to a high level. At this time, the maximum on-time generation module 40 generates a maximum on-time control signal and outputs the maximum on-time control signal to the counting module 50 and the logic control module 30. The counting module 50 calculates and generates the number of continuous maximum on-time control signals, thereby determining the state of the BUCK circuit, and outputs a second control signal through the logic control module 30 to control the upper power tube to be turned off and the lower power tube to be turned on.

[0043] Specifically, when the counting module 50 receives the maximum on-time control signal in a continuous target number of sampling clock cycles, it outputs an enable signal to the BUCK circuit. When the counting module receives the maximum on-time control signal in a continuous target number of sampling clock cycles, the counting module will output an enable signal to the BUCK circuit to which the counting module belongs, so that the BUCK circuit to which the counting module belongs is turned off after receiving the enable signal, that is, the BUCK circuit to which the counting module belongs does not work, thereby reducing the overall power consumption of the power supply circuit.

[0044] In the buck self-shutdown circuit provided by the embodiment of the present disclosure, the inductor current sampling module obtains the sampling current within the sampling clock cycle, and determines the inductor current sampling voltage within the clock cycle according to the sampling current; the comparison module outputs a first comparison voltage signal to the logic control module according to the relationship between the inductor current sampling voltage and the ramp voltage within the sampling clock cycle; the logic control module is configured to output a control signal to the power tube according to the clock control signal, the first comparison voltage signal and the maximum on-time control signal; the maximum on-time generation module determines whether to generate the maximum on-time control signal according to the relationship between the time corresponding to the first comparison voltage signal becoming a high level within the sampling clock cycle and the time corresponding to the sampling voltage being greater than the first reference voltage; and the counting module outputs an enable signal to the buck circuit when the maximum on-time control signal is received in a continuous target number of sampling clock cycles. The maximum on-time control signal generated by the maximum on-time generating module is collected in each BUCK circuit of the power supply circuit, and the number of maximum on-time control signals received in multiple consecutive clock cycles is counted by the counting module. When the counting module receives the maximum on-time control signal in the sampling clock cycles of the target number of consecutive times, the counting module outputs an enable signal to the BUCK circuit to shut down the BUCK circuit. That is, there is no need to configure additional pins on the power supply circuit. The non-working BUCK circuit in the power supply circuit is shut down through timing control, and there is no need to add additional modules such as MCU and registers to realize the shutdown of the non-working BUCK circuit. The non-working BUCK circuit can be shut down only by collecting the number of maximum on-time control signals appearing in the BUCK circuit, thereby reducing the design complexity and circuit area of ​​the power supply circuit.

[0045] In a specific embodiment, Figure 3 is a specific structural diagram of a self-shutdown circuit provided by an embodiment of the present disclosure, such as Figure 3 As shown, the comparison module 20 includes a first comparison unit and a second comparison unit; the first comparison unit is configured to output a second comparison voltage signal to the second comparison unit according to the feedback voltage and the second reference voltage; the second comparison unit is configured to output the first comparison voltage signal to the maximum on-time generation module according to the second comparison voltage signal, the inductor current sampling voltage and the ramp voltage.

[0046] Among them, the first comparison unit includes a first comparator COM1, and the second comparison unit includes a second comparator. The positive input terminal of the first comparator COM1 receives the feedback voltage VFB, the reverse input terminal of the first comparator COM1 receives the second reference voltage VREF1, the output terminal of the first comparator COM1 outputs the second comparison voltage signal VC2 to the reverse input terminal of the second comparator COM1, the positive input terminal of the second comparator COM2 receives the inductor current sampling voltage VCS and the sawtooth wave voltage VS respectively, and the output terminal of the second comparator COM2 outputs the first comparison voltage signal OFF_HS.

[0047] Combination Figure 3 , the first comparison unit compares the feedback voltage VFB and the first reference voltage VREF1. Specifically, the positive input terminal of the first comparator COM1 receives the feedback voltage VFB, and the negative input terminal of the first comparator COM1 receives the first reference voltage VREF1. When the feedback voltage VFB is greater than the first reference voltage VREF1, the second comparison voltage signal VC2 output by the first comparison unit (that is, the first comparator) is high level. When the feedback voltage VFB is less than the first reference voltage VREF1, the second comparison voltage signal VC2 output by the first comparison unit (that is, the first comparator) is low level. The positive input terminal of the second comparator COM2 receives the inductor current sampling voltage VCS and the sawtooth wave voltage VS, and the negative input terminal of the second comparator COM2 receives the second comparison voltage VCS. The second comparison unit (i.e., the second comparator) first generates a ramp voltage VRAMP (VRAMP=VC2-VS) according to the second comparison voltage signal VC2 and the sawtooth wave voltage VS, and then the second comparison unit (i.e., the second comparator) compares the relationship between the inductor current sampling voltage VCS and the ramp voltage VRAMP, and outputs a first comparison voltage signal OFF_HS. When the inductor current sampling voltage VCS is less than the ramp voltage VRAMP, the first comparison voltage signal OFF_HS output by the second comparison unit (i.e., the second comparator) is at a low level. When the inductor current sampling voltage VCS is greater than the ramp voltage VRAMP, the first comparison voltage signal OFF_HS output by the second comparison unit (i.e., the second comparator) is at a high level.

[0048] Based on the above embodiments, Figure 3 and Figure 4The logic control module 30 includes a logic control unit 31 and a main control unit 32; the logic control unit 31 is configured to output a logic control signal ON1 according to the clock control signal CLK, the feedback voltage HS_OFF and the maximum on-time control signal Max_on; the main control unit 32 is configured to control the on and off of the power tube according to the first comparison voltage signal OFF_HS and the logic control signal ON1, and generate a feedback voltage HS_OFF to the logic control unit 31 according to the collected on-off state of the power tube.

[0049] Among them, the logic control unit 31 includes a first inverter F1, a second inverter F2, a third inverter F3, a first NAND gate NAND1 and a second NAND gate NAND2, the input end of the first inverter F1 receives the clock control signal CLK, the output end of the first inverter F1 is electrically connected to the first input end of the first NAND gate NAND1, the second input end of the first NAND gate NAND1 is electrically connected to the output end of the second NAND gate NAND2, the output end of the first NAND gate NAND1 is electrically connected to the first input end of the second NAND gate NAND2 and outputs the logic control signal ON1, the input end of the second inverter F2 receives the feedback voltage HS_OFF, the output end of the second inverter F2 is electrically connected to the second input end of the second NAND gate NAND2, the input end of the third inverter F3 receives the maximum on-time control signal Max_on, and the output end of the third inverter F3 is electrically connected to the third input end of the second NAND gate NAND2.

[0050] The maximum on-time generating module includes a fourth inverter F4, a transistor NM, a current source Ibias, a capacitor C and a third comparator COM3, wherein an input end of the fourth inverter F4 receives a logic control signal ON1, an output end of the fourth inverter F4 is electrically connected to a control end of the transistor NM, a first end of the current source Ibias receives a power supply voltage signal, a second end of the current source Ibias, a first end of the capacitor C and a first end of the transistor NM are electrically connected to a positive input end of the third comparator COM3 respectively, a second end of the capacitor C and a second end of the transistor NM are electrically connected to a ground node, a reverse input end of the third comparator COM3 receives a second reference voltage VREF2, and an output end of the third comparator COM3 outputs a maximum on-time control signal Max_on.

[0051] Among them, the transistor NM is an NMOS tube.

[0052] Specific, combined Figure 3 and Figure 4In a sampling clock cycle, the clock control signal changes from a low level to a high level. At this time, the first inverter F1 receives the clock control signal CLK, and the first inverter F1 outputs a low level to the first NAND gate NAND1. The logic control signal ON1 output by the first NAND gate NAND1 is a high level. At this time, the main control unit 32 receives the high level output by the first NAND gate NAND1. The main control unit 32 outputs a first control signal to control the lower power tube S2 to turn off and the upper power tube S1 to turn on according to the received high level output by the first NAND gate NAND1. The fourth inverter F4 receives the high level output by the first NAND gate NAND1, and the fourth inverter F4 outputs a low level to the transistor NM. The transistor NM is turned off. At this time, the current source Ibias charges the capacitor C. When the BUCK circuit is in a normal working state, the time corresponding to the first comparison voltage signal OFF_HS output by the comparison module 20 changing from a low level to a high level will be located before the time corresponding to the sampling voltage being greater than the first reference voltage, that is, before the current source Ibias charges the capacitor C so that the voltage at the first terminal of the capacitor C (that is, the sampling voltage VA) is greater than the second reference voltage VREF2, the upper power tube S1 is turned on, so that the sampling current increases, and then the inductor current sampling voltage VCS increases. When the inductor current sampling voltage VCS increases to be greater than the ramp voltage, the first comparison voltage signal OFF_HS output by the comparison module 20 is a high level. At this time, after receiving the high-level first comparison voltage signal OFF_HS output by the comparison module 20, the main control unit 32 outputs the second control signal to control the upper power tube S1 to turn off, and the main control unit 32 generates a feedback voltage HS_OFF (high level) to the first control signal of the logic control unit 31. The second inverter F2, the second inverter F2 outputs a low level, the second NAND gate NAND2 outputs a high level to the second input end of the first NAND gate NAND1, at this time, the first NAND gate NAND1 outputs a low level (that is, the logic control signal ON1 output by the first NAND gate NAND1 is a low level), at this time, the main control unit receives the low level output by the first NAND gate NAND1, and the main control unit outputs a second control signal to control the lower power tube S2 to turn on according to the received low level output by the first NAND gate NAND1, and the fourth inverter F4 receives the low level output by the first NAND gate NADN1, and the fourth inverter F4 outputs a high level to the transistor NM, and the transistor NM is turned on. At this time, the capacitor C is discharged, therefore, the sampling voltage VA received by the positive input end of the third comparator COM3 is less than the second reference voltage VREF2, and the third comparator COM3 will not output the maximum on-time control signal Max_on to the logic control unit.When the BUCK circuit is in an abnormal working state, the time corresponding to the first comparison voltage signal output by the comparison module 20 changing from a low level to a high level will be located after the time corresponding to the sampling voltage being greater than the first reference voltage. Specifically, since the BUCK circuit is in an abnormal working state (the output inductor is not connected), the sampling current is 0. At this time, the inductor current sampling voltage VCS is 0. The inductor current sampling voltage VCS will always be less than the ramp voltage. The first comparison voltage signal OFF_HS output by the comparison module 20 to the main control unit 32 is a low level. The main control unit generates a feedback voltage HS_OFF (low level) to the second inverter F2 of the logic control unit. Since the feedback voltage HS_OFF output by the main control unit to the logic control unit is always a low level, the first NAND gate NAND1 outputs High level (that is, the logic control signal ON1 output by the first NAND gate NAND1 is also always high level), at this time, the fourth inverter F4 receives the high level output by the first NAND gate NAND1, the fourth inverter F4 outputs a low level to the transistor NM, the transistor NM is turned off, and the current source Ibias charges the capacitor C. Since the inductor current sampling voltage will always be less than the ramp voltage, the second inverter F2 will not receive a high level feedback voltage. Therefore, the first NAND gate will not output a low level, and the fourth inverter will not output a high level, and then the transistor will not be turned on, allowing the capacitor to discharge. Therefore, when the current source charges the capacitor so that the first terminal voltage of the capacitor (that is, the sampling voltage) is greater than the first reference voltage, the third comparator COM3 will output the maximum on-time control signal Max_on to the counting module. In addition, the third comparator COM3 also outputs a maximum on-time control signal to the input end of the third inverter F3 of the logic control unit. After receiving the maximum on-time control signal output by the third comparator COM3, the third inverter F3 outputs a low level to the second NAND gate NAND2, the second NAND gate NAND2 outputs a high level to the first NAND gate NAND1, and the first NAND gate NAND1 outputs a low level (that is, the logic control signal ON1 output by the first NAND gate NAND1 is a low level). At this time, the main control unit receives the low level output by the first NAND gate, and the main control unit outputs a second control signal to control the upper power tube S1 to turn off and the lower power tube S2 to turn on.

[0053] In a specific implementation, the counting module includes a counter, which receives a maximum on-time control signal and a clock control signal, and outputs an enable signal to the BUCK circuit when the number of maximum on-time control signals meets a target number.

[0054] In a specific implementation, when the counter receives the maximum on-time control signal within one clock control signal, the counter records 1; when the counter does not receive the maximum on-time control signal within one clock control signal, the counter records 0; when the counter is 1 for a continuous target number of sampling clock cycles, the counting module outputs an enable signal to the BUCK circuit to control the BUCK circuit to shut down.

[0055] It should be noted that the embodiment of the present disclosure does not specifically limit the target number counted by the counter. As an exemplary example, the target number can be 100 or 200, which is related to the BUCK circuit.

[0056] Based on the above embodiments, Figure 3 As shown, the BUCK self-shutdown circuit further includes a control module 50, and the control module 50 is configured to control the on and off of the power tube according to the control signal.

[0057] Specifically, when the control signal generated by the control unit in the maximum on-time generating module of the above embodiment is at a high level, the control module controls the lower power tube to be turned off and the upper power tube to be turned on. When the control signal generated by the control unit in the maximum on-time generating module of the above embodiment is at a low level, the control module controls the upper power tube to be turned off and the lower power tube to be turned on.

[0058] On the basis of the above embodiments, the embodiments of the present disclosure further provide a power supply circuit, including a plurality of BUCK self-shutdown circuits described in any one of the above embodiments, and having the beneficial effects described in any one of the above embodiments, which are not illustrated one by one in the embodiments of the present disclosure.

[0059] In a specific implementation, when an output channel of any BUCK self-shutdown circuit included in the power supply circuit is poorly soldered, that is, the OUT PIN of any BUCK self-shutdown circuit is disconnected from the output capacitor and the output inductor, the BUCK self-shutdown circuit connected to the output channel will perform self-shutdown.

[0060] On the basis of the above embodiments, the embodiments of the present disclosure further provide an electronic device, including the power supply circuit described in any one of the above embodiments, and having the beneficial effects described in any one of the above embodiments, which are not illustrated one by one in the embodiments of the present disclosure.

[0061] The electronic device provided in the embodiments of the present disclosure can be applied to flexible electronic devices to realize technologies such as augmented reality (AR), virtual reality (VR), extended reality (XR), and mixed reality (MR). For example, the display device can be the projection part of the electronic device, such as a projector, a head-up display (HUD), etc.; for another example, the display device can also be the display part of the electronic device, such as a smart phone, a smart watch, a laptop, a tablet computer, a driving recorder, a navigator, a head-mounted device, and any other device with a display screen.

[0062] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0063] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. In addition, the serial numbers of the embodiments of the present application mentioned above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0064] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0065] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A BUCK self-shutdown circuit, characterized in that: include: Inductor current sampling module, comparison module, logic control module, maximum on-time generation module and counting module; The inductor current sampling module is configured to obtain the inductor current within a sampling clock period, and determine the inductor current sampling voltage according to the inductor current; The comparison module is configured to output a first comparison voltage signal to the logic control module according to the relationship between the inductor current sampling voltage and the ramp voltage within the sampling clock period; The logic control module is configured to output a control signal to the power tube according to the clock control signal, the first comparison voltage signal and the maximum on-time control signal; The maximum on-time generating module is configured to determine whether to generate a maximum on-time control signal according to the relationship between the time corresponding to when the first comparison voltage signal becomes high level and the time corresponding to when the sampling voltage is greater than the first reference voltage within the sampling clock period; The counting module is configured to output an enable signal to the BUCK circuit when the maximum on-time control signal is received in a target number of consecutive sampling clock cycles.

2. The circuit according to claim 1, characterized in that The comparison module includes a first comparison unit and a second comparison unit; The first comparison unit is configured to output a second comparison voltage signal to the second comparison unit according to the feedback voltage and the second reference voltage; The second comparison unit is configured to output a first comparison voltage signal to the maximum on-time generation module according to the second comparison voltage signal, the inductor current sampling voltage and the sawtooth wave voltage.

3. The circuit according to claim 2, characterized in that The first comparison unit includes a first comparator, and the second comparison unit includes a second comparator. The positive input terminal of the first comparator receives a feedback voltage, the negative input terminal of the first comparator receives a second reference voltage, the output terminal of the first comparator outputs a second comparison voltage signal to the negative input terminal of the second comparator, the positive input terminal of the second comparator receives the inductor current sampling voltage and the sawtooth wave voltage respectively, and the output terminal of the second comparator outputs the first comparison voltage signal.

4. The circuit according to claim 1, characterized in that The logic control module includes a logic control unit and a main control unit; The logic control unit is configured to output a logic control signal according to the clock control signal, the feedback voltage and the maximum on-time control signal; The main control unit is configured to control the on and off of the power tube according to the first comparison voltage signal and the logic control signal, and to generate a feedback voltage to the logic control unit according to the collected on and off states of the power tube.

5. The circuit according to claim 4, characterized in that The logic control unit includes a first inverter, a second inverter, a third inverter, a first NAND gate and a second NAND gate, the input end of the first inverter receives a clock control signal, the output end of the first inverter is electrically connected to the first input end of the first NAND gate, the second input end of the first NAND gate is electrically connected to the output end of the second NAND gate, the output end of the first NAND gate is electrically connected to the first input end of the second NAND gate and outputs a control signal, the input end of the second inverter receives the feedback voltage, the output end of the second inverter is electrically connected to the second input end of the second NAND gate, the input end of the third inverter receives a maximum on-time control signal, and the output end of the third inverter is electrically connected to the third input end of the second NAND gate.

6. The circuit according to claim 1, characterized in that The maximum on-time generating module includes a fourth inverter, a transistor, a current source, a capacitor and a third comparator, wherein the input end of the fourth inverter receives a logic control signal, the output end of the fourth inverter is electrically connected to the control end of the transistor, the first end of the current source receives a power supply voltage signal, the second end of the current source, the first end of the capacitor and the first end of the transistor are electrically connected to the positive input end of the third comparator respectively, the second end of the capacitor and the second end of the transistor are electrically connected to the ground node, the reverse input end of the third comparator receives a second reference voltage, and the output end of the third comparator outputs a maximum on-time control signal.

7. The circuit according to claim 6, characterized in that The transistor is an NMOS transistor.

8. The circuit according to claim 1, characterized in that The counting module includes a counter, which receives a maximum on-time control signal and a clock control signal, and outputs an enable signal to the BUCK circuit when the number of the maximum on-time control signals meets a target number.

9. A power supply circuit, characterized in that: The invention comprises a BUCK self-shutdown circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises the power supply circuit as claimed in claim 9.

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