Auxiliary tube parameter loose type high-end ideal diode

Abstract

The invention discloses an auxiliary tube parameter loose type high-end ideal diode, which comprises a PMOS (P-channel Metal Oxide Semiconductor) main tube and a voltage comparator, and is characterized in that the voltage comparator is used for comparing the voltage difference between the drain electrode and the source electrode of the PMOS main tube V1; when the PMOS main tube V1 is positively biased, the PMOS main tube V1 is conducted; when the PMOS main tube V1 is reversely biased, the PMOS main tube V1 is cut off; the circuit further comprises a power supply VCC and a load resistor RL, the drain electrode of the PMOS main tube V1 is connected to the power supply VCC, the source electrode of the PMOS main tube V1 is connected to one end of the load resistor RL, and the other end of the load resistor RL is grounded. Compared with the prior art, the invention has the advantages that by utilizing the difference of the conduction threshold voltage of the transistor and the characteristic that the reverse breakdown voltage of the voltage-regulator tube is enough to enable the PMOS tube to be conducted, the voltage-regulator tube is adopted to replace the PMOS tube, and the combined auxiliary tube does not need the requirement of parameter consistency, so that the function of high-matching-degree paired tubes is realized, the application range is expanded, and the scheme has the advantages of very low cost, high reliability and the like. The practicability is very high, and the price, performance and the like exceed those of high-matching-degree geminate transistors.

Description

Technical Field

[0001] The invention relates to the technical field of power diodes, and in particular to a high-end ideal diode with loose auxiliary tube parameters. Background Art

[0002] In electronic products, diodes are increasingly used because of their unidirectional conduction characteristics and their ability to prevent backflow. Diodes are one of the indispensable components. However, the conduction voltage drop (V F ) is about 0.6V, although the Schottky diode conduction voltage drop (V F ) is about 0.2~0.3V, with a small voltage drop, which is welcomed by many designers. Although Schottky diodes can meet some circuit design requirements, for circuits that require extremely low conduction voltage drop, the voltage drop of Schottky diodes is still greater than the voltage drop of MOS tubes, which is difficult to meet the needs of such circuits. For some voltage-sensitive circuits, MOS tubes with low impedance characteristics are more likely to be used to improve product reliability. Therefore, it is necessary to develop a unidirectional conduction device (ideal diode) with extremely low conduction voltage drop to reduce circuit power loss and improve power efficiency. Therefore, a low-loss ideal diode is needed to further reduce the voltage drop, and it has the function of preventing backflow and protecting the previous stage to minimize the loss and extend the battery working time.

[0003] According to the polarity of the controlled power supply, it is divided into High Side (high-end, high-side, high-side) load switch and Low Side (low-end, low-side, low-side) load switch, which are similar to controlling the live wire and neutral wire of the 220V AC power supply. High-end load switch: It connects or disconnects the power supply (battery or adapter) to a specific load through the control of an external enable signal. Compared with the low-end load switch, the high-end load switch "flows" current to the load, while the low-end load switch connects or disconnects the load to the negative pole, so it "draws" current from the load. The low-end ideal diode is installed between the load and the negative pole of the power supply as a low-end drive switch to control the conduction or disconnection of the negative pole of the power supply, so it "draws" current from the load.

[0004] The combination forms of high-end ideal diodes mainly include: PMOS main tube + PNP auxiliary tube technology, PMOS main tube + PMOS auxiliary tube technology, etc. In addition, the high-end ideal diode technology implementation scheme that is most similar to the present invention is as follows.

[0005] PMOS main tube + PNP auxiliary tube technical solution: The existing technical solution includes a comparison circuit (combination logic control circuit) and a PMOS main tube. The comparison circuit consists of two independent PNP tubes or PNP pairs with the same parameters and packaged together. Two resistors R1 and R2 form a comparator circuit, such as Figure 1As shown, the PMOS tube is turned on and off: when the input voltage is not less than the output voltage, the PMOS tube is turned on; otherwise, the PMOS tube is turned off to prevent the output current from flowing back to the input end, protecting the input power circuit, which is equivalent to a high-end ideal diode. The disadvantage is that the bias resistors R1 and R2 of the PNP auxiliary tube are in the kilo-ohm level, and the static working current loss is at least in the milliampere level, which is a large current loss.

[0006] PMOS supervisor + PMOS auxiliary tube (pair of tubes) technical solution: Existing technology patent (an ultra-low loss ideal diode, patent number: CN201821304820.X), which uses PMOS supervisor to realize high-end ideal diode, including comparison circuit and PMOS supervisor, the comparison circuit consists of two independent auxiliary PMOS tubes or PMOS pairs with the same parameters and packaged together, and two resistors R1 and R2 constitute a comparator circuit, such as Figure 2 As shown, the on and off of the PMOS tube is controlled: when the input voltage is not less than the output voltage, the PMOS tube V1 is turned on (the PMOS tube V2 is turned on and the PMOS tube V3 is turned off); otherwise, the PMOS tube V1 is turned off (the PMOS tube V2 is turned on and the PMOS tube V3 is turned on), preventing the output current from flowing back to the input end, protecting the input power supply circuit, which is equivalent to a high-end ideal diode. Since the PMOS tube is a voltage device, the PMOS tube conduction voltage drop and bias current are relatively small (at the microampere level), and the loss can be ignored. Compared with the rectifier bridge composed of traditional diodes, the loss is greatly reduced. The bias resistors R1 and R2 of the PMOS auxiliary tube are in the megohm level, and the static working current loss is in the microampere level. The current loss is much smaller than the PNP auxiliary tube (pair of tubes) + PMOS tube technical solution.

[0007] Matched Pairs Transistor, referred to as Matched Pairs Transistor, is a pair of transistors of the same type (NPN, PNP, NMOS or PMOS) with very similar parameters made on the same substrate and packaged in a single chip. The temperatures of the two transistors will affect each other, and the ambient temperature will have the same effect on the two transistors. The noise coefficient, characteristic curve, amplification factor, etc. of the two transistors are required to be as consistent as possible, and the consistency can be within 10%, or even 1%. In this case, by forming a circuit through a specific wiring method, the noise of the transistor itself, the zero drift caused by temperature, and the influence of the common mode signal on the differential mode signal can be offset to a considerable extent. Matched pair transistors can be used in current mirrors, differential amplifier circuits, balanced amplifiers, mixers, detectors and limiters, etc. NPN and PNP tubes are used in push-pull emitter followers, etc. For example, AD's monolithic dual-channel NPN pair tube MAT01GHZ, NPN pair tube SSM2212RZ; CMKT2222A integrated dual-channel NPN transistor; BSS84DW-7-F, CTLDM304P-M832DS integrated dual-channel PMOS tube, CMKT2907A integrated dual PNP tube, etc., are not listed one by one.

[0008] AD company's NPN pair tube MAT01GHZ matching degree: V BE The typical value is 40μV, the maximum value is 200μV, the temperature drift is 0.15μV / ℃, and the magnification is h FE The typical value is 1.0% and the maximum value is 8.0%, which achieves a very good matching degree. It can be called a high matching pair of tubes. The disadvantage is that the price is very expensive. The unit price of a single piece in a famous domestic electronic component mall exceeds ￥90 yuan (tax included) and the unit price of 100 pieces exceeds ￥75 yuan (tax included); if purchased from overseas, the minimum order of 15 pieces is: the unit price of a single piece exceeds ￥180 yuan (tax included) and the unit price of 1,000 pieces exceeds ￥160 yuan (tax included). AD company's same series NPN pair tube MAT01AH / 883 matching degree: magnification h FE The typical value is 0.7% and the maximum is 3.0%. Overseas purchasing is used, with a minimum order of 1 piece. The unit price of a single piece exceeds ￥1,000 yuan (tax included), and the unit price of 5 pieces exceeds ￥940 yuan (tax included).

[0009] AD company's NPN pair tube SSM2212RZ matching degree: V BEThe typical value is 10μV, the maximum value is 100μV, the temperature drift is 0.03μV / ℃, and the typical value of the current gain is 0.5%, which achieves a good matching degree. It can be called a high-matching pair of tubes. The disadvantage is that the price is very expensive. The unit price of a single piece in a famous domestic electronic mall exceeds ￥60 yuan (tax included), and the unit price of 100 pieces exceeds ￥50 yuan (tax included).

[0010] The dual transistors packaged together can realize a pair of devices with high matching degree. The advantage is that there is no need for costly fine-tuning. Considering factors such as price, dual transistors packaged together are generally chosen, but the matching degree is higher than that of general single transistors, and can be used in higher precision occasions; the matching degree of high matching pairs of tubes can be within 1%, and due to the complexity of the processing technology, the price is naturally expensive, and ordinary products cannot afford it. In addition, the research and development cost of high matching pairs of tubes is high, there are few manufacturers, few models, few options, and low demand. The price is in a monopoly state and has remained high. The scope of application is greatly limited, so it is necessary to compromise between price and matching degree (performance).

[0011] The above two technical solutions require that the parameters of the PNP pair of tubes or the PMOS pair of tubes are consistent. If the parameters of the tubes are inconsistent, they cannot be used for some high-precision occasions. To solve the problem of inconsistent tube parameters, it is necessary to design a high-end ideal diode with loose auxiliary tube parameters. By using conventional and inexpensive transistors (with inconsistent auxiliary tube parameters), a high "matching" pair of tubes can be achieved, which may even exceed the high-matching pair of tubes in terms of price and performance, thereby controlling the conduction and cutoff of the PMOS main tube and enriching the implementation methods of high-end ideal diodes. Summary of the invention

[0012] The technical problem to be solved by the present invention is to overcome the above technical defects and provide a high-end ideal diode with loose auxiliary tube parameters.

[0013] In order to solve the above technical problems, the technical solution provided by the present invention is: a high-end ideal diode with loose auxiliary tube parameters, including a circuit, wherein the circuit includes a PMOS tube and a voltage comparator, and the voltage comparator is used to compare the drain and source voltage difference of the PMOS tube V1;

[0014] When the power supply voltage is forward biased, the PMOS supervisor V1 is turned on, and when the power supply voltage is reverse biased, the PMOS supervisor is turned off;

[0015] It also includes a power supply VCC and a load resistor RL. The drain of the PMOS main body V1 is connected to the power supply VCC, the source is connected to one end of the load resistor RL, and the other end of the load resistor RL is grounded.

[0016] Preferably, the voltage comparator comprises a voltage regulator tube D1 and a MOS tube respectively arranged at the drain and source ends of the PMOS main tube V1.

[0017] Preferably, the MOS tube is a PMOS auxiliary tube V3, the cathode of the voltage regulator tube D1 is connected to the drain of the PMOS main tube V1, the anode is connected to the gate of the PMOS auxiliary tube V3, and the anode of the voltage regulator tube is also connected to the bias resistor R1;

[0018] The source of the PMOS auxiliary tube V3 is connected to the source of the PMOS main tube V1 , the drain is connected to the bias resistor R2 , and the drain of the PMOS auxiliary tube V3 is also connected to the gate of the PMOS main tube V1 .

[0019] Preferably, when the PMOS tube V1 is forward biased: the voltage regulator tube D1 is turned on, the PMOS auxiliary tube V3 is turned off, and the PMOS main tube V1 is turned on;

[0020] When the PMOS tube V1 is reverse biased: the voltage regulator tube D1 is cut off, the PMOS auxiliary tube V3 is turned on, and the PMOS main tube V1 is cut off.

[0021] The advantages of the present invention compared with the prior art are:

[0022] The present invention utilizes the difference in transistor conduction threshold voltage and the reverse breakdown voltage of the voltage regulator tube that is sufficient to turn on the PMOS tube, and adopts the voltage regulator tube to replace the PMOS tube. The combined auxiliary tube does not need to have consistent parameters, and the function of a high "matching degree" pair of tubes is realized, thereby expanding the scope of application. The solution has very low cost and strong practicality, and exceeds the high matching degree pair of tubes in terms of price and performance.

[0023] The combined auxiliary tube of the technical solution of the present invention is composed of a PMOS tube + a voltage regulator tube. Both the PMOS tube and the voltage regulator tube are common components, which are cheap, have many models and manufacturers, and the parameters of the two are basically unrelated. The auxiliary tube parameter requirements are relatively loose, and the diode has conduction and cutoff characteristics, and only the conduction threshold voltage of the PMOS tube is required to meet -V Z <V TP <V F -V Z This requirement is relatively easy to achieve and easy to promote and apply. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is the ideal diode schematic diagram composed of PMOS main tube + NPN auxiliary tube in the existing technology;

[0025] Figure 2 This is the ideal diode schematic diagram composed of PMOS main tube + PMOS auxiliary tube in the prior art;

[0026] Figure 3 A high-end ideal diode realized by an auxiliary tube composed of a PMOS tube and a voltage regulator tube of the present invention;

[0027] Figure 4 for Figure 3 Forward conduction simulation;

[0028] Figure 5 for Figure 3 Reverse cutoff simulation (I);

[0029] Figure 6 for Figure 3 Reverse cutoff simulation (II);

[0030] Figure 7 for Figure 3 Reverse cutoff simulation (III). DETAILED DESCRIPTION

[0031] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0032] Zener diode, also known as Zener diode, is a diode that works specifically in the reverse breakdown state. Its forward characteristic is an exponential curve like an ordinary diode. In the reverse breakdown region, within a certain range of working current, the curve of the breakdown region is very steep, almost parallel to the vertical axis, and the cathode terminal voltage is almost unchanged, showing a voltage-stabilizing characteristic. The PN junction area is large and can pass a relatively large current. Its junction capacitance is large and the operating frequency is low. It is used in voltage-stabilized power supplies and limiting circuits. Generally speaking, the higher the doping concentration of the PN junction, the greater the charge density, and the lower the reverse breakdown voltage. The Zener diode is made according to this principle and is generally used for reverse bias. As long as the reverse current is controlled within a certain range, the Zener diode will not be damaged due to overheating. During normal use, a current-limiting resistor needs to be connected in series to prevent damage. The voltage regulation value of the Zener diode is 2.4V~75V, which is the voltage value of the E24 series, with a common ratio of 10 1 / 24 ≈1.1, voltage regulation accuracy is 5%, 2%, 1%;

[0033] YANGJIE (Yangjie)'s low-power PMOS tube BSS84, the minimum turn-on threshold voltage V marked in the data sheet TP(MIN) =-0.9V, maximum value V TP(MAX) =-2.0V, typical value V TP = -1.4V; DIODES (US-Taiwan) company's low-power PMOS tube NDS0610, the minimum turn-on threshold voltage V marked in the data sheet TP(MIN) =-1V, maximum value V TP(MAX) =-3.5V, typical value not given V TP =-1.7V; MICROCHIP's low-power PMOS tube TP5322K1-G, the minimum turn-on threshold voltage V marked in the data sheet TP(MIN) =-1V, maximum value V TP(MAX)=-2.4V, typical value not given.

[0034] The PN junction of an ordinary diode and the emitter junction of a BJT tube are turned on at a threshold voltage (forward voltage) V F =0.6V~0.7V; Zener diode stable voltage value (stable breakdown voltage) V Z(MIN) >1.0V, the stable voltage value is mostly greater than 2.4V. Generally speaking, the minimum turn-on threshold voltage of a low-power PMOS tube is V TP(MIN) Satisfies: -V Z(MIN) <V TP(MIN) <-V F , V F Not enough to turn on the PMOS tube, V Z(MIN) >-V TP It is enough to turn on the PMOS tube, so the difference in the turn-on threshold voltage can be used, so a Zener diode can be used to replace the PMOS tube V2;

[0035] exist Figure 2 On the basis of the PMOS main tube + PMOS pair tube (auxiliary tube), a Zener diode is used to replace the PMOS tube V2. The PMOS tube + voltage regulator tube constitutes the auxiliary tube to realize the high-end ideal diode schematic diagram as shown in the figure. Figure 3 As shown: a high-end ideal diode with loose auxiliary tube parameters is realized, and the theoretical analysis is as follows.

[0036] Depend on Figure 2 It can be seen that the on and off of the PMOS tube are controlled: when the input voltage is not less than the output voltage, the PMOS tube V1 is turned on (the PMOS tube V2 is turned on, and the PMOS tube V3 is turned off); otherwise, the PMOS tube V1 is turned off (the PMOS tube V2 is turned on, and the PMOS tube V3 is turned on). Figure 3 The state of the PMOS tube V3 in the schematic diagram is Figure 2 The PMOS tube V3 in the schematic diagram is consistent and meets the VCC-V F >-V TP(MAX) When the PMOS tube V1 is forward biased: the PMOS tube V1 is turned on and the PMOS tube V3 is turned off, that is, VCC>Vout (the difference between the two is small, at the beginning Vout=VCC-V F ), the voltage regulator D1 reverses and breaks down, and the gate voltage of the PMOS tube V3 is Y = VCC-V Z , the gate-source voltage difference of PMOS tube V3 is V3 GS =Y-Vout=VCC-V Z -(VCC-V F )=VCC-V Z -VCC+V F =V F -V Z >VTP , PMOS tube V3 is cut off, the drain voltage V1G of PMOS tube V3 is ≈ 0V, V1 GS =V1G-Vout≈V F -VCC<V TP , the drain-source channel of PMOS V1 is turned on.

[0037] After the drain-source channel of the PMOS V1 is turned on, assuming the on-current is I D , the drain-source channel conduction impedance is V1R DS(ON) Generally speaking, I D ×V1R DS(ON) <V F (Otherwise, there is a problem with the ideal diode circuit design), the output voltage is Vout = VCC-I D ×V1R DS(ON) , V3 GS =Y-Vout=VCC-V Z -(VCC-I D ×V1R DS(ON) )=VCC-V Z -VCC+I D ×V1R DS(ON) =I D ×V1R DS(ON) -V Z >V TP , the PMOS tube V3 still needs to be in the cut-off state.

[0038] When the PMOS tube V1 is forward biased: V F -V Z >V TP ,I D ×V1R DS -V Z >V TP , due to I D ×V1R DS <V F , that is, V F -V Z >V TP .

[0039] When the PMOS tube V1 is reverse biased, the PMOS tube V1 is cut off and the PMOS tube V3 is turned on, that is, VCC2>VCC (B=Vout=VCC2, A=VCC1=VCC), the voltage regulator D1 reversely breaks down and works in a voltage-stabilizing manner, and the gate voltage of the PMOS tube V3 is Y=VCC-V Z ; The body diode of the PMOS V1 is reversely cut off, the body diode of the V3 tube is cut off, and V3 GS =Y-Vout=VCC-V Z-VCC2<V TP , since VCC2>VCC, if V Z >-V TP Obviously, PMOS tube V3 is turned on, V1G≈Vout, V1 GS =V1G-Vout≈0V>V TP(MAX) , the PMOS supervisor V1 is cut off, the power supply VCC1 is isolated from the external power supply VCC2, and the current of the external power supply cannot flow back into the power supply VCC1, thereby achieving the purpose of protecting the power supply VCC1.

[0040] When considering the forward bias and reverse bias, the following conditions must be met at the same time: V F -V Z >V TP 、V Z >-V TP , solve for V F >V Z +V TP >0, i.e. -V Z <V TP <V F -V Z .

[0041] When the PMOS V1 is forward biased: the voltage regulator D1 breaks down and conducts, the PMOS V3 is cut off, and the V1 is turned on; when the PMOS V1 is reverse biased: the voltage regulator D1 breaks down and conducts, the PMOS V3 is turned on, and the V1 is cut off. Therefore, the conduction and cutoff of the PMOS V1 have opposite direction characteristics to those of the V3.

[0042] The auxiliary tube and bias power supply composed of PMOS tube + Zener tube realizes the function of high-end ideal diode well. The PMOS auxiliary tube V3 at the back end of the voltage comparator outputs the V1G signal to control the on and off of the PMOS main tube V1: when the power supply voltage A is greater than the high end of the load Vout (B), the PMOS main tube V1 is turned on; otherwise, the PMOS main tube V1 is turned off to prevent the power supply Vout current from being poured into the power supply circuit through the PMOS main tube, which is equivalent to a high-end ideal diode.

[0043] Figure 3 The state of the PMOS tube V3 in the schematic diagram is Figure 2 The PMOS tube V3 in the schematic diagram is consistent with VCC-V F >-V TP(MAX) When the PMOS tube V1 is forward biased: the PMOS tube V1 is turned on and the PMOS tube V3 is turned off, that is, VCC>Vout (the difference between the two is small, at the beginning Vout=VCC-V F ), the voltage regulator D1 reverses and breaks down, and the gate voltage of the PMOS tube V3 is Y = VCC-V Z, the gate-source voltage difference of PMOS tube V3 is V3 GS =Y-Vout=VCC-V Z -(VCC-V F )=VCC-V Z -VCC+V F =V F -V Z >V TP , PMOS tube V3 is cut off, the drain voltage V1G of PMOS tube V3 is ≈ 0V, V1 GS =V1G-Vout≈V F -VCC<V TP(MAX) , the drain-source channel of PMOS V1 is turned on.

[0044] After the drain-source channel of the PMOS V1 is turned on, assuming the on-current is I D , the drain-source channel conduction impedance is R1 DS Generally speaking, I D ×R1 DS <V F (Otherwise, there is a problem with the ideal diode circuit design), the output voltage is Vout = VCC-I D ×R1 DS , V3 GS =Y-Vout=VCC-V Z -(VCC-I D ×R1 DS )=VCC-V Z -VCC+I D ×R1 DS =I D ×R1 DS -V Z >V TP , the PMOS tube V3 still needs to be in the cut-off state.

[0045] When the PMOS tube V1 is forward biased: V F -V Z >V TP ,I D ×R1 DS -V Z >V TP , that is, V F -V Z >V TP .

[0046] When the PMOS tube V1 is reverse biased: the PMOS tube V1 is cut off and the PMOS tube V3 is turned on, that is, VCC2>VCC (B=Vout=VCC2, A=VCC1=VCC), the voltage regulator D1 reversely breaks down and works as a regulator, and the gate voltage of the PMOS tube V3 Y=VCC-V Z ; The body diode of the PMOS V1 is reversely cut off, the body diode of the V3 tube is cut off, and V3 GS =Y-Vout=VCC-V Z -VCC2<V TP , since VCC2>VCC, V Z >-V TP Obviously, PMOS tube V3 is turned on, V1G≈Vout, V1 GS =V1G-Vout≈0V>V TP(MAX) , the PMOS supervisor V1 is cut off, the power supply VCC1 is isolated from the external power supply VCC2, and the current of the external power supply cannot flow back into the power supply VCC1, thereby achieving the purpose of protecting the power supply VCC1.

[0047] In summary, when forward biased and reverse biased, the following conditions must be met at the same time: V F -V Z >V TP 、V Z >-V TP , solve for V F >V Z +V TP >0, i.e. -V Z <V TP <V F -V Z .

[0048] When the voltage regulator tube D1 breaks down and conducts, the PMOS tube V3 is cut off, and the V1 tube is turned on; when the PMOS tube V1 is reverse biased: the voltage regulator tube D1 breaks down and conducts, the PMOS tube V3 is turned on, and the V1 tube is cut off. Therefore, the conduction and cutoff of the PMOS tube V1 have opposite direction characteristics to those of the V3 tube.

[0049] The auxiliary tube and bias power supply composed of PMOS tube + Zener tube realizes the function of high-end ideal diode well. The PMOS auxiliary tube V3 at the back end of the voltage comparator outputs the V1G signal to control the on and off of the PMOS main tube V1: when the power supply potential A is greater than the high end Vout (B) of the load, the PMOS main tube V1 is turned on; otherwise, the PMOS main tube V1 is turned off to prevent the power supply Vout current from being poured into the power supply circuit through the PMOS main tube, which is equivalent to a high-end ideal diode.

[0050] according to Figure 3The circuit schematic is simulated and tested using the National Instruments simulation software Multisim (version V14.0). The PMOS tube is from ON Semiconductor, model NVTFS5124PLTAG, and the minimum on-threshold voltage V TP(MIN) =-1.5V, maximum value V TP(MAX) =-2.5V, typical value V not given TP (Assuming V TP =-2.0V), the on-state current can reach -6A, and the on-state impedance R DS(ON) =0.26Ω(V GS =-10V), R DS(ON) =0.38Ω(V GS =-4.5V). The voltage regulator is made by NXP, model BZX84-A2V4, and the voltage regulation value (nominal value) is V Z =2.4V±1%, the specific simulation test is as follows. Load resistance RL = 10Ω, V Z =2.4V Substitute into -V Z <V TP <V F -V Z , that is -2.4V<V TP <-1.7V, just enough to meet -V Z <V TP <V F -V Z The specific simulation test is as follows.

[0051] DC power supply forward bias simulation test (I): VCC = VCC1 = 12V (switch J1 is closed, switch J2 is open), Zener diode D1 reversely breaks down and works normally, Y = VCC-V Z =9.71V, PMOS tube V3 gate-source voltage V3 GS =Y-Vout≈9.71V-11.7V=-1.99V>V TP , V3 tube is cut off, V1G=192mV, the gate and source voltage difference of V1 tube is V1 GS =V1G-A≈0-12.0V=-12V<V TP(MAX) , PMOS is in charge of V1, the conduction current is 1.17A (detection points PR3, PR4), and the conduction voltage drop is 0.3V. Figure 4 shown.

[0052] DC power supply reverse bias simulation test (II): VCC = VCC1 = 12V, when the power supply VCC2 is reversely input, VCC2 = Vout = 12.001V (switches J1 and J2 are closed), because the voltage regulator D1 reversely breaks down and works normally, Y = VCC-V Z =9.71V, the body diode of PMOS tube V1 is cut off, and the gate-source voltage of PMOS tube V3 is V3 GS =Y-Vout≈9.71V-12.001V=-2.29V<V TP , V3 tube is turned on, V1G=VCC2≈12.0V, the gate and source voltage difference of V1 tube is V1 GS =V1G-Vout≈12.0V-12.0V=0V>V TP(MIN) , PMOS supervisor V1 cut-off, such as Figure 5 shown.

[0053] DC power supply reverse bias simulation test (III): VCC = VCC1 = 12V, when the power supply VCC2 is reversely input, VCC2 = Vout = 15V (switches J1 and J2 are closed), because the voltage regulator D1 reversely breaks down and works normally, Y = VCC-V Z =9.71V, the body diode of PMOS tube V1 is cut off, and the gate-source voltage of PMOS tube V3 is V3 GS =Y-Vout≈9.71V-15V=-5.29V<V TP(MAX) , V3 tube is turned on, V1G=VCC2≈15.0V, the gate and source voltage difference of V1 tube is V1 GS =V1G-Vout≈15.0V-15.0V=0V>V TP(MIN) , PMOS supervisor V1 cut-off, such as Figure 6 shown.

[0054] DC power supply reverse bias simulation test: VCC = VCC1 = 12V, when the power supply VCC2 is reversely input, VCC2 = Vout = 30V (switches J1 and J2 are closed), because the voltage regulator D1 reversely breaks down and works normally, Y = VCC-V Z =9.71V, the body diode of PMOS tube V1 is cut off, and the gate-source voltage of PMOS tube V3 is V3 GS =Y-Vout≈9.71V-30V=-20.29V<V TP(MAX) , V3 tube is turned on, V1G=VCC2≈30.0V, the gate and source voltage difference of V1 tube is V1 GS =V1G-Vout≈30.0V-30.0V=0V>V TP(MAX) , PMOS supervisor V1 cut-off, such as Figure 7 shown.

[0055] Beneficial effects of the present invention: The auxiliary tube used in the circuit is PMOS + voltage regulator tube. PMOS and voltage regulator tube are common components, cheap, with many models and manufacturers, and the parameters of the two are basically unrelated. The auxiliary tube parameter requirements are relatively loose, and only the PMOS tube conduction threshold voltage is required to meet: -V Z <V TP <V F -V Z This requirement is relatively easy to achieve. The combined auxiliary tube composed of PMOS + Zener tube is used in high-end ideal diode circuits. The circuit is simple, the cost is very low (the cost may be less than one thousandth of the high-matching pair of tubes, which greatly saves costs), and it is very practical.

[0056] The preferred specific embodiments of the present invention are described in detail above. It should be understood that a person skilled in the art can make many modifications and changes based on the concept of the present invention without creative work. Therefore, any technical solution that can be obtained by a person skilled in the art through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the scope of protection determined by the claims.

Claims

1. A high-end ideal diode with loose auxiliary tube parameters, characterized in that: The circuit includes a PMOS tube and a voltage comparator, and the voltage comparator is used to compare the drain and source voltage difference of the PMOS tube V1; When the power supply voltage is forward biased, the PMOS supervisor V1 is turned on, and when the power supply voltage is reverse biased, the PMOS supervisor is turned off; It also includes a power supply VCC and a load resistor RL. The drain of the PMOS main body V1 is connected to the power supply VCC, the source is connected to one end of the load resistor RL, and the other end of the load resistor RL is grounded.

2. The high-end ideal diode with loose auxiliary tube parameters according to claim 1, characterized in that: The voltage comparator includes a voltage regulator tube D1 and a MOS tube which are respectively arranged at the drain and source ends of the PMOS main tube V1.

3. The high-end ideal diode with loose auxiliary tube parameters according to claim 2, characterized in that: The MOS tube is a PMOS auxiliary tube V3, the cathode of the voltage regulator tube D1 is connected to the drain of the PMOS main tube V1, the anode is connected to the gate of the PMOS auxiliary tube V3, and the anode of the voltage regulator tube is also connected to the bias resistor R1; The source of the PMOS auxiliary tube V3 is connected to the source of the PMOS main tube V1 , the drain is connected to the bias resistor R2 , and the drain of the PMOS auxiliary tube V3 is also connected to the gate of the PMOS main tube V1 .

4. The high-end ideal diode with loose auxiliary tube parameters according to claim 3, characterized in that: When the PMOS tube V1 is forward biased: the voltage regulator tube D1 is turned on, the PMOS auxiliary tube V3 is turned off, and the PMOS main tube V1 is turned on; When the PMOS tube V1 is reverse biased: the voltage regulator tube D1 is cut off, the PMOS auxiliary tube V3 is turned on, and the PMOS main tube V1 is cut off.

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