Signal distribution circuit and operation method thereof

Abstract

A signal distribution circuit includes a signal node configured to receive a first control signal, a delay stage coupled to the signal node and configured to output a first boost signal in response to the first control signal, and a boost stage coupled to the signal node and the delay stage. The boost stage includes a pull-up circuit including a first PMOS transistor configured to couple the signal node to a supply voltage node in response to the first boost signal, and a pull-down circuit configured to couple the signal node to the supply voltage node in response to the first boost signal. The pull-down circuit includes a first NMOS transistor configured to couple the signal node to a reference voltage node in response to the first booster signal. The invention also discloses a method for operating the signal distribution circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to signal distribution circuits and methods of operating the same. Background Art

[0002] In many integrated circuit (IC) applications, control signals or other signals are output from a signal source circuit, such as a control circuit, and routed to multiple destinations. In some cases, such as for a large number of circuits, distributing the signals relies on long routing paths, which may compromise the integrity of the transmitted signals. An example is a memory circuit, where an enable signal is distributed from a control circuit to multiple local input / output (LIO) circuits. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a signal distribution circuit is provided, comprising: a signal node configured to receive a first control signal; a delay stage coupled to the signal node and configured to output a first booster signal in response to the first control signal; and a booster stage coupled to the signal node and the delay stage, wherein the booster stage comprises: a pull-up circuit comprising a first transistor configured to couple the signal node to a power supply voltage node in response to the first booster signal; and a pull-down circuit comprising a second transistor configured to couple the signal node to a reference voltage node in response to the first booster signal.

[0004] According to another aspect of an embodiment of the present application, a signal distribution circuit is provided, comprising: a first signal line and a second signal line; a driver, coupled to the first ends of the first signal line and the second signal line, and configured to output corresponding first control signals and second control signals to the first signal line and the second signal line; a booster circuit, coupled to the second end of the first signal line; and a buffer, coupled between the second end of the second signal line and the booster circuit, wherein the booster circuit comprises: a delay stage, configured to output a first booster signal in response to a first control signal received at the second end of the first signal line; and a boosting stage, coupled to the delay stage, wherein the boosting stage comprises: a pull-up circuit, configured to couple an input terminal of the buffer to a power supply voltage node in response to the first booster signal; and a pull-down circuit, configured to couple the input terminal of the buffer to a reference voltage node in response to the first booster signal.

[0005] According to another aspect of an embodiment of the present application, a method for operating a signal distribution circuit is provided, the method comprising: receiving a first control signal at a signal node of a booster circuit; outputting a booster signal from a delay stage of the booster circuit in response to the first control signal; and selectively coupling the signal node to each of a power supply voltage node and a reference voltage node using a booster stage of the control circuit in response to the first control signal and the booster signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A and Figure 1B is a schematic diagram of a signal distribution circuit according to some embodiments.

[0008] Figure 2A and Figure 2B is a schematic diagram of a signal distribution circuit according to some embodiments.

[0009] Figure 3 is a schematic diagram of a signal distribution circuit according to some embodiments.

[0010] Figure 4A and Figure 4B is a graph of operating parameters of a signal distribution circuit according to some embodiments.

[0011] Figure 5 is a schematic diagram of a signal distribution circuit according to some embodiments.

[0012] Figure 6 is a schematic diagram of a signal distribution circuit according to some embodiments.

[0013] Figure 7 is a flow chart of a method of operating a booster circuit according to some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0016] In various embodiments, booster circuits and methods include a delay stage and a booster stage, the delay stage configured to output a booster signal in response to a first control signal received at a signal node, the booster stage including pull-up and pull-down circuits configured to couple the signal node to respective power and reference voltage nodes in response to the booster signal. In some embodiments, the booster circuit is included in a signal distribution circuit, wherein a driver is configured to output a first control signal and a second control signal at first ends of first and second signal lines, and the signal node is coupled to a second end of the first signal line and a buffer coupled to a second end of the second signal line.

[0017] By including pull-up and pull-down circuits configured to control a signal node in response to a first control signal, the booster circuit can improve the integrity of the first signal by causing the buffer to drive the second end of the second signal line according to the first control signal, thereby improving the integrity of the second control signal between the first end and the second end of the second signal line. In some embodiments, the booster circuit is further configured to avoid contention between the control circuit and the buffer during a power-on sequence and / or during a continuous operating mode (e.g., during high-speed operation including control signals with short pulse widths), for example by including a suppression circuit.

[0018] According to various embodiments, Figure 1A-Figure 3 , Figure 5 and Figure 6 Each of which is a schematic diagram of a signal distribution circuit 100, 100M, 200A, 200B, 300, 500, or 600, including a corresponding booster circuit 140, 240A, 240B, 340, 540, or 640, Figure 4A and Figure 4B is a graph of operating parameters of a signal distribution circuit according to some embodiments, Figure 7 is a flow chart of a method of operating a booster circuit according to some embodiments.

[0019] In some embodiments, one or more of the booster circuits 140, 240A, 240B, 340, 540, or 640 or the signal distribution circuit 100, 100M, 200A, 200B, 300, 500, or 600 are part or all of an integrated circuit (IC). In some embodiments, one or more of the booster circuits 140, 240A, 240B, 340, 540, or 640 or the signal distribution circuit 100, 100M, 200A, 200B, 300, 500, or 600 are included in another IC circuit, such as a digital circuit, an analog circuit, and / or a memory circuit.

[0020] For ease of explanation, Figure 1A-Figure 6 In some embodiments, one or more of circuits 100, 100M, 200A, 200B, 300, 500, or 600 may include a plurality of circuits 100, 100M, 200A, 200B, 300, 500, or 600. Figure 1A-Figure 6 In addition to the features shown in , other features may be included, for example, a global control circuit configured to generate one or more control signals and / or enable signals including and / or in addition to the signals discussed below. Figure 1A-Figure 6 The circuit elements depicted in include corresponding input and output terminals, which are not labeled for the sake of clarity.

[0021] Figure 1A and Figure 1B 1 is a schematic diagram of respective signal distribution circuits 100 and 100M according to some embodiments. Signal distribution circuit 100 corresponds to a general embodiment including booster circuit 140, and signal distribution circuit 100M corresponds to a memory circuit embodiment including booster circuit 140, as described below. In some embodiments, as described below, one or both of signal distribution circuits 100 or 100M includes one of booster circuits 240A, 240B, 340, 540, or 640 instead of booster circuit 140.

[0022] The signal distribution circuit 100 (also referred to as circuit 100 in some embodiments) includes a driver 110, a load circuit 120, a buffer 130, a booster circuit 140, a booster enabling source 150 (in some embodiments), and signal lines SL1, SL2, and SL3 (in some embodiments). The driver 110 is coupled to a first end of each of the signal lines SL1, SL2, and SL3 (if present). The buffer 130 is coupled to a second end of the signal line SL1, and the load circuit 120 is coupled to the signal line SL1 between the driver 110 and the buffer 130. The booster circuit 140 is coupled to a second end of the signal lines SL2 and SL3 (if present).

[0023] Two or more circuit elements are considered to be coupled based on a direct electrical connection or an electrical connection involving one or more additional circuit elements, and thus capable of being controlled by one or more transistors or other switching devices, such as to have a resistance or an open circuit.

[0024] The driver 110 (also referred to as the control circuit 110 in some embodiments) is an electronic circuit, such as an IC, configured to output a control signal CS1 from a corresponding output terminal to a first end of the signal line SL1, to output a control signal CS2 to a first end of the signal line SL2, and in some embodiments to output a control signal CS3 to the signal line SL3.

[0025] A control signal (e.g., control signals CS1-CS3) is an electronic signal that includes transitions between a high voltage level and a low voltage level (e.g., corresponding to a high logic level and a low logic level). The high voltage or logic level corresponds to a voltage within a predefined range of a power supply voltage level (e.g., a VDD voltage level), and the low voltage or logic level corresponds to a current within a predetermined range of a reference voltage level (e.g., a VSS or ground voltage level). The timing of the control signal is affected by the rate at which the control signal transitions between the low voltage level and the high voltage level (also referred to as the slew rate in some embodiments), and a given signal transition therefore corresponds to the time that the signal voltage transitions between the high voltage level and the low voltage level.

[0026] Driver 110 is configured to generate control signals CS1 and CS2 including some or all transitions that are synchronized with each other. The transitions are considered to be synchronized with each other (also referred to as being at the same time in some embodiments) by including overlapping transition times or transition times that occur within a predetermined timing range.

[0027] In some embodiments, when each of the control signals CS1 and CS2 includes a positive transition from a low voltage level to a high voltage level or a negative transition from a high voltage level to a low voltage level at the same time, the transitions are considered to be synchronous with each other. In some embodiments, when one of the control signals CS1 or CS2 includes a positive transition while the other includes a negative transition, the transitions are considered to be synchronous with each other.

[0028] In some embodiments, the driver 110 is configured to generate each of the control signals CS1 and CS2 including a series of pulses, each pulse having a pulse width corresponding to the first and second transitions. The first and second transitions of the control signal CS1 are synchronized with the first and second transitions of the control signal CS2, so that the control signals CS1 and CS2 are complementary or synchronized (e.g., identical) pulse signals.

[0029] In some embodiments, driver 110 is configured to generate control signal CS3 including at least one transition synchronized with a second transition of one or both of control signals CS1 or CS2. In some embodiments, driver 110 is configured to generate control signal CS3 complementary to or synchronized with one or both of control signals CS1 or CS2 for an entire or given period of time in a power-on state of circuit 100.

[0030] Buffer 130 is an electronic circuit, such as an IC, which is configured to output a signal BS (also referred to as a booster signal BS in some embodiments) from an output terminal to the second end of the signal line SL in response to a voltage level received at an input terminal from the second end of the signal line SL2, the voltage level corresponding to the control signal CS2, which is propagated from the driver 110 across the signal line SL2 and boosted by the booster circuit 140, as described below.

[0031] The driver 110 and the buffer 130 are configured to output the control signals CS1 and CS2 and the signal BS coordinated with each other, so that the control signal CS1 and the signal BS are regarded as being in phase with each other, and the timing effects of the parasitic resistance and the parasitic capacitance of the signal lines SL1 and SL2 are ignored. In some embodiments, the driver 110 is configured to output the control signals CS1 and CS2 as complementary signals, and the buffer 130 includes inverting logic, such as an inverter. In some embodiments, the driver 110 is configured to output the control signals CS1 and CS2 as synchronization signals, and the buffer 130 includes non-inverting logic, such as an amplifier.

[0032] Each of the signal lines SL1-SL3 includes one or more elongated volumes of conductive material, such as one or more metals such as copper, substantially surrounded by one or more volumes of insulating material (e.g., silicon dioxide) and extending between a first end and a second end. Thus, a given signal line is characterized by distributed parasitic resistance and capacitance such that the total resistance and capacitance values ​​increase as the total length of the one or more elongated volumes of the signal line increases. The capacitance value is affected by the geometry of the signal line relative to nearby structures (e.g., other conductors), and the resistance value is affected by the type of conductive material and the geometry of the signal line (e.g., decreases with increasing cross-sectional area).

[0033] In some embodiments, two or more of the signal lines SL1-SL3 include the same conductive material and have equal cross-sectional areas, thereby having equal total resistance values ​​for a given signal line length. In some embodiments, two or more of the signal lines SL1-SL3 are located in the same metal layer of the IC, such as the first metal layer.

[0034] In some embodiments, signal line SL2 and / or SL3 (if present) includes a conductive material different from the conductive material of signal line SL1 and / or has a larger cross-sectional area than signal line SL1, so that for a given signal line length, the resistance value of signal line SL1 is greater than the resistance value of signal line SL2 and / or signal line SL3. In some embodiments, signal line SL1 is located in a lower metal layer (e.g., a first metal layer) of the IC relative to one or more upper metal layers (e.g., a third metal layer) where signal lines SL2 and / or SL3 are located, and the metal lines in each of the lower and upper layers extend in the same direction perpendicular to the direction of the metal lines in the intermediate metal layer (e.g., the second metal layer).

[0035] A given signal, such as control signals CS1-CS3, propagating from a first end to a second end of a corresponding signal line may result in a loss of signal integrity (e.g., signal delay, attenuation, waveform and / or slew rate degradation) that increases as the total resistance and capacitance values ​​increase. In some embodiments, one or more design specifications based on the integrity of a given signal are included in defining the total resistance and / or capacitance limits of the corresponding signal line and the maximum length defined thereby.

[0036] In some embodiments, as used herein, an end of a signal line refers to a location along the signal line rather than the physical end of the signal line, e.g., a location corresponding to the end of a portion of the signal line along which a corresponding one of the control signals CS1-CS3 propagates, as discussed herein.

[0037] The load circuit 120 is one or more electronic circuits, such as ICs, including an input terminal configured to receive a combination of a control signal CS1 output from the driver 110 to a first end of the signal line SL1 and a signal BS output from the buffer 130 to a second end of the signal line SL1.

[0038] exist Figure 1A In the illustrated embodiment, load circuit 120 is an instance of a plurality of separate circuits distributed along signal line SL1, each circuit including an input terminal. In some embodiments, one or more instances of load circuit 120 include a plurality of input terminals distributed along signal line SL1. In some embodiments, load circuit 120 represents a single circuit including a plurality of input terminals distributed along signal line SL1.

[0039] Compared to signal lines having a similar configuration, equal length, and not including input terminals corresponding to some or all of the input terminals in the load circuit 120, the distributed capacitance value and the total capacitance value of the signal line SL1 are higher due to the presence of the input terminals of the load circuit 120. Figure 1A and Figure 1BIn the illustrated embodiment, the signal lines SL1 and SL2 have substantially equal lengths, and thus the total capacitance of the signal line SL1 is greater than the total capacitance of the signal line SL2 based on the presence of the load circuit 120. In some embodiments, the signal lines SL1 and SL2 have unequal lengths, and the total capacitance of the signal line SL1 is greater than the total capacitance of the signal line SL2 based on the presence of the load circuit 120.

[0040] The booster circuit 140 is an electronic circuit, such as an IC, and in some embodiments includes a delay stage 142, a suppressor circuit 144, and a boost stage 146. Each of the delay stage 142 and the boost stage 146 is coupled to the second end of the signal line SL2 and the input terminal of the buffer 130 through a node SN (also referred to as a signal node SN in some embodiments).

[0041] The booster enable signal source 150 (if present) is an electronic circuit and / or signal path configured to output the booster enable signal EN1 in operation, and in some embodiments, output the booster enable signal EN2 which is complementary to the booster enable signal EN1. In some embodiments, the booster enable signals EN1 and EN2 (if present) are referred to as enable signals EN1 and EN2 or enable signals EN1 and EN2. In some embodiments, the booster enable source 150 is configured to output the enable signals EN1 and EN2 (if present) based on a received signal (e.g., a global enable signal of the circuit 100).

[0042] exist Figure 1A In the illustrated embodiment, the circuit 100 includes a booster enabling source 150 that is separate from the booster circuit 140. In some embodiments, some or all of the booster enabling source 150 is external to the circuit 100 or included in the booster circuit 140.

[0043] In some embodiments, the circuit 100 is configured to operate with the booster circuit 140 in an activated or deactivated state in response to a high or low logic level of the enable signal EN1 and EN2 (if present). Figure 2A-Figure 6In each of the embodiments discussed, the corresponding circuit 200A, 200B, 300, 500 or 600 (which can be used as circuit 100) is configured to operate together with the corresponding booster circuit 240A, 240B, 340, 540 or 640 (which can be used as booster circuit 140) in an activated state based on the booster enabling source 150 outputting an enable signal EN1 with a low logic level and an enable signal EN2 with a high logic level (if present), and to operate together with the corresponding booster circuit 240A, 240B, 340, 540 or 640 in a deactivated state based on the booster enabling source 150 outputting an enable signal EN1 with a high logic level (and an enable signal EN2 with a low logic level if present).

[0044] It is within the scope of the present disclosure that the circuit 100 is configured to operate with the booster circuit 140 in activated and deactivated states in response to enable signals EN1 and EN2 (if present).

[0045] Each of the enable signals EN1 and EN2 is configured to maintain one of a high or low logic level, e.g., corresponding to an activated or deactivated state, for a sufficient time to allow the circuit 100 to perform a power-on sequence and / or a continuous operation mode, during which the control signals CS1-CS3 include a plurality of voltage transitions corresponding to the operating frequency of the circuit 100.

[0046] As the operating frequency of circuit 100 increases, the criticality of the signal integrity of control signals CS1-CS3 relative to signal paths SL1-SL3 increases. In some embodiments, circuit 100 is configured to have a continuous operating frequency from 1 megahertz (MHz) to 500 gigahertz (GHz). In some embodiments, circuit 100 is configured to have a continuous operating frequency ranging from 100 GHz to 400 GHz.

[0047] Delay stage 142 includes one or more logic devices configured to, in operation, output at least one booster signal B1 that includes a corresponding transition in response to and delaying a corresponding transition in control signal CS2 received at node SN. In some embodiments, delay stage 142 is configured to output booster signal B1 that has a delayed transition of opposite polarity to the transition of control signal CS2. For example, as described below with respect to delay stages 242A, 242B, and 542, and Figure 2A-Figure 5 In some embodiments, delay stage 142 is configured to output booster signal B1 having a delayed transition of the same polarity as control signal CS2 transitions, e.g., as described below with respect to delay stage 642 and Figure 6 discussed.

[0048] In some embodiments, delay stage 142 is configured to output a booster signal B2 that is complementary to booster signal B1, for example, as described below with respect to delay stages 242A and 242B and Figure 2A-Figure 3 discussed.

[0049] In some embodiments, the delay stage 142 is configured to receive the enable signal EN1 in operation, and one or more logic devices are configured to output the booster signals B1 and B2 (if present) in response to the enable signal EN1. In some embodiments, the delay stage 142 is configured to output the booster signals B1 and B2 (if present) having a high logic level or a low logic level stable state in response to one of a high logic level or a low logic level of the enable signal EN1, and to output the booster signals B1 and B2 (if present) in response to the logic level of the control signal CS2 in response to the other of a high logic level or a low logic level of the enable signal EN1.

[0050] In some embodiments, delay stage 142 is not configured to receive enable signal EN1 .

[0051] In some embodiments, circuit 100 does not include booster enabling source 150 , and delay stage 142 is configured to output booster signals B1 and B2 (if present) in response to the logic level of control signal CS2 during a power-up sequence and power-up state of the entire circuit 100 .

[0052] In some embodiments, delay stage 142 includes the following reference Figure 2A-Figure 6 One of the delay stages 242A, 242B, 542, or 642 discussed.

[0053] The boost stage 146 includes logic devices arranged as a pull-down circuit 146D and a pull-up circuit 146U, each of which is coupled to the node SN. The pull-down circuit 146D includes an NMOS (N-type metal oxide semiconductor) transistor and a logic gate ( Figure 1A ), which is configured to couple node SN to a reference voltage node ( Figure 1A The reference voltage node is configured to carry a reference voltage level, such as VSS, in response to the control signal CS2 and the booster signal B1. The pull-up circuit 146U includes a PMOS (P-type metal oxide semiconductor) transistor and a logic gate ( Figure 1A ), which is configured to couple the node SN to a power supply voltage node (eg, VDD) configured to carry a power supply voltage level (eg, VDD) in response to the control signal CS2 and the booster signal B1 or B2 in operation. Figure 1A not shown).

[0054] Each of the pull-down circuit 146D and the pull-up circuit 146U is configured to couple the node SN to a corresponding one of the reference voltage node or the power supply voltage node in response to a transition of the control signal CS2 in operation, and to decouple the node SN from a corresponding one of the reference voltage node or the power supply voltage node in response to a transition of the corresponding booster signal B1 or B2 delayed from the transition of the control signal CS2.

[0055] In some embodiments, one of the pull-down circuit 146D or the pull-up circuit 146U is configured to receive the control signal CS3 during operation and, in response to a corresponding control signal CS3 transition synchronized with a control signal CS2 transition, decouple the node SN from a corresponding one of the reference voltage node or the power supply voltage node, such that the pull-down circuit 146D or the pull-up circuit 146U is thereby configured to decouple the node SN from a corresponding one of the reference voltage node or the power supply voltage node at a time different from a time corresponding to a transition of the delay booster signal B1 / B2.

[0056] In such an embodiment, when the delay between the control signal CS2 and the booster signal B1 or B2 is greater than the pulse width of the control signals CS1 and CS2, the boosting stage 146 is configured to decouple the node SN from the corresponding one of the reference voltage node or the power supply voltage node before the end of the control signal CS1 pulse, thereby preventing the buffer 130 from competing with the driver 110 for control of the signal line SL1.

[0057] In some embodiments, the pull-up circuit 146U is configured to receive an enable signal EN1, and further couple the node SN to or decouple the node SN from the power supply voltage node in response to the enable signal EN1. In some embodiments, the pull-up circuit 146U is configured to receive an enable signal EN2, and further couple the node SN to or decouple the node SN from the reference voltage node in response to the enable signal EN2.

[0058] In some embodiments, boost stage 146 includes one of boost stages 246, 346, 546, or 646, which includes the following reference Figure 2A-Figure 6 The corresponding pull-down circuit 246D, 346D, 546D or 646D and the pull-up circuit 246U, 346U, 546U or 646U are discussed.

[0059] In some embodiments, the suppression circuit 144 includes one or more logic devices configured to receive the control signal CS3 and the booster signal B2 in operation, and output the booster signal B3 to the pull-up circuit 146U in response to the control signal CS3 and the booster signal B2, whereby the pull-up circuit 146U is configured to couple the node SN to the power supply voltage node and decouple the node SN from the power supply voltage node in response to the control signal CS3 and the booster signal B2. In some embodiments, the suppression circuit 144 includes the following reference Figure 2A and Figure 2B Suppression circuit 244 discussed.

[0060] In some embodiments, the driver 110 is configured to generate each of the control signals CS1-CS2 in operation, the control signals CS1 and CS2 include the same pulse or complementary pulses having a leading pulse edge and a trailing pulse edge, so that the pulse width of the control signal CS3 is greater than the pulse widths of the control signals CS1 and CS2. In some embodiments, the driver 110 is configured to generate each of the control signals CS1 and CS2 in operation, the control signals CS1 and CS2 include the same pulse or complementary pulses having a leading pulse edge and a trailing pulse edge, and the control signal CS3, the control signal CS3 includes a pulse having a leading edge before or after the leading edges of the control signals CS1 and CS2, and a trailing edge synchronized with the trailing edges of the control signals CS1 and CS2, so that the pulse width of the control signal CS3 is greater than or less than the pulse width of the control signal CS1 or CS2.

[0061] In some embodiments, the control signal CS3 pulse corresponds to a first logic level, and the time period before and after the pulse corresponds to a second logic level, and as described above, based on the received control signal CS3 or one of the booster signals B1-B3, one or both of the pull-up circuit 146U or the pull-down circuit 146D is configured to decouple the node SN from the corresponding power supply voltage node or the reference voltage node in response to the second logic level of the control signal CS3. In some embodiments, in operation, the control signal CS3 is configured to have a second logic level during a power-on sequence of the circuit 100, whereby the node SN is decoupled from each of the power supply voltage node and the reference voltage node during the power-on sequence.

[0062] In some embodiments, the booster circuit 140 including the delay stage 142, the suppression circuit 144 in some embodiments, and the boosting stage 146 is thereby configured to selectively couple the node SN to one of the reference voltage node or the supply voltage node in response to the control signal CS2 in operation, and to decouple the node SN from one of the reference voltage node or the supply voltage node in response to the booster signals B1 and B2 (if present), both of which are based on the control signal CS2.

[0063] Thus, booster circuit 140 can be included in a signal distribution circuit (e.g., circuit 100) in which a driver (e.g., driver 110) is configured to output control signals CS1 and CS2 at first ends of first and second signal lines (e.g., signal lines SL1 and SL2), and node SN is coupled to a second end of the first signal line and a buffer (e.g., buffer 130) is coupled to a second end of the second signal line. By including pull-down and pull-up circuits 146D and 146U configured to control node SN in response to control signal CS2, booster circuit 140 can improve the integrity of control signal CS2 at the second end of signal line SL2, thereby improving the ability of the buffer to drive the second end of signal line SL1 compared to an approach that does not include booster circuit 140.

[0064] In some embodiments, for example, including those embodiments configured as described above to further control pull-down circuit 146D and / or pull-up circuit 146U of node SN in response to control signal CS3, booster circuit 140 can avoid lockup of the circuit (e.g., circuit 100) during a power-on sequence and / or continuous operation mode by preventing booster circuit 140 from causing the buffer to contend with the driver for control of the corresponding signal line (e.g., signal line SL1).

[0065] In some embodiments, booster circuit 140 can be selectively activated in response to enable signals EN1 and EN2 (if present), whereby the above-described benefits are optionally included in the operation of a circuit (eg, circuit 100 ) including booster circuit 140 .

[0066] In some embodiments, the booster circuit 140 includes the following reference Figure 2A-Figure 6 One of the booster circuits 240A, 240B, 340, 540, or 640 discussed.

[0067] exist Figure 1B In the illustrated embodiment, the memory circuit 100M (also referred to as circuit 100M or static random access memory (SRAM) circuit 100M in some embodiments) can be used as described above with respect to Figure 1A The circuit 100 discussed herein includes a local control circuit 110M that can be used as a driver 110, a local input / output (LIO) circuit 120M that can be used as a load circuit 120, an inverter 130M that can be used as a buffer 130, a booster enabling source 150M that can be used as a booster enabling source 150, and a booster circuit 140, all of which are referred to above. Figure 1A A discussion was held.

[0068] The local control circuit 110M includes a pair of first inverters (not labeled) arranged in series, which are configured to receive the sense amplifier enable signal SAEN and output a control signal CS1 to the signal line SL1 in response to the enable signal SAEN and in phase with the enable signal SAEN (ignoring the inverter switching delay). The second inverter (not labeled) is configured to receive the enable signal SAEN and output a control signal CS2 to the signal line SL2 in response to the enable signal SAEN and complementary to the enable signal SAEN (excluding the inverter switching delay).

[0069] Thus, the local control circuit 110M is configured to output the control signals CS1 and CS2 as complementary signals based on the enable signal SAEN in operation, and the local control circuit 110M and the inverter 130M are thereby configured to output the control signal CS1 and the signal BS in phase with each other.

[0070] In some embodiments, the second inverter is configured to output each of the control signals CS2 and CS3 to the corresponding signal line SL2 or SL3 in response to and complementary to the enable signal SAEN in operation.

[0071] In some embodiments, the local control circuit 110M includes a third inverter (unlabeled) that is configured to output a control signal CS3 to the signal line SL3 in response to an enable signal (unlabeled) other than the enable signal SAEN in operation, such that the control signal CS3 includes a transition that is synchronized with a transition of the control signal CS1, as discussed above with respect to the circuit 100.

[0072] In some embodiments, control signal CS3 corresponds to a precharge enable signal corresponding to circuit 100M configured to precharge one or more bit lines of a group of memory cells to a target voltage level (e.g., a power supply voltage level) as part of a read operation. In some embodiments, local control circuit 110M is configured to output control signals CS1 and CS3 including pulses having the same polarity (e.g., each pulse having a low logic level).

[0073] In some embodiments, local control circuit 110M includes an output terminal coupled to signal line SL1 located in a first metal layer of the IC, an output terminal coupled to signal line SL2 located in a third metal layer overlying the first metal layer of the IC, and in some embodiments, an output terminal coupled to signal line SL3 located in the third metal layer.

[0074] In some embodiments, circuit 100M is some or all of a memory macro (e.g., an SRAM macro including a global control circuit (not shown)), wherein local control circuit 110M is an instance LCTRL of multiple local control circuits (LCTRL), each instance corresponding to one or more banks or arrays of memory cells (e.g., SRAM cells (not shown)).

[0075] In some embodiments, the enable signal SAEN corresponds to a global sense amplifier enable signal of the memory circuit 100M, and the control signal CS1 is a local version of the enable signal SAEN. Each LIO circuit corresponds to one or more rows or columns of memory cells and includes at least one sense amplifier (not shown) configured to detect a voltage or current level output from the memory cell of the corresponding row or column in response to a combination of the control signal CS1 and the signal BS received from the signal line SL1 during a read operation. In some embodiments, the circuit 100M is configured to perform a read operation synchronized with a pulse of the control signal CS1 (e.g., within a time period corresponding to a pulse width of the control signal CS1).

[0076] The booster enabling source 150M includes a pair of inverters (not labeled) configured to receive the signal EMS in operation and output an enable signal EN1 as a buffered version of the signal EMS and, in some embodiments, output an enable signal EN2 as a buffered and inverted version of the signal EM.

[0077] As described above, signal EMS is a global enable signal of circuit 100M, which is configured to have a low logic level corresponding to activating booster circuit 140 and a high logic level corresponding to deactivating booster circuit 140. In some embodiments, circuit 100M is configured to generate control signals CS1 and CS2 having a first pulse width corresponding to signal EMS having a logic level corresponding to activating booster circuit 140, and to generate control signals CS2 and CS3 having a second pulse width greater than the first pulse width, the second pulse width having signal EMS when deactivating booster circuit 140. In some embodiments, signal EMS is received from a source external to circuit 100M.

[0078] In some embodiments, signal EMS has a low or high logic level based on, for example, an additional margin adjustment (EMA) signal received from an EMA pin. In some embodiments, signal EMS has a low or high logic level based on a configuration of circuit 100M, such as a plurality of memory cells, columns, banks, etc. In some embodiments, signal EMS is referred to as a chicken bit.

[0079] Through the above configuration, circuit 100M including booster circuit 140 as an embodiment of a memory circuit can achieve the benefits described above with respect to circuit 100, wherein control signals CS1, CS2, and CS3 (if present) are generated as part of a read operation of circuit 100M. By including booster circuit 140 configured to perform the above operations by utilizing signals that would otherwise be used in a read operation, circuit 100M can achieve these benefits with little or no impact on the overall area occupied by circuit 100M.

[0080] Figure 2A and Figure 2B 1 is a schematic diagram of respective signal distribution circuits 200A and 200B according to some embodiments. Each of the signal distribution circuits 200A and 200B (also referred to as circuits 200A and 200A in some embodiments) can be used as circuit 100 or 100M and includes a driver 110, a load circuit 120, a buffer 130, and a booster enabling source 150, all of which are referenced above. Figure 1A and Figure 1B A discussion was held.

[0081] Circuit 200A also includes booster circuit 240A, which includes delay stage 242A, suppression circuit 244 and boost stage 246, which can be used as described above with respect to Figure 1A and Figure 1B The booster circuit 140 includes the delay stage 142, the suppression circuit 144, and the boosting stage 146 discussed above. The circuit 200B also includes a booster circuit 240B, which includes a delay stage 242B, a suppression circuit 244, and a boosting stage 246, which can be used as a booster circuit including the delay stage 242B, the suppression circuit 244, and the boosting stage 246 discussed above. Figure 1A and Figure 1B The booster circuit 140 of the discussed delay stage 142, suppression circuit 144 and boosting stage 146.

[0082] like Figure 2A As shown, the delay stage 242A includes an inverter IN1 and NAND gates ND1 and ND2. Figure 2B As shown, the delay stage 242B includes an inverter IN2 and NAND gates ND1 and ND2. Each of the inverters IN1 and IN2 includes an input terminal coupled to the node SN and configured to receive the control signal CS2 from the second end of the signal line SL2.

[0083] The inverter IN1 of the delay stage 242A includes a logic gate configured to output a signal DS complementary to the control signal CS2 received from the second end of the signal line SL2 in operation. The inverter IN2 of the delay stage 242B (or one of the delay stages 542 or 642 discussed below) includes a Schmitt trigger configured to output a signal DS complementary to the control signal CS2 received from the second end of the signal line SL2 in operation.

[0084] By including a Schmitt trigger, inverter IN2 is configured to output a signal DS with improved timing and reduced process voltage temperature (PVT) dependence compared to inverter IN1, but requires a larger circuit area to implement more components and, in some embodiments, a larger feature size to address yield challenges.

[0085] In each of the delay stages 242A and 242B, the NAND gate ND1 includes an input terminal configured to receive an enable signal EN1 from the booster enabling source 150 and an input terminal coupled to an output terminal of a corresponding one of the inverters IN1 or IN2, and is thereby configured to output a booster signal B2 at an output terminal in response to the enable signal EN1 and the signal DS in operation and thereby in response to the control signal CS2.

[0086] In each of the delay stages 242A and 242B, the NAND gate ND2 includes an input terminal coupled to the output terminal of the NAND gate ND1 and thereby configured to receive the booster signal B2, and an input terminal configured to receive the enable signal EN1 from the booster enabling source 150, thereby being configured to, in operation, output the booster signal B1 at the output terminal in response to the enable signal EN1 and the booster signal B2.

[0087] The suppression circuit 244 includes a NOR (NOR) gate NR1, which includes an input terminal coupled to the output terminal of the NAND gate ND1, thereby being configured to receive the booster signal B2, and the NOR gate NR1 also includes an input terminal configured to receive the control signal CS3 from the second end of the signal line SL3, and is thereby configured to output the booster signal B3 at the output terminal in response to the booster signal B2 and the control signal CS3.

[0088] like Figure 2A and Figure 2BAs shown, the boost stage 246 includes a pull-up circuit 246U and a pull-down circuit 246D each coupled to a node SN. The pull-up circuit 246U includes a PMOS transistor P1 connected between the node SN and the power supply voltage node VDD, and a NAND gate ND3, the NAND gate ND3 includes an output terminal coupled to the gate of the transistor P1, an input terminal coupled to the output terminal of the NOR gate NR1, and an input terminal coupled to the node SN. The pull-down circuit 246D includes a NOR gate NR2 and an NMOS transistor N1 coupled between the node SN and the reference voltage node VSS, the NOR gate NR2 includes an output terminal coupled to the gate of the transistor N1, an input terminal coupled to the output terminal of the NAND gate ND2, and an input terminal coupled to the node SN.

[0089] The NAND gate ND3 of the pull-up circuit 246U is thus configured to, in operation, output a boost signal PB to the gate of the transistor P1 in response to the boost signal B3 received from the NOR gate NR1 and the control signal CS2 received from the node SN, and the transistor P1 is thus configured to selectively couple the node SN to and decouple the node SN from the power supply voltage node VDD in response to the boost signal PB.

[0090] The NOR gate NR2 of the pull-down circuit 246D is thereby configured to output a boost signal NB to the gate of the transistor N1 in response to the boost signal B1 received from the NAND gate ND2 and the control signal CS2 received from the node SN, and the transistor N1 is thereby configured to selectively couple the node SN to and decouple it from the reference voltage node VSS in response to the boost signal NB.

[0091] exist Figure 2A and Figure 2B In the illustrated embodiment, the driver 100 is configured to output control signals CS1-CS3 in operation, the control signals CS1-CS3 include tail pulse edges that are synchronized with each other, the control signal CS2 pulse includes a high logic level, and the control signal CS3 pulse includes a low logic level. In various embodiments, the control signal CS1 pulse includes a low logic level and the buffer 130 includes an inverting logic, or the control signal CS1 pulse includes a high logic level and the buffer 130 includes a non-inverting logic.

[0092] Based on the above discussion regarding circuits 100 and 100M and booster circuit 140, each of booster circuits 240A and 240B is thereby configured to receive control signal CS2 at delay stage 242A or 242B and booster stage 246, control signal CS3 at suppression circuit 244, and enable signal EN1 at delay stage 242A or 242B in operation, and to control coupling and decoupling of node SN with power supply voltage node VDD using pull-up circuit 246U, and to control coupling and decoupling of node SN with reference voltage node VSS using pull-down circuit 246D.

[0093] In some embodiments, each of the booster circuits 240A and 240B included in the respective circuits 200A or 200B is thus configured to achieve the benefits discussed above with respect to circuits 100 and 100M and booster circuit 140 .

[0094] Figure 3 is a schematic diagram of a signal distribution circuit 300 according to some embodiments. Signal distribution circuit 300 (also referred to as circuit 300 in some embodiments) may be used as circuit 100 or 100M and includes driver 110, load circuit 120, buffer 130, and booster enabling source 150, all of which are referenced above. Figure 1A and Figure 1B A discussion was held.

[0095] The circuit 300 also includes a booster circuit 340 that can be used as the booster circuit 140, including the booster circuit 340 described above with respect to Figure 2A and Figure 2B The delay stage 242A discussed above and can be used as Figure 1A and Figure 1B In some embodiments, the booster circuit 340 includes a booster circuit as described above in conjunction with the booster circuit 146. Figure 2A and Figure 2B The delay stage 242B is described instead of the delay stage 242A.

[0096] like Figure 3 As shown, the boost stage 346 includes a pull-up circuit 346U and a pull-down circuit 346D each connected to the node SN. The pull-up circuit 346U includes a transistor P1 and a NAND gate ND3, and the pull-down circuit 346D includes a transistor N1 and a NOR gate NR2. The configurations of the transistor P1 and the NAND gate ND3, and the transistor N1 and the NOR gate NR2 are the same as those described above. Figure 1A and Figure 1B described.

[0097] In various embodiments, the pull-up circuit 346U also includes a PMOS transistor P2, which is coupled in series with the transistor P1 between the node SN and the power supply voltage node VDD, and includes a gate configured to receive the control signal CS3, or the pull-down circuit 346D also includes an NMOS transistor N2, which is coupled in series with the transistor N1 between the node SN and the reference voltage node VSS, and includes a gate configured to receive the control signal CS3.

[0098] exist Figure 3 In the illustrated embodiment, transistor P2 (if present) is located between transistor P1 and a power supply voltage node VDD, and transistor N2 (if present) is located between transistor N1 and a reference voltage node VSS. In some embodiments, one of transistors P2 or N2 is located between node SN and a corresponding one of transistors P1 or N1.

[0099] The NAND gate ND3 and transistor P1 of the pull-up circuit 346U are thus configured to operate as described above with respect to Figure 2A and Figure 2B As described above, the node SN is selectively coupled to and decoupled from the power supply voltage node VDD, and the transistor P2 is thereby configured to further couple the node SN to and decouple the power supply voltage node VSS in response to the control signal CS3.

[0100] NOR gate NR2 and transistor N1 are thus configured to operate as described above with respect to Figure 2A and 2B As described above, the node SN is selectively coupled and decoupled from the reference voltage node VSS, and the transistor N2 is thereby configured to further couple and decouple the node SN from the reference voltage node VSS in response to the control signal CS3.

[0101] exist Figure 3 In the illustrated embodiment, the driver 110 is configured to output control signals CS1-CS3 including tail pulse edges that are synchronized with each other, control signal CS2 pulses including high logic levels, and control signal CS3 pulses including low logic levels corresponding to the pull-up circuit 346U including transistor P2 or high logic levels corresponding to the pull-down circuit 346D including transistor N2. In various embodiments, the control signal CS1 pulse includes a low logic level and the buffer 130 includes inverting logic, or the control signal CS1 pulse includes a high logic level and the buffer 130 includes non-inverting logic.

[0102] Based on the above discussion regarding circuits 100 and 100M and booster circuit 140, booster circuit 340 is thereby configured to receive control signal CS2 at delay stage 242A or 242B and boosting stage 346, receive control signal CS3 at pull-up circuit 346U or pull-down circuit 346D of boosting stage 346, and receive enable signal EN1 at delay stage 242A or 242B in operation, and in response to control signals CS2 and CS3, use pull-up circuit 346U to control coupling and decoupling of node SN with power supply voltage node VDD, and use pull-down circuit 346D to control coupling and decoupling of node SN with reference voltage node VSS.

[0103] In some embodiments, booster circuit 340 included in circuit 300 is thus configured to achieve the benefits discussed above with respect to circuits 100 and 100M and booster circuit 140 .

[0104] The booster circuit 340 is further configured to decouple the node SN from the corresponding one of the power supply voltage node VDD or the reference voltage node VSS before the time when the corresponding one of the transistors P1 or N1 decouples the node SN based on the boosting stage 346 including one of the transistors P2 or N2, wherein the gate of the transistor P2 or N2 is configured to receive the control signal CS3 without delay by the logic gate (e.g., the NAND gate ND3 or the NOR gate NR2), and the transistor P1 or N1 decouples the node SN when the pulse width of the control signals CS1 and CS2 is less than the delay introduced by the logic gate of the delay stage 242A or 242B and the boosting stage 346. The booster circuit 340 is thereby configured to avoid signal line contention between the driver and the buffer (e.g., the driver 110 and the buffer 130 at the first and second ends of the signal line SL1) for a shorter control signal pulse width, the buffer being controlled by the node SN voltage.

[0105] Figure 4A Depicted are operating parameters of a signal distribution circuit (eg, one of circuits 100, 100M, 200A, 200B, or 300 described above) according to some embodiments.

[0106] Figure 4A A non-limiting example of control signals CS2 and CS3 and boost signal PB as described above are included, plotted over time t. Figure 4A In the illustrated embodiment, the control signal CS2 corresponds to an enable signal, such as a sense amplifier enable signal (same as or complementary to the control signal CS1, Figure 4A(not shown), the enable signal includes a pulse with a high logic level, and the control signal CS3 corresponds to a signal including a pulse with a low logic level (e.g., a precharge signal). The leading edge (first transition) of the control signal CS3 pulse precedes the leading edge (first transition) of the control signal CS2 pulse, and the trailing edges (second transitions) of the control signals CS2 and CS3 pulses are synchronized.

[0107] Signal CS3A represents the control signal CS3 output from the driver 110 to the first end of the signal line SL3, signal CS2A represents the control signal CS2 output from the driver 100 to the first end of the signal line SL2, signal CS3B represents the control signal CS3 propagated to the second end of the signal line SL3, and signal CS2B represents the control signal CS2 propagated to the second end of the signal line SL2 and the node SN.

[0108] Time t1 represents the leading edge of the signal CS2 pulse, and time t2 represents the leading edge of the boosted signal PB pulse, wherein the leading edge of the boosted signal PB pulse is generated in response to the leading edge of the signal CSB2 pulse according to the configuration of the above-mentioned (activated) booster circuit 240A, 240B or 340.

[0109] Time t3 represents the trailing edge of the pulses of control signals CS2A and CS3A, time t4 represents the trailing edge of the pulses of control signals CS2B and CS3B, and the difference between times t3 and t4 corresponds to the propagation delay of each of the signal lines SL2 and SL3.

[0110] Time t5 represents the time at which the booster circuits 240A, 240B and 340 are configured in response to the booster signal B2 ( Figure 4A Between time t2 and t5, the boost signal PB with a low logic level turns on the transistor P1, thereby coupling the node SN to the power supply voltage node VDD. After time t5, the boost signal PB with a high logic level turns off the transistor P1.

[0111] In an embodiment including booster circuits 240A and 240B, transistor P1 is capable of coupling node SN to and decoupling node SN from power supply voltage node VDD alone, and the pulse width of the control signal CS2 pulse is long enough so that the boosted signal PB has a low logic level the entire time, which corresponds to the control signal CS1 having the same logic level as the signal BS output from buffer 130 in response to the boosted signal PB.

[0112] In an embodiment of the booster circuit 340 including the boost stage 346, the pull-up circuit 346U includes a transistor P2 configured to receive the control signal CS3 from the second end of the signal line SL3, and based on the trailing edge of the pulse of the control signal CS3B, the transistor P2 is turned off at a time t4 before the time t5, thereby decoupling the node SN from the power supply voltage node VDD at a time when the node SN would otherwise be decoupled from the power supply voltage node VDD (e.g., in an embodiment including the circuit 200A or 200B, as described above with respect to Figure 3 The node SN is decoupled from the power supply voltage node VDD before the above step.

[0113] Figure 4B Depicted are operating parameters of a signal distribution circuit (eg, one of circuits 100, 100M, 200A, 200B, or 300 described above, or circuits 500 or 600 discussed below) according to some embodiments.

[0114] Figure 4B Non-limiting examples of control signals CS1 and CS2 and boost signals PB and NB discussed above and below are included, plotted against time t. Figure 4B In the illustrated embodiment, control signals CS1 and CS2 correspond to complementary enable signals, such as sense amplifier enable signals.

[0115] Signals CS1A and CS2BA represent control signals CS1 and CS2 (received at node SN) corresponding to enable signals EN1 and EN2 (if present), EN2 having a logic level corresponding to the corresponding booster circuit 140, 240A, 240B, 340, 540, or 640 being activated, and signals CS1D and CS2BD represent control signals CS1 and CS2 corresponding to enable signals EN1 (and EN2, if present), having a logic level corresponding to the corresponding control circuit 140, 240A, 240B, 340, 540, or 640 being deactivated. Boost signals PB and NB correspond to an activated state.

[0116] The time period between time t6 and t7 corresponds to the pull-up of node SN (corresponding to the positive transition of signals CS1A and CS1D), during which time period, the pulses included in the boost signal PB include a low logic level, the boost signal NB maintains a low logic level, and the first arrow indicates the difference between the control signal CS2BA in the activated state and the control signal CS2BD in the deactivated state. Compared with the control signal CS2BD, the control signal CS2BA includes an increased slew rate and pulse amplitude.

[0117] The time period between time t8 and t9 corresponds to the pull-down boost of node SN (corresponding to the negative transition of signals CS1A and CS1D), during which time period the boost signal NB includes a pulse including a high logic level, the boost signal PB maintains a high logic level, and the second arrow indicates the difference between the control signal CS2BA in the activated state and the control signal CS2BD in the deactivated state. The control signal CS2BA includes an increased slew rate compared to the control signal CS2BD.

[0118] Figure 5 is a schematic diagram of a signal distribution circuit 500 according to some embodiments. The signal distribution circuit 500 (also referred to as circuit 500 in some embodiments) can be used as the circuit 100 or 100M and includes the circuits referenced above. Figure 1A and Figure 1B A driver 110, a load circuit 120, a buffer 130, and a booster enabling source 150 are discussed.

[0119] Circuit 500 also includes a booster circuit 540 that can be used as booster circuit 140, including a delay stage 542 that can be used as delay stage 142 and a boosting stage 546 that can be used as boosting stage 146, both of which are described above with reference to Figure 1A and Figure 1B A discussion was held.

[0120] like Figure 5 As shown, the delay stage 542 includes the above Figure 2A-Figure 3 Inverter IN1 discussed above and inverters IN4 and IN5 arranged in series. Inverter IN5 includes an output terminal configured to output booster signal B1. In some embodiments, delay stage 542 includes the above-mentioned Figure 2A and Figure 2B The inverter IN2 is discussed, not the inverter IN1.

[0121] The boost stage 546 includes a pull-up circuit 546U and a pull-down circuit 546D each coupled to the node SN. The pull-up circuit 545U includes a transistor P1 coupled to the output terminal of the NAND gate ND4, and the pull-down circuit 546D includes a transistor N1 coupled to the output terminal of the NOR gate NR3.

[0122] The NAND gate ND4 of the pull-up circuit 546U includes an input terminal configured to receive the enable signal EN1, an input terminal coupled to the output terminal of the inverter IN5 and thus configured to receive the booster signal B1, and an input terminal configured to receive the control signal CS3. The NAND gate ND4 is thus configured to output the boost signal PB to the gate of the transistor P1 in response to the enable signal EN1, the booster signal B1 and the control signal CS3 in operation, and the transistor P1 is thus configured to selectively couple the node SN to the power supply voltage node VDD and decouple it from the power supply voltage node VDD in response to the boost signal PB.

[0123] The NOR gate NR3 of the pull-down circuit 546D includes an input terminal coupled to the output terminal of the inverter IN5 and configured to receive the booster signal B1, an input terminal configured to receive the enable signal EN2, and an input terminal coupled to the node SN. The NOR gate NR3 is configured to output a boost signal NB to the gate of the transistor N1 in response to the booster signal B1, the enable signal EN2, and the control signal CS2 received from the node SN, and the transistor N1 is configured to selectively couple the node SN to the reference voltage node VSS and decouple it from the reference voltage node VSA in response to the boost signal NB.

[0124] exist Figure 5 In the illustrated embodiment, the driver 110 is configured to output control signals CS1-CS3 including tail pulse edges that are synchronized with each other, and each of the control signal CS2 pulse and the control signal CS3 pulse includes a high logic level (e.g., is the same). In various embodiments, the control signal CS1 pulse includes a low logic level and the buffer 130 includes an inverting logic, or the control signal CS1 pulse includes a high logic level and the buffer 130 includes a non-inverting logic.

[0125] Based on the above discussion regarding circuits 100 and 100M and booster circuit 140, booster circuit 540 is thus configured to, in operation, receive control signal CS2 at delay stage 542 and boosting stage 546, receive control signal CS3 at pull-up circuit 546U of boosting stage 546, receive enable signal EN1 at pull-up circuit 546U of boosting stage 546, and receive enable signal EN2 at pull-down circuit 546D of boosting stage 546 in response to control signals CS2 and CS3 and enable signals NS1 and EN2, and use pull-up circuit 546U to control coupling and decoupling of node SN with power supply voltage node VDD, and use pull-down circuit 546D to control coupling and decoupling of node SN with reference voltage node VSS.

[0126] In some embodiments, booster circuit 540 included in circuit 500 is thus configured to achieve the benefits discussed above with respect to circuits 100 and 100M and booster circuit 140. For example, compared to those embodiments including booster circuits 240A, 240B, or 340 described above, in which control signals CS2 and CS3 each do not include a high logic level (e.g., are not the same), booster circuit 540 uses fewer logic gate components, but requires a dedicated signal line SL3 that is not used in circuit 500.

[0127] Figure 6 is a schematic diagram of a signal distribution circuit 600 according to some embodiments. The signal distribution circuit 600 (also referred to as circuit 600 in some embodiments) can be used as the circuit 100 or 100M and includes all of the above referenced Figure 1A and Figure 1B A driver 110, a load circuit 120, a buffer 130, and a booster enabling source 150 are discussed.

[0128] Circuit 600 also includes a booster circuit 640 that can be used as booster circuit 140, including a delay stage 642 that can be used as delay stage 142 and a boosting stage 646 that can be used as boosting stage 146, both of which are described above with reference to Figure 1A and Figure 1B A discussion was held.

[0129] like Figure 6 As shown, the delay stage 642 includes the above Figure 2A-Figure 3 Inverter IN1 discussed above and inverter IN4 arranged in series with inverter IN1. Inverter IN4 includes an output terminal configured to output booster signal B1. In some embodiments, delay stage 642 includes the above-mentioned Figure 2A and Figure 2B The inverter IN2 is discussed, not the inverter IN1.

[0130] The boost stage 646 includes a pull-up circuit 646U and a pull-down circuit 646D, each coupled to a node SN. The pull-up circuit 640U and the pull-down circuit 646D together include a tri-state inverter IN6, which includes transistors P1 and N1 and a transistor P2 and a transistor N3 that are not shown in the figure for clarity. Figure 6 The gate of transistor P1 of pull-up circuit 646U is coupled to the output terminal of NAND gate ND5, and the gate of transistor N1 of pull-down circuit 646D is coupled to the output terminal of NOR gate NR4.

[0131] The NAND gate ND5 of the pull-up circuit 646U includes an input terminal configured to receive an enable signal EN1 and an input terminal coupled to the node SN and thereby configured to receive a control signal CS2. The NAND gate ND5 is thereby configured to output a boost signal PB to the gate of the transistor P1 in response to the enable signal EN1 and the control signal CS2 in operation. The additional PMOS transistor of the tri-state inverter IN6 includes a gate coupled to the output terminal of the inverter IN4, thereby being configured to receive the booster signal B1. Therefore, the tri-state inverter IN6 is configured to selectively couple the node SN to the power supply voltage node VDD and decouple it from the power supply voltage node VDD in operation through the transistor P1 responsive to the boost signal PB and the additional PMOS transistor responsive to the boost voltage signal B1.

[0132] The NOR gate NR4 of the pull-down circuit 646D includes an input terminal coupled to the node SN and configured to receive the control signal CS2 and an input terminal configured to receive the enable signal EN2. The NOR gate NR4 is thus configured to output the boost signal PB to the gate of the transistor N1 in response to the control signal CS2 and the enable signal EN2. The additional NMOS transistor of the tri-state inverter IN6 includes a gate coupled to the output terminal of the inverter IN4, thereby being configured to receive the booster signal B1. Therefore, the tri-state inverter IN6 is configured to selectively couple the node SN to the reference voltage node VSS and decouple it from the reference voltage node VS in operation through the transistor N1 in response to the boost signal NB and the additional NMOS transistor in response to the booster signal B1.

[0133] In various embodiments, one or both of the pull-up circuits 646U further include PMOS transistors P3 and P4 coupled in series between the output terminal of the NAND gate ND5 and the power supply voltage node VDD, with the gate of each of the transistors P3 and P4 coupled to the output terminal of the NAND gate ND5, or the pull-down circuit 646D further includes NMOS transistors N3 and N4 coupled in series between the node SN and the reference voltage node VSS, with the gate of each of the transistors N3 and N4 coupled to the node SN.

[0134] Transistors P3 and P4 and / or N3 and N4 are configured as, for example, weak transistors or slow transistors, so that in a power-on operation, in an embodiment including transistors P3 and P4, the voltage change of the boost signal PB is thereby slowed down, and in an embodiment including transistors N3 and N4, the voltage change of the node SN is thereby slowed down. Similarly, due to the presence of transistors P3 and P4 and / or N3 and N4, the possibility of a power-on lockout condition is thereby reduced.

[0135] exist Figure 6In the illustrated embodiment, the driver 110 is configured to output control signals CS1 and CS2 including tail pulse edges that are synchronized with each other, and the control signal CS2 pulse includes a high logic level. In various embodiments, the control signal CS1 pulse includes a low logic level and the buffer 130 includes an inverting logic, or the control signal CS1 pulse includes a high logic level and the buffer 130 includes a non-inverting logic.

[0136] Based on the above discussion regarding circuits 100 and 100M and booster circuit 140, booster circuit 640 is thus configured to, in operation, respond to control signal CS2 and enable signals EN1 and EN2, receive control signal CS2 at delay stage 642 and boosting stage 646, receive enable signal EN1 at pull-up circuit 646U of boosting stage 646, and receive enable signal EN2 at pull-down circuit 646D of boosting stage 646, and use pull-up circuit 644U to control coupling and decoupling of node SN with power supply voltage node VDD, and use pull-down circuit 646D to control coupling and decoupling of node SN with reference voltage node VSS.

[0137] In some embodiments, booster circuit 640 included in circuit 600 is thus configured to achieve the benefits discussed above with respect to circuits 100 and 100M and booster circuit 140. Compared to embodiments that do not include transistors P3 and P4 and / or N3 and N4 (e.g., embodiments that include booster circuits 240A, 240B, 340, or 540 described above), booster circuit 640 requires fewer logic gate components and does not rely on receiving control signal CS3, but has reduced yield based on using transistors P3 and P4 and / or N3 and N4 instead of logic gates to avoid power-on latch-up conditions.

[0138] Figure 7 700 is a flow chart of a method 700 of operating a booster circuit according to some embodiments. The method 700 (also referred to as a method 700 of operating a circuit in some embodiments) may be used in conjunction with the method described above with respect to Figure 1A-Figure 6 The booster circuit 140, 240A, 240B, 340, 540 or 640 is discussed.

[0139] Figure 7 The order in which the operations of method 700 are described is for illustration only; the operations of method 700 may be performed in the same order as described in Figure 7 In some embodiments, Figure 7 Perform the following operations before, between, during, and / or after the operations shown: Figure 7 In some embodiments, the operations of method 700 are a subset of a method of operating a signal distribution circuit (eg, circuits 100, 100M, 200A, 200B, 300, 500, or 600 described above).

[0140] At operation 702, in some embodiments, two or more control signals are output to first ends of corresponding signal lines. In some embodiments, outputting the two or more control signals to first ends of corresponding signal lines includes outputting control signals CS1, CS2, and in some embodiments, CS3 from driver 110 or local control circuit 110M to signal lines SL1, SL2, and in some embodiments, SL3, as described above with respect to Figure 1A-Figure 6 described.

[0141] At operation 704, a first control signal of the two or more control signals is received at a signal node of the booster circuit. In some embodiments, receiving the first control signal of the two or more control signals at a signal node of the booster circuit includes receiving a control signal CS2 at a signal node SN of the booster circuit 140, 240A, 240B, 340, 540, or 640, as described above with respect to Figure 1A-Figure 6 described.

[0142] In some embodiments, receiving a first control signal of the two or more control signals at a signal node of the booster circuit includes receiving a second control signal of the two or more control signals at the booster circuit. In some embodiments, receiving the second control signal at the control circuit includes receiving a control signal CS3 at the booster circuit 140, 240A, 240B, 340, 540, or 640, as described above with respect to Figure 1A-Figure 6 described.

[0143] In some embodiments, receiving a first control signal of the two or more control signals at a signal node of the booster circuit includes receiving one or more enable signals at the booster circuit. In some embodiments, receiving one or more enable signals at the control circuit includes receiving an enable signal EN1 at the booster circuit 140, 240A, 240B, 340, 540, or 640, and in some embodiments, EN2, as described above with respect to Figure 1A-Figure 6 described.

[0144] At operation 706, in response to the first control signal, a booster signal is output from a delay stage of the booster circuit. In some embodiments, outputting the booster signal from the delay stage includes outputting the booster signal from the delay stage as one of two booster signals. In some embodiments, as described above with respect to Figure 1A-Figure 6 As described, outputting the booster signal from the delay stage includes outputting one or both of the booster signals B1 or B2 from the delay stage 142 , 242A, 242B, 542 , or 642 .

[0145] In some embodiments, outputting the booster signal from the delay stage includes receiving the booster signal and the second control signal at a suppressor circuit of the booster circuit, and outputting a third booster signal from the suppressor circuit. In some embodiments, receiving the booster signal and the second control signal at the suppressor circuit, and outputting the third booster signal from the suppressor circuit includes receiving the booster signal B2 and the control signal CS3 at the suppressor circuit 144 or 244, and outputting the booster signal B3 from the suppressor circuit 144 or 244, as described above with respect to Figure 1A-Figure 2B described.

[0146] In some embodiments, outputting the booster signal from the delay stage includes outputting a booster signal voltage transition delayed from a first control signal voltage transition. In some embodiments, outputting the booster signal voltage transition delayed from the first control signal voltage transition includes outputting one or more voltage transitions of the booster signal B1-B3 delayed from a voltage transition of the control signal CS2, as described above with respect to Figure 1A-Figure 6 described.

[0147] At operation 708, in response to the first control signal and the booster signal, the boost stage of the control circuit is used to selectively couple the signal node to each of the power supply voltage node and the reference voltage node. In some embodiments, in response to the first control signal and the booster signal, using the boost stage to selectively couple the signal node to each of the power supply voltage node and the reference voltage node includes using the boost stage 146, 246, 346, 546, or 646 to selectively couple the node SN to each of the power supply current node VDD and the reference current node VSS in response to one or more of the booster signals B1-B3 and the control signal CS2, as described above with respect to Figure 1A-Figure 6 discussed.

[0148] In some embodiments, selectively coupling the signal node to the power supply voltage node using the boost stage includes outputting a first boosted signal to a first PMOS transistor of the pull-up circuit to selectively couple the signal node to the power supply voltage node. In some embodiments, outputting the first boosted signal to the first PMOS transistor of the pull-up circuit to selectively couple the signal node to the power supply voltage node includes outputting a boosted signal PB to transistor P1 of the pull-up circuit 146U, 246U, 346U, 546U, or 646U to selectively couple the node SN to the power supply voltage node VDD, as described above with respect to Figure 1A-Figure 6 discussed.

[0149] In some embodiments, selectively coupling the signal node to the reference voltage node using the boost stage includes outputting a second boosted signal to the first NMOS transistor of the pull-down circuit to selectively couple the signal node to the reference voltage node. In some embodiments, outputting the second boosted signal to the first NMOS transistor of the pull-down circuit to selectively couple the signal node to the reference voltage node includes outputting a boosted signal NB to transistor N1 of the pull-down circuit 146D, 246D, 346D, 546D, or 646D to selectively couple the node SN to the reference voltage node VSS, as described above with respect to Figure 1A-Figure 6 described.

[0150] In some embodiments, in response to the first control signal and the booster signal, selectively coupling the signal node to each of the power supply voltage node and the reference voltage node using the boosting stage includes selectively decoupling the signal node from the power supply voltage node or the reference voltage node using the boosting stage in response to the first control signal and the booster signal. In some embodiments, selectively decoupling the signal node from each of the power supply voltage node and the reference voltage node using the boosting stage in response to the first control signal and the booster signal includes selectively decoupling the node SN from each of the power supply voltage node VDD and the reference voltage node VSS using the boosting stage 146, 246, 346, 546, or 646 in response to one or more of the booster signals B1-B3 and the control signal CS2, as described above with respect to Figure 1A-Figure 6 discussed.

[0151] In some embodiments, in response to the first control signal and the booster signal, selectively coupling the signal node to each of the power supply voltage node and the reference voltage node using the boost stage includes, in response to the second control signal, selectively decoupling the signal node from one of the power supply voltage node or the reference voltage node using the boost stage. In some embodiments, selectively decoupling the signal node from one of the power supply voltage node or the reference voltage node using the boost stage in response to the second control signal includes, in response to the control signal CS3, selectively decoupling the node SN from a respective one of the power supply voltage node VDD or the reference voltage node VSS using transistors P2 or N2 of the boost stage 346, as described above with respect to Figure 3 described.

[0152] In some embodiments, selectively coupling a signal node to each of a power supply voltage node and a reference voltage node using a boost stage includes coupling the signal node to one of the power supply voltage node or the reference voltage node in response to a first control signal voltage transition, and coupling the signal node to the other of the power supply voltage node or the reference voltage node in response to a booster signal voltage transition. In some embodiments, coupling the signal node to one of the power supply voltage node or the reference voltage node in response to a first control signal voltage transition and coupling the signal node to the other of the power supply voltage node or the reference voltage node in response to a booster signal voltage transition include coupling the signal node SN to one of the power supply voltage node VDD or the reference voltage node VSS in response to a control signal CS2 voltage transition, and coupling the signal node SN to one of the power supply voltage node VDD or the reference voltage node VSS in response to a voltage transition in one of the booster signals B1-B3, as described above with respect to Figure 1A-Figure 6 described.

[0153] In some embodiments, the signal node is coupled to the other of the supply voltage node or the reference voltage node using the boost stage in response to the voltage transition in the second control signal. In some embodiments, coupling the signal node to the other of the supply voltage node or the reference voltage node using the boost stage in response to the voltage transition in the second control signal includes coupling the node SN to the other of the supply voltage node VDD or the reference voltage node VSS using the boost stage 146, 246, 346, 546, or 646 in response to the voltage transition in the control signal CS3, as described above with respect to Figure 1A-Figure 6 described.

[0154] In some embodiments, selectively coupling the signal node to each of the supply voltage node and the reference voltage node is disabled in response to one or more enable signals. In some embodiments, selectively coupling the signal node to each of the supply voltage node and the reference voltage node is disabled in response to one or more enable signals, including selectively coupling the node SN to each of the supply voltage node VDD and the reference voltage node VSS in response to enable signal EN1 (and in some embodiments, EN2).

[0155] In some embodiments, selectively coupling the signal node to each of the power supply voltage node and the reference voltage node using the boost stage includes selectively coupling an input terminal of a buffer to each of the power supply voltage node and the reference voltage node using the boost stage, the buffer including an output terminal coupled to the second end of the second signal line. In some embodiments, selectively coupling an input terminal of the buffer to each of the power supply voltage node and the reference voltage node using the boost stage (the buffer including an output terminal coupled to the second end of the second signal line) includes selectively coupling an input terminal of the buffer 130 or 130M to each of the power supply voltage node VDD and the reference voltage node VSS using the boost stage 146, 246, 346, 546, or 646, the buffer 130 or 130M including an output terminal coupled to the second end of the signal line SL1.

[0156] By performing some or all of the operations of method 700, the booster circuit controls coupling of a node to a supply voltage node and a reference voltage node in response to one or more received control signals, thereby achieving the benefits discussed above with respect to booster circuits 140, 240A, 240B, 340, 540, and 640, and in some embodiments, with respect to circuits 100, 100M, 200A, 200B, 300, 500, and 600.

[0157] In some embodiments, a signal distribution circuit includes a signal node configured to receive a first control signal, a delay stage coupled to the signal node and configured to output a first booster signal in response to the first control signal, and a booster stage coupled to the signal node and the delay stage, wherein the booster stage includes a pull-up circuit and a pull-down circuit, the pull-up circuit includes a first transistor configured to couple the signal node to a power supply voltage node in response to the first booster signal, and the pull-down circuit includes a second transistor configured to couple the signal node to a reference voltage node in response to the first booster signal. In some embodiments, the delay stage includes a first inverter including an input terminal coupled to a signal node, a first NAND gate including a first input terminal configured to receive an enable signal, a second input terminal coupled to an output terminal of the first inverter, and an output terminal configured to output a first booster signal, the second NAND gate will include a first input terminal coupled to the output terminal of the first NAND gate, a second output terminal configured to receive the enable signal, and an output terminal, the pull-up circuit includes a third NAND gate, the third NAND gate will include a first output terminal configured to receive a second booster signal based on the first booster signal, a second input terminal coupled to the signal node, and an output terminal coupled to the gate of the first transistor, and the pull-down circuit includes a first NOR gate, the first NOR gate includes a first input terminal coupled to the output terminal of the second NAND gate, a second input terminal coupled to the signal node, and an output terminal coupled to the gate of the second transistor. In some embodiments, the circuit includes a second NOR gate, the second NOR gate includes a first input terminal coupled to the output terminal of the first NAND gate, a second input terminal configured to receive a second control signal, and an output terminal coupled to the first input terminal of the third NAND gate. In some embodiments, the first inverter comprises a Schmitt trigger. In some embodiments, the circuit comprises a second inverter comprising an input terminal coupled to an output terminal of the first NAND gate and an output terminal coupled to a first input terminal of a third NAND gate, wherein the boost stage comprises a third transistor connected in series with the first transistor or in series with the second transistor, and the third transistor comprises a gate configured to receive a second control signal.In some embodiments, the delay stage includes first to third inverters coupled in series between the signal node and the boost stage, the pull-up circuit includes a NAND gate, the NAND gate includes a first input terminal configured to receive a first enable signal, a second input terminal coupled to an output terminal of the third inverter, a third input terminal configured to receive a second control signal, and an output terminal coupled to a gate of the first transistor, and the pull-down circuit includes a NOR gate, the NOR gate includes a first input terminal coupled to the output terminal of the third inverter, a second input terminal configured to receive a second enable signal, a third output terminal coupled to the signal node, and an output terminal coupled to a gate of the second transistor. In some embodiments, the delay stage includes a first inverter and a second inverter coupled in series between the signal node and the boost stage, the boost stage includes a NAND gate, a NOR gate, a tri-state inverter, the NAND gate includes a first input terminal configured to receive a first enable signal, a second input terminal coupled to the signal node, and an output terminal, the NOR gate includes a first input terminal coupled to the signal node, a second input terminal configured to receive a second enable signal, and an output terminal, the tri-state inverter includes a first transistor and a second transistor, an input terminal coupled to the output terminal of the second inverter, a first enable terminal coupled to the output terminal of the NAND gate, a second enable terminal coupled to the output terminal of the NOR gate, an output terminal coupled to the signal node, and one or both of the following: a third transistor and a fourth transistor coupled between the output terminal of the NAND gate and the power supply voltage node; or a fifth transistor and a sixth transistor coupled between the signal node and the reference voltage node. In some embodiments, the signal node is coupled to a sense amplifier enable (SAE) distribution path of a memory circuit, and the first control signal includes a sense amplifier enable signal.

[0158] In some embodiments, a signal distribution circuit includes: a first signal line and a second signal line; a driver coupled to first ends of the first signal line and the second signal line and configured to output corresponding first control signals and second control signals to the first signal line and the second signal line; a booster circuit coupled to the second end of the first signal line; and a buffer coupled between the second end of the second signal line and the booster circuit, wherein the booster circuit includes a delay stage and a booster stage, the delay stage is configured to output a first booster signal in response to the first control signal received at the second end of the first signal line, the booster stage is coupled to the delay stage, wherein the booster stage includes: a pull-up circuit configured to couple an input terminal of the buffer to a power supply voltage node in response to the first booster signal, and a pull-down circuit configured to couple the input terminal of the buffer to a reference voltage node in response to the first booster signal. In some embodiments, the signal distribution circuit includes a third signal line coupled between the driver and the booster circuit, wherein the driver is configured to output a third control signal to the third signal line, and the pull-up circuit is configured to further couple the input terminal of the buffer to the power supply voltage node in response to the third control signal. In some embodiments, the driver is configured to output the third control signal including a pulse edge synchronized with a pulse edge of the first control signal, and the booster circuit is configured to decouple the input terminal of the buffer from the power supply voltage node in response to the pulse edge of the third control signal. In some embodiments, the booster circuit is configured to further respond to an enable signal so that the booster stage couples the input terminal of the buffer to the power supply voltage node and the reference voltage node. In some embodiments, the pull-up circuit includes a NAND gate including an input terminal coupled to the input terminal of the buffer, and the pull-down circuit includes a NOR gate including an input terminal coupled to the input terminal of the buffer. In some embodiments, the buffer includes an inverter. In some embodiments, the circuit further includes a plurality of load circuits coupled to a second signal line between the driver and the output terminal of the buffer, wherein each of the plurality of load circuits is configured to receive the second control signal. In some embodiments, the driver includes a control circuit of a static random access memory (SRAM) circuit, the plurality of load circuits include a plurality of sense amplifier circuits, and the second control signal includes a sense amplifier enable signal.

[0159] In some embodiments, a method of operating a signal distribution circuit includes: receiving a first control signal at a signal node of a booster circuit; outputting a booster signal from a delay stage of the booster circuit in response to the first control signal; and selectively coupling the signal node to each of a power supply voltage node and a reference voltage node using a boosting stage of the control circuit in response to the first control signal and the booster signal. In some embodiments, outputting the booster signal includes outputting a voltage transition of the booster signal delayed from a voltage transition of the first control signal, and selectively coupling the signal node to each of the power supply voltage node and the reference voltage node using the boosting stage includes coupling the signal node to one of the power supply voltage node or the reference voltage node in response to the voltage transition of the first control signal, and coupling the signal node to the other of the power supply voltage node or the reference voltage node in response to the voltage transition of the booster signal. In some embodiments, the method includes: receiving a second control signal at the booster circuit; and coupling the signal node to the other of the power supply voltage node or the reference voltage node using the boosting stage in response to the voltage transition of the second control circuit. In some embodiments, the method includes: receiving an enable signal at the booster circuit; and selectively disabling coupling of the signal node to each of the supply voltage node and the reference voltage node in response to the enable signal.

[0160] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A signal distribution circuit, comprising: A signal node configured to receive a first control signal; a delay stage coupled to the signal node and configured to output a first booster signal in response to the first control signal; as well as a boosting stage coupled to the signal node and the delay stage, wherein the boosting stage comprises: a pull-up circuit including a first transistor configured to couple the signal node to a supply voltage node in response to the first booster signal; and The pull-down circuit includes a second transistor configured to couple the signal node to a reference voltage node in response to the first booster signal.

2. The signal distribution circuit according to claim 1, wherein: The delay stage comprises: a first inverter comprising an input terminal coupled to the signal node; The first NAND gate includes: A first input terminal configured to receive an enable signal; a second input terminal coupled to the output terminal of the first inverter; and an output terminal configured to output the first booster signal; and The second NAND gate includes: a first input terminal coupled to the output terminal of the first NAND gate; A second input terminal configured to receive the enable signal; and Output terminals, The pull-up circuit further includes a third NAND gate, and the third NAND gate includes: a first input terminal configured to receive a second booster signal based on the first booster signal; a second input terminal coupled to the signal node; and an output terminal coupled to the gate of the first transistor, and The pull-down circuit further includes a first NOR gate, wherein the first NOR gate includes: a first input terminal coupled to the output terminal of the second NAND gate; a second input terminal coupled to the signal node; and An output terminal is coupled to the gate of the second transistor.

3. The signal distribution circuit according to claim 2, further comprising: The second NOR gate includes: a first input terminal coupled to the output terminal of the first NAND gate; A second input terminal configured to receive a second control signal; and An output terminal is coupled to the first input terminal of the third NAND gate.

4. The signal distribution circuit according to claim 2, further comprising: The second inverter comprises: an input terminal coupled to the output terminal of the first NAND gate; and an output terminal coupled to the first input terminal of the third NAND gate, in, The boosting stage includes a third transistor connected in series with the first transistor or in series with the second transistor, and The third transistor includes a gate configured to receive a second control signal.

5. The signal distribution circuit according to claim 1, wherein: The delay stage includes a first inverter, a second inverter, and a third inverter coupled in series between the signal node and the boost stage, The pull-up circuit comprises a NAND gate, and the NAND gate comprises: A first input terminal configured to receive a first enable signal; a second input terminal coupled to the output terminal of the third inverter; A third input terminal configured to receive a second control signal; and an output terminal coupled to the gate of the first transistor, and The pull-down circuit includes a NOR gate, and the NOR gate includes: a first input terminal coupled to an output terminal of the third inverter; A second input terminal configured to receive a second enable signal; a third input terminal coupled to the signal node; and An output terminal is coupled to the gate of the second transistor.

6. The signal distribution circuit according to claim 1, wherein: The delay stage includes a first inverter and a second inverter coupled in series between the signal node and the boost stage, and The upgrade level includes: NAND gates, including: A first input terminal configured to receive a first enable signal; a second input terminal coupled to the signal node; and Output terminals; NOR gates, including: a first input terminal coupled to the signal node; A second input terminal configured to receive a second enable signal; and Output terminals; A three-state inverter, comprising: the first transistor and the second transistor; an input terminal coupled to an output terminal of the second inverter; a first enable terminal coupled to the output terminal of the NAND gate; a second enable terminal coupled to the output terminal of the NOR gate; and an output terminal coupled to the signal node; and Meet one or both of the following: a third transistor and a fourth transistor coupled between the output terminal of the NAND gate and the power supply voltage node; or A fifth transistor and a sixth transistor are coupled between the signal node and the reference voltage node.

7. A signal distribution circuit, comprising: a first signal line and a second signal line; a driver coupled to first ends of the first signal line and the second signal line and configured to output corresponding first control signals and second control signals to the first signal line and the second signal line; a booster circuit coupled to the second end of the first signal line; as well as a buffer coupled between the second end of the second signal line and the booster circuit, Wherein, the booster circuit comprises: a delay stage configured to output a first booster signal in response to the first control signal received at the second end of the first signal line; and a boost stage coupled to the delay stage, wherein the boost stage comprises: a pull-up circuit configured to couple an input terminal of the buffer to a supply voltage node in response to the first booster signal; and A pull-down circuit is configured to couple the input terminal of the buffer to a reference voltage node in response to the first booster signal.

8. The signal distribution circuit according to claim 7, further comprising: a third signal line coupled between the driver and the booster circuit, in The driver is configured to output a third control signal to the third signal line, and The pull-up circuit is configured to couple the input terminal of the buffer to the supply voltage node further in response to the third control signal.

9. The signal distribution circuit according to claim 7, further comprising: a plurality of load circuits coupled to the second signal line between the driver and the output terminal of the buffer, Wherein, each load circuit of the plurality of load circuits is configured to receive the second control signal.

10. A method of operating a signal distribution circuit, the method comprising: receiving a first control signal at a signal node of the booster circuit; outputting a booster signal from a delay stage of the booster circuit in response to the first control signal; as well as The signal node is selectively coupled to each of a supply voltage node and a reference voltage node using a boosting stage of the control circuit in response to the first control signal and the booster signal.

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