SOC chip ADC linearity test method, controller and test system

Abstract

The invention discloses an SOC chip ADC linearity test method, a controller and a test system. The method comprises the following steps: acquiring a signal voltage input into an analog-to-digital conversion module, and a first input signal range and a first resolution of the analog-to-digital conversion module; when the signal voltage is in the first input signal range, dividing the signal voltage into a plurality of single-step voltages; performing code value conversion on all the single-step voltages through a digital-to-analog conversion module, outputting code values, and acquiring signal voltage data after the digital-to-analog conversion module outputs each code value through an analog-to-digital conversion module to obtain acquired data; performing linear fitting operation on all the collected data to obtain a fitting straight line; calculating deviation values of all the collected data and the fitting straight line to obtain a target error value; and when the target error value is smaller than or equal to the preset boundary value, determining that the to-be-tested chip passes the linearity test. According to the embodiment of the invention, the ADC linearity test is carried out on the SOC chip in a linear fitting mode, so that the test time and cost are saved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a SOC chip ADC linearity testing method, a controller and a testing system. Background Art

[0002] SOC (System on Chip) mainly integrates peripheral interfaces such as memory, counters, serial interfaces, A / D conversion, D / A conversion, etc. on a single chip to form a chip-level computer, which performs real-time control for different application scenarios; SOC usually includes ADC (Ana log-to-Digital Converter) peripherals and DAC (Digital-to-Ana log Converter) peripherals. For SOC chips, ADC linearity is an important indicator of SOC chip performance. Traditionally, the test process of ADC linearity is too complicated, and the test time and cost required are high, which is not conducive to the mass production of SOC chips. Summary of the invention

[0003] The embodiments of the present application provide a SOC chip ADC linearity test method, a controller and a test system, which use a linear fitting method to perform ADC linearity test on the SOC chip, saving test time and test cost.

[0004] In a first aspect, an embodiment of the present application provides a method for testing linearity of an ADC of a SOC chip, which is applied to a test system, wherein the test system includes a chip to be tested, and the chip to be tested is internally provided with a digital-to-analog conversion module and an analog-to-digital conversion module connected to each other; the method includes:

[0005] Acquire a signal voltage input to the analog-to-digital conversion module, and acquire a first input signal range and a first resolution of the analog-to-digital conversion module;

[0006] When the signal voltage is within the first input signal range, dividing the signal voltage based on the first resolution and a preset number of cycles to obtain a plurality of single-step voltages;

[0007] Perform code value conversion on all the single-step voltages through the digital-to-analog conversion module, output code values ​​corresponding to the single-step voltages one by one, and collect signal voltage data after each code value is output by the digital-to-analog conversion module through the analog-to-digital conversion module to obtain collected data;

[0008] Performing a linear fitting operation on all the collected data to obtain a fitting straight line;

[0009] Calculate the deviation value between all the collected data and the fitting straight line to obtain a target error value;

[0010] When the target error value is less than or equal to a preset boundary value, it is determined that the chip under test passes the linearity test.

[0011] In some embodiments, performing code value conversion on all the single-step voltages by the digital-to-analog conversion module and outputting code values ​​corresponding to the single-step voltages one by one includes:

[0012] Acquire a second input signal range and a second resolution of the digital-to-analog conversion module;

[0013] Performing code value conversion on all the single-step voltages based on the second input signal range and the second resolution to obtain step code values ​​corresponding to the single-step voltages one by one;

[0014] Sorting all the step code values ​​to obtain a code value sequence;

[0015] The code value sequence is traversed by the digital-to-analog conversion module to output a code value corresponding to the single-step voltage in a sorting order of the code value sequence.

[0016] In some embodiments, before performing a linear fitting operation on all the collected data to obtain a fitting straight line, the method further includes:

[0017] A filtering operation is performed on all the collected data through a sliding window of a preset length.

[0018] In some embodiments, performing a linear fitting operation on all the collected data to obtain a fitting straight line includes:

[0019] Performing waveform drawing on all the collected data to obtain a sampling waveform;

[0020] Performing data screening on all the collected data according to the sampling waveform to obtain a fitting data set;

[0021] Performing linear fitting on the fitting data set by a preset least square method to obtain a fitting slope and a fitting bias;

[0022] A fitting linear function is obtained according to the fitting slope and the fitting bias, and a fitting straight line is generated based on the fitting linear function.

[0023] In some embodiments, calculating the deviation values ​​of all the collected data from the fitting straight line to obtain a target error value includes:

[0024] For each of the collected data, a distance value between the collected data and the fitting straight line is calculated according to the fitting linear function to obtain a collection deviation value;

[0025] The acquisition deviation values ​​of all the acquired data are screened to take the maximum acquisition deviation value as the target error value.

[0026] In some embodiments, after calculating the deviation values ​​between all the collected data and the fitted straight line to obtain the target error value, the method further includes:

[0027] When the target error value is greater than a preset boundary value, the signal voltage is divided based on the first resolution and a preset number of cycles to obtain a plurality of test single-step voltages;

[0028] Perform code value conversion on all the test single-step voltages through the digital-to-analog conversion module, output test code values ​​corresponding to the test single-step voltages one by one, and collect signal voltage data after the digital-to-analog conversion module outputs each test code value through the analog-to-digital conversion module to obtain test data;

[0029] Performing a linear fitting operation on all the test data to obtain a test fitting straight line;

[0030] Calculate the deviation value between all the test data and the test fitting straight line to obtain a test error value;

[0031] When the test error value is less than or equal to a preset boundary value, it is determined that the chip to be tested passes the linearity test.

[0032] In some embodiments, after calculating the deviation values ​​between all the test data and the test fitting straight line to obtain the test error value, the method further includes:

[0033] When the test error value is greater than a preset boundary value, counting the number of times the chip under test fails the linearity test;

[0034] When the test number is greater than or equal to a preset test threshold, it is determined that the chip to be tested fails the linearity test.

[0035] In a second aspect, an embodiment of the present application further provides a controller, the controller comprising a memory and a processor, the memory storing a computer program, and the processor implementing the SOC chip ADC linearity test method as described in the first aspect when executing the computer program.

[0036] In the third aspect, an embodiment of the present application also provides a test system, comprising a chip to be tested, a reference voltage module, a data processing module and a controller as described in the second aspect, wherein the controller is respectively connected to the chip to be tested, the reference voltage module and the data processing module; the chip to be tested is internally provided with a digital-to-analog conversion module and an analog-to-digital conversion module that are interconnected, the reference voltage module is connected to the digital-to-analog conversion module and the analog-to-digital conversion module, and the data processing module is connected to the analog-to-digital conversion module.

[0037] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the SOC chip ADC linearity test method as described in the first aspect.

[0038] The SOC chip ADC linearity test method provided in the embodiment of the present application has at least the following beneficial effects: the test system of the embodiment of the present application includes a chip to be tested, and the chip to be tested is internally provided with a digital-to-analog conversion module and an analog-to-digital conversion module connected to each other to realize the conversion from digital quantity to analog quantity, and can realize the conversion from analog quantity to digital quantity. Based on the above test system, the embodiment of the present application first obtains the signal voltage input to the analog-to-digital conversion module, and obtains the first input signal range and the first resolution of the analog-to-digital conversion module, so as to determine the minimum signal that the analog-to-digital conversion module can distinguish and quantize, and further determine the accuracy with which the analog-to-digital conversion module can quantize the signal. When the signal voltage input to the test system is in the first input signal range, it means that the signal voltage is within the effective range of the analog-to-digital conversion module. The signal voltage is divided based on the first resolution and the preset number of cycles to obtain multiple single-step voltages, and the signal voltage is averagely divided. Then, all single-step voltages are converted into code values ​​by the digital-to-analog conversion module, and the code values ​​corresponding to the single-step voltages are output, and the analog-to-digital conversion module collects each code value output by the digital-to-analog conversion module. The signal voltage data is obtained to obtain the collected data, thereby testing and calibrating the input signal range of the analog-to-digital conversion module, ensuring that the analog-to-digital conversion module can accurately convert the signal. After that, a linear fitting operation is performed on all collected data, thereby simplifying the complex data relationship into a linear model, obtaining a fitting straight line, and realizing data compression, which is convenient for subsequent error calculation of the collected data. After that, the deviation value of all collected data and the fitting straight line is calculated, so that the deviation value of each collected data and the fitting straight line can be obtained, and the target error value is obtained. The target error value is then compared with the preset boundary value. When the target error value is less than or equal to the preset boundary value, it means that the target error value is within the allowable range, and it can be determined that the chip to be tested passes the linearity test, thereby realizing the ADC linearity test of the SOC chip. The embodiment of the present application uses a linear fitting method to test the linearity of the analog-to-digital conversion module of the chip to be tested. The test and correction operation process is simple, does not require a complex test process, and greatly reduces the test time and test cost of ADC linearity.

[0039] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the examples of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0041] Figure 1is a system schematic diagram of a test system provided in an embodiment of the present application;

[0042] Figure 2 It is a flowchart of a specific method of the SOC chip ADC linearity test method provided in an embodiment of the present application;

[0043] Figure 3 This is a specific flow chart of converting code values ​​of all single-step voltages through a digital-to-analog conversion module provided in an embodiment of the present application;

[0044] Figure 4 It is a specific flow chart of a SOC chip ADC linearity test method provided by another embodiment of the present application;

[0045] Figure 5 It is a specific flow chart of performing linear fitting operation on all collected data provided by the embodiment of the present application;

[0046] Figure 6 is a specific flow chart for calculating the deviation value between all collected data and the fitted straight line provided in an embodiment of the present application;

[0047] Figure 7 It is a specific flow chart of a SOC chip ADC linearity test method provided by another embodiment of the present application;

[0048] Figure 8 It is a specific flow chart of a SOC chip ADC linearity test method provided by another embodiment of the present application;

[0049] Fig. 9 is a schematic diagram of the hardware structure of the controller provided in the embodiment of the present application;

[0050] Fig.10 A flow chart of a SOC chip ADC linearity test method provided as an example of the present application;

[0051] Fig.11a and Fig.11b A waveform diagram of an ADC sampling waveform provided for an example of the present application;

[0052] Fig.12a and 12b A schematic diagram of ADC linearity test data provided for an example of the present application. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0054] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0056] The SOC (System on Chip) chip ADC linearity test method provided in the embodiment of the present application can be applied to the terminal, can also be applied to the server side, and can also be software running in the terminal or the server side. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer or a smart watch, etc.; the server side can be configured as an independent physical server, or a server cluster or distributed system composed of multiple physical servers, and can also be configured as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, content distribution networks (Content De l ivery Network, CDN) and big data and artificial intelligence platforms; the software can be an application that implements the above method, etc., but is not limited to the above forms.

[0057] Embodiments of the present application can be used in numerous general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer computer devices, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present application can be described in the general context of computer executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0058] SOC (Micro Control Unit) mainly integrates memory, counter, serial interface, A / D conversion, D / A conversion and other peripheral interfaces on a single chip to form a chip-level computer, which performs real-time control for different application scenarios; SOC usually includes ADC (Ana log-to-Digital Converter) peripherals and DAC (Digital-to-Ana log Converter) peripherals. For SOC chips, ADC linearity is an important indicator of SOC chip performance. Traditionally, the test process of ADC linearity is too complicated, and the test time and cost required are high, which is not conducive to the mass production of SOC chips.

[0059] In order to solve the above problems, the embodiment of the present application provides a SOC chip ADC linearity test method, system, controller and storage medium. The test system of the embodiment of the present application includes a chip to be tested, and the chip to be tested is provided with interconnected digital-to-analog conversion modules and analog-to-digital conversion modules to realize the conversion from digital quantity to analog quantity, and can realize the conversion from analog quantity to digital quantity. Based on the above test system, the embodiment of the present application first obtains the signal voltage input to the analog-to-digital conversion module, and obtains the first input signal range and the first resolution of the analog-to-digital conversion module, so as to determine the minimum signal that the analog-to-digital conversion module can distinguish and quantize, and further determine the accuracy of the analog-to-digital conversion module to quantize the signal. When the signal voltage input to the test system is in the first input signal range, it means that the signal voltage is within the effective range of the analog-to-digital conversion module. Based on the first resolution and the preset number of cycles, the signal voltage is divided into voltages to obtain multiple single-step voltages, and the signal voltage is averagely divided. Then, all single-step voltages are converted into code values ​​by the digital-to-analog conversion module, and the code values ​​corresponding to the single-step voltages are output, and the analog-to-digital conversion module collects each code value output by the digital-to-analog conversion module. The signal voltage data is obtained to obtain the collected data, thereby testing and calibrating the input signal range of the analog-to-digital conversion module, ensuring that the analog-to-digital conversion module can accurately convert the signal. After that, a linear fitting operation is performed on all collected data, thereby simplifying the complex data relationship into a linear model, obtaining a fitting straight line, and realizing data compression, which is convenient for subsequent error calculation of the collected data. After that, the deviation value of all collected data and the fitting straight line is calculated, so that the deviation value of each collected data and the fitting straight line can be obtained, and the target error value is obtained. The target error value is then compared with the preset boundary value. When the target error value is less than or equal to the preset boundary value, it means that the target error value is within the allowable range, and it can be determined that the chip to be tested passes the linearity test, thereby realizing the ADC linearity test of the SOC chip. The embodiment of the present application uses a linear fitting method to test the linearity of the analog-to-digital conversion module of the chip to be tested. The test and correction operation process is simple, does not require a complex test process, and greatly reduces the test time and test cost of ADC linearity.

[0060] Reference Figure 1 , Figure 1 Schematic diagram of the test system provided in the embodiment of the present application.

[0061] In some embodiments, the test system includes a chip to be tested 100, a reference voltage module 200, a data processing module 300 and a controller (not shown in the figure), and the controller is respectively connected to the chip to be tested 100, the reference voltage module 200 and the data processing module 300; the chip to be tested 100 is internally provided with a digital-to-analog conversion module 110 and an analog-to-digital conversion module 120 that are interconnected, the reference voltage module 200 is connected to the digital-to-analog conversion module 110 and the analog-to-digital conversion module 120, and the data processing module 300 is connected to the analog-to-digital conversion module 120.

[0062] In some embodiments, the reference voltage module 200 in the embodiments of the present application is used to generate reference signals for the analog-to-digital conversion module 120 and the digital-to-analog conversion circuit, and the digital-to-analog conversion module 110 and the analog-to-digital conversion module 120 use the same reference signal, so that the output signal range of the digital-to-analog conversion module 110 is greater than or equal to the input signal range of the analog-to-digital conversion module 120, which is conducive to testing the ADC linearity.

[0063] The digital-to-analog conversion module 110 is used to generate an input signal for the analog-to-digital conversion module 120. The DAC conversion bit number can be greater than or less than the ADC conversion bit number, but the DAC output signal range needs to be greater than or equal to the ADC input signal range, so that it can traverse the ADC input signal range, which is conducive to subsequent ADC data processing.

[0064] The analog-to-digital conversion module 120 is used to convert the output signal of the digital-to-analog conversion module 110. The DAC output signal range is greater than or equal to the ADC input signal range. The ADC conversion result includes the ADC linearity index. The ADC linearity index is an important part of the performance of the chip under test 100 and is presented through data processing.

[0065] The data processing module 300 obtains linearity data with high confidence by performing linear fitting and maximum error calculation on the data. Compared with the traditional integral nonlinearity (INL) and differential nonlinearity (DNL) calculation methods, this method does not require a large amount of data, is simpler to process and has lower cost.

[0066] It is worth noting that the reference voltage module 200 and the data processing module 300 in the embodiment of the present application can also be arranged inside the chip under test 100, and the embodiment of the present application does not make specific limitations.

[0067] In combination with the structure of the above-mentioned test system, the SOC chip ADC linearity test method of the embodiment of the present application is described in detail below.

[0068] Reference Figure 2 , Figure 2 1 is a flowchart of a specific method of the SOC chip ADC linearity test method provided in an embodiment of the present application. In some embodiments, the SOC chip ADC linearity test method is applied but not limited to Figure 1 The test system in the method includes but is not limited to steps S101 to S106.

[0069] Step S101 , obtaining a signal voltage input to the analog-to-digital conversion module 120 , and obtaining a first input signal range and a first resolution of the analog-to-digital conversion module 120 .

[0070] In step S101 of some embodiments, the signal voltage of the input analog-to-digital conversion module 120 is obtained, and the first input signal range and the first resolution of the analog-to-digital conversion module 120 are obtained. By obtaining the input signal range of the analog-to-digital conversion module 120, signal distortion or damage caused by the input signal exceeding the input voltage limit of the analog-to-digital conversion module 120 can be avoided. By obtaining the first resolution, the ability of the analog-to-digital conversion module 120 to distinguish and quantize the minimum signal can be determined.

[0071] It can be understood that the first resolution in the embodiment of the present application is used to characterize the minimum increment of the input analog signal that the analog-to-digital conversion module 120 can distinguish. The main function of the resolution is to provide the accuracy of the quantized signal, that is, it determines the degree of fineness when the analog signal is converted into a digital signal. A high-resolution ADC can provide more quantization levels, thereby being able to more accurately represent the analog signal.

[0072] Step S102: when the signal voltage is within the first input signal range, the signal voltage is divided based on a first resolution and a preset number of cycles to obtain a plurality of single-step voltages.

[0073] In step S102 of some embodiments, when the signal voltage is within the first input signal range, it indicates that the current input signal voltage is within the input range of the analog-to-digital conversion module 120. By ensuring that the input signal is within the effective range of the analog-to-digital conversion module 120, the quantization error can be reduced and the measurement accuracy can be improved. At this time, the signal voltage is divided based on the first resolution and the preset number of cycles, thereby achieving average division of the signal voltage and obtaining multiple single-step voltages, which facilitates the subsequent conversion of the voltage data into code value data.

[0074] It is understandable that the embodiment of the present application can divide the signal voltage of the input range into two equal parts. N The signal voltage of each portion is: Voltage = (Vref + - Vref -) * Dn / 2 N , where Vref+ and Vref- are reference voltages, and Dn is the number of cycles.

[0075] In step S103, the digital-to-analog conversion module 110 performs code value conversion on all single-step voltages, outputs code values ​​corresponding to the single-step voltages, and collects signal voltage data after each code value is output by the digital-to-analog conversion module 110 through the analog-to-digital conversion module 120 to obtain collected data.

[0076] In step S103 of some embodiments, code value conversion is performed on all single-step voltages through the digital-to-analog conversion module 110, so that the digital-to-analog conversion module 110 outputs the code values ​​corresponding to the single-step voltages in order from small to large, and enables the analog-to-digital conversion module 120 to perform sampling, and outputs the code values ​​​​in a loop to the maximum code value to obtain collected data. Specifically, the signal voltage data after each code value output by the digital-to-analog conversion module 110 is collected through the analog-to-digital conversion module 120, that is, each time the digital-to-analog conversion module 110 outputs a code value, the analog-to-digital conversion module 120 will collect a signal voltage data, and after waiting for the conversion to end, the conversion data result of the analog-to-digital conversion module 120 is read to obtain the collected data, so that the input range of the entire analog-to-digital conversion module 120 can be tested and calibrated to ensure that it can accurately convert signals within the entire working range, thereby improving the test accuracy of the ADC linear test.

[0077] Step S104: perform a linear fitting operation on all collected data to obtain a fitting straight line.

[0078] In step S104 of some embodiments, a linear fitting operation is performed on all collected data to generate a fitting straight line based on a fitting linear function, thereby simplifying a complex data relationship into a linear model, and describing the data set with fewer parameters, thereby achieving data compression.

[0079] Step S105, calculating the deviation value between all collected data and the fitting straight line to obtain a target error value.

[0080] In step S105 of some embodiments, the deviation values ​​of all collected data and the fitting straight line are calculated, and all the deviation values ​​are screened to take the maximum collected deviation value as the target deviation value, so as to facilitate subsequent accurate ADC linearity testing.

[0081] Step S106 , when the target error value is less than or equal to the preset boundary value, it is determined that the chip under test 100 passes the linearity test.

[0082] In step S106 of some embodiments, the target error value is compared with the preset boundary value. When the target error value is less than or equal to the preset boundary value, it means that the chip 100 under test does not have a linearity problem, or the linearity problem is small, and the sampling data error is within the allowable range. At this time, it is determined that the chip 100 under test has passed the linearity test.

[0083] It should be noted that the preset boundary value in the embodiment of the present application can be set according to the user's needs, for example, set to 30, 40, 50, etc., and the embodiment of the present application does not make any specific restrictions.

[0084] Reference Figure 3 , Figure 3 It is a specific flow chart of converting code values ​​of all single-step voltages by the digital-to-analog conversion module 110 provided in an embodiment of the present application. In some embodiments, the method includes but is not limited to steps S201 to S204.

[0085] Step S201 , obtaining a second input signal range and a second resolution of the digital-to-analog conversion module 110 .

[0086] Step S202 , performing code value conversion on all single-step voltages based on the second input signal range and the second resolution to obtain step code values ​​corresponding to the single-step voltages.

[0087] Step S203: sort all step code values ​​to obtain a code value sequence.

[0088] Step S204 , traversing the code value sequence through the digital-to-analog conversion module 110 to output the code value corresponding to the single-step voltage according to the sorting order of the code value sequence.

[0089] In steps S201 to S204 of some embodiments, in the process of converting the code values ​​of all single-step voltages by the digital-to-analog conversion module 110, the embodiment of the present application first obtains the second input signal range and the second resolution of the digital-to-analog conversion module 110, so as to avoid signal distortion or damage caused by the input signal exceeding the input voltage limit of the digital-to-analog conversion module 110, and the ability of the digital-to-analog conversion module 110 to distinguish the minimum signal of quantization can be determined by obtaining the second resolution. After that, the digital-to-analog conversion module 110 outputs the corresponding step voltage according to the averaged single-step voltage configuration. Step code value, specifically, based on the second input signal range and the second resolution, code value conversion is performed on all single-step voltages to obtain step code values ​​corresponding to the single-step voltages one by one, and then all step code values ​​are sorted to obtain a code value sequence. Specifically, the embodiment of the present application arranges the step code values ​​from small to large to obtain a code value sequence, that is, the code values ​​in the code value sequence increase in sequence, and then the code value sequence is traversed by the digital-to-analog conversion module 110 to output the code value corresponding to the single-step voltage in the sorting order of the code value sequence, that is, the code values ​​are output in sequence from small to large, which is convenient for the subsequent analog-to-digital conversion module 120 to perform sampling.

[0090] Reference Figure 4 , Figure 4 It is a specific flow chart of a method for testing linearity of an ADC of a SOC chip provided by another embodiment of the present application. In some embodiments, the method includes but is not limited to step S301.

[0091] It should be noted that step S301 occurs before performing a linear fitting operation on all collected data to obtain a fitting straight line.

[0092] Step S301: filtering all collected data using a sliding window of a preset length.

[0093] In step S301 of some embodiments, before performing a linear fitting operation on all collected data to obtain a fitted straight line, the embodiments of the present application will also perform a filtering operation on all collected data through a sliding window of a preset length. Specifically, the sum of all values ​​in the current window is calculated through a sliding window of a preset length, and then divided by the window size to obtain the filtering result of the current point, and then a sliding average is performed from front to back. Specifically, the sliding window is moved to process the next data point, and the sliding window is moved forward one position, that is, a new data point is added, and the earliest data point is removed. For each new data point, the process of calculating the average value and the window sliding is repeated, thereby stably reducing random fluctuations in the data and having a good inhibitory effect on periodic interference.

[0094] Reference Figure 5 , Figure 5 It is a specific flow chart of performing linear fitting operation on all collected data provided by the embodiment of the present application. The method includes but is not limited to steps S401 to S404.

[0095] Step S401, waveform drawing is performed on all collected data to obtain a sampling waveform.

[0096] Step S402: Screen all collected data according to the sampling waveform to obtain a fitting data set.

[0097] Step S403 , performing linear fitting on the fitting data set by using a preset least squares method to obtain a fitting slope and a fitting bias.

[0098] Step S404, obtaining a fitting linear function according to the fitting slope and the fitting bias, and generating a fitting straight line based on the fitting linear function.

[0099] In steps S401 to S404 of some embodiments, in the process of performing linear fitting operations on all collected data, the present application first draws waveforms on all collected data to obtain sampling waveforms, so as to intuitively display the data changes of the collected data, and then performs data screening on all collected data according to the sampling waveforms. Specifically, waveform analysis is performed on the sampling waveforms, and then data screening is performed on all collected data according to the analysis results, and a certain number of collected data are selected for linear fitting to obtain a fitting data set. Thereafter, linear fitting is performed on the fitting data set by a preset least squares method. Specifically, the least squares method determines the parameters of the fitting line by minimizing the residual sum of squares between the actual observed values ​​and the fitted values, and obtains the fitting slope and fitting bias, so as to obtain the slope and intercept of the function, and then obtains the fitting linear function according to the fitting slope and fitting bias, and generates a fitting line based on the fitting linear function, so as to simplify complex data relationships into linear models, and can describe the data set with fewer parameters, thereby achieving data compression.

[0100] It should be noted that the specific process of obtaining the fitting slope and the fitting bias in the embodiment of the present application is as follows:

[0101]

[0102] Among them, k is the fitting slope, x(i) is the code value of the ergodic output, y(i) is the signal voltage data collected by the analog-to-digital conversion module 120, and size is the number of data for linear fitting, that is, the number of data in the fitting data set.

[0103]

[0104] Among them, b is the fitting bias, x(i) is the code value of the ergodic output, y(i) is the signal voltage data collected by the analog-to-digital conversion module 120, and size is the number of data for linear fitting, that is, the number of data in the fitting data set.

[0105] In some embodiments, after k is found, the solution formula for b is simplified:

[0106]

[0107] Reference Figure 6 , Figure 6 It is a specific flow chart for calculating the deviation value between all collected data and the fitting straight line provided in an embodiment of the present application. In some embodiments, the method includes but is not limited to step S501 to step S502.

[0108] Step S501: for each piece of collected data, the distance between the collected data and the fitting straight line is calculated according to the fitting linear function to obtain a collection deviation value.

[0109] Step S502: Screening the acquisition deviation values ​​of all the acquired data to take the maximum acquisition deviation value as the target error value.

[0110] In steps S501 to S502 of some embodiments, in the process of calculating the deviation values ​​of all collected data and the fitting straight line, for each collected data, the collected data is substituted into the fitting linear function to obtain the collection deviation value of the collected data, so as to obtain the deviation value of the actual observed value and the fitting linear function, and then the collection deviation values ​​of all collected data are statistically analyzed to obtain a deviation set, and all deviation values ​​in the deviation set are screened to take the largest collection deviation value as the target deviation value, so as to facilitate subsequent accurate ADC linear testing.

[0111] Reference Figure 7 , Figure 7 It is a specific flow chart of a method for testing linearity of an ADC of a SOC chip provided by another embodiment of the present application. In some embodiments, the method includes but is not limited to steps S601 to S605.

[0112] It should be noted that steps S601 to S605 occur after the deviation values ​​between all collected data and the fitting straight line are calculated to obtain the target error value.

[0113] Step S601, when the target error value is greater than a preset boundary value, the signal voltage is divided based on a first resolution and a preset number of cycles to obtain a plurality of test single-step voltages.

[0114] In step S602, the digital-to-analog conversion module 110 performs code value conversion on all test single-step voltages, outputs test code values ​​corresponding to the test single-step voltages one by one, and collects signal voltage data after each test code value is output by the digital-to-analog conversion module 110 through the analog-to-digital conversion module 120 to obtain test data.

[0115] Step S603: perform a linear fitting operation on all test data to obtain a test fitting straight line.

[0116] Step S604, calculating the deviation value between all test data and the test fitting straight line to obtain a test error value.

[0117] Step S605 , when the test error value is less than or equal to the preset boundary value, it is determined that the chip under test 100 passes the linearity test.

[0118] In some embodiments, in steps S601 to S605, after calculating the deviation values ​​of all collected data and the fitting straight line to obtain the target error value, when the target error value is greater than the preset boundary value, it means that the current target error value exceeds the set boundary value, that is, exceeds the allowable error range. At this time, it is necessary to execute steps S101 to S105 again. Specifically, based on the first resolution and the preset number of cycles, the signal voltage is divided into voltages to obtain multiple test single-step voltages, and then all the test single-step voltages are converted into code values ​​through the digital-to-analog conversion module 110, and the test code values ​​corresponding to the test single-step voltages are output, and the digital-to-analog conversion module 120 collects the digital-to-analog conversion module 110 output through the analog-to-digital conversion module 120. The signal voltage data after each test code value is obtained to obtain the test data. After that, a linear fitting operation is performed on all the test data to obtain a test fitting straight line. The deviation values ​​of all the test data and the test fitting straight line are calculated to obtain a test error value. The test error value and the preset boundary value are continuously compared. When the test error value is less than or equal to the preset boundary value, it is determined that the chip 100 to be tested has passed the linearity test, thereby realizing an accurate test of the ADC linearity of the chip 100 to be tested, and being able to more accurately determine whether the chip meets the performance requirements. This method reduces the misjudgment caused by a single test error and reduces the misjudgment caused by random fluctuations or instantaneous interference during the test, making the test results more stable and reliable.

[0119] Reference Figure 8 , Figure 8 It is a specific flow chart of a method for testing linearity of an ADC of a SOC chip provided by another embodiment of the present application. In some embodiments, the method includes but is not limited to steps S701 to S702.

[0120] It should be noted that step S701 to step S702 occur after the deviation values ​​between all test data and the test fitting straight line are calculated to obtain the test error value.

[0121] Step S701 , when the test error value is greater than a preset boundary value, the number of times the chip under test 100 fails the linearity test is counted.

[0122] Step S702 : when the number of tests is greater than or equal to a preset test threshold, it is determined that the chip under test 100 fails the linearity test.

[0123] In steps S701 to S702 of some embodiments, after calculating the deviation values ​​of all test data and the test fitting straight line to obtain the test error value, when the test error value is greater than the preset boundary value, it means that the test result of the linear test performed again on the chip 100 to be tested still exceeds the allowable error range. At this time, it is necessary to count the number of times the chip 100 to be tested fails the linearity test, and then compare the number of tests with the preset test threshold. When the number of tests is greater than or equal to the preset test threshold, it means that the number of times the chip 100 to be tested fails the linearity test has exceeded the maximum number set by the system. At this time, determining that the chip 100 to be tested fails the linearity test can improve production efficiency while improving product reliability.

[0124] See also Fig. 9 , Fig. 9 The hardware structure of the controller provided in the embodiment of the present application is illustrated, and the controller includes:

[0125] The processor 901 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0126] The memory 902 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 902 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 902, and the processor 901 calls and executes the SOC chip ADC linearity test method of the embodiment of this application;

[0127] Input / output interface 903, used to implement information input and output;

[0128] Communication interface 904, used to realize communication interaction between the device and other devices, which can be realized through wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WI FI, Bluetooth, etc.);

[0129] A bus 905 that transmits information between various components of the device (e.g., the processor 901, the memory 902, the input / output interface 903, and the communication interface 904);

[0130] The processor 901 , the memory 902 , the input / output interface 903 and the communication interface 904 are connected to each other in communication within the device via a bus 905 .

[0131] In order to more clearly explain the SOC chip ADC linearity test method, controller and SOC chip ADC test system of the embodiments of the present application, specific examples are given below for illustration.

[0132] Example 1:

[0133] Example 1 Figure 1 The SOC chip ADC test system in is used as an example to illustrate.

[0134] In some embodiments, a SOC chip ADC is used for testing, and the ADC input signal range is 0 to 3V, where Vref+ is 3V and Vref- is 0V.

[0135] refer to Fig.10 , Fig.10 A flowchart of a SOC chip ADC linearity testing method provided as an example of the present application.

[0136] Step S1: confirming the voltage averaging range according to the ADC input voltage range.

[0137] In some embodiments, the signal voltage of the input range is divided into 4096 parts (N=12), and the signal voltage of each part is Voltage=(Vref+-Vref-)*Dn / 2 N =3*Dn / 2 N (Dn is the number of cycles).

[0138] Step S2: The DAC outputs a corresponding step code value according to the evenly divided single-step voltage configuration.

[0139] In some embodiments, the DAC output signal range is 0 to 3V, the DAC bit number is 12 bits, the ADC input signal is divided into 4096 parts (N=12), and Voltage=(Vref+-Vref-)*Dn / 2 N =3*Dn / 2 N , which just corresponds to the DAC code value 0 to 4095;

[0140] Step S3: The DAC code values ​​are outputted in order from small to large, and ADC sampling is enabled, and the DAC code values ​​are outputted cyclically until the maximum code value is reached, and the ADC sampling data is saved; the test count value is increased by 1.

[0141] In some embodiments, the ADC and DAC initialization codes are executed, and the DAC code value changes from 0 to 4095 in sequence. Each time the DAC outputs a signal voltage of a code value, the ADC collects a signal voltage data to obtain a voltage of 4096 code values.

[0142] Step S4: Perform sliding filtering on the ADC sampling data.

[0143] In some embodiments, a sliding window filtering operation is performed on all sampled data of the ADC, and the sliding window length M is set to 4.

[0144] Step S5: Perform linear fitting on the filtered data using the least squares method.

[0145] In some embodiments, the sampling data is linearly fitted using the least squares method, and according to the ADC sampling waveform, 1800 data starting from the 2048th data are selected for linear fitting.

[0146] Specifically, the slope can be calculated by slope=calculateSlope(adc_buf,1800), and the bias can be calculated by intercept=calculateIntercept(adc_buf,1800,slope). After calculating the slope and the bias, the embodiment of the present application counts the maximum error by adc_error=calculateError(adc_buf,3720,slope,intercept).

[0147] Step S6: Calculate the error between all sampling values ​​of the ADC and the fitted straight line, and calculate the maximum error value MaxError.

[0148] Step S7: Determine whether the MaxError value is greater than the boundary value.

[0149] In some embodiments, the present application embodiment compares the maximum error value MaxError with a set boundary value 50, and an ADC that exceeds the boundary value is deemed to fail.

[0150] Step S8: When the MaxError value is greater than the boundary value, determine whether the test count value is greater than 3.

[0151] Step S9: When the MaxError value is less than or equal to the boundary value, it is determined that the maximum error value is within the boundary value and PASS is returned.

[0152] Step S10: If the error value still exceeds the boundary value after multiple tests, FAI L is returned.

[0153] In some embodiments, if the ADC maximum error value MaxError of a certain SOC chip exceeds 50, the above test is repeatedly performed. If the maximum error values ​​MaxError of the three tests all exceed 50, it is determined that the corresponding SOC chip FAI L.

[0154] refer to Fig.11a and Fig.11b , 11a and Fig.11b A waveform diagram of an ADC sampling waveform provided for an example of the present application.

[0155] In some embodiments, a SOC chip with ADC linearity deviation (abnormal SOC chip) and a SOC chip with ADC linearity preference (normal SOC chip) are selected, and the ADC sampling waveforms of the two are compared. Fig.11a and 11b As shown, we can see the manifestation of ADC linearity problem in the sampling waveform, where the horizontal axis is the DAC output code value and the vertical axis is the ADC sampling data; Fig.11a The ADC sampling waveform has a sharp corner at the bottom. Fig.11b The ADC sampling waveform has no sharp corner at the bottom.

[0156] refer to Fig.12a and 12b , 12a and 12b are schematic diagrams of ADC linearity test data provided in an example of the present application.

[0157] In some embodiments, 100 SOC chips with ADC linearity deviation (abnormal SOC chips) and 100 SOC chips with ADC linearity preference (normal SOC chips) are selected, and the ADC linearity test data (MaxError) of the two are compared. Fig.12a and 12b As shown, we can see the manifestation of ADC linearity problems in linearity test data, where the horizontal axis is different chips and the vertical axis is linearity test data (MaxError); Fig.12a The ADC linearity test data (MaxError) are all above 50. Figure 12b The ADC linearity test data (MaxError) of the chip are all below 50; the set boundary value is: Limit = 50, and the SOC chip can be judged as PASS / FAIL based on the ADC linearity test data (MaxError). Fig.12a The SOC chips are all FAI L, Figure 12b All SOC chips pass.

[0158] In some embodiments, the ADC linearity test method of the embodiment of the present application uses a linear fitting method to test the ADC linearity of the SOC chip and make a judgment on the SOC chip. The hardware connection / software operation is simple and does not require a complicated test process, which greatly reduces the test time and test cost of the ADC linearity.

[0159] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the above-mentioned SOC chip ADC linearity test method is implemented.

[0160] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0161] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0162] It can be understood by those skilled in the art that Figure 1-9 The technical solutions shown in the figure do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than those shown in the figure, or a combination of certain steps, or different steps.

[0163] The system embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.

[0164] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0165] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0166] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0167] In the several embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of systems or units, which can be electrical, mechanical or other forms.

[0168] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0169] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0170] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0171] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A method for testing the linearity of an SOC chip ADC, characterized in that: Applied to a test system, the test system includes a chip to be tested, and the chip to be tested is internally provided with a digital-to-analog conversion module and an analog-to-digital conversion module connected to each other; the method includes: Acquire a signal voltage input to the analog-to-digital conversion module, and acquire a first input signal range and a first resolution of the analog-to-digital conversion module; When the signal voltage is within the first input signal range, dividing the signal voltage based on the first resolution and a preset number of cycles to obtain a plurality of single-step voltages; Perform code value conversion on all the single-step voltages through the digital-to-analog conversion module, output code values ​​corresponding to the single-step voltages one by one, and collect signal voltage data after each code value is output by the digital-to-analog conversion module through the analog-to-digital conversion module to obtain collected data; Performing a linear fitting operation on all the collected data to obtain a fitting straight line; Calculate the deviation value between all the collected data and the fitting straight line to obtain a target error value; When the target error value is less than or equal to a preset boundary value, it is determined that the chip under test passes the linearity test.

2. The SOC chip ADC linearity test method according to claim 1, characterized in that: The converting all the single-step voltages into code values ​​by the digital-to-analog conversion module, and outputting code values ​​corresponding to the single-step voltages one by one, comprises: Acquire a second input signal range and a second resolution of the digital-to-analog conversion module; Performing code value conversion on all the single-step voltages based on the second input signal range and the second resolution to obtain step code values ​​corresponding to the single-step voltages one by one; Sorting all the step code values ​​to obtain a code value sequence; The code value sequence is traversed by the digital-to-analog conversion module to output a code value corresponding to the single-step voltage in a sorting order of the code value sequence.

3. The SOC chip ADC linearity test method according to claim 1, characterized in that: Before performing a linear fitting operation on all the collected data to obtain a fitting straight line, the method further includes: A filtering operation is performed on all the collected data through a sliding window of a preset length.

4. The SOC chip ADC linearity test method according to claim 1, characterized in that: The performing a linear fitting operation on all the collected data to obtain a fitting straight line includes: Performing waveform drawing on all the collected data to obtain a sampling waveform; Performing data screening on all the collected data according to the sampling waveform to obtain a fitting data set; Performing linear fitting on the fitting data set by a preset least square method to obtain a fitting slope and a fitting bias; A fitting linear function is obtained according to the fitting slope and the fitting bias, and a fitting straight line is generated based on the fitting linear function.

5. The SOC chip ADC linearity testing method according to claim 4, characterized in that: The step of calculating the deviation values ​​between all the collected data and the fitted straight line to obtain a target error value includes: For each of the collected data, a distance value between the collected data and the fitting straight line is calculated according to the fitting linear function to obtain a collection deviation value; The acquisition deviation values ​​of all the acquired data are screened to take the maximum acquisition deviation value as the target error value.

6. The SOC chip ADC linearity testing method according to claim 1, characterized in that: After calculating the deviation values ​​between all the collected data and the fitting straight line to obtain the target error value, the method further includes: When the target error value is greater than a preset boundary value, the signal voltage is divided based on the first resolution and a preset number of cycles to obtain a plurality of test single-step voltages; Perform code value conversion on all the test single-step voltages through the digital-to-analog conversion module, output test code values ​​corresponding to the test single-step voltages one by one, and collect signal voltage data after the digital-to-analog conversion module outputs each test code value through the analog-to-digital conversion module to obtain test data; Performing a linear fitting operation on all the test data to obtain a test fitting straight line; Calculate the deviation value between all the test data and the test fitting straight line to obtain a test error value; When the test error value is less than or equal to a preset boundary value, it is determined that the chip to be tested passes the linearity test.

7. The SOC chip ADC linearity test method according to claim 6, characterized in that: After calculating the deviation values ​​between all the test data and the test fitting straight line to obtain the test error value, the method further includes: When the test error value is greater than a preset boundary value, counting the number of times the chip under test fails the linearity test; When the test number is greater than or equal to a preset test threshold, it is determined that the chip to be tested fails the linearity test.

8. A controller, characterized in that: The controller includes a memory and a processor, the memory stores a computer program, and the processor implements the SOC chip ADC linearity testing method as described in any one of claims 1 to 7 when executing the computer program.

9. A testing system, characterized in that: It includes a chip to be tested, a reference voltage module, a data processing module and a controller as claimed in claim 8, wherein the controller is respectively connected to the chip to be tested, the reference voltage module and the data processing module; the chip to be tested is internally provided with a digital-to-analog conversion module and an analog-to-digital conversion module that are interconnected, the reference voltage module is connected to the digital-to-analog conversion module and the analog-to-digital conversion module, and the data processing module is connected to the analog-to-digital conversion module.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the SOC chip ADC linearity testing method as described in any one of claims 1 to 7.

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