Bandwidth mismatch calibration system and method of time-interleaved architecture ADC

Abstract

The invention relates to the technical field of semiconductor integrated circuits, and discloses a bandwidth mismatch calibration system and method of a time-interleaved architecture ADC (Analog to Digital Converter). The system comprises N sub-ADCs, N bandwidth adjustment units and a controller. Firstly, a unified calibration signal is input into all sub-ADCs, and each sub-ADC samples the transition edge of the signal. The controller detects and determines a transition point error of each sub-ADC at the transition edge based on the sampling output of each sub-ADC. The controller calculates bandwidth adjustment code words for the corresponding sub-ADCs based on the difference between the error and a preset target value. The code word is used for driving the bandwidth adjusting unit to adjust the bandwidth of the corresponding sub-ADC, so that the bandwidths of all the sub-ADCs tend to be consistent through closed-loop feedback, and automatic and accurate calibration of bandwidth mismatch is realized.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and in particular to a calibration technique for bandwidth mismatch in analog-to-digital converters (ADCs) using time-interleaved (TI) architectures. Background Technology

[0002] The descriptions in this section are intended only to provide background information for the implementation of this application and should not be construed as an admission or implication that they constitute prior art.

[0003] With the ever-increasing demands for data transmission rates in modern communications, radar, and testing equipment, high-speed, high-precision analog-to-digital converters (ADCs) have become crucial components. The function of an ADC is to convert analog signals from the real world into digital signals for subsequent digital signal processing. Among the various performance indicators of an ADC, bandwidth (BW) is a core parameter, defining the frequency range of input analog signals that the ADC can effectively process. Typically, bandwidth is defined as the frequency point at which the amplitude of the input signal attenuates to approximately 70.7% (i.e., -3dB). If the frequency of the input signal exceeds the ADC's bandwidth, its amplitude and detail will be severely attenuated, resulting in signal distortion.

[0004] To overcome the bottleneck of sampling rate in a single ADC, the time-interleaved (TI) architecture is widely adopted. This architecture achieves an equivalent high-speed sampling rate N times that of the sub-ADCs by using N lower-speed sub-ADCs in parallel and assigning a reasonable sampling clock phase to each sub-ADC.

[0005] However, in actual integrated circuit manufacturing, due to variations and uncertainties in process technology, voltage, and temperature, it is difficult to achieve completely consistent analog characteristics among the parallel-operating sub-ADCs. Bandwidth mismatch is a common non-ideal effect, where the actual bandwidth of each sub-ADC differs. When a high-frequency analog signal is input to a TI-ADC, the wider-bandwidth sub-ADC attenuates it less, while the narrower-bandwidth sub-ADC attenuates it more. Ultimately, when these sampled signals, attenuated to varying degrees, are combined in the digital domain, harmonic distortion and spurious signals are introduced, severely degrading the overall dynamic performance of the TI-ADC, such as spurious-free dynamic range (SFDR).

[0006] To address the bandwidth mismatch problem, most existing technologies employ digital domain calibration schemes. These schemes typically analyze the signal at the digital backend to detect the error introduced by the bandwidth mismatch, and then compensate the sampled data using a digital finite impulse response (FIR) filter. However, these traditional digital calibration schemes have several drawbacks. First, to achieve accurate compensation, the filter coefficients of the FIR filter need to be calculated, which often involves complex mathematical operations, such as matrix inversion, making it computationally difficult and resource-intensive. Second, for an N-channel TI-ADC, N-1 FIR filters are typically required for perfect matching; as the number of channels N increases, the chip area and power consumption of the calibration circuit also increase significantly. Furthermore, some schemes require the input signal to be a specific single-tone signal to simplify the mathematical model for coefficient calculation. However, in practical applications, generating high-frequency, high-purity single-tone signals requires additional dedicated circuitry, increasing the overall system cost and design complexity. Summary of the Invention

[0007] One objective of this application is to provide a bandwidth mismatch calibration system and method for a time-interleaved architecture ADC, aiming to solve the technical problems of high mathematical computational complexity, large hardware overhead, and dependence on specific single-tone signals in existing bandwidth mismatch calibration schemes for time-interleaved architecture ADCs.

[0008] This application discloses a bandwidth mismatch calibration system for a time-interleaved architecture ADC. The time-interleaved architecture ADC includes N sub-ADCs operating at the same sampling frequency and with equal sampling phase intervals, where N is an integer greater than 1. The system also includes a controller and N bandwidth adjustment units.

[0009] The N bandwidth adjustment units correspond to the N sub-ADCs respectively, and the bandwidth adjustment units are used to adjust the bandwidth of the corresponding sub-ADC according to the received bandwidth adjustment codeword;

[0010] The input terminals of the N sub-ADCs are coupled to a calibration signal, and each of the N sub-ADCs can sample the transition edge of the calibration signal;

[0011] The controller is configured to receive the sampled digital signals output by the N sub-ADCs, detect and determine the transition point error obtained by each sub-ADC at the transition edge of the calibration signal, and for at least one of the N sub-ADCs, calculate a bandwidth adjustment codeword corresponding to the sub-ADC based on the difference between the transition point error of the sub-ADC and a preset target value, and output the bandwidth adjustment codeword to the bandwidth adjustment unit corresponding to the sub-ADC to adjust the bandwidth of the sub-ADC, thereby making the bandwidths of the N sub-ADCs more consistent and realizing bandwidth mismatch calibration; wherein, the transition point is the sampling point of the sub-ADC whose sampled value is closest to the preset reference value, and the transition point error is the difference between the sampled value of the sub-ADC at the transition point and the preset reference value.

[0012] In a preferred embodiment, the calibration signal is generated by dividing a high-speed sampling clock by a ratio coprime to N, and the clock signals of the N sub-ADCs are obtained by the high-speed sampling clock with different phase shifts.

[0013] In a preferred embodiment, a multiplexer is further included, wherein the N input terminals of the multiplexer are respectively coupled to the output terminals of the N sub-ADCs, and the digital signals output by the N sub-ADCs after sampling are combined into a single digital signal and transmitted to the controller.

[0014] In a preferred embodiment, the transition edge is a rising edge and / or a falling edge; the preset reference value is zero;

[0015] When determining the transition point error of each sub-ADC, the controller performs a long-term average of the multiple transition point error values ​​obtained by sampling multiple transition edges of each sub-ADC to reduce the impact of noise.

[0016] In a preferred embodiment, the preset target value is determined based on the average value of the transition point errors of the N sub-ADCs, thereby adjusting the bandwidth of the N sub-ADCs in opposite directions.

[0017] In a preferred embodiment, the preset target value is set as the transition point error value of a specific sub-ADC among the N sub-ADCs, thereby adjusting the bandwidth of the remaining sub-ADCs toward the bandwidth of that specific sub-ADC.

[0018] In a preferred embodiment, the bandwidth adjustment codeword is calculated as an iterative process executed by the controller, including the following steps:

[0019] a) In each iteration, calculate an adjustment value, where the adjustment value = (transition point error - preset target value) × gain, and the gain is a coefficient greater than 0 and less than 1.

[0020] b) Add the amount to be adjusted to a cumulative value;

[0021] c) If the current absolute value of the cumulative value is sufficient to match at least one minimum unit of bandwidth adjustment codeword, then generate the corresponding bandwidth adjustment codeword output and subtract an amount equivalent to the generated bandwidth adjustment codeword from the cumulative value to update the cumulative value;

[0022] Continue iterating through steps a) to c) until calibration is complete.

[0023] This application also discloses a bandwidth mismatch calibration method for a time-interleaved architecture ADC, wherein the ADC includes N sub-ADCs operating at the same sampling frequency and with equal sampling phase intervals, where N is an integer greater than 1, and the method includes:

[0024] A calibration signal is provided to the input terminals of the N sub-ADCs, and it is ensured that all N sub-ADCs can sample the transition edge of the calibration signal;

[0025] The N sub-ADCs sample the transition edge of the calibration signal. Based on the digital signal of the sampled values ​​output by the N sub-ADCs, the transition point error obtained by each sub-ADC at the transition edge of the calibration signal is detected and determined. The transition point is the sampling point of the sub-ADC whose sampled value is closest to the preset reference value. The transition point error is the difference between the sampled value of the sub-ADC at the transition point and the preset reference value.

[0026] For at least one of the N sub-ADCs, based on the difference between the transition point error of the sub-ADC and the preset target value, a bandwidth adjustment codeword corresponding to the sub-ADC is calculated, and the bandwidth of the sub-ADC is adjusted according to the bandwidth adjustment codeword, so that the bandwidth among the N sub-ADCs tends to be consistent, thereby realizing the calibration of bandwidth mismatch.

[0027] In a preferred embodiment, the calibration signal is generated by dividing a high-speed sampling clock by a ratio coprime to N, and the clock signals of the N sub-ADCs are obtained by the high-speed sampling clock with different phase shifts.

[0028] In a preferred embodiment, the transition edge is a rising edge and / or a falling edge; the preset reference value is zero.

[0029] In the embodiments of this application, the bandwidth mismatch problem in the frequency domain is cleverly transformed into an easily measurable amplitude error problem in the digital domain, namely the transition point error. This avoids the high-complexity mathematical operations required for digital FIR filter compensation in traditional schemes, such as matrix inversion. By directly adjusting the bandwidth in the analog domain, this scheme does not require the use of a large number of digital filters, which significantly reduces the power consumption and area overhead of the calibration circuit. At the same time, it avoids the additional circuit cost and difficulty of generating high-precision single-tone signals to simplify mathematical analysis. Ultimately, it achieves a low-cost, low-complexity, and efficient automatic calibration, which significantly improves key performance indicators such as the spurious-free dynamic range of the time-interleaved ADC.

[0030] Furthermore, by dividing the high-speed sampling clock to generate the calibration signal, and ensuring that the division ratio is coprime to the number of sub-ADCs N, it can be ensured that the transition edge of the calibration signal can be sampled equally by each sub-ADC. This establishes a stable and predictable sampling relationship, effectively avoiding the clock drift problem that may be introduced by using an asynchronous signal source, thereby guaranteeing the accuracy of the transition point error measurement and the reliability of the calibration process.

[0031] Furthermore, by averaging the error values ​​at multiple transition points obtained from sampling at multiple transition edges of each sub-ADC over a long period in the controller, the interference of random noise in the system on the measurement results can be effectively suppressed. This averaging method can extract the true and constant error components caused by bandwidth mismatch, thereby improving the accuracy and stability of bandwidth adjustment codeword calculation and avoiding unnecessary fluctuations in the calibration system due to noise.

[0032] Furthermore, by setting the preset target value as the average of the transition point errors of the N sub-ADCs, the bandwidth of all sub-ADCs can be adjusted to converge towards a common intermediate value. This counter-adjustment strategy can typically achieve bandwidth matching of all channels with a small adjustment step size, which helps to accelerate the convergence of the calibration process and is an efficient way to achieve global bandwidth matching.

[0033] Furthermore, by setting a preset target value as the transition point error value of a specific sub-ADC, a master-slave calibration mode can be implemented, which adjusts the bandwidth of all other sub-ADCs to align with the bandwidth of that specific sub-ADC. When there is a reference channel in the system with known optimal performance, this method can accurately replicate the bandwidth characteristics of that channel to all other channels to achieve overall performance optimization.

[0034] Furthermore, by introducing a "cumulative value," even very small adjustments calculated in a single instance are not discarded but accumulated. The system only adjusts when these small adjustments accumulate to a level sufficient to trigger a minimum codeword change. This is equivalent to integrating the error over time, overcoming the resolution limitations of hardware quantization. This results in a final bandwidth matching accuracy higher than the physical resolution of the adjusted codeword, achieving more precise bandwidth consistency between sub-ADCs. The accumulation mechanism naturally acts as a low-pass filter. It is insensitive to single, random noise or measurement jitter because these random errors cancel each other out during accumulation. Only persistent, systematic errors representing true bandwidth mismatch are effectively accumulated. This makes the calibration process converge more smoothly and stably, avoiding oscillations caused by overly frequent or drastic adjustments, and ensuring the reliability of the calibration results.

[0035] The various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as having been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; it is impossible to use both simultaneously. Feature E can be technically combined with feature C. Therefore, the solution A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution A+B+C+E should be considered as having been recorded. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of a bandwidth mismatch calibration system for a time-interleaved architecture ADC according to an embodiment of this application;

[0037] Figure 2 This is a schematic diagram of an ideal square wave clock signal and its signal shape after passing through a sub-ADC.

[0038] Figure 3 This is a schematic diagram of two sub-ADCs sampling the calibration signal under bandwidth mismatch conditions according to an embodiment of this application;

[0039] Figure 4 and Figure 5 This is a simulation result diagram based on an embodiment of this application. Detailed Implementation

[0040] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0042] The first embodiment of this application relates to a bandwidth mismatch calibration system for a time-interleaved architecture ADC. The time-interleaved architecture ADC includes N sub-ADCs operating at the same sampling frequency and with equal sampling phase intervals, where N is an integer greater than 1. The bandwidth mismatch calibration system also includes a multiplexer, a controller, and N bandwidth adjustment units.

[0043] Each sub-ADC samples the input analog signal according to its own clock signal. Each sampling forms a sampling point with a sample value, which is output as a digital signal.

[0044] The N bandwidth adjustment units correspond to the N sub-ADCs. Each bandwidth adjustment unit adjusts the bandwidth of its corresponding sub-ADC based on the received bandwidth adjustment codeword. The bandwidth adjustment units can be combined within the sub-ADCs or operate independently of their respective sub-ADCs.

[0045] The inputs of N sub-ADCs are coupled to a calibration signal. To ensure that all N sub-ADCs can sample the transition edge of the calibration signal, in one embodiment, the calibration signal can be generated by dividing a high-speed sampling clock, with the division ratio being coprime to N. The clock signals of the N sub-ADCs are obtained by different phase shifts of the high-speed sampling clock. In other embodiments, in addition to the clock signal, NRZ signals, PAM signals, etc., can also be used.

[0046] The multiplexer's N inputs are coupled to the outputs of N sub-ADCs, merging the digital signals sampled by the N sub-ADCs into a single digital signal that is transmitted to the controller. The multiplexer is optional; if not used, the controller can directly receive the digital signals output by each sub-ADC.

[0047] The controller is configured to detect and determine the transition point error of each sub-ADC at the transition edge of the calibration signal based on the received digital signal. For one or more sub-ADCs among N sub-ADCs (preferably, all N sub-ADCs are adjusted simultaneously), based on the difference between the transition point error of that sub-ADC and a preset target value, a bandwidth adjustment codeword corresponding to that sub-ADC is calculated, and the bandwidth adjustment codeword is output to the bandwidth adjustment unit corresponding to that sub-ADC to adjust the bandwidth of that sub-ADC, thereby making the bandwidths of the N sub-ADCs more consistent and achieving bandwidth mismatch calibration. Here, the transition point is the sampling point of the sub-ADC whose sampled value is closest to the preset reference value, and the transition point error is the difference between the sampled value of the sub-ADC at the transition point and the preset reference value. In the presence of noise, there may be sampling points with both positive and negative values ​​(but all near the preset reference value). If there are two sampling points closest to the preset reference value, one can be selected according to a certain rule (e.g., prioritizing positive values). The transition edge is a rising edge and / or a falling edge. The preset reference value can be zero or other fixed values.

[0048] Optionally, in one embodiment, when determining the transition point error of each sub-ADC, the controller performs a long-term average of multiple transition point error values ​​obtained by sampling multiple transition edges for each sub-ADC to reduce the impact of noise.

[0049] Optionally, in one embodiment, the preset target value is determined based on the average of the transition point errors of the N sub-ADCs, thereby adjusting the bandwidth of the N sub-ADCs in opposite directions.

[0050] Optionally, in one embodiment, the preset target value is set as the transition point error value of a specific sub-ADC among the N sub-ADCs, thereby adjusting the bandwidth of the remaining sub-ADCs toward the bandwidth of that specific sub-ADC.

[0051] Optionally, in one embodiment, the bandwidth adjustment codeword is calculated as an iterative process executed by the controller, including the following steps:

[0052] a) In each iteration, calculate an adjustment value: Adjustment value = (Transition point error - Preset target value) × Gain, where the gain is a coefficient greater than 0 and less than 1. For example, the gain could be 2. -12 2 -10 0.01, 0.5, etc.

[0053] b) Add the amount to be adjusted to a cumulative value;

[0054] c) If the current absolute value of the cumulative value is sufficient to match at least one minimum unit of bandwidth adjustment codeword, then generate the corresponding bandwidth adjustment codeword output and subtract the amount equivalent to the generated bandwidth adjustment codeword from the cumulative value to update the cumulative value;

[0055] Continue iterating through steps a) to c) until calibration is complete.

[0056] In digital control systems, bandwidth adjustment codewords are quantized and have a minimum adjustment step (i.e., the bandwidth change corresponding to a change of one least significant bit (LSB) in the codeword). When the gain is very small (e.g., 2^32 GHz), -12 The adjustment value calculated as (transition point error - preset target value) × gain might be very small, possibly smaller than the minimum step size of the bandwidth adjustment codeword. Discarding this adjustment value would cause the calibration process to stall. By introducing a "cumulative value," even if the adjustment value calculated in a single step is very small, it will not be discarded but accumulated. The system will only adjust when these small adjustment values ​​accumulate to a level sufficient to trigger a codeword change of the minimum step size. This is equivalent to integrating the error over time, thus overcoming the resolution limitations imposed by hardware quantization.

[0057] In direct proportional control, a large gain is required to respond to small errors, but this can easily lead to system overshoot or even oscillation around the target value, especially in the presence of noise. Setting a small gain value increases system stability and avoids oscillations in bandwidth adjustments between sub-ADCs. The accumulation mechanism naturally acts as a low-pass filter. It is insensitive to single, random noise or measurement jitter because these random errors cancel each other out during accumulation. Only persistent, systematic errors representing true bandwidth mismatch are effectively accumulated. This makes the calibration process converge more smoothly and stably, avoiding oscillations caused by overly frequent or drastic adjustments, and ensuring the reliability of the calibration results.

[0058] Furthermore, the sampling and error detection processes of an ADC inevitably introduce noise. This noise causes the calculated "transition point error" to fluctuate with each measurement. The accumulated value is averaged over time over the error. High-frequency random noise components tend to zero during accumulation, while the true, constant mismatch error accumulates steadily. Therefore, this method effectively filters out measurement noise interference, allowing bandwidth adjustment decisions to be based on more reliable long-term trends rather than instantaneous noise, significantly enhancing the robustness of the entire calibration system.

[0059] Optionally, in one embodiment, the controller may be implemented by a dedicated digital logic circuit that performs the detection of bandwidth mismatch and the calculation of calibration codewords entirely in hardware. This digital logic circuit may include the following modules:

[0060] Data distribution module: Located at the input of the controller, it receives the combined digital signal from the multiplexer. This module redistributes the serial data stream to the internal processing channels of the corresponding sub-ADCs according to their sampling order.

[0061] Transition Point Detection Module: Each internal processing channel is equipped with a transition point detection module. This module is configured to monitor the input data stream, identify the zero-crossing point of the signal by comparing the sign change of the sampled values ​​(e.g., from negative to positive), and determine the sampled point closest to a preset reference value (e.g., zero level) as the transition point.

[0062] Error Calculation and Averaging Module: This module is connected to the transition point detection module and is used to calculate the difference between the transition point sample value and the preset reference value, thereby obtaining the instantaneous transition point error for that sampling period. In addition, this module may also include an accumulator and a shifter (for division operations) to accumulate and average multiple instantaneous error values ​​over a long period to reduce the impact of random noise.

[0063] Target value calculation module: This module collects the average transition point error calculated from all channels and calculates the target value according to a preset strategy. For example, it can be an adder and shifter network to calculate the average of all errors; or a multiplexer to select a specific sub-ADC error as the target value.

[0064] Codeword generation module: This module is the core computing unit of the controller. For each sub-ADC that needs to be adjusted, this module obtains its average error from the error calculation and averaging module, obtains the target value from the target value calculation module, and then performs the operation "codeword = (error value - target value) × gain" through a subtractor and a multiplier (or shifter, used to implement gain), finally generating the bandwidth adjustment codeword.

[0065] Timing control unit: Usually implemented in the form of a finite state machine (FSM), it is used to coordinate the workflow of all the above modules, ensure that data flows correctly and orderly between the modules, and control the timing of the final codeword output.

[0066] This all-hardware implementation offers fast processing speed and low power consumption, making it suitable for applications with stringent requirements for calibration speed and energy efficiency.

[0067] Optionally, in another embodiment, the controller may consist of an embedded microprocessor or digital signal processor (DSP) core, along with associated memory (RAM and ROM) and peripheral interfaces. The calibration algorithm is stored as firmware in read-only memory (ROM) and executed by the processor. Its workflow is as follows:

[0068] Data acquisition: The processor reads the digital signal blocks output by the multiplexer through the input interface and stores them in the internal random access memory (RAM).

[0069] Software Processing: The processor executes the calibration program stored in ROM. This program is implemented through a software algorithm: it iterates through the data in RAM, identifying the sampling points belonging to each sub-ADC according to the sampling order. It searches for sign changes in the data sequence of each sub-ADC, locates the transition point, and calculates its error compared to a preset reference value (zero). An accumulated variable is maintained in RAM for each sub-ADC to perform a moving average or cumulative average on the calculated transition point error. Based on a preset mode (e.g., averaging mode or specified target mode), the target value for this iteration is calculated. The bandwidth adjustment codeword for each sub-ADC is calculated using the formula: "Bandwidth Adjustment Codeword = (Transition Point Error - Preset Target Value) × Gain".

[0070] Codeword output: The processor writes the calculated bandwidth adjustment codeword into the registers of the output interface. These registers are directly connected to the bandwidth adjustment units of each sub-ADC.

[0071] This processor-based implementation offers exceptional flexibility. The logic of the calibration algorithm, such as the averaging method, target value selection strategy, and gain magnitude, can be modified and optimized through firmware updates without altering the hardware design.

[0072] Alternatively, in another embodiment, a hybrid implementation combining a hardware accelerator and a microcontroller can be used. The hardware accelerator handles the highest-speed, most computationally resource-intensive tasks. It connects directly to the multiplexer output, performing data allocation, transition point detection, and instantaneous error calculation in real time. It writes the calculated instantaneous error values ​​for each channel into a shared dual-port RAM. The microcontroller, acting as the main control unit, has a significantly reduced workload. Instead of processing the raw high-speed data stream, it periodically reads the pre-processed error values ​​from the shared memory. The microcontroller then executes subsequent algorithms, including averaging the error values, calculating the target value, generating the final bandwidth adjustment codeword, and outputting the codeword. In this architecture, the hardware accelerator ensures real-time processing of the high-speed data stream, while the microcontroller provides software-defined flexibility for complex control logic (such as adaptive gain adjustment, mode switching, etc.). This approach achieves a good balance between performance, power consumption, and flexibility.

[0073] Bandwidth adjustment units can be implemented in several ways. For example, a variable resistor consisting of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) can be used instead of a fixed resistor along the signal path that determines the circuit bandwidth. The MOSFET is biased in the linear region (or bipolar junction transistor region), and its equivalent resistance changes with its gate voltage. The bandwidth adjustment codeword can be converted into a corresponding gate control voltage using a small digital-to-analog converter (DAC). Bandwidth is typically inversely proportional to the RC product. When the bandwidth adjustment codeword changes, the gate voltage of the MOSFET changes accordingly, altering its equivalent resistance R, thereby adjusting the RC time constant and ultimately achieving precise bandwidth adjustment. Increasing the codeword decreases the resistance, thus increasing the bandwidth, and vice versa. Alternatively, a capacitor array consisting of multiple small capacitors and switches can be connected in parallel at critical nodes in the circuit (such as the load side of an amplifier). Each switch is controlled by a single bit of the bandwidth adjustment codeword. The total capacitance of the circuit is the sum of the capacitances that are conducting in all parallel branches. By controlling which switches are closed using the bandwidth adjustment codeword, the total capacitance C of that node can be precisely changed. Since bandwidth is typically inversely proportional to capacitance C (e.g., BW∝1 / RC or BW∝gm / C), changing the total capacitance value effectively adjusts the bandwidth. For example, in the amplifier or buffer circuit that forms the front end of a sub-ADC, the bias current source can be adjusted by a programmable digital control circuit. The bandwidth adjustment codeword directly controls the magnitude of the current source's output current. The transconductance (gm) of the amplifier is typically proportional to its bias current. Since the amplifier's bandwidth is proportional to gm / C, adjusting the bias current directly changes gm, thus adjusting the circuit's bandwidth. Increasing the bias current increases the transconductance, thereby widening the bandwidth, but this also increases power consumption.

[0074] To more clearly illustrate the technical solution of this application, the bandwidth mismatch calibration system of this application will be further described in detail below using a time-interleaved ADC system containing two sub-ADCs (N=2) as an example.

[0075] The system architecture of this embodiment is as follows: Figure 1 As shown, it mainly includes sub-ADC1, sub-ADC2, a multiplexer, and a bandwidth error detection module that acts as a controller. Each sub-ADC (sub-ADC1 and sub-ADC2) integrates a bandwidth adjustment unit, which receives digital bandwidth adjustment codewords from the controller and adjusts the analog bandwidth of its respective sub-ADC accordingly.

[0076] Before calibration begins, the system first configures the clock. There is a high-frequency system sampling clock, and the operating clocks for sub-ADC1 and sub-ADC2 are also present. Figure 1Clock 1 and Clock 2 in the above are obtained by different phase shifts of the high-frequency sampling clock. They operate at the same sampling frequency and their sampling phases differ by 180 degrees to achieve equally spaced sampling. In another embodiment, the time-interleaved architecture ADC can contain more than two sub-ADCs, for example, three sub-ADCs, whose clocks differ by 120 degrees from each other.

[0077] The specific steps of the calibration process are as follows:

[0078] 1. Input Calibration Signal: A calibration signal, which can be a clock signal, is provided to the common input terminal of the system. In this embodiment, the calibration signal is obtained by dividing the aforementioned high-frequency system sampling clock, and the division ratio is coprime to the number of sub-ADCs (N=2). For example, a clock divided by 3 or 5 can be used. This coprime relationship ensures that the rising and falling edges (i.e., transition edges) of the calibration signal can be uniformly sampled by sub-ADC1 and sub-ADC2 over a sufficiently long period of time. In this embodiment, only the rising edge of the calibration signal can be sampled. In other embodiments, only the falling edge of the calibration signal can be used, or both the rising and falling edges of the calibration signal can be sampled.

[0079] 2. Sampling and Combining: The analog calibration signal is input to sub-ADC1 and sub-ADC2. Because each sub-ADC's input stage circuit has low-pass filtering characteristics, the steep transition edge of the ideal square wave clock signal will gradually change after passing through the sub-ADC, forming a transition slope with a certain gradient (e.g., ...). Figure 2 (As shown). Sub-ADC1 and sub-ADC2 alternately sample this ramped signal according to their respective sampling clocks. The two parallel digital signals obtained after sampling are sent to a multiplexer, combined into a single high-speed digital signal stream, and transmitted to the controller.

[0080] 3. Error Detection and Calculation: After receiving the digital signal stream, the controller performs the following operations: First, the controller identifies which sampling points come from sub-ADC1 and which come from sub-ADC2 based on the data source order. Next, the controller detects transition points in the data sequence of each sub-ADC. A transition point is defined as the sampling value that is closest to a preset reference value (zero level in this embodiment).

[0081] In a perfect clock signal, the rising edge jumps instantaneously from low to high, precisely crossing the center "0". In reality, after the signal is filtered by the sub-ADC, this transition edge becomes gentler, forming a ramp. The sub-ADC's sampling clock will fall somewhere on this "ramp" of the transition edge. The voltage value captured by the sub-ADC at that moment and converted into a digital quantity is called the "transition point captured by the sub-ADC". Due to the influence of sampling timing and noise, this point is unlikely to fall exactly on the ideal "0". Therefore, the value of this "transition point" is usually a value close to 0. Figure 3 In this context, the difference between this value and the ideal zero point is labeled as "err1" and "err2".

[0082] like Figure 3 As shown, due to bandwidth mismatch, it is assumed that the bandwidth of sub-ADC1 is smaller and the bandwidth of sub-ADC2 is larger. This means that the transition slope generated by sub-ADC1 is gentler, while the transition slope generated by sub-ADC2 is steeper. Therefore, in the case of a small offset at the sampling time, the difference between the transition point sampled by sub-ADC1 and the zero level (denoted as transition point error err1) will be smaller than the transition point error err2 sampled by sub-ADC2.

[0083] To eliminate the influence of random noise in the system, the controller accumulates and averages the errors err1 and err2 detected over a long period of time to obtain stable average error values ​​err1_avg and err2_avg.

[0084] 4. Adjustment Codeword Generation and Update: The controller calculates and updates the bandwidth adjustment codeword based on the average error value using an iterative adjustment strategy based on cumulative error. This strategy sets a "cumulative value" variable (initially 0) within the controller for each sub-ADC's adjustment loop to achieve calibration accuracy exceeding the minimum step size of the adjustment unit. The specific steps are as follows:

[0085] a) Calculating the target value and the variable to be adjusted: In this embodiment, the controller adopts a counter-adjustment strategy. First, a target value is calculated, which is set as the average of two average errors, i.e., target value = (err1_avg + err2_avg) / 2. Then, a "variable to be adjusted" is calculated for each sub-ADC:

[0086] The adjustment value of sub-ADC1 = (err1_avg - target value) × gain

[0087] The adjustment value of sub-ADC2 = (err2_avg - target value) × gain

[0088] Here, the gain is a coefficient less than 1 (in this embodiment, the gain is 2). -11This is done to ensure the stability of convergence. The "amount to be adjusted" represents the ideal adjustment range expected in this iteration.

[0089] b) Accumulate the adjustment quantity: The controller adds the calculated adjustment quantity to the cumulative value of the corresponding sub-ADC:

[0090] Cumulative value 1 = Cumulative value 1 + Adjustment amount of sub-ADC1

[0091] Cumulative value 2 = Cumulative value 2 + Adjustment amount of sub-ADC2

[0092] c) Determine, generate codewords, and update the cumulative value: The bandwidth adjustment codeword is a quantized integer with a minimum adjustment unit (LSB). The controller determines the updated cumulative value. If its absolute value is sufficient to match at least one LSB codeword change, it generates the corresponding bandwidth adjustment codeword (e.g., codeword 1 and codeword 2) and outputs it to the bandwidth adjustment unit. Subsequently, the equivalent amount of the generated codeword is subtracted from the cumulative value, and the remaining amount is carried over to the next iteration for further accumulation.

[0093] For example, suppose one unit of codeword is equivalent to a value of 1.0. If the current cumulative value 1 is -0.8, which is insufficient to generate a codeword, then no codeword is output this time, and the cumulative value remains at -0.8. In the next iteration, if the calculated adjustment amount is -0.5, then the new cumulative value 1 becomes -1.3. At this point, its absolute value has exceeded 1.0, so the controller generates a "codeword 1" output of -1 unit, and simultaneously updates the cumulative value 1 to -1.3 - (-1.0) = -0.3.

[0094] 5. Feedback Adjustment and Precise Convergence: The calculated codewords 1 and 2 are fed back to the bandwidth adjustment units within sub-ADC1 and sub-ADC2, respectively. Since err1_avg is less than the target value, its accumulated value tends to be negative, resulting in a negative codeword and increasing the bandwidth of sub-ADC1. Simultaneously, since err2_avg is greater than the target value, its accumulated value tends to be positive, resulting in a positive codeword and decreasing the bandwidth of sub-ADC2.

[0095] Steps 1 to 5 above constitute a closed-loop feedback. Through this iterative feedback based on accumulated values, even if the amount to be adjusted in a single calculation is too small to directly generate a codeword, the error information it carries will not be lost, but will be "memorized" by the system in the accumulated value until it accumulates to a level sufficient to trigger an effective adjustment. This loop will continuously iterate, allowing the bandwidths of sub-ADC1 and sub-ADC2 to be precisely adjusted. Ultimately, the average errors err1_avg and err2_avg of both will converge highly to the target value.

[0096] The simulation results of this embodiment are as follows: Figure 4 and Figure 5 As shown. Figure 4 The horizontal axis represents the number of iterations, and the vertical axis represents the bandwidth. Figure 4 As can be seen, the bandwidths of sub-ADC1 and sub-ADC2 quickly converge, and eventually the bandwidth difference converges to a minimum value, such as 40MHz. This value is less than the minimum adjustment step size of the bandwidth adjustment unit (such as 100MHz), marking the completion of the calibration process.

[0097] Through the above embodiments, the calibration method of this application transforms the complex bandwidth mismatch problem into an easily manageable amplitude error problem, eliminating the need for complex digital filters and matrix inversion operations. After calibration, the performance of the entire time-interleaved ADC system is significantly improved. Figure 5 The experimental results show that the spurious-free dynamic range (SFDR) can be improved from 42.39 dB to 60.72 dB without calibration, achieving a performance improvement of approximately 18 dB. Figure 5 The red line represents the data before calibration, and the blue line represents the data after calibration. When a sinusoidal signal is input to the ADC, ideally there should only be a high blue line. However, due to bandwidth mismatch in the sub-ADC, a second high red line will appear. After calibration, in the blue spectrum, the blue line at the position of the second high red line is significantly reduced, reaching a normal noise level.

[0098] The second embodiment of this application relates to a bandwidth mismatch calibration method for a time-interleaved architecture ADC, the ADC comprising N sub-ADCs operating at the same sampling frequency and with equal sampling phase intervals, where N is an integer greater than 1, the method comprising the following steps:

[0099] In step 101, a calibration signal (analog signal) is provided to the input terminals of the N sub-ADCs, and it is ensured that the N sub-ADCs can sample the transition edge of the calibration signal.

[0100] Next, in step 102, the N sub-ADCs sample the transition edges of the calibration signal. Based on the digital output signals of the N sub-ADCs (i.e., the digital signals representing the sampling results), the transition point error obtained by each sub-ADC at the transition edge of the calibration signal is detected and determined. The transition point is the point in the sub-ADC's sampled values ​​that is closest to the preset reference value, and the transition point error is the difference between the sub-ADC's sampled value at the transition point and the preset reference value. The outputs of each sub-ADC can be combined into one signal in a multiplexer for post-processing, or the signals can be obtained from each sub-ADC separately and processed. The transition edge can be a rising edge and / or a falling edge. The preset reference value can be zero or other fixed values.

[0101] Then proceed to step 103. For at least one of the N sub-ADCs, based on the difference between the transition point error of the sub-ADC and the preset target value, calculate the bandwidth adjustment codeword corresponding to the sub-ADC, and adjust the bandwidth of the sub-ADC according to the bandwidth adjustment codeword, so that the bandwidth among the N sub-ADCs tends to be consistent, thereby realizing the calibration of bandwidth mismatch.

[0102] Optionally, in one embodiment, the calibration signal is generated by dividing the high-speed sampling clock by a ratio coprime to N, and the clock signals of the N sub-ADCs are obtained by different phase offsets of the high-speed sampling clock. In other embodiments, in addition to clock signals, NRZ signals, PAM signals, etc., can also be used.

[0103] The first embodiment is a system implementation corresponding to this embodiment. The technical details in the first embodiment can be applied to this embodiment, and the technical details in this embodiment (such as the iterative adjustment method of the bandwidth adjustment codeword in the first embodiment) can also be applied to the first embodiment.

[0104] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0105] This specification includes combinations of various embodiments described herein. Individual references to embodiments (e.g., “one embodiment”, “some embodiments”, or “preferred embodiments”) do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated to be mutually exclusive or are readily apparent to those skilled in the art. It should be noted that the word “or” is used in a non-exclusive sense throughout this specification unless the context explicitly indicates or requires it.

[0106] All references to this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the contents of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A bandwidth mismatch calibration system for a time-interleaved architecture ADC, wherein the time-interleaved architecture ADC comprises N sub-ADCs operating at the same sampling frequency and with equal sampling phase intervals, where N is an integer greater than 1, characterized in that, The system also includes a controller and N bandwidth adjustment units; The N bandwidth adjustment units correspond to the N sub-ADCs respectively, and the bandwidth adjustment units are used to adjust the bandwidth of the corresponding sub-ADC according to the received bandwidth adjustment codeword; The input terminals of the N sub-ADCs are coupled to a calibration signal, and each of the N sub-ADCs can sample the transition edge of the calibration signal; The controller is configured to receive the sampled digital signals output by the N sub-ADCs, detect and determine the transition point error obtained by each sub-ADC at the transition edge of the calibration signal, and for at least one of the N sub-ADCs, calculate a bandwidth adjustment codeword corresponding to the sub-ADC based on the difference between the transition point error of the sub-ADC and a preset target value, and output the bandwidth adjustment codeword to the bandwidth adjustment unit corresponding to the sub-ADC to adjust the bandwidth of the sub-ADC, thereby making the bandwidths of the N sub-ADCs more consistent and realizing bandwidth mismatch calibration; wherein, the transition point is the sampling point of the sub-ADC whose sampled value is closest to the preset reference value, and the transition point error is the difference between the sampled value of the sub-ADC at the transition point and the preset reference value.

2. The bandwidth mismatch calibration system for a time-interleaved architecture ADC as described in claim 1, characterized in that, The calibration signal is generated by dividing the high-speed sampling clock, with the division ratio being coprime to N. The clock signals of the N sub-ADCs are obtained by the high-speed sampling clock through different phase shifts.

3. The bandwidth mismatch calibration system for a time-interleaved architecture ADC as described in claim 1, characterized in that, It also includes a multiplexer, whose N input terminals are respectively coupled to the output terminals of the N sub-ADCs, and combines the digital signals output by the N sub-ADCs after sampling into a single digital signal for transmission to the controller.

4. The bandwidth mismatch calibration system for a time-interleaved architecture ADC as described in claim 1, characterized in that, The transition edge is a rising edge and / or a falling edge; the preset reference value is zero; When determining the transition point error of each sub-ADC, the controller performs a long-term average of the multiple transition point error values ​​obtained by sampling multiple transition edges of each sub-ADC to reduce the impact of noise.

5. The bandwidth mismatch calibration system for a time-interleaved architecture ADC as described in claim 1, characterized in that, The preset target value is determined based on the average value of the transition point error of the N sub-ADCs, thereby adjusting the bandwidth of the N sub-ADCs in opposite directions.

6. The bandwidth mismatch calibration system for a time-interleaved architecture ADC as described in claim 1, characterized in that, The preset target value is set as the transition point error value of a specific sub-ADC among the N sub-ADCs, thereby adjusting the bandwidth of the remaining sub-ADCs toward the bandwidth of that specific sub-ADC.

7. The bandwidth mismatch calibration system for a time-interleaved architecture ADC as described in any one of claims 1-6, characterized in that, The bandwidth adjustment codeword is calculated as an iterative process executed by the controller, including the following steps: a) In each iteration, calculate an adjustment amount, the adjustment amount = (transition point error - preset target value) × gain, where the gain is a coefficient greater than 0 and less than 1; b) Add the amount to be adjusted to a cumulative value; c) If the current absolute value of the cumulative value is sufficient to match at least one minimum unit of bandwidth adjustment codeword, then generate the corresponding bandwidth adjustment codeword output and subtract an amount equivalent to the generated bandwidth adjustment codeword from the cumulative value to update the cumulative value; Continue iterating through steps a) to c) until calibration is complete.

8. A bandwidth mismatch calibration method for a time-interleaved architecture ADC, wherein the ADC comprises N sub-ADCs operating at the same sampling frequency and with equal sampling phase intervals, where N is an integer greater than 1, characterized in that, The method includes: A calibration signal is provided to the input terminals of the N sub-ADCs, and it is ensured that all N sub-ADCs can sample the transition edge of the calibration signal; The N sub-ADCs sample the transition edge of the calibration signal. Based on the digital signal of the sampled values ​​output by the N sub-ADCs, the transition point error obtained by each sub-ADC at the transition edge of the calibration signal is detected and determined. The transition point is the sampling point of the sub-ADC whose sampled value is closest to the preset reference value. The transition point error is the difference between the sampled value of the sub-ADC at the transition point and the preset reference value. For at least one of the N sub-ADCs, based on the difference between the transition point error of the sub-ADC and the preset target value, a bandwidth adjustment codeword corresponding to the sub-ADC is calculated, and the bandwidth of the sub-ADC is adjusted according to the bandwidth adjustment codeword, so that the bandwidth among the N sub-ADCs tends to be consistent, thereby realizing the calibration of bandwidth mismatch.

9. The bandwidth mismatch calibration method for a time-interleaved architecture ADC as described in claim 8, characterized in that, The calibration signal is generated by dividing the high-speed sampling clock, with the division ratio being coprime to N. The clock signals of the N sub-ADCs are obtained by the high-speed sampling clock through different phase shifts.

10. The bandwidth mismatch calibration method for a time-interleaved architecture ADC as described in claim 8 or 9, characterized in that, The transition edge is a rising edge and / or a falling edge; the preset reference value is zero.

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