Control circuit, method and chip of analog-to-digital converter

Abstract

The embodiment of the invention provides a control circuit and method of an analog-to-digital converter and a chip, the circuit comprises the analog-to-digital converter, a buffer, a test circuit and a central processor, the analog-to-digital converter generates a conversion completion signal after a first conversion result is obtained after channel conversion is completed, and the test circuit controls the analog-to-digital converter based on the conversion completion signal. Checking whether a second conversion result currently stored in the register corresponding to the channel is read by the central processing unit, if the second conversion result is read, generating a write signal, writing the first conversion result into the register, and if the second conversion result is not read, storing the first conversion result and the channel number of the channel corresponding to the first conversion result into a buffer, therefore, the condition that the first conversion result is stored in the register and the unread second conversion result is covered under the condition that the second conversion result currently stored in the register is not read by the central processing unit is avoided, and reliable storage of the conversion result data of the analog-to-digital converter is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a control circuit, method and chip of an analog-to-digital converter. Background Art

[0002] Analog-to-Digital Converter (ADC) plays a vital role in modern electronic systems. Its main function is to convert analog signals into digital signals. ADC usually has multiple conversion channels, which enable ADC to sample and convert multiple analog signals simultaneously or sequentially, thus meeting the needs of multi-signal processing in complex systems.

[0003] In common implementations, each ADC conversion channel is equipped with an independent register to store its own conversion results. Although this design simplifies data management, it may expose some potential problems under high sampling rates or heavy system loads. Specifically, since the central processing unit (CPU) may be delayed when processing other tasks, it may not be able to read the current conversion result stored in the register in time. In this case, a new conversion result may be quickly generated and overwrite the current conversion result, causing data loss or confusion of results. Summary of the invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a control circuit, method and chip for an analog-to-digital converter that overcomes the above problems or at least partially solves the above problems.

[0005] In order to solve the above problems, an embodiment of the present invention discloses a control circuit of an analog-to-digital converter, the control circuit comprising: an analog-to-digital converter, a buffer, a check circuit and a central processing unit;

[0006] The analog-to-digital converter comprises at least one channel and at least one register, one channel corresponds to one register; the analog-to-digital converter is used to generate a conversion completion signal after the channel conversion is completed to obtain a first conversion result, and to generate an interrupt signal when the first conversion result is stored in the buffer; the register is used to store the first conversion result of the corresponding channel based on a write signal;

[0007] The checking circuit is used to check whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit based on the conversion completion signal; if the second conversion result has been read by the central processing unit, a write signal is generated; if the second conversion result has not been read by the central processing unit, the first conversion result is stored in the buffer;

[0008] The central processing unit is used for reading the first conversion result from the register when the interrupt signal is not detected; and reading the first conversion result from the buffer when the interrupt signal is detected.

[0009] Optionally, the verification circuit is further configured to store the channel number of the channel corresponding to the first conversion result in the buffer if the second conversion result is not read by the central processing unit.

[0010] Optionally, the central processing unit is further configured to read the second conversion result from the register when the interrupt signal is detected.

[0011] Optionally, the verification circuit is used to obtain a read flag bit of the register from the register; and determine whether the second conversion result has been read by the central processing unit based on the read flag bit.

[0012] Optionally, the checking circuit is used to set the overflow flag position of the register to invalid if the second conversion result has been read by the central processing unit; and to set the overflow flag position of the register to valid if the second conversion result has not been read by the central processing unit.

[0013] Optionally, the checking circuit is used to control the write pointer of the buffer to remain unchanged if the second conversion result has been read by the central processing unit;

[0014] If the second conversion result is not read by the central processing unit, the write pointer of the buffer is controlled to increase by one, and the first conversion result is stored in the buffer space corresponding to the write pointer.

[0015] Accordingly, an embodiment of the present invention discloses a control method for an analog-to-digital converter, which is applied to the control circuit as described above. The method includes:

[0016] The analog-to-digital converter generates a conversion completion signal after the channel conversion is completed to obtain a first conversion result, and generates an interrupt signal when the first conversion result is stored in the buffer; the register is used to store the first conversion result of the corresponding channel based on the write signal;

[0017] Based on the conversion completion signal, the verification circuit verifies whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit; if the second conversion result has been read by the central processing unit, a write signal is generated; if the second conversion result has not been read by the central processing unit, the first conversion result is stored in the buffer;

[0018] The first conversion result is read from the register by the central processing unit when the interrupt signal is not detected; and the first conversion result is read from the buffer when the interrupt signal is detected.

[0019] Optionally, the method further includes:

[0020] If the second conversion result is not read by the central processing unit through the checking circuit, the channel number of the channel corresponding to the first conversion result is stored in the buffer.

[0021] Optionally, the method further includes:

[0022] The second conversion result is read from the register by the central processing unit when the interrupt signal is detected.

[0023] Optionally, the checking, by the checking circuit based on the conversion completion signal, whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit includes:

[0024] Obtaining a read flag bit of the register from the register based on the conversion completion signal by the inspection circuit;

[0025] It is determined whether the second conversion result has been read by the central processing unit according to the read flag bit.

[0026] Optionally, the method further includes:

[0027] If the second conversion result has been read by the central processing unit through the checking circuit, the overflow flag of the register is set to invalid;

[0028] If the second conversion result is not read by the central processing unit, the overflow flag of the register is set to be valid.

[0029] Optionally, the method further includes:

[0030] If the second conversion result has been read by the central processing unit through the checking circuit, the write pointer of the buffer is controlled to remain unchanged;

[0031] If the second conversion result is not read by the central processing unit, storing the first conversion result in the buffer comprises:

[0032] If the second conversion result is not read by the central processing unit, the write pointer of the buffer is controlled to increase by one, and the first conversion result is stored in the buffer space corresponding to the write pointer.

[0033] Correspondingly, an embodiment of the present invention discloses a chip, wherein the chip includes the control circuit of the above analog-to-digital converter.

[0034] The embodiments of the present invention include the following advantages:

[0035] A control circuit of an analog-to-digital converter according to an embodiment of the present invention comprises: an analog-to-digital converter, a buffer, a verification circuit and a central processing unit, wherein the analog-to-digital converter comprises at least one channel and at least one register, wherein one channel corresponds to one register, the analog-to-digital converter is used to generate a conversion completion signal after the channel conversion is completed to obtain a first conversion result, and to generate an interrupt signal when the first conversion result is stored in the buffer, the register is used to store the first conversion result of the corresponding channel based on a write signal, the verification circuit is used to verify whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit based on the conversion completion signal, if the second conversion result has been read by the central processing unit, a write signal is generated, if the second conversion result has not been read by the central processing unit, the first conversion result is stored in the buffer, thereby avoiding the situation where the first conversion result is stored in the register and the unread second conversion result is overwritten when the second conversion result currently stored in the register has not been read by the central processing unit, thereby realizing reliable storage of the conversion result data of the analog-to-digital converter. The central processing unit is used to read the first conversion result from the register when no interrupt signal is detected, read the first conversion result from the buffer when an interrupt signal is detected, and read the second conversion result from the register, thereby avoiding the problem of failure to timely read the current conversion result stored in the register, resulting in loss and confusion of the read data. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a structural diagram of a control circuit of an analog-to-digital converter according to an embodiment of the present invention;

[0037] Figure 2 The present invention is a flowchart of a control method for an analog-to-digital converter according to an embodiment of the present invention.

[0038] Reference numerals: analog-to-digital converter 10 , channel 11 , register 12 , buffer 20 , check circuit 30 , central processing unit 40 . DETAILED DESCRIPTION

[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] Analog-to-digital converters play a vital role in modern electronic systems. Their main function is to convert analog signals into digital signals. ADCs usually have multiple conversion channels, which enable ADCs to sample and convert multiple analog signals simultaneously or sequentially, thus meeting the needs of multi-signal processing in complex systems.

[0041] In common implementations, each ADC conversion channel is equipped with an independent register to store its own conversion results. Although this design simplifies data management, it may expose some potential problems under high sampling rates or heavy system loads. Specifically, due to the delay of the central processor when processing other tasks, it may not be able to read the current conversion result stored in the register in time. In this case, the new conversion result may be quickly generated and overwrite the current conversion result, causing data loss or confusion of results.

[0042] One of the core concepts of an embodiment of the present invention is that a conversion completion signal is generated by an analog-to-digital converter after the channel conversion is completed to obtain a first conversion result. Based on the conversion completion signal, a verification circuit verifies whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit. If it has been read, a write signal is generated to write the first conversion result to the register. If it has not been read, the first conversion result is stored in a buffer, thereby avoiding the situation in which the first conversion result is stored in the register and the unread second conversion result is overwritten when the second conversion result currently stored in the register has not been read by the central processing unit, thereby achieving reliable storage of the conversion result data of the analog-to-digital converter.

[0043] Reference Figure 1 , shows a structural diagram of a control circuit of an analog-to-digital converter according to an embodiment of the present invention, which may specifically include the following structure:

[0044] The analog-to-digital converter 10 , the buffer 20 , the checking circuit 30 and the central processing unit 40 .

[0045] Analog-to-digital converters are used to convert analog signals (such as voltage or current) into digital signals. The working principle of analog-to-digital converters includes: sampling, the analog-to-digital converter first samples the input analog signal, that is, measuring the value of the analog signal at a specific point in time; quantization, the sampled analog signal value is quantized into discrete digital values, and the quantization process converts the continuous analog signal into a finite number of discrete levels; encoding: the quantized digital value is encoded into binary form to form a digital signal.

[0046] The analog-to-digital converter 10 includes at least one channel 11 and at least one register 12 , and one channel 11 corresponds to one register 12 .

[0047] The channel of an analog-to-digital converter refers to the number of analog input signals it can process simultaneously. A multi-channel analog-to-digital converter can process multiple input signals simultaneously and convert them into digital signals. Different input channels are usually selected through a multiplexer. A single-channel analog-to-digital converter can only process one input signal. The internal structure of the analog-to-digital converter contains various types of registers for storing and processing data, which may include: sampling and holding registers, which are used to store the voltage value of the input signal at the sampling moment so that the ADC can accurately quantize, including sampling switches, holding capacitors and buffer amplifiers; quantization registers, which are used to store quantized digital values, that is, to convert continuous analog signals into discrete digital values, including comparator arrays and encoding logic; encoding registers, which are used to encode quantized digital values ​​into binary form to form digital signals, including logic gates and shift registers; control registers, which are used to store and process control signals and control the conversion process of the ADC, including state machines and control logic; status registers, which are used to store the working status information of the ADC, such as conversion completion flags, overflow flags, etc., including status bits and flag bits; configuration registers, which are used to store the configuration parameters of the ADC, such as resolution, sampling rate, input range, etc., including configuration bits and parameter storage units,

[0048] The analog-to-digital converter 10 is used to generate a conversion completion signal after the channel 11 completes the conversion to obtain a first conversion result, and to generate an interrupt signal when the first conversion result is stored in the buffer 20. The conversion completion signal (End of Conversion Signal, referred to as EOC signal) is used to indicate the end of the ADC conversion process.

[0049] The register 12 is used to store the first conversion result of the corresponding channel 11 based on the write signal.

[0050] Register 12 may be a result register, which is used to store the converted conversion result to ensure that the converted data can be read and processed by an external system. The result register transmits the stored data to an external system (such as a microcontroller, a processor) through an interface circuit (such as a parallel interface, a serial interface). Before the data is read, the result register maintains the stability of the conversion result to prevent data loss or damage. The result register comprises: a data storage unit for storing the converted digital data. The number of bits of the data storage unit is usually consistent with the resolution of the analog-to-digital converter, such as 8 bits, 12 bits, 16 bits, etc.; a read control logic for controlling the data read operation. The read control logic usually includes a read enable signal (Read Enable) and an address decoding logic; an interface circuit for communicating with an external system to transmit the stored data. The interface circuit may be a parallel interface, a serial interface, or other types of interfaces.

[0051] The depth of register 12 is 1. Registers with a depth of 1 are used to temporarily store a single data item. During data transmission, registers can be used to cache data to ensure the integrity of the data during transmission. When an external system writes data to a register, the register stores the data item. If there is already data in the register, the new data overwrites the old data. When an external system reads data from the register, the register outputs the stored data item.

[0052] The verification circuit 30 is used to verify whether the second conversion result currently stored in the register 12 corresponding to the channel 11 has been read by the central processing unit 40 based on the conversion completion signal; if the second conversion result has been read by the central processing unit 40, a write signal is generated; if the second conversion result has not been read by the central processing unit 40, the first conversion result is stored in the buffer 20.

[0053] The analog-to-digital converter 10 generates a conversion completion signal after the conversion of channel 11 is completed and the first conversion result is obtained. That is to say, there is a new first conversion result that needs to be stored at this time. The verification circuit 30 needs to verify whether the second conversion result currently stored in the register 12 corresponding to the channel 11 has been read by the central processing unit 40. If the second conversion result has been read by the central processing unit 40, that is, the second conversion result currently stored in the register 12 can be overwritten, a write signal is generated. After receiving the write signal, the register 12 stores the first conversion result in the register 12 according to the write signal. The first conversion result overwrites the second conversion result, that is, the second conversion result is updated to the first conversion result.

[0054] If the second conversion result is not read by the central processing unit 40, then the first conversion result cannot be stored in the register 12 at this time. If the first conversion result is stored in the register 12, it will overwrite the first conversion result that is not read by the central processing unit 40, resulting in data confusion. Therefore, the first conversion result is stored in the cache 20, and the second conversion result is still stored in the register 12.

[0055] The buffer 20 may be a FIFO (First In, First Out) memory. The FIFO memory is a first-in, first-out queue structure, which means that the first data to enter will be taken out first. FIFO is widely used in the fields of digital signal processing, communication systems, embedded systems, etc., especially when data needs to be temporarily stored and processed in sequence later. The IFO memory is used to temporarily store data to ensure the integrity of the data during transmission, store and read data in a first-in, first-out order, ensure that the processing order of the data is consistent with the input order, and can be used for flow control to balance the production and consumption rate of data. The FIFO memory includes: a storage unit, and the storage unit of the FIFO is used to store data items. The number of storage units determines the depth of the FIFO (that is, the number of data items that can be stored); Write Pointer: The write pointer is used to indicate the location of the next write data. After each data is written, the write pointer will increment; Read Pointer: The read pointer is used to indicate the location of the next read data. After each data is read, the read pointer will increment; Status signal: FIFO usually provides status signals, such as full (Full), empty (Empty), half full (Half Full), etc., to indicate the storage status of FIFO; Control logic: The control logic is used to manage the read and write operations of FIFO to ensure the correct storage and reading of data. The working principle of FIFO is data writing: When the external system writes data to FIFO, the data is stored in the storage unit pointed to by the write pointer, and the write pointer increments; Data reading: When the external system reads data from FIFO, the data is read from the storage unit pointed to by the read pointer, and the read pointer increments; Status detection: The external system can determine the storage status of FIFO by detecting the status signal of FIFO (such as full, empty) to avoid overflow or data loss.

[0056] The central processing unit 40 is configured to read the first conversion result from the register 12 when the interrupt signal is not detected; and read the first conversion result from the buffer 20 when the interrupt signal is detected.

[0057] The analog-to-digital converter 10 generates an interrupt signal when the first conversion result is stored in the buffer 20. When the interrupt signal is not detected, that is, the first conversion result is stored in the register 12, the first conversion result is read from the register 12 at this time. When the interrupt signal is detected, that is, the first conversion result is stored in the buffer 20, the first conversion result is read from the buffer 20 at this time.

[0058] When a conversion completion signal is detected and the second conversion result currently stored in the register 12 corresponding to the channel has not been read by the central processing unit 40, the first conversion result is stored in the cache 20, thereby avoiding the problem of the second conversion result currently stored in the register 12 being overwritten when it is not read by the central processing unit 40. The first conversion result is stored in the cache 20 only when it is not read, thereby avoiding caching duplicate results, reducing the time required for the software program to screen data, and making the system run faster. At the same time, it can reduce the depth of the FIFO, reduce the area of ​​the overall circuit, and save costs.

[0059] A control circuit of an analog-to-digital converter according to an embodiment of the present invention comprises: an analog-to-digital converter, a buffer, a verification circuit and a central processing unit, wherein the analog-to-digital converter comprises at least one channel and at least one register, wherein one channel corresponds to one register, the analog-to-digital converter is used to generate a conversion completion signal after the channel conversion is completed to obtain a first conversion result, and to generate an interrupt signal when the first conversion result is stored in the buffer, the register is used to store the first conversion result of the corresponding channel based on a write signal, the verification circuit is used to verify whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit based on the conversion completion signal, if the second conversion result has been read by the central processing unit, a write signal is generated, if the second conversion result has not been read by the central processing unit, the first conversion result is stored in the buffer, thereby avoiding the situation where the first conversion result is stored in the register and the unread second conversion result is overwritten when the second conversion result currently stored in the register has not been read by the central processing unit, thereby realizing reliable storage of the conversion result data of the analog-to-digital converter. The central processing unit is used to read the first conversion result from the register when no interrupt signal is detected, read the first conversion result from the buffer when an interrupt signal is detected, and read the second conversion result from the register, thereby avoiding the problem of failure to timely read the current conversion result stored in the register, resulting in loss and confusion of the read data.

[0060] In an embodiment of the present invention, the checking circuit 30 is further configured to store the channel number of the channel corresponding to the first conversion result in the buffer 20 if the second conversion result has not been read by the central processing unit 40 .

[0061] When the verification circuit 30 detects that the second conversion result has not been read by the central processing unit 40, it not only stores the first conversion result in the buffer 20, but also stores the channel number of the channel corresponding to the first conversion result in the buffer 20. In this way, when the central processing unit 40 subsequently reads data from the buffer 20, it can know the first conversion result and the channel number of the channel corresponding to the first conversion result. Since one register 20 corresponds to one channel, when the central processing unit 40 reads the conversion result from the register 20, it also knows the channel corresponding to this conversion result.

[0062] In the embodiment of the present invention, the central processor 40 is further configured to read the second conversion result from the register when the interrupt signal is detected.

[0063] When the CPU 40 detects the interrupt signal, it needs to read the first conversion result from the buffer 10 and also needs to speed up the reading of the second conversion result from the register 12 .

[0064] In order to speed up the reading of data by the central processing unit 40, the following measures can be taken: set the overflow interrupt as a high-priority interrupt to ensure that the processor can respond to the overflow event in a timely manner; allow interrupt nesting, that is, during the interrupt processing, allow higher-priority interrupt requests to interrupt the current interrupt handler to ensure that high-priority events can be processed in a timely manner; when an overflow is detected, the system can pre-fetch data from the buffer or memory to the cache (such as L1, L2 cache) in advance to reduce the delay in data reading; use the processor's pipeline operation to prepare data reading instructions in advance to reduce the waiting time for data reading; in a multi-core processor system, multiple cores can be used to process data reading tasks in parallel to increase the data reading speed; distribute data reading tasks to multiple cores or threads, and use parallel processing capabilities to accelerate data reading.

[0065] In the embodiment of the present invention, the checking circuit 30 is used to obtain a read flag of the register 12 from the register 12; and determine whether the second conversion result has been read by the central processing unit according to the read flag.

[0066] The read flag of register 12 indicates whether the second conversion result currently stored in register 12 has been read by the central processing unit 40. The read flag is a single bit used to indicate whether the data in the result register has been read or processed. A read flag of 1 indicates that the data has not been read (valid), and a read flag of 0 indicates that the data has been read (invalid). Before writing new data to the result register, the system will detect whether the read flag in the current result register is valid (that is, the read flag is 1). If the read flag is valid, it indicates that the data in the current result register has not been read. At this time, writing new data will cause data overwriting, resulting in overflow.

[0067] In an embodiment of the present invention, the verification circuit 30 is used to set the overflow flag position of the register 12 to invalid if the second conversion result has been read by the central processing unit 40; if the second conversion result has not been read by the central processing unit 40, the overflow flag position of the register 12 is valid.

[0068] The check circuit 30 is used to set the overflow flag of the register 12 to invalid if the second conversion result has been read by the central processing unit 40, indicating that the data has not overflowed; if the second conversion result has not been read by the central processing unit 40, it indicates that writing new data at this time will cause data overwriting, thereby causing overflow, so the overflow flag of the register 12 is set to valid.

[0069] In the embodiment of the present invention, the checking circuit 30 is used to control the write pointer of the buffer 20 to remain unchanged if the second conversion result has been read by the central processing unit 40 .

[0070] The checking circuit 30 is used for storing the first conversion result in the register 12 if the second conversion result has been read by the central processing unit 40, controlling the write pointer of the buffer 20 to remain unchanged, and not storing data in the buffer 20.

[0071] If the second conversion result is not read by the central processing unit 40 , the write pointer of the buffer 12 is controlled to increase by one, and the first conversion result is stored in the buffer space corresponding to the write pointer.

[0072] The checking circuit 30 is used to control the write pointer of the buffer 12 to increase by one to point to the next available storage location if the second conversion result is not read by the central processing unit 40, indicating that the first conversion result needs to be stored in the buffer 12, and store the first conversion result in the buffer space corresponding to the write pointer.

[0073] The test circuit 30 is responsible for detecting whether the register 12 of the current channel overflows. Before writing new data to the register 12, the test circuit 30 will detect whether the read flag in the current register 12 is valid (i.e., the read flag is 1). If the read flag is valid, it means that the data in the current result register has not been read. At this time, writing new data will cause data overwriting, resulting in overflow. When overflow is detected, the test circuit 30 will control the write pointer of the buffer 20 to add 1 to point to the next available storage location. After the write pointer is updated, the test circuit 30 will control the buffer 20 to store the conversion result to the new address space. At this time, the register 12 of the channel does not cache new results and retains the last conversion result. When overflow is detected, an interrupt signal is generated to notify the processor that there is an emergency event that needs to be handled, and the interrupt signal is transmitted to the processor through the interrupt controller. After the central processing unit 40 detects the interrupt request signal, it suspends the current execution process and saves the current execution status (such as the program counter and register status). The central processing unit 40 jumps to the corresponding interrupt handler according to the type of the interrupt request signal to execute the overflow event processing. In the interrupt handler, the processor will accelerate the reading of the conversion results in the cache 20 to ensure that the data will not be lost. After the interrupt handler is executed, the central processing unit 40 will clear the overflow flag, indicating that the overflow event has been processed.

[0074] The check circuit 30 is responsible for detecting whether the register 12 of the current channel overflows. If overflow occurs, the write pointer of the buffer 20 will be increased by 1, and the storage space of the buffer 20 will save the conversion result of this time. At this time, the register 12 of the channel does not cache new results, retains the last conversion result and generates an overflow interrupt, which is passed to the processor through the interrupt controller. In the interrupt processing program, the central processing unit 40 will accelerate the reading of the conversion result in the buffer 20 and clear the overflow flag to ensure the correct processing of data and the normal operation of the system.

[0075] By adding a buffer 20 to store the conversion results and channel serial numbers of each channel 11 of the analog-to-digital converter 10, and a circuit to check whether the data in the register 12 overflows, the write address of the buffer 20 is increased each time an overflow occurs, thereby avoiding caching duplicate results, reducing the time required for the software program to screen data, and making the system run faster. At the same time, the depth of the buffer 20 can also be reduced, reducing the area of ​​the overall circuit and saving costs.

[0076] Reference Figure 2 , shows a flow chart of a control method of an analog-to-digital converter according to an embodiment of the present invention, which may specifically include the following steps:

[0077] Step 101, generating a conversion completion signal through the analog-to-digital converter after the channel conversion is completed to obtain a first conversion result, and generating an interrupt signal when the first conversion result is stored in the buffer; the register is used to store the first conversion result of the corresponding channel based on the write signal.

[0078] Step 102, based on the conversion completion signal, the verification circuit verifies whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit; if the second conversion result has been read by the central processing unit, a write signal is generated; if the second conversion result has not been read by the central processing unit, the first conversion result is stored in the buffer.

[0079] Step 103, reading the first conversion result from the register by the central processing unit when the interrupt signal is not detected; and reading the first conversion result from the buffer when the interrupt signal is detected.

[0080] A control circuit of an analog-to-digital converter according to an embodiment of the present invention comprises: an analog-to-digital converter, a buffer, a verification circuit and a central processing unit, wherein the analog-to-digital converter comprises at least one channel and at least one register, wherein one channel corresponds to one register, the analog-to-digital converter is used to generate a conversion completion signal after the channel conversion is completed to obtain a first conversion result, and to generate an interrupt signal when the first conversion result is stored in the buffer, the register is used to store the first conversion result of the corresponding channel based on a write signal, the verification circuit is used to verify whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit based on the conversion completion signal, if the second conversion result has been read by the central processing unit, a write signal is generated, if the second conversion result has not been read by the central processing unit, the first conversion result is stored in the buffer, thereby avoiding the situation where the first conversion result is stored in the register and the unread second conversion result is overwritten when the second conversion result currently stored in the register has not been read by the central processing unit, thereby realizing reliable storage of the conversion result data of the analog-to-digital converter. The central processing unit is used to read the first conversion result from the register when no interrupt signal is detected, read the first conversion result from the buffer when an interrupt signal is detected, and read the second conversion result from the register, thereby avoiding the problem of failure to timely read the current conversion result stored in the register, resulting in loss and confusion of the read data.

[0081] In an embodiment of the present invention, the method further includes:

[0082] If the second conversion result is not read by the central processing unit through the checking circuit, the channel number of the channel corresponding to the first conversion result is stored in the buffer.

[0083] In an embodiment of the present invention, the method further includes:

[0084] The second conversion result is read from the register by the central processing unit when the interrupt signal is detected.

[0085] In an embodiment of the present invention, the step 102 of checking whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit by the checking circuit based on the conversion completion signal may specifically include the following sub-steps:

[0086] Sub-step S21, obtaining a read flag bit of the register from the register based on the conversion completion signal by the inspection circuit;

[0087] Sub-step S22, determining whether the second conversion result has been read by the central processing unit according to the read flag bit.

[0088] In an embodiment of the present invention, the method further includes:

[0089] If the second conversion result has been read by the central processing unit through the checking circuit, the overflow flag of the register is set to invalid;

[0090] If the second conversion result is not read by the central processing unit, the overflow flag of the register is set to be valid.

[0091] In an embodiment of the present invention, the method further includes:

[0092] If the second conversion result has been read by the central processing unit through the checking circuit, the write pointer of the buffer is controlled to remain unchanged;

[0093] If the second conversion result is not read by the central processing unit, storing the first conversion result in the buffer comprises:

[0094] If the second conversion result is not read by the central processing unit, the write pointer of the buffer is controlled to increase by one, and the first conversion result is stored in the buffer space corresponding to the write pointer.

[0095] A control circuit of an analog-to-digital converter according to an embodiment of the present invention comprises at least one channel and at least one register, one channel corresponds to one register, the analog-to-digital converter is used to generate a conversion completion signal after the channel conversion is completed to obtain a first conversion result, and to generate an interrupt signal when the first conversion result is stored in a buffer, the register is used to store the first conversion result of the corresponding channel based on a write signal, the verification circuit is used to verify whether the second conversion result currently stored in the register corresponding to the channel has been read by a central processing unit based on the conversion completion signal, if the second conversion result has been read by the central processing unit, a write signal is generated, if the second conversion result has not been read by the central processing unit, the first conversion result is stored in the buffer, the central processing unit is used to read the first conversion result from the register when no interrupt signal is detected, read the first conversion result from the buffer when an interrupt signal is detected, and read the second conversion result from the register. After the channel conversion is completed and the first conversion result is obtained, a conversion completion signal is generated by the analog-to-digital converter. Based on the conversion completion signal, the verification circuit verifies whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit. If it has been read, a write signal is generated to write the first conversion result to the register. If it has not been read, the first conversion result is stored in the buffer, thereby avoiding the situation where the first conversion result is stored in the register and the unread second conversion result is overwritten when the second conversion result currently stored in the register has not been read by the central processing unit, thereby realizing reliable storage of the conversion result data of the analog-to-digital converter.

[0096] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0097] An embodiment of the present invention further discloses a chip, wherein the chip includes the control circuit of the analog-to-digital converter as described above.

[0098] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0099] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0100] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0101] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0102] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0103] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0104] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0105] The control circuit, method and chip of an analog-to-digital converter provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technicians in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A control circuit of an analog-to-digital converter, characterized in that: The control circuit includes: an analog-to-digital converter, a buffer, a test circuit and a central processing unit; The analog-to-digital converter comprises at least one channel and at least one register, one channel corresponds to one register; the analog-to-digital converter is used to generate a conversion completion signal after the channel conversion is completed to obtain a first conversion result, and to generate an interrupt signal when the first conversion result is stored in the buffer; the register is used to store the first conversion result of the corresponding channel based on a write signal; The checking circuit is used to check whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit based on the conversion completion signal; if the second conversion result has been read by the central processing unit, a write signal is generated; if the second conversion result has not been read by the central processing unit, the first conversion result is stored in the buffer; The central processing unit is used for reading the first conversion result from the register when the interrupt signal is not detected; and reading the first conversion result from the buffer when the interrupt signal is detected.

2. The method according to claim 1, characterized in that The checking circuit is further configured to store the channel number of the channel corresponding to the first conversion result in the buffer if the second conversion result has not been read by the central processing unit.

3. The control circuit according to claim 1, characterized in that: The central processing unit is further configured to read the second conversion result from the register when the interrupt signal is detected.

4. The control circuit according to claim 1, characterized in that: The checking circuit is used for obtaining a read flag of the register from the register; and judging whether the second conversion result has been read by the central processing unit according to the read flag.

5. The control circuit according to claim 1, characterized in that: The checking circuit is used for setting the overflow flag of the register to invalid if the second conversion result has been read by the central processing unit; If the second conversion result is not read by the central processing unit, the overflow flag of the register is set to be valid.

6. The control circuit according to claim 1, characterized in that: The checking circuit is used to control the write pointer of the buffer to remain unchanged if the second conversion result has been read by the central processing unit; If the second conversion result is not read by the central processing unit, the write pointer of the buffer is controlled to increase by one, and the first conversion result is stored in the buffer space corresponding to the write pointer.

7. A control method for an analog-to-digital converter, characterized in that: Applied to the control circuit as claimed in claim 1, the method comprises: The analog-to-digital converter generates a conversion completion signal after the channel conversion is completed to obtain a first conversion result, and generates an interrupt signal when the first conversion result is stored in the buffer; the register is used to store the first conversion result of the corresponding channel based on the write signal; Based on the conversion completion signal, the verification circuit verifies whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit; if the second conversion result has been read by the central processing unit, a write signal is generated; if the second conversion result has not been read by the central processing unit, the first conversion result is stored in the buffer; The first conversion result is read from the register by the central processing unit when the interrupt signal is not detected; and the first conversion result is read from the buffer when the interrupt signal is detected.

8. The method according to claim 7, characterized in that The method further comprises: If the second conversion result is not read by the central processing unit through the checking circuit, the channel number of the channel corresponding to the first conversion result is stored in the buffer.

9. The method according to claim 7, characterized in that: The method further comprises: The second conversion result is read from the register by the central processing unit when the interrupt signal is detected.

10. The method according to claim 7, characterized in that The checking, based on the conversion completion signal, by the checking circuit, whether the second conversion result currently stored in the register corresponding to the channel has been read by the central processing unit comprises: Obtaining a read flag bit of the register from the register based on the conversion completion signal by the inspection circuit; It is determined whether the second conversion result has been read by the central processing unit according to the read flag bit.

11. The method according to claim 7, characterized in that The method further comprises: If the second conversion result has been read by the central processing unit through the checking circuit, the overflow flag of the register is set to invalid; If the second conversion result is not read by the central processing unit, the overflow flag of the register is set to be valid.

12. The method according to claim 7, characterized in that The method further comprises: If the second conversion result has been read by the central processing unit through the checking circuit, the write pointer of the buffer is controlled to remain unchanged; If the second conversion result is not read by the central processing unit, storing the first conversion result in the buffer comprises: If the second conversion result is not read by the central processing unit, the write pointer of the buffer is controlled to increase by one, and the first conversion result is stored in the buffer space corresponding to the write pointer.

13. A chip comprising the control circuit of the analog-to-digital converter according to claims 1-6.

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