High-speed column-level single-slope analog-to-digital converter and conversion method thereof

Abstract

The invention relates to the field of analog-to-digital converters, in particular to a high-speed column-level single-slope analog-to-digital converter and a conversion method thereof, and the converter comprises two or more columns of column-level analog-to-digital converter circuits, a row full-counting judgment circuit and a slope generator; the conversion method comprises the following steps: reading a frame pixel signal to be processed, and quantizing the pixel signal; the pixel signals are accessed to a column-level analog-to-digital converter; quantizing each column of pixels of the row in parallel; the slope generator is reset when the trigger full counting judgment circuit works; and judging whether each row of pixels of the frame of image are quantized or not, and processing a pixel signal of the next row or the next frame according to a judgment result. According to the invention, the quantization process and the row time of the ADC are optimized, the frame time is reduced, and the frame rate of the CMOS image sensor is further improved.

Description

Technical Field

[0001] The invention relates to the field of analog-to-digital converters, and in particular to a high-speed column-level single-slope analog-to-digital converter and a conversion method thereof. Background Art

[0002] CMOS (Complementary Metal Oxide Semiconductor) image sensor (CIS) is an important component of machine vision system.

[0003] ADC (Analog-to-Digital Converter) is an important part of data conversion in CMOS image sensors, and directly affects the main parameters of CIS products such as accuracy and speed.

[0004] At present, the application field of high-speed target capture has high requirements for the speed of CIS, that is, the readout frame rate. In the design of high-speed CIS, the column-level ADC architecture is mainly used. This architecture has the advantages of multi-channel parallel readout, small chip area, low power consumption and low noise. Among them, a single ADC often uses the SS (single-slope)-ADC structure with simple structure and good consistency. Combined with the column-level ADC architecture, it can achieve small area and high-speed performance indicators. The frame rate of the CMOS image sensor is related to the time required for the ADC to convert a frame of image, that is, the frame time. The column-level single-slope analog-to-digital converter can effectively shorten the frame time by means of multi-channel parallelism, and divide the frame time into multiple row times, thereby improving the frame rate of the CIS. Such as Figure 1 FIG. 4 is a chip structure diagram of a prior art CMOS image sensor. Figure 2 Shown Figure 1 The working timing diagram of the chip shown in the figure. Currently, the common circuit architectures for reducing line time include multi-slope SS-ADC, multi-slope SS-ADC, and SS-ADC combined with time-to-digital converter TDC.

[0005] In the prior art, there is a multi-slope SS-ADC described in patent publication number CN114567738A. This solution decomposes a slope quantization process into two parts, realizes two-step coarse and fine quantization, shortens the line time, and thus improves the frame rate of the CMOS image sensor. There are the following problems: first, each quantization starts with a comparison between the slope initial voltage and the pixel voltage. When there is a large voltage difference, the required clock cycle increases exponentially; second, each quantization of a row of pixels requires the ramp generator and the counter to completely traverse the entire analog domain and digital domain data interval, and will not stop immediately after all pixels in a row are quantized, resulting in a large amount of time waste and low quantization efficiency.

[0006] The above problems are caused by the working characteristics of conventional SS-ADC, which directly limits the CIS frame rate. Summary of the invention

[0007] In view of this, the present invention discloses a high-speed column-level single-slope analog-to-digital converter and a conversion method thereof, so as to further optimize the row time and thus improve the quantization efficiency.

[0008] A high-speed column-level single-slope analog-to-digital converter comprises: two or more column-level analog-to-digital converter circuits, a row full count determination circuit, and a ramp generator, wherein each column-level analog-to-digital converter circuit comprises: an S / H sampling and holding circuit, a comparator, a counter, and a latch;

[0009] Further, the connection mode of the column-level analog-to-digital converter circuit of each column is as follows: the S / H sampling and holding circuit is respectively connected to the input end of the comparator and the output end of the ramp generator, the output end of the comparator is connected to the input end of the counter, the output end of the counter is connected to the input end of the latch, the output end of the latch is connected to the input end of the row full count determination circuit; the output end of the row full count determination circuit is connected to the input end of the ramp generator;

[0010] A high-speed column-level single-slope analog-to-digital conversion method comprises the steps of:

[0011] Step 1: The single slope analog-to-digital converter reads the frame pixel signal to be processed, quantizes the pixel signal, and starts the frame time;

[0012] Step 2: Connect the row pixel signal to be processed to the column-level analog-to-digital converter and start the row time;

[0013] Step 3: The column-level analog-to-digital converter quantizes each column of pixels in the row in parallel;

[0014] Step 4: When the row full count judgment circuit is triggered to work, the pixel quantization of the row is completed, the ramp generator is reset, and the row time ends;

[0015] Step 5, determine whether each row of pixels in the frame image has been quantized; if not, access the next row of pixel signals, compare them with the size of the pixel signals in this row, obtain the working mode of the quantization stage of the next row of pixel signals, return to step 2 and quantize the next row according to the working mode; if so, the quantization of the frame image is completed, the frame time is completed, return to step 1 and quantize the next frame.

[0016] The beneficial effects of the present invention include:

[0017] By adding a row full count determination circuit, after the quantization of all pixel voltages in a row is completed, the row time is controlled by the circuit, thereby improving the quantization efficiency of a single pixel signal; by adopting an S / H circuit, a new ramp generator, and a column-level SS-ADC architecture that separately configures a counter with a bidirectional counter architecture for each column, the quantization process and row time of the ADC are dynamically reduced, the frame time is reduced, and the frame rate of the CMOS image sensor is further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The chip structure diagram of the prior art CMOS image sensor;

[0019] Figure 2 It is a chip operation timing diagram of a prior art CMOS image sensor;

[0020] Figure 3 A chip structure diagram of a high-speed column-level single-slope analog-to-digital converter used in an embodiment;

[0021] Figure 4 A single-column structure diagram of a high-speed column-level single-slope analog-to-digital converter in an embodiment;

[0022] Figure 5 It is a working timing diagram of the high-speed column-level single-slope analog-to-digital converter in the embodiment;

[0023] Figure 6 It is a flow chart of the high-speed column-level single-slope analog-to-digital conversion method of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution, characteristics and advantages of the present invention more clearly understood, the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0025] Embodiment 1 is a preferred embodiment of the high-speed column-level single-slope analog-to-digital converter of the present invention. The single-column structure of the high-speed column-level single-slope analog-to-digital converter is as follows: Figure 4 The column-level analog-to-digital converter circuit in the figure includes: S / H sampling and holding circuit, comparator, counter, and latch.

[0026] Furthermore, the connection method of each column-level analog-to-digital converter circuit is as follows: the S / H sampling and holding circuit is respectively connected to the input end of the comparator and the output end of the ramp generator, the output end of the comparator is connected to the input end of the counter, the output end of the counter is connected to the input end of the latch, the output end of the latch is connected to the input end of the row full count determination circuit; the output end of the row full count determination circuit is connected to the input end of the ramp generator.

[0027] Specifically, the S / H sampling and holding circuit structure is used to change the starting voltage of the ramp voltage generated by the ramp generator, and includes 5 switches S1~S5 and 1 capacitor CH; its connection method is: one end of S1 is connected to the negative electrode of the comparator, and the other end is respectively connected to the positive electrode of the comparator, one end of S2, and one end of CH; the other end of S2 is respectively connected to the positive ramp voltage output end of the ramp generator and one end of S3; the other end of S3 is respectively connected to the other end of CH, one end of S4, and one end of S5; the other end of S4 is connected to the negative ramp voltage output end of the ramp generator; and the other end of S5 is connected to the reference voltage.

[0028] Furthermore, the row full count decision circuit is implemented by a digital logic unit or a switch array, and is triggered after the quantization of a row of pixels is completed, and is used to output a control signal to stop the ramp generator from working and reset the ramp generator.

[0029] Furthermore, the ramp generator is implemented by a digital-to-analog converter DAC or a switched capacitor integration circuit, and is used to generate a linear ramp voltage with an opposite slope.

[0030] Furthermore, the counter adopts a bidirectional counter architecture and has four working states: reset, up counting, down counting, and maintaining count value.

[0031] Embodiment 2 is a preferred embodiment of the high-speed column-level single-slope analog-to-digital conversion method of the present invention. The method flow chart is as follows: Figure 6 As shown, the steps include:

[0032] Step 1: The single slope analog-to-digital converter reads the frame pixel signal to be processed, quantizes the pixel signal, and starts the frame time.

[0033] Specifically, when the exposure of a frame of image is completed, the pixel array in front of the analog-to-digital converter generates a pixel signal, the column-level circuit starts to work, and the frame time starts, which means that the current frame of image enters the quantization stage.

[0034] Step 2: Connect the row pixel signal to be processed to the column-level analog-to-digital converter and start the row time.

[0035] Specifically, the start of a row time means that the pixels in this row enter the quantization stage.

[0036] Step 3: The column-level analog-to-digital converter quantizes each column of pixels in the row in parallel.

[0037] Specifically, the S / H circuit inputs the ramp signal into the positive terminal of the comparator, and the comparator starts to compare the ramp signal at the positive terminal with the pixel signal at the negative terminal. The counter performs a counting operation, and the comparator output flips, indicating that the pixel signal is quantized. The quantization process is parallel processing.

[0038] Step 4: When the row full count determination circuit is triggered, the pixel quantization of the row is completed, the ramp generator is reset, and the row time ends.

[0039] Specifically, when all the columns of pixels in a row are quantized, the row full count judgment circuit is triggered. At this time, the counter maintains the current count value and saves the count value to the latch as the quantization result. The S / H sampling and holding circuit starts to work and saves the voltage value of the pixel signal of this row to the plate of the capacitor. This operation uses the plate voltage of the capacitor in the S / H sampling and holding circuit as the starting value of the ramp voltage when the next row is quantized, shortening the working time of the ramp voltage and improving the quantization efficiency. The voltage is judged with the size of the pixel signal value of the next row to determine the direction of the ramp voltage connected when the next row is quantized and the counting direction of the counter to ensure that the quantization stage proceeds normally.

[0040] Furthermore, the row full count decision circuit can be implemented by a digital logic unit or a switch array. After detecting that all pixels in a row have been quantized, the ramp generator is stopped and reset, thereby ending the row time.

[0041] Step 5, determine whether each row of pixels in the frame image has been quantized; if not, access the next row of pixel signals, compare them with the size of the pixel signals in this row, obtain the working mode of the quantization stage of the next row of pixel signals, return to step 2 and quantize the next row according to the working mode; if so, the quantization of the frame image is completed, the frame time is completed, return to step 1 and quantize the next frame.

[0042] Specifically, if not every row of pixels in the frame image has been quantized, the pixel signal of the next row is connected, and compared with the pixel signal of the current row stored on the capacitor CH. When comparing the pixel signal sizes of two adjacent rows, if the pixel signal of the current row is larger than that of the next row, the comparator outputs a high level, the next row is connected to a descending slope during the quantization phase, and the column counter counts down; if the pixel signal of the current row is smaller than that of the next row, the comparator outputs a low level, the next row is connected to an ascending slope during the quantization phase, and the column counter counts up; the quantization of the next row is started, and the quantization result of the current row in the latch is read out at the same time. If the quantization of every row of pixels in the frame image is completed, the frame time ends.

[0043] Embodiment 3 is another preferred embodiment of the high-speed column-level single-slope analog-to-digital converter of the present invention:

[0044] like Figure 3 The chip structure diagram using a high-speed column-level single-slope analog-to-digital converter is shown.

[0045] Furthermore, if Figure 4 The figure shows a single-column structure diagram of the high-speed column-level single-slope analog-to-digital converter in this embodiment. The front structure PGA (Programmable Gain Amplifier) ​​of the digital-to-analog converter processes the pixel signals of the first column of pixels Pixel-11, Pixel-21, ..., Pixel-n1 and outputs Vsig_11, Vsig_21, ..., Vsig_n1 to the negative terminal of the comparator in sequence.

[0046] Furthermore, the ramp generator can generate a linear ramp voltage with opposite and symmetrical slopes. That is, the positive ramp voltage Vramp+ and the negative ramp voltage Vramp- are output by ports VUP and VDOWN, respectively. Among them, Vramp+ increases linearly from Vref to Vref+Vrange, and Vramp- decreases linearly from Vref to Vref-Vrange, ensuring that in the quantization stage, no matter the pixel voltage of the previous row stored on the upper plate of capacitor CH is any voltage value between Vref and Vref+Vrange, the ramps Vramp+ and Vramp- can ensure that the ramp voltage VCH connected to the positive end of the comparator during quantization can traverse the entire Vrange, ensuring that VCH covers the pixel voltage. The reset operation of the ramp generator is set to be reset through the RST port when all pixels in a row are quantized.

[0047] Furthermore, the comparator works in the quantization stage to compare the pixel signal with the ramp voltage. According to the VCOMP output by the comparator, the three working states of the bidirectional counter can be controlled: up counting UP, down counting DOWN, and holding HOLD. When the quantization of a frame of image is completed, the bidirectional counters of all columns can be cleared through the timing control module.

[0048] Furthermore, the latch can latch the count value of the counter in the holding phase. When all latches of a row of pixels are latched, the row full count decision circuit can be triggered, and the circuit outputs Vramp_rst to reset the ramp generator and end the row time.

[0049] Further, switches S0, S1, S2, S3, S4, S5 and capacitor CH constitute the sampling and holding circuit of the present invention. The upper plate positive end of capacitor CH is connected to switches S1, S2 and the positive end of the comparator, and is responsible for maintaining the pixel voltage and the ramp voltage provided to the comparator in different working stages. Its lower plate is connected to switches S3, S4, S5, and the synchronization of the ramp voltage on the upper plate can be achieved through the charge conservation principle. Switch S0 controls the access of the pixel signal. When closed, the pixel signal accesses the negative end of the comparator. Switch S1 is responsible for transferring the pixel to the positive end of the comparator after the quantization of a row of pixels is completed, as the starting voltage of the ramp voltage in the next quantization. Switches S2, S3, and S4 are responsible for controlling the access of the ramp signal. S2 is only turned on for a period of time when the first row of pixels in each frame image is quantized, and Vramp+ is directly connected to the positive end of the comparator. S3 and S4 respectively control Vramp+ and Vramp- to access the lower plate of capacitor CH. According to the principle of capacitor charge conservation, the voltage on the upper plate of the capacitor can be synchronously increased or decreased with the ramp, and connected to the positive end of the comparator to participate in pixel quantization. Switch S5 is responsible for the access of the lower plate reset voltage Vref. The function of this voltage is to ensure that the voltage on the upper plate of the capacitor will not change suddenly when the ramp is connected, and the ramp voltage can accurately start working from the voltage of the previous row of pixels.

[0050] like Figure 5 The figure shows the working timing diagram of the high-speed column-level single-slope analog-to-digital converter in this embodiment, which includes a continuous quantization process for three pixel signals in a column, where the vertical axis represents the voltage value v, and the horizontal axis Time represents the timing process t. Vrange is the pixel voltage range. The voltage generated by the pixel after exposure is within this range after PGA processing. Vref is the starting reference voltage of the range. The range of the pixel voltage VSIGNAL is Vref to Vref+Vrange. Vsig_11 represents the pixel voltage generated by the pixel in the first row and first column of the pixel array after exposure, Vsig_21 represents the pixel voltage generated by the pixel in the first row and first column, and Vsig_31 represents the pixel voltage generated by the pixel in the third row and first column, represented by the dotted line. VCH represents the capacitor C HThe voltage change of the upper plate (positive terminal) is represented by the solid line ratio. t1 to t11 represent different working stages. The working states of VCOMP, S0, S1, S2, S3, S4, and S5 are all represented by digital logic voltages, where VCOMP logic level 0 indicates that its positive terminal voltage is lower than the negative terminal voltage, and the comparator outputs a low level, and VCOMP logic level 1 indicates that its positive terminal voltage is higher than the negative terminal voltage, and the comparator outputs a high level. The logic levels of S0 to S5 represent the working state of the switch, 0 represents the switch is open, and 1 represents the switch is closed. COUNTER represents the four working states of the comparator, namely reset, count up, count down, and hold. In the hold stage, the quantization results of the three pixels Vsig_11, Vsig_21, and Vsig_31 are saved respectively, that is, the counter counting results C1, C2, and C3. The timing t1 to t11 includes the quantization process of a column of three consecutive pixel signals Vsig_11, Vsig_21, and Vsig_31.

[0051] Furthermore, Vsig_11 is quantified during the period from t1 to t3, specifically:

[0052] Time t1 is the quantization preparation stage. During this time, the comparator, counter, and latch are reset and cleared. S5 is closed to charge the capacitor C H The lower plate is reset and ready to start quantization.

[0053] The t2 stage is the pixel signal quantization stage. S0 is closed to connect the pixel signal of the first row of the pixel array to the negative terminal of the corresponding column comparator. At the same time, S2 is opened to connect the positive ramp Vramp+ of the ramp generator to the capacitor C. H The upper plate and the positive terminal of the comparator, at this time the comparator works normally and the counter counts up.

[0054] The t3 stage is the latch stage. When the Vramp+ voltage rises to Vsig_11, the t3 stage is reached. In this stage, the comparator flips to a high level, the counter pauses counting and holds the current count value C1, and saves C1 to the latch. The switch S2 is turned on to pause the ramp voltage and access the comparator of the current column and C H The upper plate and close switch S1 to store Vsig_11 to C H Upper plate, during this process S5 is closed throughout to ensure that the capacitor C H The voltage of the lower plate is Vref, which ensures the normal charge storage function.

[0055] During the period from t4 to t7, the next row of pixels, namely the pixel signal Vsig_21, is quantized. This process is similar to the process from t1 to t3, except that a comparison and determination phase is added before the pixel signal quantization phase to determine the working logic of the overall circuit during the quantization phase. The process is as follows:

[0056] The t4 stage is the quantization preparation stage, at which the comparator is reset, the counter continues to hold the quantization value C1 of the previous stage, and the latch outputs the quantization value C1 of the first row of pixels. During this period, switch S0 is open and ready to input the pixel signal Vsig_21. S2 does not work and remains open from the quantization of the first row of pixels until the quantization of a frame of image is completed. After that, the access of the ramp signal is controlled by S3 and S4 and cooperates with the capacitor C H Connect to the positive terminal of the comparator for quantization. At this time, the capacitor C H The upper plate maintains the voltage Vsig_11, and S5 is closed to maintain the lower plate voltage Vref.

[0057] The t5 stage is the comparison and judgment stage, and the switch S0 is closed to connect the pixel signal Vsig_21 to compare with the Vsig_11 at the positive end of the comparator. When Vsig_21 is greater than Vsig_11, it is hoped that the positive end of the comparator will be connected to a rising slope and the counter will continue to count upward from the current value in the quantization logic to complete the quantization of Vsig_21. When Vsig_21 is less than Vsig_11, it is hoped that a falling slope with the same slope will be connected and the counter will count downward to complete the quantization. In this example, Vsig_21 is greater than Vsig_11, and the comparator signal Vcomp is at a logic low level at this time, which determines the subsequent quantization logic.

[0058] The quantization phase begins at stage t6, S3 is closed and S5 is opened, and the capacitor C H The lower plate is connected to the rising ramp Vramp+. Due to the conservation of capacitor charge, the voltage on the upper plate of the capacitor starts to rise from Vsig_11 and traverses Vrange. The counter starts counting upward from C1.

[0059] The t7 stage is the latch stage. When the comparator flips, the logic level of Vcomp changes to make a judgment and enter this stage. The counter pauses counting and holds the current count value C2, and saves C2 to the latch. S3 opens to stop the ramp Vramp+ and connects to the capacitor C H Lower plate, and close switch S5 to C H The lower plate is reset, and then switch S1 is closed to store Vsig_21 into C H The upper electrode plate prepares for the quantization of the next row of pixel signals.

[0060] In the stage from t8 to t11, Vsig_31 in the third row of pixels is quantized. The work content of this process corresponds to the stage from t4 to t7, that is, it includes a quantization preparation stage, a comparison and judgment stage, a quantization stage, and a latching stage.

[0061] Starting from time t8, the comparator is reset, the counter continues to hold the quantization value C2 of the previous stage, and the latch outputs the quantization value C2 of the second row of pixels. HThe upper plate maintains the voltage Vsig_21, and S5 is closed to maintain the lower plate voltage Vref.

[0062] In the t9 phase, the switch S0 is closed, the pixel signal Vsig_31 of the third row is connected and compared with the positive terminal Vsig_21 of the comparator. Assuming that Vsig_31 is less than Vsig_21, the comparator flips to a high level to determine the circuit working logic of the quantization phase.

[0063] At stage t10, Vsig_31 is quantized, S4 is closed and S5 is opened, and capacitor C H The lower plate is connected to the descending ramp Vramp-. Due to the conservation of capacitor charge, the voltage on the upper plate of the capacitor starts to decrease from Vsig_21 and traverses Vrange. The counter starts to count downward from C2.

[0064] The t11 stage is the latch stage. The comparator output Vcomp flips to a low level. The counter stops counting and holds the current count value C3, and saves C3 to the latch. S4 opens to stop the ramp Vramp-connected to the capacitor C H Lower plate, and close switch S5 to C H The lower plate is reset, and then switch S1 is closed to store Vsig_31 into C H The upper electrode plate prepares for the quantization of the fourth row of pixel signals.

[0065] Furthermore, the above process can represent the quantization process of all pixels in a frame of pixel quantization. In the present invention, the clock cycles occupied by the quantization stage of different pixels are not fixed, while the clock cycles occupied by the quantization preparation stage, the comparison and determination stage, and the latch stage are fixed. The row time is determined by the pixel signal with the most clock cycles occupied by the quantization stage in a row of pixels, rather than by a fixed T clk ×2 M Representation.

[0066] Furthermore, let the pixel array size be n×n, and the pixel voltage being quantized in the hth row and lth column be V sig (h,l), the pixel voltage of the previous row is V sig (h-1,l). The calculation formula of the travel time T is:

[0067]

[0068] Among them, V sig (1, l) represents the pixel voltage being quantized in row 1 and column l, V range Represents the pixel signal range, V ref Indicates the starting value of the ramp voltage, T clkrepresents the circuit clock cycle, M represents the resolution of the single slope analog-to-digital converter, h is an array representing the number of rows, and l is an array representing the number of columns.

[0069] When the pixel array size n×n is very large, the frame time can be approximately considered as:

[0070]

[0071] Where H is the number of rows in the pixel array, the value is n, T clk Represents the clock period, 2≤h≤n, 1≤l≤n.

[0072] Furthermore, it can be seen that the frame time is related to the pixel voltage difference generated by pixels in adjacent rows of the same column. In large-array image sensors, the pixel voltage difference collected between adjacent rows of most pixels will be very small compared to the entire quantization voltage range Vrange, that is, The value of will be small in most cases, which will cause most of the line time to be reduced during the quantization process, thereby reducing the frame time.

[0073] Finally, it should be noted that the above only describes some embodiments of the present invention. For those skilled in the art, it is conceivable that various changes, modifications, substitutions and deformations may be made to these embodiments without departing from the principles and spirit of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents, and the above-mentioned actions should be covered within the scope of protection of the present invention.

Claims

1. A high-speed column-level single-slope analog-to-digital converter, characterized in that: include: Two or more column-level analog-to-digital converter circuits, a row full count determination circuit, and a ramp generator; Each column-level analog-to-digital converter circuit includes: S / H sampling and holding circuit, comparator, counter, latch; The connection method is as follows: the S / H sampling and holding circuit is respectively connected to the input end of the comparator and the output end of the ramp generator, the output end of the comparator is connected to the input end of the counter, the output end of the counter is connected to the input end of the latch, the output end of the latch is connected to the input end of the row full count judgment circuit; the output end of the row full count judgment circuit is connected to the input end of the ramp generator.

2. The high-speed column-level single-slope analog-to-digital converter according to claim 1, characterized in that: The S / H sampling and holding circuit structure is used to change the starting voltage of the ramp voltage generated by the ramp generator.

3. The high-speed column-level single-slope analog-to-digital converter according to claim 2, characterized in that: The S / H sample-and-hold circuit includes five switches S1 to S5 and one capacitor CH; The connection method is as follows: one end of S1 is connected to the negative electrode of the comparator, and the other end is respectively connected to the positive electrode of the comparator, one end of S2, and one end of CH; the other end of S2 is respectively connected to the positive slope voltage output end of the ramp generator and one end of S3; the other end of S3 is respectively connected to the other end of CH, one end of S4, and one end of S5; the other end of S4 is connected to the negative slope voltage output end of the ramp generator; and the other end of S5 is connected to the reference voltage.

4. The high-speed column-level single-slope analog-to-digital converter according to claim 1, characterized in that: The row full count decision circuit is implemented by a digital logic unit or a switch array; the row full count decision circuit outputs a control signal after the quantization of a row of pixels is completed, and the control signal stops the ramp generator from working and resets the ramp generator.

5. The high-speed column-level single-slope analog-to-digital converter according to claim 1, characterized in that: The counter adopts a bidirectional counter architecture and has four working states: reset, up counting, down counting, and maintain count value.

6. A high-speed column-level single-slope analog-to-digital conversion method, characterized in that: A high-speed column-level single-slope analog-to-digital converter according to any one of claims 1 to 5; Includes steps: Step 1: The single slope analog-to-digital converter reads the frame pixel signal to be processed, quantizes the pixel signal, and starts the frame time; Step 2: Connect the row pixel signal to be processed to the column-level analog-to-digital converter and start the row time; Step 3: The column-level analog-to-digital converter quantizes each column of pixels in the row in parallel; Step 4: When the row full count judgment circuit is triggered to work, the pixel quantization of the row is completed, the ramp generator is reset, and the row time ends; Step 5, determine whether each row of pixels in the frame image has been quantized; if not, access the next row of pixel signals, compare them with the size of the pixel signals in this row, obtain the working mode of the quantization stage of the next row of pixel signals, return to step 2 and quantize the next row according to the working mode; if so, the quantization of the frame image is completed, the frame time is completed, return to step 1 and quantize the next frame.

7. The high-speed column-level single-slope analog-to-digital conversion method according to claim 6, characterized in that: Quantizing each column of pixels in the row includes: the S / H sampling and holding circuit inputs a ramp signal to the comparator, the comparator compares the pixel signal of the row with the ramp signal, and the counter performs a counting operation.

8. The high-speed column-level single-slope analog-to-digital conversion method according to claim 7, characterized in that: When comparing the pixel signal sizes of two adjacent rows, if the pixel signal of this row is larger than that of the next row, the comparator outputs a high level, the next row is connected to a descending slope in the quantization stage, and the counter counts down; if the pixel signal of this row is smaller than that of the next row, the comparator outputs a low level, the next row is connected to a rising slope in the quantization stage, and the counter counts up.

9. The high-speed column-level single-slope analog-to-digital conversion method according to claim 6, characterized in that: The row time for ending the quantization of this row includes: the counter maintains the current value, the latch latches the counting result, the S / H sampling and holding circuit saves the voltage value of the pixel signal of this row, and serves as the starting value for the ramp generator to generate the ramp voltage when the next row is quantized.

10. The high-speed column-level single-slope analog-to-digital conversion method according to claim 6, characterized in that: The calculation formula of the row time T is: Among them, V sig (1, l) represents the pixel voltage being quantized in row 1 and column l, V range Represents the pixel signal range, V ref Indicates the starting value of the ramp voltage, T clk represents the circuit clock cycle, M represents the resolution of the single slope analog-to-digital converter, h represents the number of rows, l represents the number of columns, n represents the number of pixel array rows, V sig (h, l) represents the pixel voltage being quantized at the hth row and the lth column, V sig (h-1, l) represents the pixel voltage being quantized at the h-1th row and lth column.

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