Apparatus and method for reducing power consumption in bit flipping decoder

Abstract

The invention relates to an apparatus and method for reducing power consumption in a bit flipping decoder. A memory system includes a memory device and a controller. The memory device is configured to output a codeword. The controller is configured to establish a plurality of variable nodes and a plurality of check nodes according to the codeword, and schedule a decoding operation to ensure that the number of checksum updates during one cycle of the decoding operation does not exceed a threshold set to be less than the number of check nodes, where the decoding operation includes an iterative operation, where the iterative operation is a non-iterative operation. And each iterative operation comprises a plurality of sub-iterative operations.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to Korean Patent Application No. 10-2023-0151658, filed on November 6, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure described herein relate to a memory system, and more particularly, to an apparatus and method for reducing power consumption in a memory system. Background Art

[0004] Data processing systems including communication systems, memory systems or data storage devices are developed to store more data in the memory devices and to transfer the data stored in the memory devices faster. The memory devices may include non-volatile memory cells and / or volatile memory cells for storing data.

[0005] Various communication systems and data processing systems may place high demands on the complexity and performance of low-density parity check (LDPC) decoders. Bit flip decoders may be suitable for such applications. Column hierarchical scheduling can be a way to increase convergence speed and error correction performance. In addition, hierarchical decoding can bring improved decoding performance with low computational complexity in LDPC decoder implementations. Summary of the invention

[0006] Embodiments of the present disclosure may provide a memory device, a memory system, a controller included in the memory system, a data processing system including the memory system or the memory device, or a communication system for transmitting data.

[0007] Embodiments of the present disclosure may provide an apparatus and method capable of reducing maximum power consumed by a bit-flipping decoder configured to detect or correct errors included in a data entry transmitted from a communication system or a memory system.

[0008] In an embodiment, a memory system may include: a memory device configured to output a codeword; and a controller configured to: establish multiple variable nodes and multiple check nodes according to the codeword; and schedule a decoding operation to ensure that the number of checks and updates occurring during a cycle of the decoding operation does not exceed a threshold value, which is set to be less than the number of check nodes, wherein the decoding operation includes an iterative operation, and each iterative operation includes multiple sub-iterative operations.

[0009] The controller may be configured to, when the number of checksum updates occurring during the first loop exceeds a threshold, delay at least one sub-iteration operation of one or more checksum updates exceeding the threshold to a next loop of the first loop.

[0010] In the memory system, the total number of iteration operations and sub-iteration operations may be changed by checking and updating.

[0011] The controller may be configured to perform thermal throttling based on a maximum power consumption preset in response to a threshold value.

[0012] The controller may be further configured to change the threshold value based on an operating state of the memory system.

[0013] The controller may include: an operation circuit configured to calculate or estimate whether a bit flip occurs; a manager configured to determine whether to perform a bit flip on a result calculated or estimated by the operation circuit; a buffer configured to store a bit flip target that is not applied according to a decision of the manager; a multiplexer configured to output one of the outputs of the manager and the buffer; and a register configured to store a checksum update in response to the output of the multiplexer.

[0014] The manager may be configured to determine whether to perform bit flipping according to a first control signal corresponding to a threshold value.

[0015] The multiplexer may output one of the outputs of the manager and the buffer according to a second control signal based on the schedule.

[0016] The controller may further include control logic configured to track whether the iteration operation and the sub-iteration operation are performed, and output the first control signal and the second control signal based on the schedule.

[0017] In another embodiment of the present disclosure, a method for decoding a codeword in a memory system may include: establishing multiple variable nodes and multiple check nodes based on the codeword; performing flip calculations to determine whether bit flipping occurs for multiple variable nodes based on the multiple check nodes during a decoding operation including an iterative operation, each iterative operation including multiple sub-iterative operations; when the number of checksum updates that occur during one cycle of the decoding operation does not exceed a threshold value set to be less than the number of check nodes, determining whether a checksum update is scheduled based on the flip calculation; and performing the iterative operation and the sub-iterative operation based on the schedule.

[0018] The method may further include: when the number of checksum updates occurring during the first cycle exceeds a threshold, storing a portion of the checksum updates exceeding the threshold; and determining whether the stored checksum updates occur in a schedule for a next cycle of the first cycle.

[0019] The total number of iterations and sub-iterations can be changed by checking and updating.

[0020] The method may further include performing thermal throttling based on a maximum power consumption preset in response to a threshold value.

[0021] The method may further include changing the threshold value based on an operating state of the memory system.

[0022] In another embodiment of the present disclosure, a memory system may include: a low-density parity check (LDPC) decoder configured to perform a decoding operation based on a preset threshold, the decoding operation including at least one iterative operation, the iterative operation including at least one sub-iterative operation; and control logic configured to determine the threshold based on an operating state of the memory system and determine a schedule as to whether to perform an iterative operation or a sub-iterative operation in a cycle of a decoding operation of the LDPC decoder.

[0023] The memory system may further include a memory device configured to output a codeword. The control logic may be configured to: establish a plurality of variable nodes and a plurality of check nodes according to the codeword; and schedule the decoding operation to ensure that the number of checksum updates occurring during a cycle does not exceed a threshold value, which is set to be less than the number of check nodes.

[0024] The control logic may be configured to, when the number of checksum updates occurring during the first loop exceeds a threshold, delay at least one sub-iteration operation of one or more checksum updates exceeding the threshold to a next loop of the first loop. The total number of iterative operations and sub-iteration operations may be changed by the checksum updates.

[0025] The control logic may be configured to perform thermal throttling based on a maximum power consumption preset in response to a threshold value.

[0026] The LDPC decoder may include: an operation circuit configured to calculate or estimate whether a bit flip occurs; a manager configured to determine whether to perform a bit flip on a result calculated or estimated by the operation circuit; a buffer configured to store a bit flip target that is not applied according to a decision of the manager; a multiplexer configured to output one of the outputs of the manager and the buffer; and a register configured to store a checksum update in response to the output of the multiplexer. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The description herein refers to the drawings, wherein like reference numerals refer to like parts throughout.

[0028] Figure 1 A data processing system according to an embodiment of the present disclosure is described.

[0029] Figure 2 A low density parity check (LDPC) code according to another embodiment of the present disclosure is described.

[0030] Figure 3 A communication system according to another embodiment of the present disclosure is described.

[0031] Figure 4 An LDPC decoding operation according to another embodiment of the present disclosure is described.

[0032] Figure 5 An LDPC decoding operation according to another embodiment of the present disclosure is described.

[0033] Figure 6 An LDPC decoding operation according to another embodiment of the present disclosure is described.

[0034] Figure 7 Adjustment of LDPC decoding operations according to another embodiment of the present disclosure is described.

[0035] Figure 8 The effects of the LDPC decoding operation are described.

[0036] Fig. 9 An LDPC decoder according to another embodiment of the present disclosure is described.

[0037] Fig.10 An LDPC decoder according to another embodiment of the present disclosure is described.

[0038] Fig.11 The configuration and design of a memory system according to another embodiment of the present disclosure is described.

[0039] Fig.12 A memory system according to another embodiment of the present disclosure is described.

[0040] Fig.13 A memory system according to another embodiment of the present disclosure is described. DETAILED DESCRIPTION

[0041] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any disclosed embodiment.

[0042] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “optional embodiments,” etc.) are intended to indicate that any of these features are included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

[0043] In this disclosure, the terms "comprises," "comprising," "includes," and "including" are open ended. As used in the appended claims, these terms specify the presence of the elements described, and do not exclude that one or more other elements are present or added. The terms in the claims do not exclude that the device includes additional components, e.g., interface units, circuits, etc.

[0044] In the present disclosure, various units, circuits, or other components may be described or claimed to be "configured to" perform one or more tasks. In this case, "configured to" is used to represent a structure by indicating that the block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Therefore, even if the block / unit / circuit / component is not currently running, such as not turned on or activated, it can be said that the specified block / unit / circuit / component is configured to perform a task. The blocks / units / circuit / components used with the "configured to" language include hardware, such as circuits, memories storing program instructions that can be run to implement operations, etc. In addition, "configured to" may include general structures (e.g., general circuits) manipulated by software and / or firmware (e.g., FPGAs or general processors running software) to operate in a manner that can perform the relevant tasks. "Configured to" may also include making a manufacturing process (e.g., a semiconductor manufacturing facility) suitable for manufacturing devices, such as integrated circuits suitable for implementing or performing one or more tasks.

[0045] As used in this disclosure, the term "machine", "circuit" or "logic" refers to all of the following: (a) hardware circuit implementations only (e.g., implementations of analog and / or digital circuits only) and (b) combinations of circuits with software and / or firmware, such as (as applicable to): (i) a combination of processors or (ii) a portion of a processor / software that includes a digital signal processor, software and memory that work together to enable a device such as a mobile phone or server to perform various functions; and (c) a circuit that requires software or firmware to operate even if the software or firmware is not physically present (e.g., a microprocessor or a portion of a microprocessor). This definition of "machine", "circuit" or "logic" applies to all uses of the term in this application (including any claims). As another example, as used in this application, the term "machine", "circuit" or "logic" also covers implementations of only one processor or multiple processors or a portion of a processor and their (or their) accompanying software and / or firmware. The term "machine", "circuit" or "logic" also covers integrated circuits of storage devices, for example, if applicable to a specific claim element.

[0046] As used herein, the terms "first", "second", "third", etc. are used as labels for the nouns preceding them and do not imply any type of ordering, such as spatial, temporal, logical ordering, etc. The terms "first", "second", and "third" do not necessarily mean that the first value must be written before the second value. In addition, although these terms can be used to identify various components in this article, these components are not limited by these terms. These terms are used to distinguish one component from another component, otherwise their names are the same or similar. For example, a first circuit can be distinguished from a second circuit.

[0047] In addition, the term "based on" is used to describe one or more factors that affect the determination. The term does not exclude other factors that may affect the determination. That is, the determination may be based solely on these factors, or at least in part on these factors. Consider the case of the phrase "A is determined based on B." Although in this case, B is a factor that affects the determination of A, such a phrase does not exclude that the determination of A is also based on C. In other cases, A may be determined based solely on B.

[0048] Embodiments will now be described with reference to the drawings, wherein like reference numerals refer to like elements throughout.

[0049] Figure 1 A data processing system 100 according to an embodiment of the present disclosure is described.

[0050] Reference Figure 1, the data processing system 100 may include a memory system 110 and a host 102 coupled or connected to the memory system 110. For example, the host 102 and the memory system 110 may be coupled to each other via a data bus, a host cable, etc. to perform data communication.

[0051] The memory system 110 may include a memory device 150 and a controller 130. The memory device 150 and the controller 130 in the memory system 110 may be considered as physically separate components or elements. The memory device 150 and the controller 130 may be connected via at least one data path. For example, the data path may include a channel and / or a way.

[0052] According to an embodiment, the memory device 150 and the controller 130 may be components or elements divided by function. In addition, according to an embodiment, the memory device 150 and the controller 130 may be implemented with a single chip or a plurality of chips.

[0053] The controller 130 may perform data input and output (input / output) operations (e.g., read operations, program operations, erase operations, etc.) in response to a request or command input from an external device (e.g., the host 102). For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of nonvolatile memory cells included in the memory device 150 is transferred to the controller 130. In addition, the controller 130 may independently perform operations regardless of a request or command input from the host 102. With respect to the operating state of the memory device 150, the controller 130 may perform operations such as garbage collection (GC), wear leveling (WL), and bad block management (BBM) for checking whether a storage block is a bad block and disposing of the bad block.

[0054] The memory device 150 may include a plurality of memory chips 252 (e.g., NAND flash memory chips) connected to the controller 130 through a plurality of channels CH0, CH1, ..., CH1_n and paths W0, ..., W_k. The memory chip 252 may include a plurality of memory planes or a plurality of memory dies. According to an embodiment, the memory plane may be regarded as a logical partition or a physical partition including at least one storage block, a driving circuit capable of controlling an array including a plurality of non-volatile memory cells, and a buffer capable of temporarily storing data input to or output from the non-volatile memory cells. Each memory plane or each memory die may support an interleaved mode in which a plurality of data input / output operations are performed in parallel or simultaneously. According to an embodiment, the storage blocks included in each memory plane or each memory die may be grouped into super storage blocks to input / output a plurality of data entries. The internal configuration of the memory device 150 shown in the above figure may be changed based on the operating performance of the memory system 110. The embodiments of the present disclosure may not be limited to Figure 1 The internal configuration described in .

[0055] The controller 130 may control a program operation or a read operation on the memory device 150 in response to a write request or a read request input from the host 102. According to an embodiment, the controller 130 may execute firmware to control a program operation or a read operation in the memory system 110. Here, the firmware may refer to a flash translation layer (FTL). Figure 3 and Figure 4 An example of FTL is described in detail. According to an embodiment, the controller 130 may be implemented with a microprocessor, a central processing unit (CPU), an accelerator, etc. According to an embodiment, the memory system 110 may be implemented with at least one multi-core processor, a co-processor, etc.

[0056] The memory 144 may be used as a working memory of the memory system 110 or the controller 130, while temporarily storing transaction data for operations performed in the memory system 110 and the controller 130. According to an embodiment, the memory 144 may be implemented with a volatile memory. For example, the memory 144 may be implemented with a static random access memory (SRAM), a dynamic random access memory (DRAM), or both. The memory 144 may be provided within the controller 130, but implementation is not limited thereto. The memory 144 may be located inside or outside the controller 130. For example, the memory 144 may be implemented by an external volatile memory having a memory interface that transmits data and / or signals between the memory 144 and the controller 130.

[0057] According to an embodiment, the controller 130 may further include an error correction code (ECC) circuit 266 configured to perform error checking and correction on data transmitted between the controller 130 and the memory device 150. The ECC circuit 266 may be implemented as a separate module, circuit, or firmware in the controller 130, but according to an embodiment, may also be implemented in each memory chip 252 included in the memory device 150. The ECC circuit 266 may include a program, circuit, module, system, or device for detecting and correcting error bits of data processed by the memory device 150.

[0058] According to an embodiment, the ECC circuit 266 may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder may perform error correction encoding on the data to be programmed into the memory device 150 to generate encoded data with parity bits added, and store the encoded data in the memory device 150. When the controller 130 reads the data stored in the memory device 150, the ECC decoder may detect and correct the error bits contained in the data read from the memory device 150. For example, after performing error correction decoding on the data read from the memory device 150, the ECC circuit 266 may determine whether the error correction decoding is successful, and output an instruction signal based on the result of the error correction decoding, such as a correction success signal or a correction failure signal. The ECC circuit 266 may use the parity bits generated during the ECC encoding process for the data stored in the memory device 150 to correct the error bits of the read data entry. When the number of error bits is greater than or equal to the number of correctable error bits, the ECC circuit 266 may not correct the error bits, but may output a correction failure signal indicating that the correction error bits failed.

[0059] According to an embodiment, the ECC circuit 266 may perform error correction operations based on coded modulation such as low-density parity check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM), block coded modulation (BCM), etc. The ECC circuit 266 may include all circuits, modules, systems and / or devices that perform error correction operations based on at least one of the above codes.

[0060] According to an embodiment, the controller 130 and the memory device 150 may send and receive a command CMD, an address ADDR, or a codeword LDPC_CODE. For example, the codeword LDPC_CODE may be a codeword (N, K) LDPC_CODE including (N+K) bits or symbols. The codeword (N, K) LDPC_CODE may include an information word INFO_N and a parity check PARITY_K. The information word INFO_N may include N bits or symbols INFO0, ..., INFO (N-1) , and the parity check PARITY_K may include K bits or symbols PARITY0, ..., PARITY (K-1) Here, N and K are natural numbers and may vary according to the design of the LDPC code.

[0061] For example, if N bits or symbols INFO0, ..., INFO (N-1) The input information word INFO_N is LDPC encoded, and the code word (N, K) LDPC_CODE can be generated. The code word (N, K) LDPC_CODE may include (N+K) bits or symbols LDPC_CODE0, ..., LDPC_CODE (N+K)-1 . An LDPC code may be a type of linear block code. A linear block code may be described by a generator matrix G or a parity check matrix H. As a characteristic of the LDPC code, most elements (e.g., entries) of the parity check matrix consist of zeros (0), and the number of its non-zero elements is small compared to the code length, so probability-based iterative decoding is possible. For example, the first proposed LDPC code may be defined by a parity check matrix having a non-systematic form. The parity check matrix may be designed to have consistently low weights in its rows and columns. Here, the weight indicates the number of "1"s included in a column or row of the parity check matrix.

[0062] For example, regarding all codewords (N,K)LDPC_CODE, the characteristics of the linear code may satisfy Equation 1 or Equation 2 shown below.

[0063] LDPC_CODE H T =0 (Equation 1)

[0064]

[0065] In Equation 1 and Equation 2, H represents a parity check matrix, LDPC_CODE represents a codeword, and LDPC_CODE i represents the i-th bit of the codeword, and (N+K) represents the length of the codeword. Moreover, h iindicates the i-th column of the parity check matrix H. The parity check matrix H may include (N+K) columns equal to the number of bits of the LDPC codeword. Equation 2 shows that the i-th column h of the parity check matrix H i and the i-th codeword bit LDPC_CODE i The sum of the products is "0", so the i-th column h i Will be combined with the i-th codeword bit LDPC_CODE i Related.

[0066] Figure 2 An LDPC code according to another embodiment of the present disclosure is described.

[0067] Figure 2 An example of a parity check matrix H of an LDPC code having 4 rows and 6 columns and its Tanner graph is shown. Figure 2 , because the parity check matrix H has 6 columns, a codeword with a length of 6 bits can be generated. The codeword generated by H becomes an LDPC codeword, and each column in the parity check matrix H can correspond to each of the 6 bits in the codeword.

[0068] The Tanner graph of the LDPC code encoded and decoded based on the parity check matrix H may include 6 variable nodes 240, 242, 244, 246, 248, 250 and 4 check nodes 252, 254, 256, 258. Here, the i-th column and the j-th row of the parity check matrix H correspond to the i-th variable node and the j-th check node, respectively. In addition, the value 1 (i.e., the meaning of a value other than 0) at the intersection of the i-th column and the j-th row of the parity check matrix H of the LDPC code means that there is an edge connecting the i-th variable node and the j-th check node on the Tanner graph, such as Figure 2 shown.

[0069] The degree of a variable node and a check node in the Tanner graph of an LDPC code refers to the number of edges (i.e., lines) connected to each node. The number of edges can be equal to the number of non-zero entries (e.g., 1) in the column or row corresponding to the node in the parity check matrix of the LDPC code. For example, in Figure 2 In the example, the degrees of variable nodes 240, 242, 244, 246, 248, and 250 are 2, 1, 2, 2, 2, and 2, respectively. The degrees of check nodes 252, 254, 256, and 258 are 2, 4, 3, and 2, respectively. In addition, Figure 2 Each column of the parity check matrix H corresponds to Figure 2 The number of non-zero entries of the variable node can be consistent with the above order 2, 1, 2, 2, 2, 2. Figure 2 Each row of the parity check matrix H corresponds to Figure 2The number of non-zero entries of the check node can be consistent with the aforementioned order 2, 4, 3, 2.

[0070] LDPC codes can be used to Figure 2 The decoding process of the iterative decoding algorithm of the sum-product algorithm for the bipartite graph listed in . Here, the sum-product algorithm is a message passing algorithm. The message passing algorithm may include operations or processes for exchanging messages through edges on the bipartite graph and calculating and updating output messages based on messages input to variable nodes or check nodes.

[0071] Here, the value of the i-th coded bit can be determined based on the message of the i-th variable node. According to an embodiment, the value of the i-th coded bit can be obtained by both hard decision and soft decision. Therefore, the performance of the i-th bit ci of the LDPC codeword can correspond to the performance of the i-th variable node of the Tanner graph, which can be determined according to the position of "1" and the number of "1" in the i-th column of the parity check matrix. The performance of the (N+K) codeword bits in the codeword may be affected by the position of "1" and the number of "1" in the parity check matrix, which means that the parity check matrix may greatly affect the performance of the LDPC code. Therefore, a method for designing a good parity check matrix is ​​needed to design an LDPC code with excellent performance.

[0072] According to an embodiment, for ease of implementation, a quasi-cyclic LDPC (QC-LDPC) code using a QC parity check matrix may be used as a parity check matrix. The QC-LDPC code is characterized in having a parity check matrix including a zero matrix in the form of a small square matrix or a cyclic permutation matrix. In this case, the permutation matrix may be a matrix in which all elements of the square matrix are 0 or 1 and each row or column contains only one "1". In addition, the cyclic permutation matrix may be a matrix obtained by cyclically shifting each entry of the permutation matrix from left to right.

[0073] Figure 3 A communication system according to another embodiment of the present disclosure is described.

[0074] Reference Figure 3 , the communication system may include but is not limited to a first communication device COMM_DEVICE_1 310 for transmitting a signal or data or a second communication device COMM_DEVICE_2 320 for receiving a signal or data. The first communication device 310 may include an LDPC encoder 312 and a transmitter 314. The second communication device 320 may include a receiver 322 and an LDPC decoder 324. Here, the LDPC encoder 312 and the LDPC decoder 324 may be based on Figure 2 The LDPC code described in is used to encode or decode a signal or data.

[0075] Reference Figure 1 and Figure 3 , components for encoding or decoding signals or data based on LDPC codes may be implemented in a memory system 110 including a controller 130, a communication system including communication devices 310, 320, or a data processing system 100 including the memory system 110 based on its operation, configuration, and performance.

[0076] According to an embodiment, when a decoding process is performed using a sum-product algorithm (SPA), an LDPC code can provide performance close to capacity performance. For hard decision decoding, a bit flip (BF) algorithm based on an LDPC code is proposed. The BF algorithm can flip a bit, a symbol, or a bit group (e.g., change "0" to "1", or vice versa) based on the value of a flip function (FF) calculated at each iteration or each iterative operation. The FF associated with the variable node (VN) can be a reliability measure of the corresponding bit decision and can depend on the binary value (checksum) of the check node (CN) connected to the VN. The BF algorithm may be simpler than the sum-product algorithm (SPA), but simplicity may have an impact on performance. In order to reduce this performance difference, various types of BF algorithms are proposed. The BF algorithm can be designed to improve the FF (i.e., the reliability measure of the VN) and / or the method of selecting the bit, symbol, or bit group to be flipped, thereby providing different degrees of bit error rate (BER) or improving convergence speed performance in response to a reduction or increase in complexity.

[0077] Figure 4 An LDPC decoding operation according to another embodiment of the present disclosure is described. Figure 4 The Layered Belief Propagation (LBP) algorithm for LDPC codes is described as an example.

[0078] Reference Figures 1 to 4 , low-density parity-check (LDPC) codes may be a class of error correction codes that are widely used in digital communications and data storage systems based on their near-capacity error correction performance. LDPC codes use a sparse parity-check matrix, which enables efficient decoding with good error correction capabilities. The layered belief propagation (LBP) algorithm, also known as "turbo decoding" or "flooding," is an iterative decoding algorithm for LDPC codes. In each iteration, messages may be passed between variable nodes and check nodes on a bipartite graph representation of the LDPC code. These messages may represent a probability distribution of possible bit values ​​and are specified for each repetition operation.

[0079] In the context of the layered belief propagation (LBP) algorithm for LDPC codes, the parity check matrix can be divided into several separate sub-matrices or "layers". Afterwards, the decoding process can be performed layer by layer. In each layer, variable-check and check-variable message updates can be performed like standard BP. However, once a particular layer is processed, the updated messages can be immediately used to process the next layer in the same global iteration. This layered belief propagation (LBP) algorithm can make the decoding algorithm converge faster compared to standard BP, in which all layers are updated only once at the same time at each global iteration. Therefore, layered belief propagation (LBP) LDPC decoding can provide benefits such as reduced complexity and increased speed while maintaining improved error correction performance.

[0080] Reference Figure 4 , a check node unit (CNU) and a variable node unit (VNU) can be established. Here, the check node unit (CNU) can include 5 check nodes C0, C1, C2, C3, C4, and the variable node unit (VNU) can include 10 variable nodes V0, V1, V2, V3, V4, V5, V6, V7, V8, V9. Figure 2 The settings of the check node unit (CNU) and the variable node unit (VNU) are determined in the same manner as the LDPC code described in .

[0081] Figure 4 The figure above conceptually describes a single iteration among multiple iterations. The layered belief propagation (LBP) algorithm for LDPC codes may include a decoding process described as various stages or levels of iterations and sub-iterations. Iterations may include a complete traversal of all layers or groups of the parity check matrix of the LDPC code. In each iteration, messages may be passed between variable nodes and check nodes based on local observations and received messages. These iterations may continue until a stop or termination condition is met, such as reaching a maximum number of iterations or achieving satisfactory error correction.

[0082] Figure 4 The following figure conceptually depicts a single sub-iteration within an iteration. An iteration may include multiple sub-iterations. For example, a sub-iteration may be represented by a solid line and other sub-iterations may be represented by a dashed line. Although an iteration involves a traversal of all layers of the LDPC code at one time, a sub-iteration may specifically involve an update process that occurs within each individual layer during the entire iteration. A sub-iteration may include intermediate steps within an iteration, where message updates occur within individual layers of an LDPC decoding process based on a hierarchical belief propagation (LBP) algorithm. Hierarchical belief propagation decoding is characterized by the following operation: the parity check matrix is ​​divided into several separate sub-matrices or layers and updated one layer at a time, rather than updating all check nodes simultaneously (corresponding to a full iteration) as in traditional belief propagation (BP).

[0083] According to an embodiment, each overall iteration may include multiple sub-iterations corresponding to each layer of the LDPC code structure. Here, each layer can be updated independently before entering the next layer in the same global iteration. The advantage of this approach is that it can generally achieve faster convergence than the standard belief propagation algorithm. This is because the updated information in one layer can be immediately available when processing subsequent layers in the same overall iteration.

[0084] Figure 5 The LDPC decoding operation according to another embodiment of the present disclosure is described. Specifically, Figure 5 The LDPC decoding process is described by dividing it into iterations and sub-iterations Figures 1 to 4 The LDPC decoding process is shown.

[0085] Reference Figure 4 and Figure 5 Each of the multiple iterations (eg, iteration 1, iteration 2, iteration 3) may include multiple sub-iteration operations (V k and Cv k ). Here, k refers to a natural number between 1 and L. The number of variable nodes and check nodes can be as follows Figure 2 and Figure 4 The sub-iteration may include operations such as access, error correction, and flip confirmation of variable nodes (VN) repeated within one iteration. Specifically, V k Cv refers to the variable node (VN) of the kth subgroup, and all k variable nodes can get the entire variable node (VN) set. k Can refer to V k There is a set of connected check nodes (CN).

[0086] According to the LDPC decoder (e.g., Figure 1 and Fig.12 In order to improve the performance of the ECC circuit 266 shown in the figure, multiple iterations (e.g., iteration 1, iteration 2, iteration 3) can be performed until a predetermined maximum number of iterations is reached or a stop condition is satisfied. Each of the multiple iteration operations (iteration 1, iteration 2, iteration 3) may include multiple sub-iterations (V1&Cv1, V2&Cv2, V3&Cv3, V4&Cv4, ..., V L &Cv L ). Multiple sub-iterations may be performed sequentially in response to the configuration of the variable nodes and the check nodes. The LDPC decoder may be configured by referring to Cv k To update (e.g., bit flipping, error correction) V k and accordingly, Cv k Value reversal can occur in (e.g., satisfied: 0, not satisfied: 1).

[0087] Figure 6 The LDPC decoding operation according to another embodiment of the present disclosure is described. Figure 5 An embodiment is described in which iterations and sub-iterations are performed sequentially, but Figure 6 An embodiment is shown in which sub-iterations within each iteration are executed in a pipelined manner.

[0088] Reference Figure 6 According to the passage of time (t) or the progress of the loop, the decoding process can perform multiple iterations (iteration 1, iteration 2, iteration 3) or multiple sub-iterations (V1&Cv1, V2&Cv2, V3&Cv3, V4&Cv4, ..., V L &Cv L ). The multiple sub-iterations included in the iteration (V1&Cv1, V2&Cv2, V3&Cv3, V4&Cv4, ..., V L &Cv L ) may not be performed simultaneously, but may be performed in a pipelined manner, thereby reducing the time or cycles taken to complete an iteration. Here, a pipelined method or approach may include several independent processing stages (e.g., sub-iterations) connected in series, so that the output of a particular sub-iteration can be used for the next sub-iteration. This pipelined approach is mainly effective in breaking down the complex decoding process into separate steps, so that each step can be performed in parallel or independently.

[0089] By executing multiple sub-iterations (V1&Cv1, V2&Cv2, V3&Cv3, V4&Cv4, ..., V L &Cv L ), the time and cycles required for the decoding process can be reduced. However, the amount of calculations performed at a specific timing or in a specific cycle may increase. In addition, the variation in the amount of calculations performed at a specific time or in a specific cycle (or the deviation between the amounts of calculations) may increase. For these reasons, when designing the internal configuration of the memory system 110, the maximum power consumption allocated to the LDPC decoder may increase, so that the operational safety or performance of the memory system 110 may deteriorate in a low-power environment or operating condition.

[0090] Figure 7 Adjustment of LDPC decoding operations according to another embodiment of the present disclosure is described. Figure 7 Describes the delay included in multiple sub-iterations (V1 & Cv1, V2 & Cv2, V3 & Cv3, V4 & Cv4, ..., V L &Cv L ) in the present invention.

[0091] Reference Figure 7 ,like Figure 6 As described, the iteration includes multiple sub-iterations (V1&Cv1, V2&Cv2, V3&Cv3, V4&Cv4, ..., V L &Cv L ) can be performed in a pipelined manner. The LDPC decoder may have a threshold value on the amount of computation performed for a sub-iteration in a particular loop or at a particular timing. For example, in the second sub-iteration (V2 & Cv2) within a particular iteration, too many bit flips may occur, causing the amount of computation to reach a threshold value (e.g., exceeding a constraint). In addition, the bit flips that occur in the third sub-iteration (V3 & Cv3) within the iteration may be less than the threshold value. In addition, the bit flips that occur in the fourth sub-iteration (V4 & Cv4) within the iteration may occur relatively rarely. Although it may be difficult to predict in advance the number of bit flips that occur in each sub-iteration, the number of bit flips that occur in each sub-iteration may be greater than or less than the threshold value.

[0092] Because there is variation or deviation in the number of bit flips in the sub-iterations executed at a specific timing or in a specific loop, the power consumption may also vary due to the variation or deviation in the bit flips. Therefore, if more than a threshold number of bit flips occur in the second sub-iteration (V2 & Cv2), a portion of the second sub-iteration (V2 & Cv2) may be delayed. Figure 7 , part of the second subiteration (V2 & Cv2) (C V2' ) can be executed in the initially executed loop, and the remainder of the second subiteration (V2 & Cv2) (C V2” ) can be executed in the next loop.

[0093] In addition, although the bit flips that occur in the third sub-iteration (V3 & Cv3) may be smaller than the threshold, the remainder (C V2” ) can be executed at the time or cycle of the third sub-iteration (V3 & Cv3). Therefore, only a portion (Cv3') of the third sub-iteration (V3 & Cv3) can be executed at this point or cycle. The remaining portion (Cv3") of the third sub-iteration (V3 & Cv3) can be executed in the next cycle.

[0094] If the bit flip that occurs in the fourth sub-iteration (V4&Cv4) is relatively small, then the remainder (Cv3'') of the third sub-iteration (V3&Cv3) and all (Cv4) of the fourth sub-iteration (V4&Cv4) will be executed in this loop.

[0095] Reference Figures 4 to 7In the hierarchical belief propagation (LBP) algorithm, iterations and sub-iterations can be individually designed into multiple layers, and multiple unit operations that can be distinguished from each other can be hierarchically scheduled. Specifically, in order to reduce the amount of calculation of low-level iterations or unit operations that can be performed in each cycle to below a preset threshold, the LDPC decoder can delay some calculations or operations included in the low-level iterations or unit operations performed in the current cycle to the next cycle. According to an embodiment, if the low-level calculations or operations are delayed in this manner, the total amount of calculations performed during the LDPC decoding operation can be changed (e.g., reduced).

[0096] Figure 8 The effects of the LDPC decoding operation are described. The amount of computation performed in an LDPC decoder is substantially proportional to the amount of power consumed therein. Figure 8 The relationship between the time required for the decoding process performed by an LDPC decoder and the amount of computation or power consumption is described.

[0097] Reference Figure 8 , the amount of computation or power consumption of the decoding operation performed by the LDPC decoder can be reduced at a rate proportional to the amount, and the amount of computation or power consumption of the time to perform the decoding operation can be explained by exponential decay in a two-dimensional graph. For example, due to the operational characteristics of LDPC decoding, in the process of error checking and recovery of specific data, at the beginning of the decoding operation, any bit of the data may have an error, so many bit flips may occur at the beginning. However, as the decoding process proceeds, the number of bits with a higher probability of being error-free in the data increases, which can reduce the bit flips within a certain time or cycle. However, if the specific data contains uncorrectable ECC (UECC) errors, the bit flips may not decrease as the decoding operation proceeds. Therefore, in order to improve the operational performance of LDPC decoding, the maximum number of bit flips proportional to the number of check nodes and the degree of the check nodes can be set higher. In response to these characteristics of the LDPC decoder, a first maximum power consumption threshold (P_MAX1) that the LDPC decoder can use can be set. For example, the first maximum power consumption threshold (P_MAX1) can be set to correspond to a time point or cycle where the most bit flips occur due to the operational characteristics of the LDPC decoding. Here, the first maximum power consumption threshold (P_MAX1) may be associated with thermal throttling of the LDPC decoder, controller, or memory system. Thermal throttling may be designed to cool and protect chips or components of the LDPC decoder, controller, or memory system in response to heavy workloads.

[0098] Reference Figure 7 and Figure 8, setting a threshold for calculations or bit flips that occur during an iteration or sub-iteration. If the number of bit flips exceeds the threshold, the corresponding operation (e.g., an iteration or sub-iteration associated with at least one bit flip that exceeds the threshold) can be delayed until the next time or loop. In this case, the deviation between the number of bit flips can be reduced during each time or loop of performing the decoding process. In addition, the maximum power consumption that can be used by the LDPC decoder can be reduced, such as a second maximum power consumption threshold (P_MAX2) set in response to a threshold for bit flips. For example, the second maximum power consumption threshold (P_MAX2) can be set within a range of 40% to 70% of the first maximum power consumption threshold (P_MAX1).

[0099] According to an embodiment, when a threshold value for bit flipping is set, the decoding time may be longer (e.g., increased) compared to a case where a threshold value for bit flipping is not set. However, due to the threshold value, the maximum power consumed by the LDPC decoder in a specific time or cycle during the decoding time can be reduced. If the maximum power consumed by at least one module (e.g., LDPC decoder) included in the memory system 110 operating in a low power environment can be reduced, the memory system 110 can have various advantages. This will be referred to later. Fig.11 Describe these advantages.

[0100] Fig. 9 An LDPC decoder according to another embodiment of the present disclosure is described.

[0101] Reference Fig. 9 , the LDPC decoder may include a bit flip operation circuit 540 and a checksum register circuit 550. The bit flip operation circuit 540 may be configured to receive data or a codeword (D) and a feedback bit value (C) and output a flip function value (F) based on the codeword (D) and the feedback bit value (C). The checksum register circuit 550 may be configured to store the flip function value (F), determine whether to flip a bit in response to the flip function value (F), and output the feedback bit value (C). The feedback bit value (C) output from the checksum register circuit 550 may be flipped or may not be flipped.

[0102] Reference Fig. 9 The bit flip information (Bit Flip Info) of the LDPC decoder described in , as the decoding time elapses, an iteration or a sub-iteration included in an iteration may be performed. For example, a bit flip may occur in a plurality of sub-iterations (i.e., an area marked with a pattern), or may not occur in a plurality of sub-iterations (i.e., an area without a pattern). Figure 6 and Fig. 9, it is difficult to predict or estimate whether a bit flip in an LDPC decoder occurs in a specific iteration or a specific sub-iteration. If no threshold is set, a large deviation in estimating whether a bit flip occurs in a cycle or timing of the decoding process can be expected.

[0103] Fig.10 An LDPC decoder according to another embodiment of the present disclosure is described.

[0104] Reference Fig.10 , the LDPC decoder may include a bit flip operation circuit 540 and a checksum register circuit 550. In addition, the LDPC decoder may further include a bit flip (BF) manager 560, a queue 570, and a multiplexer 580 disposed between the bit flip operation circuit 540 and the checksum register circuit 550.

[0105] The bit flip operation circuit 540 may be configured to receive data or a codeword (D) and a feedback bit value (C) and output a flip function value (F) based on the codeword (D) and the feedback bit value (C).

[0106] After receiving the flip function value (F) from the bit flip operation circuit 540, the bit flip manager 560 may include circuits, logic, circuits, modules, or devices that can be configured to determine whether to apply the flip function value (F) immediately or delay the flip function value (F). The bit flip manager 560 may receive a first control signal (R). At this time, the first control signal R may correspond to Figure 7 and Figure 8 In response to the first control signal (R), the bit flip manager 560 may be configured to distinguish or classify the flip function value (F) received from the bit flip operation circuit 540 into an immediate processing bit flip function value (Fs) and a delayed processing bit flip function value (Fm).

[0107] The queue 570 may be configured to temporarily store the delayed bit flip function value (Fm) delivered from the bit flip manager 560. The queue 570 may output the stored function value first according to its design characteristics (eg, First In First Out (FIFO) method).

[0108] The multiplexer 580 may be configured to output one of the delayed processing bit flip function value (Fm) delivered from the queue 570 and the immediate processing bit flip function value (Fs) output from the bit flip manager 560 as a flip function value (F') to the checksum register circuit 550. The multiplexer 580 may receive a second control signal (S). The second control signal (S) may be determined based on an iteration or sub-iteration executed at a current timing or loop and an iteration or sub-iteration to be executed at a next timing or loop during the decoding process.

[0109] The checksum register circuit 550 may be configured to store the flip function value (F') sent through the multiplexer 580, and determine whether to flip the bit to generate and output the feedback bit value (C) in response to the stored flip function value (F'). The feedback bit value (C) output from the checksum register circuit 550 may be flipped or may not be flipped.

[0110] Fig.10 The bit flip information (Bit Flip Info) of the LDPC decoder described in Fig. 9 That is, if there is no decoding operation based on the same data or codeword as the bit flip information (Bit Flip Info) of the LDPC decoder described in Fig.10 If a first control signal (R) is set corresponding to a threshold in the bit flip manager 560 to determine whether to apply a bit flip function value (F), the bit reversal that occurs in an iteration or sub-iteration performed in each cycle of the decoding time (time) (e.g., an area indicated by a pattern) may be substantially the same.

[0111] However, referring to Fig.10 , when a threshold value (e.g., about 50%) is set, 1 / 2 of the bit flips occurring in a specific cycle (a) are applied in that cycle, but the remaining 1 / 2 of the bit flips can be applied later (e.g., applied in the next cycle of cycle (a)). Similarly, 1 / 2 of the bit flips occurring in another cycle (b) are applied in that cycle, but the remaining 1 / 2 can be applied later (e.g., applied in the next cycle of cycle (b)). In addition, 1 / 2 of the bit flips occurring in another cycle (c) can be applied later (e.g., applied in the next cycle of cycle (c)).

[0112] For convenience of description, the threshold is set to a certain proportion of the maximum estimated value of the bit flip that may occur. According to an embodiment, the threshold can be set to limit the number of check nodes that perform sub-iterations. For example, referring to Figure 4 , multiple sub-iterations can be distinguished from each other based on the check nodes C0, C1, C2, C3, C4 involved in each sub-iteration. If five check nodes are set, and the number of sub-iterations executed in each cycle during the decoding operation is limited to three of the five check nodes, then each cycle can only execute the sub-iterations corresponding to the three check nodes without delay, while the sub-iterations corresponding to the other two check nodes can be delayed and executed in a later cycle.

[0113] Reference Fig.10The bit flip information (Bit Flip Info) of the LDPC decoder described in , as the decoding time passes, the iteration and the multiple sub-iterations included in the iteration are not all executed in a specific cycle. In each cycle, several sub-iterations in which the bit flip update is below the threshold among the multiple sub-iterations can be executed. Therefore, the bit flips that may occur through the sub-iterations (the area indicated by the pattern) will be distributed below the threshold of the calculation or bit flip. Figure 7 and Figure 8 , it is possible to reduce the deviation in the timing of the decoding time in the LDPC decoder or whether a bit flip occurs in the loop.

[0114] According to an embodiment, the LDPC decoder may include control logic configured to track whether iterations and sub-iterations are executed, and output a first control signal R and a second control signal S for scheduling. In addition, according to an embodiment, the first control signal R may be replaced with a preset table value, etc.

[0115] According to an embodiment, Figure 1 The controller 130 described in can be configured to check the operating state of the memory system 110 and adjust the operating performance of the ECC circuit 266 including the LDPC decoder. For example, according to the operating state of the memory system 110, the controller 130 can set, change or adjust the threshold of the LDPC decoder.

[0116] Fig.11 The configuration and design of a memory system according to another embodiment of the present disclosure is described. Figure 1 The memory system 110 described in the embodiment may include multiple components or modules capable of performing preset or assigned functions and roles, such as Fig.12 and Fig.13 The memory system 110 or controller 130, 400 described in Fig.11 , various embodiments of the memory system 110 are described based on maximum allowed values ​​of power consumption of various components (eg, module 1, decoder) within the memory system 110.

[0117] Reference Fig.11 , a maximum allowable value of power consumption may be set or designed for each of a plurality of components (module 1, decoder) included in the memory system 110. For example, the maximum allowable value of the first module (module 1) may be α, and the maximum allowable value of the LDPC decoder (decoder) may be β. The maximum allowable value of the memory system 110 (e.g., the total components included in the memory system 110) may be Ω.

[0118] like Figure 7 , Figure 8 and Fig.10As shown, if the second maximum power consumption threshold (P_MAX2) is lowered by setting a threshold in the LDPC decoder, the maximum allowable value (β↓) of the LDPC decoder can be lowered. In the first embodiment (Example 1), if the maximum allowable value of the memory system 110 does not change (Ω) and the maximum allowable value of the LDPC decoder is reduced by an amount (β↓), the maximum allowable value (α↑) of the first module (module 1) can be increased. In this case, the operating performance of the first module (module 1) can be improved.

[0119] As shown in the Nth embodiment (Embodiment N), the maximum allowable value of the memory system 110 can be reduced (Ω↓) as the maximum allowable value of the LDPC decoder is reduced (β↓). In this case, the operational safety of the memory system 110 in a low power environment can be improved.

[0120] As described above, because the memory system 110 includes a plurality of components or a plurality of modules, various designs for improving the performance of the memory system 110 are possible when the maximum allowed value of the LDPC decoder is reduced (β↓).

[0121] Fig.12 A data processing system 100 according to an embodiment of the present disclosure is described.

[0122] Reference Fig.12 , the data processing system 100 may include a memory system 110 and a host 102 coupled or connected to the memory system 110. For example, the host 102 and the memory system 110 may be coupled to each other via a data bus, a host cable, etc. to perform data communication.

[0123] The memory system 110 may include a memory device 150 and a controller 130. The memory device 150 and the controller 130 in the memory system 110 may be considered as physically separate components or elements. The memory device 150 and the controller 130 may be connected via at least one data path. For example, the data path may include a channel and / or a passage. According to an embodiment, Figure 1 The controller 130 shown coupled to the memory device 150 may correspond to Fig.12 and Fig.13 Controllers 130, 400 are shown. Figure 1 , Fig.12 and Fig.13 The controllers 130 , 400 shown may be implemented via a system on a chip (SoC).

[0124] The memory device 150 may include a plurality of memory chips 252 (e.g., NAND flash memory chips) connected to the controller 130 through a plurality of channels CH0, CH1, ..., CHn and paths W0, ..., W_k. The memory chip 252 may include a plurality of memory planes or a plurality of memory dies. According to an embodiment, the memory plane may be regarded as a logical partition or a physical partition including at least one storage block, a driving circuit capable of controlling an array including a plurality of non-volatile memory cells, and a buffer capable of temporarily storing data input to or output from the non-volatile memory cells. Each memory plane or each memory die may support an interleaved mode, in which a plurality of data input and output (input / output) operations are performed in parallel or simultaneously. According to an embodiment, the storage blocks in each memory plane or each memory die included in the memory device 150 may be grouped into super storage blocks to input / output a plurality of data entries. Fig.12 The internal configuration of the memory device 150 shown may be changed based on the operating performance of the memory system 110. Fig.12 The internal configuration described in .

[0125] According to an embodiment, the memory device 150 and the controller 130 may be components or elements divided by function. In addition, according to an embodiment, the memory device 150 and the controller 130 may be implemented with a single chip or a plurality of chips.

[0126] The controller 130 may perform a data input / output operation (e.g., a read operation, a program operation, an erase operation, etc.) in response to a request or command input from an external device (e.g., the host 102). For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of nonvolatile memory cells included in the memory device 150 is transferred to the controller 130. In addition, the controller 130 may perform an operation independently regardless of a request or command input from the host 102. With respect to the operating state of the memory device 150, the controller 130 may perform operations such as garbage collection (GC), wear leveling (WL), and bad block management (BBM) for checking whether a storage block is a bad block and disposing of the bad block.

[0127] Each memory chip 252 may include a plurality of storage blocks. A storage block may be understood as a group of nonvolatile memory cells in which data is removed together by a single erase operation. Although not shown, a storage block may include a page, which is a group of nonvolatile memory cells and stores data together during a single programming operation, or outputs data together during a single read operation. For example, a storage block may include a plurality of pages. The memory device 150 may include a voltage supply circuit capable of supplying at least one voltage to a storage block. The voltage supply circuit may provide a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the nonvolatile memory cells included in the storage block.

[0128] The host 102 interacting with the memory system 110 or the data processing system 110 including the memory system 110 and the host 102 may be a mobile electronic device (e.g., a vehicle), a portable electronic device (e.g., a mobile phone, an MP3 player, a laptop computer, etc.), and a non-portable electronic device (e.g., a desktop computer, a game console, a TV, a projector, etc.). The host 102 may provide interaction between the host 102 and a user using the data processing system 100 or the memory system 110 through at least one operating system (OS). The host 102 sends a plurality of commands corresponding to user requests to the memory system 110, and the memory system 110 performs data input / output operations corresponding to the plurality of commands (e.g., operations corresponding to the user requests).

[0129] Reference Fig.12 , the controller 130 in the memory system 110 operates with the host 102 and the memory device 150. As shown, the controller 130 may have a layered structure including a host interface layer (HIL) 220, a flash translation layer (FTL) 240, and a memory interface layer or flash interface layer (FIL) 260.

[0130] Fig.12 The host interface layer (HIL) 220, the flash translation layer (FTL) 240 and the memory interface layer or flash interface layer (FIL) 260 included in the memory system 110 described in the embodiment are shown as an embodiment. The host interface layer (HIL) 220, the flash translation layer (FTL) 240 and the flash interface layer (FIL) 260 may be implemented in various forms according to the operation performance of the memory system 110. According to an embodiment, the host interface layer (HIL) 220, the flash translation layer (FTL) 240 and the flash interface layer (FIL) 260 may perform operations through a plurality of cores or processors having a pipeline structure included in the controller 130.

[0131] The host 102 and the memory system 110 may use a set of predetermined data communication rules or procedures or a preset interface to send and receive data between the two. Examples of rules or procedures of data communication standards or interfaces for sending and receiving data supported by the host 102 and the memory system 110 include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), Peripheral Component Interconnect Express (PCIe or PCI-e), Serial SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), etc. According to an embodiment, the host 102 and the memory system 110 may be connected to each other via a Universal Serial Bus (USB). Universal Serial Bus (USB) is a highly scalable, hot-swappable, plug-and-play serial interface that can ensure cost-effective standard connections with peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, and video conferencing cameras.

[0132] The memory system 110 may support high-speed non-volatile memory (NVMe). High-speed non-volatile memory (NVMe) is an interface based at least on high-speed peripheral component interconnect (PCIe), which is designed to improve the performance and design flexibility of the host 102, server, computing device, etc. equipped with the memory system 110. PCIe can use a slot or a specific cable to connect a computing device (e.g., host 102) and a peripheral device (e.g., memory system 110). For example, PCIe can use multiple pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one wire (e.g., x1, x4, x8, or x16) to achieve high-speed data communication of more than hundreds of megabits per second (Mbps). According to an embodiment, the PCIe scheme can achieve a bandwidth of tens to hundreds of gigabits per second (Gbps).

[0133] The buffer manager 280 in the controller 130 may control input / output of data or operation information in conjunction with the host interface layer (HIL) 220, the flash translation layer (FTL) 240, and the memory interface layer or flash interface layer (FIL) 260. To this end, the buffer manager 280 may set or establish various buffers, caches, or queues in the memory, and control data input / output of the buffers, caches, or queues, or data transmission between the buffers, caches, or queues in response to requests or commands generated by the host interface layer (HIL) 220, the flash translation layer (FTL) 240, and the memory interface layer or flash interface layer (FIL) 260. For example, the controller 130 may temporarily store read data provided from the memory device 150 in response to a request from the host 102 before providing the read data to the host 102. Moreover, the controller 130 may temporarily store write data provided from the host 102 in the memory before storing the write data in the memory device 150. When controlling operations such as a read operation, a program operation, and an erase operation performed in the memory device 150, read data or write data transmitted or generated between the controller 130 in the memory system 110 and the memory device 150 may be stored and managed in a buffer, a queue, etc. in the memory established by the buffer manager 280. In addition to the read data or the write data, the buffer manager 280 may also store signals or information (e.g., mapping data, a read command, a program command, etc. for performing operations such as programming and reading data between the host 102 and the memory device 150) in a buffer, a cache, a queue, etc. in the memory. The buffer manager 280 may set or manage a command queue, a program memory, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, a mapping buffer / cache, etc.

[0134] The host interface layer (HIL) 220 may handle commands, data, etc. sent from the host 102. By way of example and not limitation, the host interface layer 220 may include a command queue manager 222 and an event queue manager 224. The command queue manager 222 may sequentially store commands, data, etc. received from the host 102 in a command queue, and output the stored commands and / or data to the event queue manager 224, for example, in the order in which the commands and / or data are stored in the command queue manager 222. The event queue manager 224 may sequentially send events for processing commands, data, etc. received from the command queue. According to an embodiment, the event queue manager 224 may classify, manage, or adjust commands, data, etc. received from the command queue. According to an embodiment, the host interface layer 220 may include an encryption manager (Encryp) 226 configured to encrypt a response or output data to be sent to the host 102, or to decrypt an encrypted portion of a command or data sent from the host 102.

[0135] A plurality of commands or data of the same characteristics may be sent from the host 102 to the memory system 110, or a plurality of commands and data of different characteristics may be sent to the memory system 110 after being mixed or shuffled by the host 102. For example, a plurality of commands for reading data (i.e., read commands) may be transmitted, or commands for reading data (i.e., read commands) and commands for programming / writing data (i.e., write commands) may be sent alternately to the memory system 110. The command queue manager 222 of the host interface layer 220 may sequentially store the commands, data, etc. sent from the host 102 in the command queue. Thereafter, the host interface layer 220 may estimate or predict which internal operation the controller 130 will perform according to the characteristics of the commands, data, etc. sent from the host 102. The host interface layer 220 may determine the processing order and priority of the commands, data, etc. based on their characteristics. According to the characteristics of the command, data, etc. sent from the host 102, the event queue manager 224 in the host interface layer 220 is configured to receive an event from the buffer manager 280, which should be processed or handled inside the memory system 110 or the controller 130 according to the command, data, etc. input from the host 102. Then, the event queue manager 224 can transmit the event including the command, data, etc. to the flash translation layer (FTL) 240.

[0136] According to an embodiment, the flash translation layer (FTL) 240 may include a host request manager (HRM) 242, a mapping manager (MM) 244, a state manager 246, and a block manager (BM / BBM) 248. According to an embodiment, the flash translation layer (FTL) 240 may implement a multi-threading scheme to perform data input / output (I / O) operations. The multi-threaded FTL may be implemented by a multi-core processor using multi-threading included in the controller 130. For example, the host request manager (HRM) 242 may manage events sent from an event queue. The mapping manager (MM) 244 may handle or control mapping data. The state manager 246 may perform operations such as garbage collection (GC) or wear leveling (WL) after checking the operating state of the memory device 150. The block manager 248 may run commands or instructions on blocks in the memory device 150.

[0137] The host request manager (HRM) 242 may use the mapping manager (MM) 244 and the block manager 248 to handle or process requests according to read and program commands and events passed from the host interface layer 220. The host request manager (HRM) 242 may send a query request to the mapping manager (MM) 244 to determine a physical address corresponding to a logical address input along with the event. The host request manager (HRM) 242 may send a read request together with the physical address to the memory interface layer 260 to process the read request, i.e., handle the event. In one embodiment, the host request manager (HRM) 242 may send a program request (or a write request) to the block manager 248 to program data to a specific blank page in the memory device 150 where no data is stored, and then a mapping update request corresponding to the program request may be sent to the mapping manager (MM) 244 to update items related to the programmed data in the information that maps the logical address and the physical address to each other.

[0138] The block manager 248 may convert the program requests passed from the host request manager (HRM) 242, the mapping manager (MM) 244, and / or the state manager 246 into flash program requests for the memory device 150 to manage the flash blocks in the memory device 150. In order to maximize or improve the programming or writing performance of the memory system 110, the block manager 248 may collect the program requests and send the flash program requests for multi-plane and one-shot programming operations to the memory interface layer 260. In an embodiment, the block manager 248 sends several flash program requests to the memory interface layer 260 to enhance or maximize the parallel processing of the multi-channel and multi-directional flash controller.

[0139] In an embodiment, the block manager 248 may manage the blocks in the memory device 150 according to the number of valid pages, select and erase blocks without valid pages when a free block is needed, and select blocks with the least number of valid pages when it is determined that garbage collection is to be performed. The state manager 246 may perform garbage collection to move valid data stored in the selected blocks to the free blocks and erase the data stored in the selected blocks so that the memory device 150 may have enough free blocks (i.e., free blocks without data).

[0140] When the block manager 248 provides information about the block to be erased to the state manager 246, the state manager 246 may check all flash pages of the block to be erased to determine whether each page of the block is valid. For example, to determine the validity of each page, the state manager 246 may identify the logical address recorded in the out-of-band (OOB) area of ​​each page of the memory device 150. To determine whether each page is valid, the state manager 246 may compare the physical address of the page with the physical address mapped to the logical address obtained from the query request. The state manager 246 sends a programming request to the block manager 248 for each valid page. When the programming operation is completed, the mapping table may be updated by the mapping manager 244.

[0141] The mapping manager 244 may manage mapping data, such as a logical-physical mapping table. The mapping manager 244 may process various requests generated by the host request manager (HRM) 242 or the state manager 246, such as queries, updates, etc. The mapping manager 244 may store the entire mapping table in the memory device 150 (e.g., flash memory / non-volatile memory) and cache mapping entries according to the storage capacity of the memory 144. When a mapping cache miss occurs when processing a query or update request, the mapping manager 244 may send a read request to the memory interface layer 260 to load the relevant mapping table stored in the memory device 150. When the number of dirty cache blocks in the mapping manager 244 exceeds a certain threshold, a program request may be sent to the block manager 246 to obtain a clean cache block and the dirty mapping table may be stored in the memory device 150.

[0142] When performing garbage collection, the state manager 246 copies the valid page to the free block, and the host request manager (HRM) 242 can program the latest version of the data for the page of the same logical address and issue an update request at the same time. When the state manager 246 requests a mapping update in a state where the copying of the valid page is not completed normally, the mapping manager 244 may not perform a mapping table update. This is because: when the state manager 246 requests a mapping update, the mapping request is issued with the old physical information, and the copying of the valid page is completed later. The mapping manager 244 can perform a mapping update operation when or only when the latest mapping table still points to the old physical address to ensure accuracy.

[0143] The memory interface layer or flash interface layer (FIL) 260 may exchange data, commands, status information, etc. with the plurality of memory chips 252 in the memory device 150 through a data communication method. According to an embodiment, the memory interface layer 260 may include a state check scheduler (SM / SC) 262 and a data path manager (DPC) 264. The state check scheduler 262 may check and determine the operation state of the plurality of memory chips 252 connected to the controller 130. The operation state may represent the state of the plurality of channels CH0, CH1, ..., CHn and the plurality of paths W0, ..., W_k, etc. The transmission and reception of data or commands may be scheduled in response to the operation state of the plurality of memory chips 252 and the plurality of channels CH0, CH1, ..., CHn. The data path manager 264 may control the transmission and reception of data, commands, etc. through the plurality of channels CH0, CH1, ..., CHn and the paths W0, ..., W_k based on the information sent from the state check scheduler 262. According to an embodiment, the data path manager 264 may include a plurality of transceivers, each transceiver corresponding to each of the plurality of channels CH0, CH1, ..., CHn. In addition, according to an embodiment, the status check schedule manager 262 and the data path manager 264 included in the memory interface layer 260 may be implemented as a memory control sequence generator or coupled with the memory control sequence generator.

[0144] According to an embodiment, the memory interface layer 260 may further include an error correction code (ECC) circuit 266 configured to perform error checking and correction on data transmitted between the controller 130 and the memory device 150. The ECC circuit 266 may be implemented as a separate module, circuit, or firmware in the controller 130, but according to an embodiment, may also be implemented in each memory chip 252 included in the memory device 150. The ECC circuit 266 may include a program, circuit, module, system, or device for detecting and correcting error bits of data processed by the memory device 150.

[0145] In order to find and correct any errors in the data transmitted from the memory device 150, the ECC circuit 266 may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder may perform error correction encoding on the data to be programmed into the memory device 150 to generate encoded data with parity bits added, and store the encoded data in the memory device 150. When the controller 130 reads the data stored in the memory device 150, the ECC decoder may detect and correct the error bits contained in the data read from the memory device 150. For example, after performing error correction decoding on the data read from the memory device 150, the ECC circuit 266 may determine whether the error correction decoding is successful, and output an instruction signal based on the result of the error correction decoding, such as a correction success signal or a correction failure signal. The ECC circuit 266 may use the parity bits generated during the ECC encoding process for the data stored in the memory device 150 to correct the error bits of the read data entry. When the number of error bits is greater than or equal to the number of correctable error bits, the ECC circuit 266 may not correct the error bits, but output a correction failure signal indicating that the correction of the error bits failed.

[0146] According to an embodiment, the ECC circuit 266 may perform error correction operations based on coded modulation such as low-density parity check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM), block coded modulation (BCM), etc. The ECC circuit 266 may include all circuits, modules, systems and / or devices that perform error correction operations based on at least one of the above codes.

[0147] For example, the encoder in the ECC circuit 266 can generate a codeword as a unit of data to which the ECC is applied. A codeword of length n bits can include k bits of user data and (nk) bits of parity. The code rate can be calculated as (k / n). The higher the code rate, the more user data can be stored in a given codeword. When the length of the codeword is long and the code rate is small, the error correction capability of the ECC circuit 266 can be improved. In addition, the ECC circuit 266 uses information read from channels CH0, CH1, ... CHn to perform decoding. The decoder in the ECC circuit 266 can be divided into a hard decision decoder and a soft decision decoder according to how many bits represent the information to be decoded. The hard decision decoder uses the memory unit output information represented by 1 bit to decode, and the 1 bit of information used at this time is called hard decision information. The soft decision decoder uses more accurate memory unit output information composed of 2 bits or more bits, which is called soft decision information. The ECC circuit 266 can use hard decision information or soft decision information to correct errors contained in the data.

[0148] According to an embodiment, to improve error correction capability, ECC circuit 266 may use a concatenated code using two or more codes. In addition, ECC circuit 266 may use a product code that divides a codeword into several rows and columns and applies different relatively short ECCs to each row and column.

[0149] According to an embodiment, the manager included in the host interface layer 220, the flash translation layer (FTL) 240, and the memory interface layer or flash interface layer (FIL) 260 may be implemented with a general-purpose processor, an accelerator, a dedicated processor, a co-processor, a multi-core processor, etc. According to an embodiment, the manager may be implemented by firmware working in cooperation with the processor.

[0150] According to an embodiment, the memory device 150 is implemented as a nonvolatile memory such as a flash memory, for example, a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable ROM (EPROM), an electrically erasable ROM (EEPROM), a magnetic (MRAM), a NAND flash memory, a NOR flash memory, etc. In another embodiment, the memory device 150 may be implemented by at least one of a phase change random access memory (PCRAM), a resistance random access memory (ReRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), a spin transfer torque magnetic random access memory (STT-MRAM), etc.

[0151] Fig.13 A data storage system according to an embodiment of the present disclosure is described. Fig.13A memory system including multiple cores or multiple processors is shown, which is an example of a data storage system. The memory system can support a high-speed non-volatile memory (NVMe) protocol.

[0152] NVMe is a transmission protocol designed for solid-state storage that operates much faster than traditional hard drives. NVMe can support higher input / output operations per second (IOPS) and lower latency, thereby increasing data transfer speeds and improving the overall performance of data storage systems. Unlike SATA, which is designed for hard drives, NVMe can exploit the parallelism of solid-state storage to use multiple queues and processors (e.g., CPUs) more efficiently. NVMe is designed to allow the host to use multiple threads to implement higher bandwidth. NVMe can make full use of the parallelism provided by SSDs. However, due to limited scalability of firmware within SSDs, limited computing power, and high hardware contention, the memory system may not be able to process a large number of I / O requests in parallel.

[0153] Reference Fig.13 , a host as an external device can be connected to the memory system through multiple PCIe Gen3.0 channels, a PCIe physical (PHY) layer 412, and a PCIe core 414. The controller 400 may include three embedded processors 432A, 432B, 432C, each processor using two cores 302A, 302B. According to an embodiment, multiple cores 302A, 302B or multiple embedded processors 432A, 432B, 432C can be implemented with a tensor processing unit (TPU).

[0154] The plurality of embedded processors 432A, 432B, 432C may be coupled to an internal DRAM (e.g., DDR) controller 434 via a processor interconnect. The controller 400 further includes a low density parity check (LDPC) sequencer 460, a direct memory access (DMA) engine or controller 420, a scratch pad memory 450 for metadata management, and an NVMe controller 410. The components within the controller 400 may be coupled to a plurality of channels connected to a plurality of memory packages (NAND flash) 152 via a flash physical (PHY) layer (e.g., a NAND flash physical layer) 440. The plurality of memory packages 152 may correspond to Fig.12 Multiple memory chips 252 described in.

[0155] According to an embodiment, the NVMe controller 410 included in the controller 400 is a storage controller designed for use with a solid-state drive (SSD) using an NVMe interface. The NVMe controller 410 can manage the SSD and the computer CPU (e.g., Fig.12The NVMe controller 410 can support fast data transfer rates using a simplified, low-overhead protocol.

[0156] According to an embodiment, the scratch pad 450 may be a storage area for temporarily storing data set by the NVMe controller 410. The scratch pad 450 may be used to store data waiting to be written to multiple memory packages 152. The scratch pad 450 may also be used as a buffer to speed up the write process, which typically uses a small amount of dynamic random access memory (DRAM) or static random access memory (SRAM). When a write command is run, the data may be first written to the scratch pad 450 and then transferred to multiple memory packages 152 in larger blocks. The scratch pad 450 may be used as a temporary storage buffer to help optimize the write performance of multiple memory packages 152. The scratch pad 450 may be used as an intermediate storage device for data before the data is written to the non-volatile memory unit.

[0157] The direct memory access (DMA) controller 420 included in the controller 400 is a component that transfers data between the NVMe controller 410 and the host memory in the host without involving the processor of the host. The DMA engine 420 can support the NVMe controller 410 to read or write data directly from the host memory without the intervention of the host processor. According to an embodiment, the DMA controller 420 can use a DMA descriptor to implement or support high-speed data transfer between the host and the NVMe device, and the DMA descriptor includes information about data transfer, such as a buffer address, a transfer length, and other control information.

[0158] A low-density parity check (LDPC) sorter 460 in the controller 400 is a component that performs error correction on data stored in a plurality of memory packages 152. Here, an LDPC code is an error correction code that is generally used in a NAND flash memory to reduce a bit error rate. The LDPC sorter 460 may be designed to immediately process encoding and decoding of LDPC codes when reading data from and writing data to a NAND flash memory. According to an embodiment, the LDPC sorter 460 may divide the data into a plurality of blocks, encode each block using an LDPC code, and store the encoded data in a plurality of memory packages 152. Thereafter, when the encoded data is read from a plurality of memory packages 152, the LDPC sorter 460 may decode the encoded data based on the LDPC code and correct errors that may have occurred during a write operation or a read operation. The LDPC sorter 460 may correspond to Fig.12 ECC circuit 266 described in .

[0159] In addition, although Fig.12 and Fig.13 An example of a memory system including a memory device 150 or a plurality of memory packages 152 capable of storing data is shown, but a data storage system according to an embodiment of the present disclosure may not be limited to Fig.12 and Fig.13 For example, the memory device 150, the plurality of memory packages 152, or the data storage device controlled by the controller 130, 400 may include a volatile or non-volatile memory device. Fig.13 In the embodiment, it is described that the controller 400 can communicate with a host (see FIG. 1 ) placed outside the memory system through a high-speed NVME (NVMe) interface and a high-speed PCI (PCIe). Fig.12 In an embodiment, the controller 400 may perform data communication with at least one host through a protocol such as a computing express link (CXL).

[0160] In addition, according to an embodiment, an apparatus and method for distributed processing or allocation / reallocation of multiple instructions in a controller including multiple processors of a pipeline structure according to an embodiment of the present disclosure can be applicable to a data processing system including multiple memory systems or multiple data storage devices. For example, a memory pool system (MPS) is a very general, adaptable, flexible, reliable and efficient memory management system in which a memory pool, such as a logical partition of a main memory or storage device reserved for processing one or a group of tasks, can be used to control or manage a storage device connected to a controller. A controller including multiple processors in a pipeline structure can control the transfer of data and programs to a memory pool controlled or managed by a memory pool system (MPS).

[0161] As described above, according to the embodiments of the present disclosure, the operational safety of a controller or a memory system may be improved or enhanced by reducing power consumed to check and correct errors included in data transmitted from a memory device of the memory system.

[0162] Additionally, data input / output performance (eg, I / O throughput) of a memory system may be improved by reducing power consumption of a controller within the memory system or providing an efficient or effective manner for power allocation or power consumption in the controller or memory system.

[0163] Method described herein, process and / or operation can be performed by code or instruction to be run by computer, processor, controller or other signal processing device.Computer, processor, controller or other signal processing device can be those described herein or those outside the element described herein.Due to the algorithm forming the method or the basis of operation of computer, processor, controller or other signal processing device is described in detail, therefore the code or instruction for implementing the operation of method embodiment can convert computer, processor, controller or other signal processing device into a special processor, to perform the method herein.

[0164] Moreover, another embodiment may include a computer-readable medium, such as a non-transitory computer-readable medium, for storing the above-mentioned code or instructions. The computer-readable medium may be a volatile or non-volatile memory or other storage device, which may be detachably or fixedly connected to a computer, processor, controller or other signal processing device, which will run the code or instructions to perform the operations of the method embodiments or apparatus embodiments of the present invention.

[0165] The controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features of the embodiments disclosed herein may be implemented, for example, in non-transient logic, which may include hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may be, for example, any of a variety of integrated circuits including, but not limited to, application specific integrated circuits, field programmable gate arrays, combinations of logic gates, systems on chips, microprocessors, or other types of processing or control circuits.

[0166] When implemented at least in part with software, controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may include, for example, a memory or other storage device for storing codes or instructions to be run by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or those outside the elements described herein. Since the algorithm forming the basis of the method or operation of the computer, processor, microprocessor, controller, or other signal processing device is described in detail, the code or instructions for implementing the operation of the method embodiment can convert the computer, processor, controller, or other signal processing device into a special-purpose processor to perform the method described herein.

[0167] Although the present teaching has been shown and described for specific embodiments, it will be apparent to those skilled in the art from this disclosure that various changes and modifications may be made without departing from the spirit and scope of the present disclosure as defined in the appended claims. In addition, the embodiments may be combined to form additional embodiments.

Claims

1. A memory system, comprising: A memory device outputs a code word; as well as Controller: Establishing a plurality of variable nodes and a plurality of check nodes according to the codeword; and A decoding operation is scheduled to ensure that the number of checksum updates occurring during one cycle of the decoding operation does not exceed a threshold value set to be less than the number of check nodes, wherein the decoding operation includes iterative operations and each iterative operation includes a plurality of sub-iterative operations.

2. The memory system according to claim 1, wherein: When the number of checksum updates occurring during a first cycle exceeds the threshold, the controller delays at least one sub-iteration operation associated with one or more checksum updates exceeding the threshold to a next cycle of the first cycle.

3. The memory system according to claim 2, wherein: The total number of the iteration operation and the sub-iteration operation is changed by the checksum update.

4. The memory system according to claim 1, wherein: The controller performs thermal throttling based on a maximum power consumption preset in response to the threshold value.

5. The memory system according to claim 1, wherein: The controller changes the threshold further based on an operating state of the memory system.

6. The memory system according to claim 1, wherein: The controller comprises: Operate circuits to calculate or estimate whether a bit flip has occurred; a manager, determining whether to perform the bit flipping on a result calculated or estimated by the operation circuit; a buffer to store bit flip targets that are not applied based on a determination by the manager; a multiplexer that outputs one of the outputs of the manager and the buffer; and A register stores the checksum and is updated in response to the output of the multiplexer.

7. The memory system according to claim 6, wherein: The manager determines whether to perform the bit flipping according to a first control signal corresponding to the threshold.

8. The memory system according to claim 7, wherein: The multiplexer outputs one of the outputs of the manager and the buffer according to a second control signal based on the schedule.

9. The memory system according to claim 6, wherein: The controller further comprises: The control logic tracks whether the iteration operation and the sub-iteration operation are executed, and outputs the first control signal and the second control signal based on the schedule.

10. A method for decoding a codeword in a memory system, comprising: Establishing a plurality of variable nodes and a plurality of check nodes according to the codeword; performing a flip calculation to determine whether a bit flip occurs for the plurality of variable nodes based on the plurality of check nodes during a decoding operation including an iterative operation, each iterative operation including a plurality of sub-iterative operations; determining whether scheduling of the checksum update occurs based on the rollover calculation when the number of checksum updates occurring during one cycle of the decoding operation does not exceed a threshold value set to be less than the number of the check nodes; as well as The iteration operation and the sub-iteration operation are performed based on the schedule.

11. The method according to claim 10, further comprising: When the number of checksum updates occurring during the first cycle exceeds the threshold, storing a portion of the checksum updates exceeding the threshold; as well as A determination is made as to whether a stored checksum update occurs in a schedule for a next cycle of the first cycle.

12. The method according to claim 11, wherein: The total number of the iteration operation and the sub-iteration operation is changed by the checksum update.

13. The method according to claim 10, further comprising: Thermal throttling is performed based on a maximum power consumption preset in response to the threshold.

14. The method according to claim 10, further comprising: The threshold is changed based on an operating state of the memory system.

15. A memory system comprising: A low density parity check decoder, i.e., an LDPC decoder, performs a decoding operation based on a preset threshold, wherein the decoding operation includes at least one iterative operation, and the iterative operation includes at least one sub-iterative operation; as well as The control logic determines the threshold value based on the operation state of the memory system and determines a schedule as to whether the iterative operation or the sub-iterative operation is performed in one cycle of a decoding operation of the LDPC decoder.

16. The memory system of claim 15, further comprising: A memory device outputs a code word, Wherein, the control logic: Establishing a plurality of variable nodes and a plurality of check nodes according to the codeword; and The decoding operation is scheduled to ensure that the number of checksum updates occurring during one cycle of the decoding operation does not exceed a threshold, the threshold being set to be less than the number of check nodes.

17. The memory system of claim 16, wherein: When the number of checksum updates occurring during the first loop exceeds the threshold, the control logic delays at least one sub-iteration operation of one or more checksum updates exceeding the threshold to a next loop of the first loop.

18. The memory system of claim 17, wherein: The total number of the iteration operation and the sub-iteration operation is changed by the checksum update.

19. The memory system according to claim 15, wherein: The control logic performs thermal throttling based on a maximum power consumption preset in response to the threshold.

20. The memory system of claim 15, wherein: The LDPC decoder comprises: Operate circuits to calculate or estimate whether a bit flip has occurred; a manager, determining whether to perform the bit flipping on a result calculated or estimated by the operation circuit; a buffer to store bit flip targets that are not applied based on a determination by the manager; a multiplexer that outputs one of the outputs of the manager and the buffer; and A register stores the checksum and is updated in response to the output of the multiplexer.

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