Anti-high-frequency bias sampling device and method

Abstract

The invention discloses an anti-high-frequency bias sampling device and method. The sampling position of the next beat is updated in real time by comprehensively considering the hopping condition and the sampling position of the data to be oversampled of the previous beat, the data to be oversampled of the current beat is sampled based on the latest sampling position, and finally the sampled data with the dynamic bit width is output with the fixed bit width. Compared with the prior art, the method has the advantages that higher frequency offset can be tolerated by updating the sampling position in real time; the logic is simple, and does not need to calculate source and sink end frequency offset like a traditional method, so that more resources can be saved; the method is high in universality, and can be applied to bearer networks such as Ethernet, optical transport networks and the like, and even all places needing oversampling in digital communication.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a device and method for resisting high-frequency oversampling. Background Art

[0002] In digital communications, oversampling means that the frequency of received data is twice that of sent data. For low-speed services in the 5G bearer network, the clock frequency is generally less than 622Phz, and the Serdes (Serializer-Deserializer) clock frequency is generally higher than 1Ghz. If the Serdes clock frequency is N times that of the low-speed service (N is an integer greater than 2), then after the low-speed service is transmitted via Serdes, 1-bit data is naturally copied to N-bit. However, due to the frequency deviation between the Serdes clock frequency and the clock frequency of the low-speed service, sometimes the copied data is not the standard N times, and the data may be copied N-1 times or N+1 times. In order to recover the data of the low-speed service after transmission via Serdes, an oversampling module needs to be introduced.

[0003] In related technologies, oversampling is to calculate the clock frequency deviation of the source and destination by counting the number of clock offsets, or to calculate the clock frequency deviation of the source and destination by counting the intervals between two adjacent frame headers using the sampling clock, and then determine the sampling strategy; when updating the sampling position of valid data, it is only based on the "01" jump in the data. The study found that its defects are that when determining the sampling strategy, it is necessary to calculate the clock frequency deviation of the source and destination first, resulting in a waste of circuit resources and a slow update of the sampling position; when the frequency deviation is large, the sampling position of the valid data is only updated based on the "01" jump in the data, which is prone to sampling errors. Summary of the invention

[0004] In view of the defects of the prior art, the present application provides a high-frequency bias-resistant oversampling device and method, which can tolerate higher frequency deviations, save more circuit resources, and have strong versatility.

[0005] In a first aspect, an embodiment of the present application provides a high-frequency oversampling resistance device, the high-frequency oversampling resistance device comprising:

[0006] a sampling position determination module, configured to determine a value of a sampling position register corresponding to the (i+1)th beat according to a value of a sampling position register corresponding to the i-th beat and a jump condition of valid to-be-oversampled data inputted at the i-th beat, wherein i is a positive integer greater than or equal to 1;

[0007] A data sampling module is used to sample valid data to be oversampled inputted for each beat according to the value of a sampling position register corresponding to each beat, so as to obtain sampling data corresponding to each beat;

[0008] The bit width conversion module is used to convert the sampled data into a fixed Q bit width output.

[0009] In combination with the first aspect, in one implementation, the high-frequency oversampling resistance device further includes:

[0010] The transition edge search module is used to determine the transition status of the valid data to be oversampled input in each beat.

[0011] In combination with the first aspect, in one implementation, the data to be oversampled is P-bit-width parallel data to be oversampled, and the transition edge search module is specifically used for:

[0012] For the latest data to be oversampled inputted in the latest beat, when the valid signal indication of the latest data to be oversampled is valid, cache the data of the latest data to be oversampled at the lowest transmission priority for one beat;

[0013] Combining the latest data to be oversampled and the data to be oversampled in the previous shot at the lowest bit of transmission priority into (P+1)-bit data;

[0014] An indication register with a width of P is obtained by performing XOR on every two adjacent bits of the (P+1)-bit data, and is used to indicate the transition of the latest data to be oversampled, wherein when the value of the k-th bit in the indication register is 1, it indicates that the k-th bit of the latest data to be oversampled has a transition compared to the (k-1-th bit).

[0015] In combination with the first aspect, in one implementation, the data sampling module is further used for:

[0016] The sampling data corresponding to each beat is stored in a sampling data register, and the bit width of the sampling data register is the maximum number of sampling bits per beat.

[0017] In combination with the first aspect, in one implementation, the bit width conversion module is specifically configured to:

[0018] The sampled data in the sampled data register is stored in the output buffer register, wherein the bit width of the output buffer register is 2Q;

[0019] When the value of the pointer register is greater than or equal to Q or when the value of the pointer register is greater than or equal to 2Q, the data on the Q bit with the highest transmission priority will be output. The value of the pointer register is used to indicate the starting position of the remaining space of the output buffer register.

[0020] In a second aspect, an embodiment of the present application provides a method for resisting high-frequency biased oversampling, and the method for resisting high-frequency biased oversampling includes:

[0021] Determine the value of the sampling position register corresponding to the (i+1)th beat according to the value of the sampling position register corresponding to the i-th beat and the jump condition of the valid to-be-oversampled data inputted in the i-th beat, where i includes a positive integer greater than or equal to 1;

[0022] According to the value of the sampling position register corresponding to each beat, the valid data to be oversampled inputted for each beat is sampled to obtain the sampling data corresponding to each beat;

[0023] Convert the sampled data into a fixed Q-bit width output.

[0024] In combination with the second aspect, in one implementation, the method for resisting high-frequency oversampling further includes:

[0025] Determine the transition status of the valid data to be oversampled input in each beat.

[0026] In conjunction with the second aspect, in one implementation, determining a transition condition of valid data to be oversampled input per beat includes:

[0027] For the latest data to be oversampled inputted in the latest beat, when the valid signal indication of the latest data to be oversampled is valid, cache the data of the latest data to be oversampled at the lowest transmission priority for one beat;

[0028] Combining the latest data to be oversampled and the data to be oversampled in the previous shot at the lowest bit of transmission priority into (P+1)-bit data;

[0029] An indication register with a width of P is obtained by performing XOR on every two adjacent bits of the (P+1)-bit data, and is used to indicate the transition of the latest data to be oversampled, wherein when the value of the k-th bit in the indication register is 1, it indicates that the k-th bit of the latest data to be oversampled has a transition compared to the (k-1-th bit).

[0030] In conjunction with the second aspect, in one implementation, after obtaining the sampling data corresponding to each beat, the method further includes:

[0031] The sampling data corresponding to each beat is stored in a sampling data register, and the bit width of the sampling data register is the maximum number of sampling bits per beat.

[0032] In conjunction with the second aspect, in one implementation, converting the sampled data into a fixed Q-bit width output includes:

[0033] The sampled data in the sampled data register is stored in the output buffer register, wherein the bit width of the output buffer register is 2Q;

[0034] When the value of the pointer register is greater than or equal to Q or when the value of the pointer register is greater than or equal to 2Q, the data on the Q bit with the highest transmission priority will be output. The value of the pointer register is used to indicate the starting position of the remaining space of the output buffer register.

[0035] The beneficial effects brought by the technical solution provided by the embodiments of the present application include:

[0036] 1. By updating the sampling position in real time, higher frequency deviation can be tolerated;

[0037] 2. The logic is simple and there is no need to calculate the source and sink frequency deviation as in the traditional method, which can save more resources;

[0038] 3. It has strong versatility and can be applied to bearer networks such as Ethernet and optical transport networks, and even to all places where oversampling is required in digital communications. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 This is a functional module diagram of an embodiment of the high-frequency oversampling device of the present application;

[0040] Figure 2 Schematic diagram of an application scenario of an anti-high frequency oversampling device in an embodiment;

[0041] Figure 3 This is a schematic diagram of a "01" jump search in an embodiment of the present application;

[0042] Figure 4 A schematic diagram of determining a sampling position in an embodiment of the present application;

[0043] Figure 5 This is a sampling schematic diagram in an embodiment of the present application;

[0044] Figure 6 This is a schematic diagram of bit width conversion in an embodiment of the present application;

[0045] Figure 7 This is a flow chart of an embodiment of a method for resisting high-frequency oversampling of the present application. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0047] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0048] In a first aspect, an embodiment of the present application provides a high-frequency oversampling resistance device.

[0049] In one embodiment, referring to Figure 1 , Figure 1 This is a functional module diagram of an embodiment of the high-frequency oversampling device of the present application. Figure 1 As shown, the high frequency over-sampling device comprises:

[0050] The sampling position determination module 20 is used to determine the value of the sampling position register corresponding to the (i+1)th beat according to the value of the sampling position register corresponding to the i-th beat and the jump condition of the valid to-be-oversampled data inputted at the i-th beat, wherein i includes a positive integer greater than or equal to 1;

[0051] In this embodiment, the value of the sampling position register corresponding to the next beat is determined according to the value of the sampling position register corresponding to the previous beat and the jump condition of the input valid data to be oversampled, so as to update the sampling position in real time, and a higher frequency deviation can be tolerated. Among them, the high-frequency deviation oversampling device also includes a jump edge search module 10, which is used to determine the jump condition of the valid data to be oversampled input in each beat.

[0052] In one embodiment, the data to be oversampled is P-bit-width parallel data to be oversampled, and the transition edge search module 10 is specifically used for:

[0053] For the latest data to be oversampled inputted in the latest beat, when the valid signal indication of the latest data to be oversampled is valid, the data of the latest data to be oversampled at the lowest bit of the transmission priority is cached for one beat; the latest data to be oversampled and the data of the last beat of the data to be oversampled at the lowest bit of the transmission priority are combined into (P+1)-bit data; and an indication register with a width of P bits is obtained by performing an XOR operation on every two adjacent bits of the (P+1)-bit data, which is used to indicate the jump of the latest data to be oversampled, wherein when the value of the kth bit in the indication register is 1, it indicates that the kth bit of the latest data to be oversampled jumps compared with the (k-1)th bit.

[0054] For ease of explanation, the following text uses 7 times (N=7) oversampling for explanation, that is, the aforementioned Serdes clock frequency is 7 (N=7) times the low-speed bearer network service clock frequency, the oversampled input data bit width is 40-bit (P=40), the output data bit width is 40-bit (Q=40), and the parallel data transmission direction is set to low bits first and high bits last. However, it should be stated that the present application scheme is also applicable to all places in digital communications where oversampling is required. Figure 2 , Figure 2Schematic diagram of an application scenario of an anti-high frequency oversampling device in an embodiment. Figure 2 As shown, the Serdes clock frequency is 7 times of the low-speed bearer network service configured by the instrument, and the configured oversampling multiple is 7 times oversampling. The oversampled data after Serdes transmission is processed by the anti-high-frequency bias oversampling device and output to the logic module.

[0055] The data after Serdes transmission enters the transition edge search module 10, which searches for the "01" transition of the input 40-bit bit width parallel valid data to be oversampled in real time. When the valid signal indication of the input 40-bit bit width parallel data to be oversampled is valid, the 39-bit of the current 40-bit bit width parallel data to be oversampled is cached for one beat, and the current 40-bit data to be oversampled is combined with the 39-bit cached data of the previous oversampled data into 41-bit data. The 41-bit data is XORed for every two adjacent bits to obtain the 40-bit bit width indication register change[39:0]. The indication register change[39:0] is used to indicate the "01" transition of the current 40-bit bit width parallel data to be oversampled. If a certain bit value in change[39:0] is 1, it means that the bit of the input 40-bit bit width parallel data to be oversampled has a "01" transition compared to the previous bit. Figure 3 As shown, Figure 3 This is a schematic diagram of the "01" jump search in an embodiment of the present application. Figure 3 As shown, the first row of data has 41 bits in total, of which the rightmost bit 0 is the 39th bit of data cached in the previous shot to be oversampled, and the remaining 40 bits are the 40 bits of data to be oversampled in the current shot. The 41-bit data is XORed by two adjacent bits in sequence. 00 or 11 are XORed to 0; 01 or 10 are XORed to 1. Figure 3 , the first row din[0] and din[1] are XORed to get the second row change[0], the first row din[1] and din[2] are XORed to get the second row change[1], and so on, finally getting the second row 40-bit data change[39:0], which indicates the jump status of the 40-bit data to be oversampled.

[0056] Further, refer to Figure 4 , Figure 4 FIG. 1 is a schematic diagram of determining a sampling position in an embodiment of the present application. Figure 4 The sampling position determination module updates the value of the next beat 40-bit wide sampling position register according to the "01" jump of the current beat oversampled data with a 40-bit width and the current beat sampling position register with a 40-bit width. Figure 4 The left column indicates the current beat oversampled data "01" jump status indication register change[39:0], the upper row indicates the updated value of the next beat oversampled data sampling position register sample_posi[39:0], and the right side indicates the specific bit value of the current oversampled data sampling position register sample_posi. The value of the sampling position register corresponding to the (i+1) beat is determined according to the value of the sampling position register corresponding to the i-th beat and the jump status of the valid oversampled data input in the i-th beat, including the following situations:

[0057] Case 1: First check whether chang

[39] is 1. If change

[39] is 1, it means that the oversampled data din

[39] has a "01" jump. At this time, regardless of whether the din

[39] jump is a normal jump or an abnormal jump, and the value of the sampling position register sample_posi is what, directly update the value of the sampling position register sample_posi. Figure 4 As shown in the row where chang

[39] is located. Figure 4 The figure shows an example of updating the value of the sampling position register in the 1:7 sampling mode, that is, under normal circumstances, only the middle bit of each continuous 7-bit data is sampled, and the 7-bit data is either 0000000 or 1111111. As mentioned earlier, chang

[39] indicates the jump of the highest bit data of the current 40-bit data to be oversampled. chang

[39] is 1, which means that the highest bit data has a jump. Then the highest bit data must be the first bit of the next continuous 7-bit oversampled data. The other 6 bits of the continuous 7-bit are the lowest 6 bits of the next 40-bit oversampled data. Therefore, the first sampling position of the next 40-bit data to be oversampled is the 2nd bit, and then count 7 bits from right to left as the next sampling position. In this way, all the sampling positions of the next oversampled data are obtained. Figure 4 As shown in the figure, the first sampling position of the row where chang

[39] is 1 is the 2-bit from right to left, and the next sampling position is the 9-bit by counting forward 7 bits, and so on for other positions.

[0058] Case 2: If change

[39] is 0, check whether change

[38] is 1. If change

[38] is 1, it means that the oversampled data din

[38] has a "01" jump. At this time, regardless of whether the din

[38] jump is a normal jump or an abnormal jump, and the value of the sampling position register sample_posi is what, directly update the value of the sampling position register sample_posi. Figure 4As shown in the row where chang

[38] is located. When chang

[39] is 0 and change

[38] is 1, that is, the 38-bit data of the current 40-bit oversampled data jumps, then the 38-bit, 39-bit and the lowest 5-bit data of the next 40-bit oversampled data of the current shot form a continuous 7-bit sampling data. The middle position of this continuous 7-bit data is the 1-bit of the next 40-bit oversampled data. Therefore, the first sampling position of the next 40-bit oversampled data is the 1-bit. Figure 4 As shown, by counting forward 7 bits, the next sampling position is the 8th bit, and the other sampling positions are deduced in the same way.

[0059] Case 3: If change

[39] is 0 and change

[38] is 0, then check whether change

[37] is 1. When change

[39] and change

[38] are 0 and change

[37] is 1, that is, the 37-bit data of the current 40-bit oversampled data has a jump. Then the 37-bit, 38-bit, 39-bit of the current 40-bit oversampled data and the lowest 4-bit data of the next 40-bit oversampled data form a continuous 7-bit sampled data. Since 3 bits of the continuous 7-bit data are located in the current 40-bit oversampled data, it is necessary to consider whether the value of the sampling position sample_posi

[39] of the current 40-bit oversampled data is 1 to determine whether the current jump is an abnormal jump and the first sampling position of the next 40-bit oversampled data.

[0060] At this time, if sample_posi

[39] is 1, it means that the 39th bit of the current 40-bit oversampled data has been sampled, which means that the sampling position of the continuous 7-bit sampled data has been advanced by one bit, indicating that the jump of the 37th bit of the current oversampled data is an abnormal 8-bit jump instead of a normal 7-bit jump. At this time, since the continuous 7-bit sampled data has been sampled at the 39th bit of the current oversampled data, the first sampling position of the next 40-bit oversampled data is the middle bit position of the next continuous 7-bit sampled data. The next continuous 7-bit sampled data is from the 4th bit to the 10th bit, so the first sampling position is the 7th bit. Then, by counting 7 bits forward, the next sampling position is the 14th bit, and the other sampling positions are deduced in the same way, such as Figure 4 As shown in the first line of chang

[37] .

[0061] At this time, if sample_posi

[39] is 0, it means that this continuous 7-bit sampled data has not been sampled in the current beat. Then the sampling position of this continuous 7-bit sampled data must be the 0th bit of the next beat of 40-bit oversampled data. Then, by counting forward 7 bits, the next sampling position is the 7th bit, and the other sampling positions are deduced in the same way, such as Figure 4 As shown in the second line of chang

[37] .

[0062] Case 4: If chang

[39] and change

[38] are 0 and change

[37] is 0, then check whether change

[36] is 1. If change

[36] is 1, then consider whether the din

[36] transition is a normal 7-bit transition, or an abnormal 6-bit transition or 8-bit transition. If the current sampling position sample_posi

[39] value is 0 and sample_posi

[38] value is 0, then din

[39] and din

[38] are not sampled, indicating that this is an abnormal 6-bit transition. Update the value of the sampling position register sample_posi as follows: Figure 4 As shown in the first line of chang

[36] ; if the current sampling position sample_posi

[39] value is 1 or sample_posi

[38] value is 1, then din

[39] has been sampled or din

[38] has been sampled, indicating that this is a normal 7-bit or abnormal 8-bit jump, then the value of the sampling position register sample_posi is updated as follows Figure 4 As shown in the second line of chang

[36] .

[0063] Case 5: According to the above method, change[39:0] is detected from high to low in sequence. Since it is 7 times oversampling, the current sampling position detection condition is 7-bit cycle from high to low according to change[39:0]. If the detection change[39:0] is all 0, it means that the current oversampled data din[39:0] has not experienced any "01" jump, then only according to the value of the current sampling position register sample_posi, update the value of the next sampling position register sample_posi[39:0]. Among them:

[0064] If sample_posi

[39] is 1, it means that the 39-bit data of the current beat to be oversampled has been sampled. Then, counting forward 7 bits, the next sampling position appears at the 6-bit of the next beat of 40-bit data to be oversampled. The other sampling positions are deduced by counting forward 7 bits, such as Figure 4 The first row of dft.

[0065] Similarly, if sample_posi

[38] is 1, it means that the 38-bit data of the current beat to be oversampled has been sampled. Then, counting forward 7 bits, the next sampling position appears at the 5-bit of the next beat of 40-bit data to be oversampled. The other sampling positions are deduced by counting forward 7 bits, such as Figure 4 The second row of dft.

[0066] The same applies to other situations, such as Figure 4 The other rows of dft are shown.

[0067] The data sampling module 30 is used to sample the valid data to be oversampled inputted for each beat according to the value of the sampling position register corresponding to each beat, so as to obtain the sampling data corresponding to each beat;

[0068] In this embodiment, the data sampling module 30 further stores the sampling data corresponding to each beat into a sampling data register, and the bit width of the sampling data register is the maximum number of sampling bits per beat.

[0069] Reference Figure 5 , Figure 5 This is a sampling diagram in one embodiment of the present application. Figure 5 As shown, the data sampling module 30 samples the 40-bit parallel oversampled data din[39:0] input in the current beat according to the value of the 40-bit sampling position register sample_posi[39:0] updated in the previous beat, wherein the bit position of 1 in the sampling position register sample_posi[39:0] is the bit position for sampling the 40-bit oversampled data.

[0070] The sampled data is stored in the sample data register sample_data[5:0]. Because it is a 1:7 sampling mode, that is, only one bit is sampled for each continuous 7-bit data, then on average, 40 / 7≈5.7 bits of data can be sampled for each 40-bit oversampled data. Considering the change in sampling position and the possibility of abnormal jumps, the sampled data does not exceed 6-bit, either 5-bit or 6-bit, so the bit width of the sample data register is set to 6-bit, and a vld indication is given for each 1-bit, that is, sample_data_vld[5:0]. If 6-bit data is sampled, sample_data_vld[5:0]=6'b11_1111; if 5-bit data is sampled, sample_data_vld[5:0]=6'b01_1111.

[0071] like Figure 5As shown, the 6th bit, 13th bit, 20th bit, 27th bit and 34th bit of the sampling position register sample_posi[39:0] are 1, then the 6th bit, 13th bit, 20th bit, 27th bit and 34th bit of the oversampled data din[39:0] are taken out in sequence and stored in the sampling data register sample_data[5:0] in sequence, and at the same time, the sampled 5-bit data gives the corresponding valid indication vld and stores it in the register sample_data_vld[5:0].

[0072] The bit width conversion module 40 is used to convert the sampled data into a fixed Q bit width output.

[0073] In this embodiment, the bit width conversion module 40 is specifically used to: store the sampled data in the sampled data register into the output buffer register, and the bit width of the output buffer register is 2Q; when the value of the pointer register is greater than or equal to Q or when the value of the pointer register is greater than or equal to 2Q, output the data on the Q bit with the highest transmission priority, and the value of the pointer register is used to indicate the starting position of the remaining space of the output buffer register.

[0074] Reference Figure 6 , Figure 6 Schematic diagram of bit width conversion in one embodiment of the present application. Figure 6 As shown, it means that the bit width conversion module 40 converts the sampled data with variable bit width per beat into a fixed 40-bit bit width output. In order to facilitate the control of the fixed bit width of the output data, an 80-bit bit width output buffer register storage[79:0] is set; a 7-bit bit width pointer register storage_posi[6:0] is used to indicate the starting position of the remaining space of storage[79:0].

[0075] like Figure 6As shown, at the beginning, the output buffer register storage[79:0] is empty, and the pointer register storage_posi[6:0] has a value of 0; if the first beat has valid sampled data of 6 bits, it is stored in the output buffer register storage[5:0] (because the input data to be oversampled is transmitted in the low bit first, that is, the low bit 0 is the highest transmission priority bit, and the sampled 6-bit data is also transmitted in the low bit first, oversampling does not change the bit order, and the output also requires the low bit to be transmitted first, so it should be stored in sequence from the low bit), and the value of the pointer register storage_posi[6:0] is 6; if the second beat has valid sampled data of 5 bits, it is stored in the output buffer register storage[10:6], and the value of the pointer register storage_posi[6:0] is 11. Similarly, when the output buffer storage[79:0] is full, it continues to be stored from storage[0], and the cycle repeats.

[0076] At the same time, the output of the data of the output buffer register storage[79:0] is controlled according to the value of the pointer register storage_posi[6:0]. When the value of the pointer register storage_posi[6:0] exceeds 40 or 79, 40-bit wide data is output, and the dynamic bit width sampling data is completed with fixed bit width output.

[0077] The beneficial effects brought by the technical solution provided by the embodiments of the present application include:

[0078] 1. By updating the sampling position in real time, higher frequency deviation can be tolerated;

[0079] 2. The logic is simple and there is no need to calculate the source and sink frequency deviation as in the traditional method, which can save more resources;

[0080] 3. It has strong versatility and can be applied to bearer networks such as Ethernet and optical transport networks, and even to all places where oversampling is required in digital communications.

[0081] In a second aspect, an embodiment of the present application also provides a method for resisting high-frequency oversampling.

[0082] In one embodiment, referring to Figure 7 , Figure 7 This is a flow chart of an embodiment of the method for resisting high-frequency oversampling in this application. Figure 7 As shown, the anti-high frequency bias oversampling method includes:

[0083] Step S10, determining the value of the sampling position register corresponding to the (i+1)th beat according to the value of the sampling position register corresponding to the i-th beat and the transition condition of the valid to-be-oversampled data inputted at the i-th beat, wherein i is a positive integer greater than or equal to 1;

[0084] Step S20, sampling the valid data to be oversampled inputted for each beat according to the value of the sampling position register corresponding to each beat, to obtain the sampling data corresponding to each beat;

[0085] Step S30, converting the sampled data into a fixed Q bit width output.

[0086] Furthermore, in one embodiment, the method for resisting high-frequency oversampling further includes:

[0087] Determine the transition status of the valid data to be oversampled input in each beat.

[0088] Further, in one embodiment, the step of determining the transition condition of valid data to be oversampled inputted per beat includes:

[0089] For the latest data to be oversampled inputted in the latest beat, when the valid signal indication of the latest data to be oversampled is valid, cache the data of the latest data to be oversampled at the lowest transmission priority for one beat;

[0090] Combining the latest data to be oversampled and the data to be oversampled in the previous shot at the lowest bit of transmission priority into (P+1)-bit data;

[0091] An indication register with a width of P is obtained by performing XOR on every two adjacent bits of the (P+1)-bit data, and is used to indicate the transition of the latest data to be oversampled, wherein when the value of the k-th bit in the indication register is 1, it indicates that the k-th bit of the latest data to be oversampled has a transition compared to the (k-1-th bit).

[0092] Furthermore, in one embodiment, after obtaining the sampling data corresponding to each beat, the method further includes:

[0093] The sampling data corresponding to each beat is stored in a sampling data register, and the bit width of the sampling data register is the maximum number of sampling bits per beat.

[0094] Further, in one embodiment, converting the sampled data into a fixed Q-bit width output includes:

[0095] The sampled data in the sampled data register is stored in the output buffer register, wherein the bit width of the output buffer register is 2Q;

[0096] When the value of the pointer register is greater than or equal to Q or when the value of the pointer register is greater than or equal to 2Q, the data on the Q bit with the highest transmission priority will be output. The value of the pointer register is used to indicate the starting position of the remaining space of the output buffer register.

[0097] The specific embodiments of the method for resisting high-frequency over-sampling refer to the various embodiments of the above-mentioned device for resisting high-frequency over-sampling, which will not be described in detail here.

[0098] It should be noted that the serial numbers of the above-mentioned embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.

[0099] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit "first", "second" and "third" to different types.

[0100] In the description of the embodiments of the present application, "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a specific way.

[0101] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; the “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.

[0102] In some processes described in the embodiments of the present application, multiple operations or steps that appear in a specific order are included, but it should be understood that these operations or steps may not be executed in the order in which they appear in the embodiments of the present application or in parallel, and the sequence number of the operation is only used to distinguish the different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed in sequence or in parallel, and these operations or steps may be combined.

[0103] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD) as described above, and includes a number of instructions for a terminal device to execute the methods described in each embodiment of the present application.

[0104] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A high frequency oversampling device, characterized in that: The high frequency oversampling resistance device comprises: a sampling position determination module, configured to determine a value of a sampling position register corresponding to the (i+1)th beat according to a value of a sampling position register corresponding to the i-th beat and a jump condition of valid to-be-oversampled data inputted at the i-th beat, wherein i is a positive integer greater than or equal to 1; A data sampling module is used to sample valid data to be oversampled inputted for each beat according to the value of a sampling position register corresponding to each beat, so as to obtain sampling data corresponding to each beat; The bit width conversion module is used to convert the sampled data into a fixed Q bit width output.

2. The high frequency oversampling device according to claim 1, characterized in that: The anti-high frequency over-sampling device also includes: The transition edge search module is used to determine the transition status of the valid data to be oversampled input in each beat.

3. The high frequency oversampling device according to claim 2, characterized in that: The data to be oversampled is P-bit-width parallel data to be oversampled, and the transition edge search module is specifically used for: For the latest data to be oversampled inputted in the latest beat, when the valid signal indication of the latest data to be oversampled is valid, cache the data of the latest data to be oversampled at the lowest transmission priority for one beat; Combining the latest data to be oversampled and the data to be oversampled in the previous shot at the lowest transmission priority into (P+1)-bit data; An indication register with a width of P is obtained by performing XOR on every two adjacent bits of the (P+1)-bit data, and is used to indicate the transition of the latest data to be oversampled, wherein when the value of the k-th bit in the indication register is 1, it indicates that the k-th bit of the latest data to be oversampled has a transition compared to the (k-1-th bit).

4. The high frequency oversampling device according to claim 1, characterized in that: The data sampling module is also used to: The sampling data corresponding to each beat is stored in a sampling data register, and the bit width of the sampling data register is the maximum number of sampling bits per beat.

5. The high frequency oversampling device according to claim 4, characterized in that: The bit width conversion module is specifically used for: The sampled data in the sampled data register is stored in the output buffer register, wherein the bit width of the output buffer register is 2Q; When the value of the pointer register is greater than or equal to Q or when the value of the pointer register is greater than or equal to 2Q, the data on the Q bit with the highest transmission priority will be output. The value of the pointer register is used to indicate the starting position of the remaining space of the output buffer register.

6. A method for resisting high-frequency oversampling, characterized in that: The anti-high frequency oversampling method comprises: Determine the value of the sampling position register corresponding to the (i+1)th beat according to the value of the sampling position register corresponding to the i-th beat and the jump condition of the valid to-be-oversampled data inputted in the i-th beat, where i includes a positive integer greater than or equal to 1; According to the value of the sampling position register corresponding to each beat, the valid data to be oversampled inputted for each beat is sampled to obtain the sampling data corresponding to each beat; Convert the sampled data into a fixed Q-bit width output.

7. The method for resisting high-frequency oversampling as claimed in claim 6, characterized in that: The anti-high frequency oversampling method also includes: Determine the transition status of the valid data to be oversampled input in each beat.

8. The method for resisting high-frequency oversampling as claimed in claim 7, characterized in that: The step of determining the transition of valid data to be oversampled input per beat includes: For the latest data to be oversampled inputted in the latest beat, when the valid signal indication of the latest data to be oversampled is valid, cache the data of the latest data to be oversampled at the lowest transmission priority for one beat; Combining the latest data to be oversampled and the data to be oversampled in the previous shot at the lowest bit of transmission priority into (P+1)-bit data; An indication register with a width of P is obtained by performing XOR on every two adjacent bits of the (P+1)-bit data, and is used to indicate the transition of the latest data to be oversampled, wherein when the value of the k-th bit in the indication register is 1, it indicates that the k-th bit of the latest data to be oversampled has a transition compared to the (k-1-th bit).

9. The method for resisting high-frequency oversampling as claimed in claim 1, characterized in that: After obtaining the sampling data corresponding to each beat, the method further includes: The sampling data corresponding to each beat is stored in a sampling data register, and the bit width of the sampling data register is the maximum number of sampling bits per beat.

10. The method for resisting high-frequency oversampling as claimed in claim 9, characterized in that: The step of converting the sampled data into a fixed Q-bit width output comprises: The sampled data in the sampled data register is stored in the output buffer register, wherein the bit width of the output buffer register is 2Q; When the value of the pointer register is greater than or equal to Q or when the value of the pointer register is greater than or equal to 2Q, the data on the Q bit with the highest transmission priority will be output. The value of the pointer register is used to indicate the starting position of the remaining space of the output buffer register.

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