Communication system, ultrasonic radar, vehicle

Abstract

The present invention discloses a communication system, an ultrasonic radar, and a vehicle, relating to the field of communication technologies. The system includes: a configuration register for receiving and storing configuration data generated by an external data source, where the configuration data includes data to be transmitted and baud rate configuration data for determining the data transmission rate; a timer connected to the configuration register and a clock source, for determining the trigger signal sending moment according to the baud rate configuration data, and sending an internal trigger signal when the current moment determined according to the clock source reaches the trigger signal sending moment; a data shift register connected to the configuration register, for receiving and storing the data to be transmitted, and outputting target data to a sending device when receiving the internal trigger signal, where the target data is the bit of the data in the data shift register that is closest to the output port during the shift process; and a sending device for sending the target data to a receiving device.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and in particular, to a communication system, an ultrasonic radar, and a vehicle. Background Art

[0002] With the popularization of intelligent vehicles, ultrasonic radars are almost installed on every vehicle. Basically, single-line communication protocols are used for ultrasonic sensors on the market. The communication protocol of ultrasonic waves has strict requirements for timing, and even a little deviation may lead to communication failure. Commonly used control methods are pre-emptive in software, and the ultrasonic communication control has the highest priority, which may cause delays or packet losses in other controls and communications, and the load rates of devices such as processors and controllers are very high. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to some extent. For this purpose, the first object of the present invention is to propose a communication system to reduce the possibility of delay or packet loss and reduce the load.

[0004] The second object of the present invention is to propose an ultrasonic radar.

[0005] The third object of the present invention is to propose a vehicle.

[0006] To achieve the above object, an embodiment of the first aspect of the present invention proposes a communication system. The system includes: a configuration register for receiving and storing configuration data generated by an external data source, where the configuration data includes data to be sent and baud rate configuration data for determining a data transmission rate; a timer connected to the configuration register and a clock source for determining a trigger signal sending time according to the baud rate configuration data, and sending an internal trigger signal when it is determined according to the clock source that the current time reaches the trigger signal sending time; a data shift register connected to the configuration register for receiving and storing the data to be sent, and outputting target data to a sending device when receiving the internal trigger signal, where the target data is the bit data in the data shift register that is closest to the output port during the shifting process; and the sending device for sending the target data to a receiving device.

[0007] In addition, the communication system according to the embodiment of the present invention may further have the following additional technical features:

[0008] In an embodiment of the present invention, the system further includes a first-in first-out (FIFO) controller and a static random access memory (SRAM). The FIFO controller is connected to the configuration register, and the SRAM is connected to the FIFO controller and the data shift register. Wherein, the FIFO controller is configured to obtain the data to be transmitted from the configuration register, write the data to be transmitted into the SRAM, and control the SRAM to write the data to be transmitted into the data shift register.

[0009] In an embodiment of the present invention, the number of the data shift registers is N, where N is a positive integer, and the output configurations of any two of the data shift registers are different. The FIFO controller is further configured to: determine a target register from the N data shift registers according to the output configuration, obtain a plurality of data frames based on the data to be transmitted, and write one of the plurality of data frames into the target register when the target register is in an idle state until all the plurality of data frames are written into the target register.

[0010] In an embodiment of the present invention, the timer is an N-channel timer, and the N channels of the timer are respectively connected to the N data shift registers in a one-to-one correspondence.

[0011] In an embodiment of the present invention, the system further includes a multiplexer. The multiplexer is connected to the timer, an external trigger device, and the data shift register. The multiplexer is configured to send the received trigger signal to the data shift register when receiving an internal trigger signal sent by the timer or an external trigger signal sent by the external trigger device.

[0012] In an embodiment of the present invention, the number of the sending devices is multiple, and the system further includes a sending device selector and a configuration selector. The sending device selector is connected to the data shift register, the configuration selector, and the multiple sending devices. Wherein, the configuration selector is configured to determine a target sending device from the multiple sending devices, and control the sending device selector to output the target data to the target sending device when the sending device selector receives the target data output by the data shift register.

[0013] In an embodiment of the present invention, each of the sending devices is configured with a plurality of input / output ports, and each input / output port is configured with a corresponding routing. The sending device is specifically configured to: determine a target routing from the multiple routings, and send the target data to the receiving device through the input / output port corresponding to the target routing when receiving the target data.

[0014] In an embodiment of the present invention, the system further includes: an interrupt control device, configured to output an interrupt signal to the outside when at least one of the configuration register and the first-in first-out controller fails, so that an external interrupt control device controls the interruption of the communication system according to the interrupt signal, and output a transmission completion signal to the outside when the data to be transmitted is transmitted to the receiving device.

[0015] To achieve the above object, an embodiment of the second aspect of the present invention provides an ultrasonic radar, including an ultrasonic sensor and the above communication system.

[0016] To achieve the above object, an embodiment of the third aspect of the present invention provides a vehicle, including the above ultrasonic radar.

[0017] According to the communication system, ultrasonic radar, and vehicle of the embodiments of the present invention, it is provided that the communication system includes a configuration register for receiving and storing configuration data, where the configuration data includes data to be transmitted and baud rate configuration data for determining the data transmission rate; a timer connected to the configuration register and a clock source, configured to determine the triggering signal transmission time according to the baud rate configuration data, and transmit an internal triggering signal when the current time determined according to the clock source reaches the triggering signal transmission time; a data shift register connected to the configuration register, configured to receive and store the data to be transmitted, and output target data to a transmitting device when receiving the internal triggering signal, where the target data is the bit data in the data shift register that is closest to the output port during the shifting process; and a transmitting device for transmitting the target data to a receiving device. Through this communication system, after the configuration data is generated, data transmission can be achieved in a purely hardware manner, thereby liberating the controller. The controller has sufficient time to process other tasks and interrupts, reducing the possibility of delays or packet losses in other communications and controls. Moreover, there will be no timing deviation caused by software operations, thus avoiding communication failures.

[0018] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present invention. Description of the Drawings

[0019] Figure 1 is a block diagram of the communication system according to an embodiment of the present invention;

[0020] Figure 2 is a schematic diagram of the structure of a communication system according to an example of the present invention;

[0021] Figure 3 is a flowchart of the operation of a communication system according to an example of the present invention;

[0022] Figure 4It is a structural block diagram of an ultrasonic radar according to an embodiment of the present invention;

[0023] Figure 5 It is a structural block diagram of a vehicle according to an embodiment of the present invention. Detailed implementation manners

[0024] The communication system, ultrasonic radar, and vehicle according to embodiments of the present invention will be described below with reference to the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described with reference to the accompanying drawings are exemplary and should not be construed as limiting the present invention.

[0025] Figure 1 It is a structural block diagram of a communication system according to an embodiment of the present invention.

[0026] As Figure 1 shown, the communication system 100 includes: a configuration register 101 for receiving and storing configuration data generated by an external data source, where the configuration data includes data to be transmitted and baud rate configuration data for determining the data transmission rate; a timer 102 connected to the configuration register 101 and a clock source, for determining the trigger signal transmission time according to the baud rate configuration data, and transmitting an internal trigger signal when the current time reaches the trigger signal transmission time determined according to the clock source; a data shift register 103 connected to the configuration register 101, for receiving and storing the data to be transmitted, and outputting target data to a transmitting device 104 when receiving the internal trigger signal, where the target data is the bit data in the data shift register 103 that is closest to the output port during the shifting process; a transmitting device 104 for transmitting the target data to a receiving device.

[0027] Specifically, in order to generate a required communication waveform according to the configuration and reduce the load requirement of the MCU, a communication system 100 is designed, which includes a configuration register 101, a timer 102, and a data shift register 103.

[0028] Among them, the configuration register 101 is used to receive and store configuration data, and the configuration data includes data to be transmitted and baud rate configuration data for determining the data transmission rate.

[0029] The configuration data received by the above configuration register 101 is the data sent by the data source that generates the configuration data. For example, assuming that the above communication system 100 is used for an ultrasonic radar, the external data source that sends the configuration data to the configuration register 101 is the processor in the ultrasonic radar. That is, after the ultrasonic probe generates a signal, the processor in the ultrasonic radar generates configuration data to be sent to the configuration register 101 according to the signal generated by the ultrasonic probe.

[0030] The above baud rate configuration data is data used to configure the baud rate. Since the baud rate is a unit for measuring the data transmission rate, indicating the number of symbols transmitted per second, therefore, the transmission time interval between two adjacent data symbols can be obtained according to the baud rate configuration data when sending the data to be sent.

[0031] Therefore, since the transmission time interval is known, Timer 102 can obtain the trigger signal transmission moment based on this, and then determine the current moment according to the clock source. When the current moment reaches the trigger signal transmission moment, an internal trigger signal is sent, and this internal trigger signal is sent to the data shift register 103.

[0032] That is to say, first, the configuration register 101 stores the data to be sent and the baud rate configuration data.

[0033] According to the baud rate configuration data, the transmission time interval for the data shift register 103 to send data can be obtained.

[0034] The configuration register 101 writes the data to be sent into the data shift register 103. The data shift register 103 outputs the data to be sent one by one. When the data shift register 103 sends data, it needs to be controlled by Timer 102 and sent according to the above transmission time interval. For example, assume the data to be sent is 010, the transmission time interval determined according to the baud rate configuration data is 1 s, and assume the data shift register 103 is a register with only one output port. Then the data shift register 103 will send the data to be sent in the order of 0, 1, 0, and under the control of Timer 102, the data shift register 103 sends 1 bit of data every 1 s. That is, after sending 0, 1 is sent after an interval of 1 s, and 0 is sent after another interval of 1 s.

[0035] After receiving the data to be sent, the sending device 104 can send the data to be sent to the receiving device. For example, if analog signal transmission is required, the sending device 104 can generate an analog signal waveform according to the data to be sent. For example, if the data to be sent is 101, the generated analog signal waveform is high level, low level, high level, and then this analog signal waveform is sent to the receiving device. Another example is that if digital signal transmission is required, the sending device 104 can generate an actual transmitted data packet according to the data to be sent, and then send this data packet to the receiving device.

[0036] Taking the ultrasonic radar as an example to illustrate the above communication system 100.

[0037] Specifically, the ultrasonic probe in the ultrasonic radar usually uses a single-wire communication protocol. To implement functions such as wave transmission, ultrasonic reception, and parameter configuration of the probe, communication needs to be carried out according to the established communication protocol. The communication timing requirements of the ultrasonic chip are relatively high. If the waveform time deviation is large, it will lead to communication failure. Usually, it is implemented in software. The main process is as follows:

[0038] One ultrasonic ranging may require communication with multiple probes. First, the communication data needs to be unpacked and decomposed into the timing sequence to be sent.

[0039] The MCU (Microcontroller Unit) interrupt needs to support preemption. Set a timer 102, and the priority of this timer 102 is the highest.

[0040] When communication is required, turn on the timer 102.

[0041] Enter the timer 102 interrupt and make judgments according to the sending timing logic. The sending status of multiple probes needs to be judged, and the corresponding input and output ports are controlled according to the comparison value.

[0042] Judge whether the output is completed, and turn off the timer 102 after completion.

[0043] It can be seen that after the ultrasonic probe in the ultrasonic radar generates a signal, when communicating through software, preemption and interruption are required. The software implementation of ultrasonic communication has relatively high requirements for the MCU. It must support preemption and frequent entry into interrupts. Moreover, if the sending timing deviates due to software deviation, it may lead to communication failure.

[0044] However, if the communication system 100 of the embodiment of the present invention is adopted in the ultrasonic radar, after obtaining the signal generated by the ultrasonic probe, the data to be sent and the baud rate configuration data are obtained according to the signal, and then the data to be sent and the baud rate configuration data are written into the configuration register 101. Subsequently, the communication system 100 of the embodiment of the present invention can complete the communication.

[0045] It can be seen that when the communication system 100 of the embodiment of the present invention conducts communication, it is implemented by pure hardware without software intervention, and there will be no deviation in timing caused by software operations, thus leading to communication failure. Moreover, since the specific communication is implemented by pure hardware, the MCU can be liberated, and the MCU has sufficient time to process other tasks and interrupts, reducing the possibility of delay or packet loss in other communications and controls.

[0046] Accordingly, the communication system 100 is provided with a configuration register 101 for receiving and storing configuration data, where the configuration data includes data to be transmitted and baud rate configuration data for determining the data transmission rate; a timer 102 connected to the configuration register 101 and a clock source, for determining the sending time of a trigger signal according to the baud rate configuration data, and sending an internal trigger signal when the current time determined according to the clock source reaches the sending time of the trigger signal; a data shift register 103 connected to the configuration register 101, for receiving and storing the data to be transmitted, and outputting target data to a sending device 104 when receiving the internal trigger signal, where the target data is the bit of the data in the data shift register 103 that is closest to the output port during the shifting process; and a sending device 104 for sending the target data to a receiving device. Through this communication system 100, after the configuration data is generated, data transmission can be achieved in a purely hardware manner, thus liberating the MCU. The MCU has sufficient time to process other tasks and interrupts, reducing the possibility of delays or packet losses in other communications and controls. Moreover, there will be no timing deviation caused by software operations, thus avoiding communication failures.

[0047] In some embodiments of the present invention, the communication system 100 further includes a first-in first-out (FIFO) controller and a static random access memory. The FIFO controller is connected to the configuration register 101, and the static random access memory is connected to the FIFO controller and the data shift register 103. The FIFO controller is configured to obtain the data to be transmitted from the configuration register 101, write the data to be transmitted into the static random access memory, and control the static random access memory to write the data to be transmitted into the data shift register 103.

[0048] In some embodiments of the present invention, the number of data shift registers 103 is N, where N is a positive integer, and the output configurations of any two data shift registers 103 are different. The FIFO controller is further configured to: determine a target register from the N data shift registers 103 according to the output configuration, obtain multiple data frames according to the data to be transmitted, and write one frame of the multiple data frames into the target register when the target register is in an idle state until all the multiple data frames are written into the target register.

[0049] The above output configuration may be the output rate, format, level, timing, etc.

[0050] That is to say, the above N data shift registers 103 correspond to N outputs, and each output has a different output configuration. The FIFO controller needs to select the output configuration it needs according to the output configurations of the data shift registers 103, determine the corresponding data shift register 103 as the target register, and the FIFO controller also needs to obtain multiple data frames according to the data to be transmitted.

[0051] Further, when the target register is in an idle state, the first-in-first-out controller needs to select one data frame from the above-mentioned multiple data frames and write the data frame into the target register. The target register outputs the data frame bit by bit.

[0052] After the target register completes the output of the data frame, the target register enters the idle state again. At this time, the first-in-first-out controller will select another data frame and write the data frame into the target register so that the target register sends the data frame. Repeat the above process until all the above-mentioned multiple data frames are written into the target register.

[0053] In some embodiments of the present invention, the timer 102 is an N-channel timer 102, and the N channels of the timer 102 are respectively connected to N data shift registers 103 in a one-to-one correspondence.

[0054] In some embodiments of the present invention, the communication system 100 further includes: a multiplexer, which is connected to the timer 102, an external trigger device, and the data shift register 103. The multiplexer is configured to send the received trigger signal to the data shift register 103 when receiving an internal trigger signal sent by the timer 102 or an external trigger signal sent by the external trigger device.

[0055] In some embodiments of the present invention, the number of the sending devices 104 is multiple, and the system further includes a sending device selector and a configuration selector. The sending device selector is connected to the data shift register 103, the configuration selector, and multiple sending devices 104; wherein, the configuration selector is configured to determine a target sending device 104 from the multiple sending devices 104, and when the sending device selector receives the target data output by the data shift register 103, control the sending device selector to output the target data to the target sending device 104.

[0056] In some embodiments of the present invention, the sending device 104 is configured with multiple input / output ports, and each input / output port is configured with a corresponding route. The sending device 104 is specifically configured to: determine a target route from the multiple routes, and when receiving the target data, send the target data to the receiving device through the input / output port corresponding to the target route.

[0057] In some embodiments of the present invention, the communication system 100 further includes: an interrupt control device, which is configured to output an interrupt signal to the outside when at least one of the configuration register 101 and the first-in-first-out controller fails, so that the external interrupt control device performs interrupt control on the communication system 100 according to the interrupt signal, and output a transmission completion signal to the outside when the data to be sent is sent to the receiving device.

[0058] Among them, an interrupt control device can be set to be connected to the configuration register 101 and the first-in first-out controller, and is used to send an interrupt signal to an external interrupt control device when at least one of the configuration register 101 and the first-in first-out controller fails, so that the external interrupt control device can perform interrupt control on the communication system 100 when receiving the interrupt signal.

[0059] Moreover, the interrupt control device can be set to not only judge whether the configuration register 101 and the first-in first-out controller fail, but also judge whether other parts of the communication system 100 fail. At this time, it can be set that the configuration register 101 or the first-in first-out controller is also used to obtain the current state of other parts of the communication system 100 and send the current state to the interrupt control device, or the interrupt control device can directly obtain the current state of other parts of the communication system 100.

[0060] The following will be described in conjunction with Figure 2 the specific examples shown.

[0061] In Figure 2 the specific example shown, the communication system 100 includes a configuration register 101, a timer 102, two data shift registers 103, a first-in first-out controller 105, a static random access memory 106, a multiplexer 107, two sending devices 104, and an interrupt control device 108. In the sending device 104, a routing management module is included, and the routing management module is used to manage the routing table to implement routing management according to the routing table.

[0062] Specifically, the configuration register 101 is mainly the part configured by the user, involving the configuration of the data bit length of the path communication output. The data is stored in the configuration register 101, and the configuration data stored in the configuration register 101 may include address configuration, waveform polarity configuration (the above-mentioned data to be sent), baud rate configuration data, routing table configuration, etc. The routing table configuration can be used to indicate which input / output ports 109 a data shift register 103 outputs to.

[0063] In Figure 2 it, the configuration register 101 obtains configuration data through the APB BUS (Advanced Peripheral Bus).

[0064] The first-in first-out controller 105 transfers data into the data shift register 103 according to the state of the actual data shift register 103 through parameters such as the configured data frame size, and outputs the working state of the first-in first-out controller 105 according to the overall data.

[0065] The static random access memory 106 mainly stores data for single-wire communication. Since this module supports simultaneous output of multiple configurations, the address of the static random access memory 106 can be split into multiple parts and supports configurability. The address allocation of the static random access memory 106 supports multiple types of configurations. For example, the static random access memory 106 can be configured as a whole and fixedly transported to the first data shift register 103. For another example, the static random access memory 106 can be split into two parts and transported to two data shift registers 103 respectively. For yet another example, the static random access memory 106 can be split into four parts and transported to 4 data shift registers 103 respectively.

[0066] The timer 102 mainly provides the clock for single-wire communication, configures data according to the set baud rate, and drives the data output of the data shift register 103 into the routing management module based on the clock issued by the clock source 112. Moreover, an external trigger can also be used as the output drive for the routing management module.

[0067] Optionally, the timer 102 can also be set as a multi-channel timer 102, so that each channel can drive an independent data shift register 103. At this time, the multiplexer 107 can be not set. Moreover, it can also be set that when the data output of the corresponding channel is completed, control information can be output to implement the enable control for closing the corresponding channel of the timer 102.

[0068] The data shift register 103 realizes data output through the drive of the clock source. When the data in the data shift register 103 is completely output, the data shift register 103 can be updated according to the actual output data status. Each data shift register 103 needs to be configured to output to which routing management module, and the input and output port 109 can be controlled in the routing management module.

[0069] The routing management module routes the data output by the data shift register 103 to the input and output port 109 configured for output according to the actually configured input and output port 109.

[0070] Moreover, when outputting through the input and output port 109, it can be output by one input and output port 109, or can be output by multiple input and output ports 109. That is to say, it can be set to send the target data using one route, or can be set to send the target data using multiple routes. When outputting by multiple input and output ports 109, the data on each input and output port 109 is the same.

[0071] Each data shift register 103 supports multiple numbers of routing output configurations, and the pins supporting the input and output port 109 can be fixed in the design. Figure 2In it, PIN is used to represent the pin, Figure 2 PIN A, …, PIN E in it are the specific numbers of the pins.

[0072] Moreover, in Figure 2 In the shown example, a transmission device selector 110 and a configuration selector 111 are also set.

[0073] Specifically, in Figure 2 there are 2 transmission devices 104, and N in the N data shift registers 103 is also set to 2.

[0074] Moreover, different transmission devices 104 are set, and their configured routes are the same. That is to say, when it is necessary to realize data transmission using a certain route, both of the two transmission devices 104 can achieve this data transmission.

[0075] At this time, since the number of data shift registers 103 is two, the transmission device 104 selected by the configuration selector 111 is used, and data transmission is achieved through the transmission device selector 110, so that the data output by any one of the data shift registers 103 can be input to any one of the transmission devices 104.

[0076] The interrupt control device 108 can be used to send an interrupt signal to the external interrupt control device 108 when at least one of the configuration register 101 and the first-in first-out controller 105 fails. This failure can be, for example, a trigger error. That is to say, if the interrupt control device 108 finds that the configuration register 101 fails, or the first-in first-out controller 105 fails, or both the configuration register 101 and the first-in first-out controller 105 fail, an interrupt signal is sent.

[0077] Moreover, the interrupt control device 108 can also be used to send feedback information to the customer after the main channel data output is completed.

[0078] The specific working process can be referred to Figure 3 . In Figure 3 the above communication system 100 is a single-wire communication module.

[0079] First, configure the single-wire communication module register.

[0080] Specifically, the data to be sent and the data length are written into the static random access memory 106, and information such as output polarity, baud rate configuration data, and route configuration is configured into the configuration register 101.

[0081] Enable the single-wire communication module and start the communication.

[0082] The data in the static random access memory 106 is transferred to the shift register (the above data shift register 103).

[0083] The shift register shifts under the trigger signal, and the data is output to the sending device 104. The trigger signal can be sent by the timer 102 or an external trigger.

[0084] The sending device 104 includes multiple routing modules (the above-mentioned routing management modules). The sending device 104 outputs the data to the configured input / output port according to the configured routing assignment.

[0085] After all the data in the shift register has been shifted out, it is judged whether to continue to move data from the static random access memory 106 to the shift register according to the set output data length. If the output is not completed, return to the above process of moving the data to the shift register.

[0086] When all outputs are completed, close the channel output. If it is an internal trigger, send a control signal to the timer 102 to close the channel count of the timer 102. When it is an external trigger, close the external trigger source through the interrupt software. When the interrupt is enabled, send an interrupt signal to the customer.

[0087] In summary, the communication system of the embodiment of the present invention is provided. The communication system includes a configuration register for receiving and storing configuration data, where the configuration data includes data to be sent and baud rate configuration data for determining the data transmission rate; a timer connected to the configuration register and the clock source for determining the trigger signal sending time according to the baud rate configuration data, and sending an internal trigger signal when the current time determined according to the clock source reaches the trigger signal sending time; a data shift register connected to the configuration register for receiving and storing the data to be sent, and outputting target data to the sending device when receiving the internal trigger signal, where the target data is the bit of data in the data shift register that is closest to the output port during the shifting process; a sending device for sending the target data to the receiving device. Through this communication system, after the configuration data is generated, data sending can be realized in a pure hardware manner, thus liberating the MCU. The MCU has sufficient time to process other tasks and interrupts, reducing the possibility of delay or packet loss in other communications and controls. Moreover, there will be no timing deviation caused by software operations, resulting in communication failure.

[0088] Furthermore, the present invention proposes an ultrasonic radar.

[0089] Figure 4 It is the structural block diagram of the ultrasonic radar of the embodiment of the present invention.

[0090] As Figure 4 shown, the ultrasonic radar 1000 includes an ultrasonic sensor 200 and the above-mentioned communication system 100.

[0091] The ultrasonic radar according to the embodiment of the present invention can, through the communication system of the above embodiment, realize data transmission in a pure hardware manner after the configuration data is generated, thereby liberating the MCU. The MCU has sufficient time to process other tasks and interrupts, reducing the possibility of delay or packet loss in other communications and controls. Moreover, there will be no timing deviation caused by software operations, thus avoiding communication failures.

[0092] Further, the present invention proposes a vehicle.

[0093] Figure 5 It is a structural block diagram of the vehicle according to the embodiment of the present invention.

[0094] As Figure 5 shown, the vehicle 10 includes the above ultrasonic radar 1000.

[0095] The vehicle according to the embodiment of the present invention can, through the above ultrasonic radar, realize data transmission in a pure hardware manner after the configuration data is generated, thereby liberating the MCU. The MCU has sufficient time to process other tasks and interrupts, reducing the possibility of delay or packet loss in other communications and controls. Moreover, there will be no timing deviation caused by software operations, thus avoiding communication failures.

[0096] It should be noted that the logic and / or steps represented in the flowchart or described in other ways herein can be considered as an ordered list of executable instructions for implementing logical functions, which can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in combination with these instruction execution systems, apparatuses, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion having one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or otherwise processing as appropriate, and then storing it in a computer memory.

[0097] It should be understood that each part of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented by hardware, as in another embodiment, any one or a combination of the following technologies well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0098] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0099] In the description of this specification, the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and should not be construed as a limitation on the present invention.

[0100] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0101] In the description of this specification, unless otherwise specified, terms such as "installed", "connected", "joined", "fixed", etc. shall be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0102] In the present invention, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature can be that the first feature is directly above or obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature can be that the first feature is directly below or obliquely below the second feature, or merely indicates that the horizontal height of the first feature is lower than that of the second feature.

[0103] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A communication system, characterized in that, The system includes: A configuration register for receiving and storing configuration data generated by an external data source, where the configuration data includes data to be transmitted and baud rate configuration data for determining the data transmission rate; A timer connected to the configuration register and a clock source, for determining the trigger signal transmission time according to the baud rate configuration data, and transmitting an internal trigger signal when the current time reaches the trigger signal transmission time determined according to the clock source; A data shift register connected to the configuration register, for receiving and storing the data to be transmitted, and outputting target data to a transmitting device when receiving the internal trigger signal, where the target data is the bit of data in the data shift register that is closest to the output port during the shift process; The transmitting device for transmitting the target data to a receiving device; The system further includes: A multiplexer connected to the timer, an external trigger device, and the data shift register, for transmitting the received trigger signal to the data shift register when receiving the internal trigger signal transmitted by the timer or the external trigger signal transmitted by the external trigger device; The transmitting device is configured with a plurality of input / output ports, and each input / output port is configured with a corresponding route. Specifically, the transmitting device is used for: Determining a target route from the plurality of routes, and when receiving the target data, transmitting the target data to the receiving device through the input / output port corresponding to the target route.

2. The communication system according to claim 1, wherein The system further includes a first-in first-out controller and a static random access memory. The first-in first-out controller is connected to the configuration register, and the static random access memory is connected to the first-in first-out controller and the data shift register; where The first-in first-out controller is used to obtain the data to be transmitted from the configuration register, write the data to be transmitted into the static random access memory, and control the static random access memory to write the data to be transmitted into the data shift register.

3. The communication system according to claim 2, wherein The number of the data shift registers is N, where N is a positive integer, and the output configurations of any two data shift registers are different. The first-in first-out controller is further used for: Determining a target register from the N data shift registers according to the output configuration, obtaining a plurality of data frames according to the data to be transmitted, and when the target register is in an idle state, writing one frame of the plurality of data frames into the target register until all the plurality of data frames are written into the target register.

4. The communication system according to claim 3, wherein, The timer is an N-channel timer, and the N channels of the timer are respectively connected to the N data shift registers in one-to-one correspondence.

5. The communication system according to claim 1, wherein The number of the transmitting devices is multiple. The system further includes a transmitting device selector and a configuration selector. The transmitting device selector is connected to the data shift register, the configuration selector, and the multiple transmitting devices; Among them, the configuration selector is used to determine a target sending device from multiple sending devices, and when the sending device selector receives the target data output by the data shift register, it controls the sending device selector to output the target data to the target sending device.

6. The communication system according to claim 2, characterized in that The system further includes: An interrupt control device, configured to output an interrupt signal to the outside when at least one of the configuration register and the first-in first-out controller fails, so that an external interrupt control device performs interrupt control on the communication system according to the interrupt signal, and output a transmission completion signal to the outside when the data to be transmitted is transmitted to the receiving device.

7. An ultrasonic radar, characterized in that, It includes an ultrasonic sensor and the communication system according to any one of claims 1-6.

8. A vehicle, characterized in that, It includes the ultrasonic radar according to claim 7.

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