Constant current control circuit with charge pump type overvoltage protection and LED constant current driving circuit

Abstract

According to the constant-current control circuit with charge pump type overvoltage protection and the LED constant-current drive circuit provided by the invention, the overvoltage detection circuit is connected with the external resistor to realize output overvoltage protection setting, so that a special output voltage detection and conversion circuit is avoided, the circuit is simplified, and the cost is reduced; besides, a charge pump circuit is also added, so that the constant-current control circuit can continuously adjust the output current to realize constant-voltage control when reaching a set overvoltage protection point, thereby remarkably improving the working stability in an overvoltage protection state.

Description

Technical Field

[0001] The present invention relates to the technical field of LED lighting, and in particular to a constant current control circuit with charge pump type overvoltage protection and an LED constant current drive circuit. Background Art

[0002] LED lighting drive circuits all have constant current outputs. When the load is open, the output voltage of the constant current output power supply will increase uncontrollably. Therefore, if the load has poor contact or is hot-plugged, the abnormally high output voltage will damage the components of the drive circuit or the LED lamp beads. Therefore, most drive circuits need to have an output overvoltage protection function.

[0003] The realization of the overvoltage protection function of the LED lighting driver circuit depends largely on the LED driver chip used. Most of the LED driver chips have an overvoltage protection function, which can easily realize simple and easy-to-use overvoltage protection. However, with the increasingly stringent cost requirements, the drive circuit is becoming more and more simple. For example, in low-power drive circuits, many non-isolated suspended buck drive circuits are used. In power supplies with isolation requirements, it is very common to use a primary-side feedback flyback constant current drive circuit. When using a non-isolated suspended buck drive circuit, in order to reduce the cost of inductance, a single-winding inductor is often used as a power inductor. Since both ends of the output end of the suspended buck drive circuit are high voltage relative to the ground, if the high voltage of the output voltage is converted into a low voltage signal relative to the ground and input to the IO pin of the driver chip for overvoltage protection, a certain peripheral circuit cost is required. However, it is impossible to use winding feedback to realize output voltage detection using a single-winding inductor, so a special method is required to realize the output overvoltage protection function. The primary-side feedback flyback LED constant current drive circuit using a 2-winding transformer also has this problem. Since there is no feedback winding to detect the output voltage, the isolation requirement requires a considerable peripheral circuit cost if a dedicated output voltage detection circuit is used. An indirect detection method is also required to achieve output overvoltage protection.

[0004] In the above-mentioned single-winding inductor suspension buck drive circuit and 2-winding transformer primary side feedback flyback LED constant current drive circuit, the output overvoltage protection function can be achieved by detecting the inductor demagnetization time. The drive circuit generally operates in zero current conduction mode. The peak current of the inductor can be sampled by the current sampling resistor. When the power inductor value is determined, the demagnetization time of the inductor can reflect the size of the output voltage. The lower the output voltage, the longer the demagnetization time, and the higher the output voltage, the shorter the demagnetization time. The LED driver chip uses an external resistor to set a time. When it is detected that the inductor demagnetization time is lower than the set time, it is considered that the output voltage has reached the overvoltage protection threshold and the overvoltage protection is triggered.

[0005] In the overvoltage protection circuit using the inductor demagnetization time, the existing overvoltage protection detection mechanism and overvoltage protection response are generally to immediately shut down the driver after detecting that the inductor demagnetization time is less than the set time, wait for the output to discharge slowly, restart again after a period of time, and the output voltage rises again after restarting to trigger the overvoltage shutdown again. In order to fully discharge the output, the discharge time may be set from a few milliseconds to more than ten milliseconds. The response method using this mechanism can effectively prevent the output voltage from rising too high. However, when the output voltage is close to the set overvoltage protection voltage, the change in ambient temperature affects the LED lamp bead voltage or the input voltage fluctuates, causing the output current to change, and then the output voltage changes may trigger the overvoltage protection function to produce visible flicker, which may affect the product experience. Summary of the invention

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a constant current control circuit and an LED constant current drive circuit with charge pump overvoltage protection, which are used to solve the technical problems of overvoltage detection of the LED constant current drive circuit in the prior art and the inability to work stably when the output voltage reaches the set overvoltage point.

[0007] To achieve the above-mentioned purpose and other related purposes, the present invention provides a constant current control circuit with charge pump overvoltage protection, the circuit comprising: an output overvoltage detection circuit, a charge pump circuit, a constant current reference modulation circuit, an overvoltage shutdown circuit, an error amplifier circuit, an output current synthesis circuit, a timing control circuit, a logic control circuit, a peak current comparator, a drive circuit and an LEB circuit; wherein the output overvoltage detection circuit is provided with an external resistor end, an overvoltage setting resistor is connected between the external resistor end and the ground; the drive circuit is provided with a drive output end; the LEB circuit is provided with a current sampling input end, a current sampling resistor is connected between the current sampling input end and the ground; the output overvoltage detection circuit has its input end connected to the output end of the drive circuit and the output end of the error amplifier circuit, and its output end is connected to the input end of the charge pump circuit; the input end of the charge pump circuit is connected to the output end of the drive circuit and the output end of the error amplifier circuit, and its output end is connected to the input end of the charge pump circuit; The output end is connected to the input end of the constant current reference modulation circuit and the input end of the overvoltage shutdown circuit; the output end of the constant current reference modulation circuit is connected to the error amplifier circuit; the input end and the output end of the overvoltage shutdown circuit are connected to the timing control circuit; the input end of the error amplifier circuit is connected to the output end of the output current synthesis circuit and the output end of the timing control circuit, and the output end is connected to the input end of the peak current comparator; the input end of the output current synthesis circuit is connected to the output end of the drive circuit and the output end of the LEB circuit; the output end of the timing control circuit is connected to the input end of the logic control circuit; the input end of the logic control circuit is connected to the output end of the peak current comparator, and the output end is connected to the input end of the drive circuit; the output end of the drive circuit is connected to the output end of the LEB circuit; the output end of the LEB circuit is connected to the input end of the peak current comparator.

[0008] In one embodiment of the present invention, the output overvoltage detection circuit includes: a reference input terminal, an external resistor terminal, a switch signal input terminal, a peak current signal input terminal, a zero current state input terminal, a discharge pulse output terminal and a charge pulse output terminal; the charge pump circuit includes: a discharge pulse input terminal, a charge pulse input terminal and a control voltage output terminal; the constant current reference modulation circuit includes: a constant current reference input terminal, a control voltage input terminal and an output current reference output terminal; the overvoltage shutdown circuit includes: a first reference voltage input terminal, a second reference voltage input terminal, an overvoltage shutdown signal input terminal, a control voltage input terminal and an overvoltage protection output terminal; the error amplifier circuit includes: a minimum peak current reference input terminal , output current reference input terminal, output current signal input terminal, overvoltage shutdown signal input terminal and peak current signal output terminal; the output current synthesis circuit includes: current signal input terminal, zero current state input terminal, switch signal input terminal and output current signal output terminal; the timing control circuit includes: overvoltage protection input terminal, overvoltage shutdown signal output terminal; the logic control circuit includes: overcurrent signal input terminal, overvoltage shutdown signal input terminal and switch control output terminal; the drive circuit includes: input terminal, drive output terminal, zero current state output terminal, switch state output terminal; the LEB circuit includes: sampling current input terminal, switch signal input terminal and current signal output terminal; the output overvoltage detection The reference input terminal of the measuring circuit is connected to a fixed reference voltage, an overvoltage setting resistor is connected between the external resistance terminal and the ground to set the overvoltage protection point, the switch signal input terminal is connected to the switch state output terminal of the driving circuit, the peak current signal input terminal is connected to the peak current signal output terminal of the error amplifier circuit, the zero current state input terminal is connected to the zero current state output terminal of the driving circuit, the discharge pulse output terminal is connected to the discharge pulse input terminal of the charge pump circuit, and the charging pulse output terminal is connected to the charging pulse input terminal of the charge pump circuit; the control voltage output terminal of the charge pump circuit is connected to the control voltage input terminal of the constant current reference modulation circuit and the control voltage input terminal of the overvoltage shutdown circuit; the constant current reference input terminal of the constant current reference modulation circuit is connected to a fixed The reference voltage and the output current reference output are connected to the output current reference input of the error amplifier circuit; the first reference input and the second reference input of the overvoltage shutdown circuit are respectively connected to two fixed reference voltage signals, the overvoltage shutdown signal input is connected to the overvoltage shutdown signal output of the timing control circuit, and the overvoltage protection output is connected to the overvoltage protection input of the timing control circuit; the minimum peak current reference input of the error amplifier circuit is connected to a fixed reference voltage, the output current signal input is connected to the output current signal output of the output current synthesis circuit, the overvoltage shutdown signal input is connected to the overvoltage shutdown signal output of the timing control circuit, and the peak current signal output is connected to the first input of the peak current comparator;The current signal input end of the output current synthesis circuit is connected to the current signal output end of the LEB circuit, the zero-current state input end is connected to the zero-current state output end of the drive circuit, and the switch signal input end is connected to the switch state output end of the drive circuit; the overvoltage shutdown signal output end of the timing control circuit is connected to the overvoltage shutdown signal input end of the logic control circuit; the overcurrent signal input end of the logic control circuit is connected to the output end of the overcurrent comparator, and the switch control output end is connected to the input end of the drive circuit; the switch state output end of the drive circuit is connected to the switch signal input end of the LEB circuit; the current signal output end of the LEB circuit is connected to the second input end of the peak current comparator. ;

[0009] In one embodiment of the present invention, the LEB circuit is used to remove the voltage spikes on the sampling current input terminal and output a clean current signal through the current signal output terminal; the output current synthesis circuit is used to output an output current signal representing the output current size to the output current signal input terminal of the error amplifier circuit through the output current signal output terminal according to the input current signal from the current signal output terminal of the LEB circuit, the zero current state signal from the zero current state output terminal of the drive circuit, and the switch signal from the switch state output terminal of the drive circuit; the error amplifier circuit is used to output an output current signal representing the output current size according to the output current reference signal from the output current reference output terminal of the constant current reference modulation circuit and the output current synthesis circuit. The output current signal at the output current signal output end outputs the peak current signal through the peak current signal output end, so that the output current signal is equal to the output current reference signal; the peak current comparator is used to compare the peak current signal at the peak current signal output end of the error amplifier circuit and the current signal output at the current signal output end of the LEB circuit, and when the current signal reaches the peak current signal, the flip control logic control circuit outputs a shutdown signal; the logic control circuit is used to output a switch control signal through the switch control output end according to the overvoltage shutdown signal at the overvoltage shutdown signal output end of the timing control circuit and the signal output from the output end of the peak current comparator; the drive circuit is used to output a switch control signal according to the switch control output of the logic control circuit The overvoltage detection circuit is used to generate a timing signal according to the voltage of the external resistor terminal, and output a charge pump discharge pulse signal through the discharge pulse output terminal and a charge pulse signal through the charge pulse output terminal according to the zero current state signal from the zero current state output terminal of the drive circuit and the generated timing signal; the charge pump circuit is used to output a control voltage signal through the control voltage output terminal according to the discharge pulse signal and the charge pulse signal from the discharge pulse output terminal and the charge pulse output terminal of the overvoltage detection circuit; the constant current reference modulation circuit is used to generate a control voltage signal according to the magnitude of the control voltage from the control voltage output terminal of the charge pump circuit The output current signal output from the output current reference output terminal is adjusted to a small extent, so as to perform constant voltage control by adjusting the output current size; the overvoltage shutdown circuit is used to control the control voltage signal from the control voltage output terminal of the charge pump circuit to increase to a fixed reference voltage connected to the first reference input terminal when the output current drops to an extremely low level when the application circuit of the constant current control circuit is unloaded, and still cannot stabilize the output voltage at a set value, and to output an overvoltage shutdown signal through the overvoltage protection output terminal to control the drive circuit to be completely shut down; the timing control circuit is used to output a shutdown signal through the overvoltage shutdown signal output terminal when the overvoltage shutdown signal from the overvoltage shutdown output terminal of the overvoltage shutdown circuit is valid, so as to stop the drive circuit from outputting the drive signal.

[0010] In one embodiment of the present invention, the overvoltage detection circuit includes: an amplifier, an NMOS tube, a first PMOS tube, a second PMOS tube, a switch, a timing capacitor, a comparator, a pulse generating circuit, an inverter and a 2-input NAND gate; wherein the amplifier, the NMOS tube, the first PMOS tube, the second PMOS tube, the switch and the overvoltage setting resistor form a current source circuit; the positive input terminal of the amplifier is connected to the reference input terminal, the negative input terminal is connected to the external resistor terminal and the source of the NMOS tube, and the output terminal is connected to the gate of the NMOS tube; the drain of the NMOS tube is connected to the drain and gate of the first PMOS tube, and the source is connected to the negative input terminal of the amplifier and the external resistor terminal; the drain of the first PMOS tube is connected to its gate The source of the second PMOS tube is connected to the power supply voltage, the drain is connected to the first end of the switch, the first end of the timing capacitor and the positive input end of the comparator, and the gate is connected to the gate of the first PMOS tube; the control end of the switch is connected to the switch signal input end, and the second end is grounded; the first end of the timing capacitor is connected to the first end of the switch, and the second end is grounded; the negative input end of the comparator is connected to the peak current signal input end; the input end of the pulse generating circuit is connected to the zero current state input end, and the output end is connected to the discharge pulse output end; the input end of the inverter is connected to the output end of the comparator, and the output end is connected to the first input end of the 2-input NAND gate; the second input end of the 2-input NAND gate is connected to the zero current state input end, and the output end is connected to the charging pulse output end.

[0011] In one embodiment of the present invention, the charge pump circuit includes: a constant current source, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a capacitor; wherein the drain of the first PMOS tube is connected to its gate and the first end of the constant current source, and the source is connected to the power supply; the second end of the constant current source is grounded; the drain of the second PMOS tube is connected to the drain and the gate of the first NMOS tube, the gate is connected to the gate of the first PMOS tube, and the source is connected to the power supply; the The drain is connected to the source of the fourth PMOS tube, the gate is connected to the charging pulse input terminal, and the source is connected to the power supply; the drain of the fourth PMOS tube is connected to the first end of the capacitor and to the control voltage output terminal; the drain and gate of the first NMOS tube are connected together and connected to the drain of the second PMOS tube, and the source is grounded; the drain of the second NMOS tube is connected to the drain of the fourth PMOS tube, the gate is connected to the gate of the first NMOS tube, and the source is connected to the drain of the third NMOS tube; the drain of the third NMOS tube is connected to the source of the second NMOS tube, the gate is connected to the discharge pulse input terminal, and the source is grounded.

[0012] In one embodiment of the present invention, the constant current reference modulation circuit includes: a first voltage buffer, a second voltage buffer, a first resistor, a second resistor, a first NMOS tube, and a second NMOS tube; wherein the input end of the first voltage buffer is connected to the constant current reference input end, and the output end is connected to the first end of the first resistor; the input end of the second voltage buffer is connected to the control voltage input end, and the output end is connected to the first end of the second resistor; the second end of the first resistor is connected to the current reference output end; the second end of the second resistor is connected to the drain and gate of the first NMOS tube; the drain and gate of the first NMOS tube are connected together and connected to the second end of the second resistor, and the source is grounded; the gate of the second NMOS tube is connected to the gate of the first NMOS tube, the drain is connected to the second end of the first resistor, and the source is grounded.

[0013] In one embodiment of the present invention, the overvoltage shutdown circuit includes: a voltage buffer, a switch, and a comparator; wherein the input end of the voltage buffer is connected to the second reference voltage input end, and the output end is connected to the first end of the switch; the second end of the switch is connected to the control voltage input end, and the control end is connected to the overvoltage shutdown signal input end; the positive input end of the comparator is connected to the control voltage input end, the negative input end is connected to the first reference voltage input end, and the output end is connected to the overvoltage protection output end.

[0014] In one embodiment of the present invention, the error amplifier circuit includes: an amplifier, an error amplifier, a first NMOS transistor, a second NMOS transistor, a first resistor, a capacitor, a second resistor, and a switch; wherein the positive input terminal of the amplifier is connected to the minimum peak current reference input terminal, the negative input terminal is connected to the source of the first NMOS transistor and the peak current signal output terminal, and the output terminal is connected to the gate of the first NMOS transistor; the drain of the first NMOS transistor is connected to the power supply voltage, the gate is connected to the output terminal of the amplifier, and the source is connected to the negative input terminal of the amplifier and the peak current signal output terminal; the positive input terminal of the error amplifier is connected to the output current reference input terminal, the negative input terminal is connected to the second terminal of the first resistor and the first terminal of the capacitor, and the output terminal is connected to the gate of the second NMOS transistor and the second terminal of the capacitor; the drain of the second NMOS transistor is connected to the power supply voltage, and the source is connected to the first terminal of the second resistor and the peak current signal output terminal; the first terminal of the first resistor is connected to the output current signal input terminal, and the second terminal is connected to the first terminal of the capacitor and the negative input terminal of the error amplifier; the second terminal of the capacitor is connected to the first terminal of the switch; the second terminal of the switch is grounded, and the control terminal is connected to the overvoltage shutdown signal input terminal; the second terminal of the second resistor is grounded.

[0015] In one embodiment of the present invention, the driving output terminal and the sampling current input terminal are connected to a power MOS tube; the driving output terminal periodically outputs a high or low voltage to periodically turn on or off the power MOS tube to perform current constant control; the sampling current input terminal is also connected to a current sampling resistor to perform current sampling during the period when the power MOS tube is turned on.

[0016] To achieve the above-mentioned purpose and other related purposes, the present invention provides an LED constant current driving circuit, the circuit comprising: an overvoltage setting resistor, a power MOS tube, a current sampling resistor, a rectifier diode, a power inductor, a load and the constant current control circuit with charge pump type overvoltage protection; wherein the first end of the overvoltage setting resistor is connected to the external resistor end of the constant current control circuit, and the second end is grounded; the gate of the power MOS tube is connected to the driving output end of the constant current control circuit, the drain is connected to the first end of the power inductor and the first end of the rectifier diode, and the source is connected to the first end of the current sampling resistor; the first end of the current sampling resistor is connected to the sampling current input end of the constant current control circuit; the first end of the rectifier diode is connected to the first end of the inductor, and the second end is connected to the input voltage; the second end of the power inductor is connected to the second end of the load; the first end of the load is connected to the input voltage, and the second end is connected to the second end of the power inductor.

[0017] As described above, the present invention is a constant current control circuit and an LED constant current drive circuit with charge pump overvoltage protection, which have the following beneficial effects: the present invention provides a constant current control circuit with overvoltage protection function, which realizes output overvoltage protection setting by connecting the overvoltage detection circuit to an external resistor, avoids the use of a dedicated output voltage detection and conversion circuit, simplifies the circuit and reduces costs; in addition, the present invention also adds a charge pump circuit, so that the constant current control circuit can continuously adjust the output current to achieve constant voltage control when the set overvoltage protection point is reached, thereby significantly improving the working stability in the overvoltage protection state. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Shown is a structural schematic diagram of a constant current control circuit with charge pump overvoltage protection in one embodiment of the present invention.

[0019] Figure 2 Shown is a structural schematic diagram of a constant current control circuit with charge pump overvoltage protection in one embodiment of the present invention.

[0020] Figure 3 It is a schematic structural diagram of an LED constant current driving circuit in one embodiment of the present invention.

[0021] Figure 4 It is a working waveform diagram when the output voltage VOUT does not reach the set over-voltage protection point in one embodiment of the present invention.

[0022] Figure 5 It is a working waveform diagram when the output voltage VOUT reaches the set overvoltage protection point in one embodiment of the present invention.

[0023] Figure 6 Shown is a waveform diagram of constant voltage control in one embodiment of the present invention.

[0024] Figure 7 Shown is a waveform diagram of the overvoltage shutdown control working process in one embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0026] It should be noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present invention. It should be understood that other embodiments may also be used, and that mechanical composition, structure, electrical and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present invention is limited only by the claims of the published patents. The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0027] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a part is said to "include" a certain constituent element, unless otherwise stated, it does not exclude other constituent elements, but means that other constituent elements may be included.

[0028] The terms first, second and third mentioned herein are used to describe various parts, components, regions, layers and / or segments, but are not limited thereto. These terms are only used to distinguish a certain part, component, region, layer or segment from other parts, components, regions, layers or segments. Therefore, the first part, component, region, layer or segment described below may refer to the second part, component, region, layer or segment within the scope of the present invention.

[0029] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0030] The present invention provides a constant current control circuit with charge pump overvoltage protection, which realizes output overvoltage protection setting by connecting an overvoltage detection circuit to an external resistor, avoids the use of a special output voltage detection and conversion circuit, simplifies the circuit and reduces costs; in addition, the present invention also adds a charge pump circuit, so that the constant current control circuit can continuously adjust the output current to realize constant voltage control when the set overvoltage protection point is reached, thereby significantly improving the working stability in the overvoltage protection state.

[0031] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0032] like Figure 1 A structural schematic diagram of a constant current control circuit with charge pump overvoltage protection in an embodiment of the present invention is shown.

[0033] The circuit includes: an output overvoltage detection circuit 201, a charge pump circuit 202, a constant current reference modulation circuit 203, an overvoltage shutdown circuit 204, an error amplifier circuit 205, an output current synthesis circuit 206, a timing control circuit 207, a logic control circuit 208, a peak current comparator 209, a drive circuit 210 and an LEB circuit 211; the output overvoltage detection circuit 201 is provided with an external resistor terminal ROVP, and an overvoltage setting resistor is connected between the external resistor terminal ROVP and the ground; the drive circuit 210 is provided with a drive output terminal GATE; the LEB circuit 211 is provided with a current sampling input terminal CS, and a current sampling resistor is connected between the current sampling input terminal CS and the ground;

[0034] The output overvoltage detection circuit 201 has its input end connected to the output end of the drive circuit 210 and the output end of the error amplifier circuit 205, and its output end connected to the input end of the charge pump circuit 202; the output end of the charge pump circuit 202 is connected to the input end of the constant current reference modulation circuit 203 and the input end of the overvoltage shutdown circuit 204; the output end of the constant current reference modulation circuit 203 is connected to the error amplifier circuit 205; the input end and the output end of the overvoltage shutdown circuit 204 are connected to the timing control circuit 207; the input end of the error amplifier circuit 205 is connected to the output end of the output current synthesis circuit 206, the timing control circuit 207, and the output end of the error amplifier circuit 205. 07, the output end is connected to the input end of the peak current comparator 209; the input end of the output current synthesis circuit 206 is connected to the output end of the drive circuit 210 and the output end of the LEB circuit 211; the output end of the timing control circuit 207 is connected to the input end of the logic control circuit 208; the input end of the logic control circuit 208 is connected to the output end of the peak current comparator 209, and the output end is connected to the input end of the drive circuit 210; the output end of the drive circuit 210 is connected to the output end of the LEB circuit 211; the output end of the LEB circuit 211 is connected to the input end of the peak current comparator 209.

[0035] In one embodiment, if Figure 2The output overvoltage detection circuit 201 includes: a reference input terminal VREF1, an external resistor terminal ROVP1, a switch signal input terminal DRVon1, a peak current signal input terminal VPK1, a zero current state input terminal ZC1, a discharge pulse output terminal P11 and a charge pulse output terminal P12; the charge pump circuit 202 includes: a discharge pulse input terminal P21, a charge pulse input terminal P22 and a control voltage output terminal VC1; the constant current reference modulation circuit 203 includes: a constant current reference input terminal VI, a control voltage input terminal VC2 and an output current reference output terminal VIREF1; the overvoltage shutdown circuit 204 includes: a first reference voltage input terminal Vovh, a second reference voltage input terminal Vovl, an overvoltage shutdown signal input terminal OVSD1, a control voltage input terminal VC3 and an overvoltage protection output terminal OVP1; the error amplifier circuit 205 includes: a minimum peak current reference input terminal VPKmin, an output current reference input terminal VIREF2 , output current signal input terminal VIOUT1, overvoltage shutdown signal input terminal OVSD2 and peak current signal output terminal VPK2; the output current synthesis circuit 206 includes: current signal input terminal VCS1, zero current state input terminal ZC2, switch signal input terminal DRVon2 and output current signal output terminal VIOUT2; the timing control circuit 207 includes: overvoltage protection input terminal OVP2, overvoltage shutdown signal output terminal OVSD3; the logic control circuit 208 includes: overcurrent signal input terminal OC, overvoltage shutdown signal input terminal OVSD4 and switch control output terminal ON; the drive circuit 210 includes: input terminal, drive output terminal GATE (not shown in the figure), zero current state output terminal ZC3 (not shown in the figure), switch state output terminal DRVon3 (not shown in the figure); the LEB circuit 211 includes: sampling current input terminal CS, switch signal input terminal DRVon4 and current signal output terminal VCS2;

[0036] The reference input terminal VREF1 of the output overvoltage detection circuit 201 is connected to a fixed reference voltage VRFF, the external resistor terminal ROVP1 is connected to a pin of the constant current control circuit, and a resistor is connected between the pin and the ground to set the output overvoltage point when in use, the switch signal input terminal DRVon1 is connected to the switch state output terminal DRVon3 of the drive circuit 210, the peak current signal input terminal VPK1 is connected to the peak current signal output terminal VPK2 of the error amplifier circuit 205, the zero current state input terminal ZC1 is connected to the zero current state output terminal ZC3 of the drive circuit 210, the discharge pulse output terminal P11 is connected to the discharge pulse input terminal P21 of the charge pump circuit 202, and the charging pulse output terminal P12 is connected to the charging pulse input terminal P2 of 202. 2; the control voltage output terminal VC1 of the charge pump circuit 202 is connected to the control voltage input terminal VC2 of the constant current reference modulation circuit 203 and the control voltage input terminal VC3 of the overvoltage shutdown circuit 204; the constant current reference input terminal VI of the constant current reference modulation circuit 203 is connected to a fixed reference voltage, and the output current reference output terminal VIREF1 is connected to the output current reference input terminal VIREF2 of the error amplifier circuit 205; the first reference input terminal Vovh and the second reference input terminal Vovl of the overvoltage shutdown circuit 204 are respectively connected to two fixed reference voltage signals, the overvoltage shutdown signal input terminal OVSD1 is connected to the overvoltage shutdown signal output terminal OVSD2 of the timing control circuit 207, and the overvoltage protection output terminal OVP1 is connected to the fixed reference voltage. The overvoltage protection input terminal OVP2 of the timing control circuit 207; the minimum peak current reference input terminal VPKmin of the error amplifier circuit 205 is connected to a fixed reference voltage, the output current signal input terminal VIOUT1 is connected to the output current signal output terminal VIOUT2 ​​of the output current synthesis circuit 206, the overvoltage shutdown signal input terminal OVSD2 is connected to the overvoltage shutdown signal output terminal OVSD3 of the timing control circuit 207, and the peak current signal output terminal VPK2 is connected to the first input terminal of the peak current comparator 209; the current signal input terminal VCS1 of the output current synthesis circuit 206 is connected to the current signal output terminal VCS2 of the LEB circuit 211, and the zero-power state input terminal ZC2 is connected to the zero current state of the drive circuit 210. The state output terminal ZC3 and the switch signal input terminal DRVon2 are connected to the switch state output terminal DRVon3 of the driving circuit 210; the overvoltage shutdown signal output terminal OVSD3 of the timing control circuit 207 is connected to the overvoltage shutdown signal input terminal OVSD4 of the logic control circuit 208; the overcurrent signal input terminal OC of the logic control circuit 208 is connected to the output terminal of the overcurrent comparator 209, and the switch control output terminal ON is connected to the input terminal of the driving circuit 210; the switch state output terminal DRVon3 of the driving circuit 210 is connected to the switch signal input terminal DRVon4 of the LEB circuit 211; the current signal output terminal VCS2 of the LEB circuit 211 is connected to the second input terminal of the peak current comparator 209.

[0037] In one embodiment, the LEB circuit 211, the output current synthesis circuit 206, the error amplifier circuit 205, the peak current comparator 209, the logic control circuit 208 and the driving circuit 210 form a constant current control loop.

[0038] The LEB circuit 211 is used to remove the voltage spikes on the sampling current input terminal CS, and output a clean current signal VCS through the current signal output terminal VCS2, thereby improving the accuracy of output current sampling and the stability of switch control; the output current synthesis circuit 206 is used to output the output current signal VIOUT representing the output current size to the output current signal input terminal VIOUT1 of the error amplifier circuit 205 through the output current signal output terminal VIOUT2 ​​according to the input current signal VCS from the current signal output terminal VCS2 of the LEB circuit 211, the zero current state signal ZC from the zero current state output terminal ZC3 of the drive circuit 210, and the switch signal DRVon of the switch state output terminal DRVon3 of the drive circuit 210; the error amplifier circuit 205 is used to output the peak current signal VIOUT representing the output current size through the peak current signal output terminal VPK2 according to the input output current reference signal VIREF from the output current reference output terminal VIREF1 of the constant current reference modulation circuit 203 and the output current signal VIOUT from the output current signal output terminal VIOUT of the output current synthesis circuit 206. The error amplifier circuit 205 has a minimum peak current limiting function, and the peak current signal VPK is not less than the input minimum peak current reference voltage VPKmin; the peak current comparator 209 is used to compare the peak current signal VPK of the peak current signal output terminal VPK2 of the error amplifier circuit 205 and the current signal VCS output from the current signal output terminal VCS2 of the LEB circuit 211, and when the current signal VCS reaches the peak current signal VPK, the control logic control circuit 208 is flipped to output a shutdown signal; the logic control circuit 208 is used to output a switch control signal ON through the switch control output terminal ON according to the over-voltage shutdown signal OVSD of the over-voltage shutdown signal output terminal OVSD2 of the timing control circuit 207 and the signal OC output from the output terminal of the peak current comparator 209; the drive circuit 210 is used to output the switch control signal ON according to the switch control output terminal ON of the logic control circuit 208, and output the drive voltage GATE through the drive output terminal GATE;

[0039] The overvoltage detection circuit 201 is used to generate a timing signal according to the voltage of the external resistor terminal ROVP1, and output the charge pump discharge pulse signal P1 through the discharge pulse output terminal P11 and the charging pulse signal P2 through the charging pulse output terminal P12 according to the zero current state signal ZC from the zero current state output terminal ZC3 of the driving circuit 210 and the generated timing signal; the charge pump circuit 202 is used to output the control voltage signal VC through the control voltage output terminal VC1 according to the discharge pulse signal P1 and the charging pulse signal P2 from the discharge pulse output terminal P11 and the charging pulse output terminal P2 of the overvoltage detection circuit 201; when the discharge pulse signal P1 and the charging pulse signal P2 are invalid, VC is discharged to zero, and when the charging pulse signal P2 is valid, VC gradually increases. VC is used to adjust the output current through the constant current reference modulation circuit 203 to achieve constant voltage control. The constant current reference modulation circuit 203 is used to adjust the output current signal VIREF output from the output current reference output terminal VIREF1 according to the size of the control voltage VC from the control voltage output terminal VC1 of the charge pump circuit 202, so as to perform constant voltage control by adjusting the output current size; when the control voltage VC is 0, the drive circuit 210 operates in a normal constant current state, and the output current signal VIREF is a maximum value equal to VI. When the control voltage VC increases, the output current signal VIREF decreases as the control voltage VC increases, thereby controlling the output current to decrease. The overvoltage shutdown circuit 204 is used to control the control voltage signal VC from the control voltage output terminal VC of the charge pump circuit 202 to rise to a fixed reference voltage connected to the first reference input terminal Vovh when the output current drops to an extremely low level when the application circuit of the constant current control circuit is unloaded, and the overvoltage shutdown signal OVP is output through the overvoltage protection output terminal OVP1 to control the drive circuit 210 to be completely shut down, thereby avoiding the output voltage from being out of control; the timing control circuit 207 is used to output the shutdown signal OVSD through the overvoltage shutdown signal output terminal OVSD3 to stop the drive circuit from outputting the drive signal when the overvoltage shutdown signal OVP from the overvoltage shutdown output terminal OVP of the overvoltage shutdown circuit 204 is valid, and the shutdown signal OVSD is reset and restarted after the set time.

[0040] In one embodiment, the overvoltage detection circuit 201 includes: an amplifier I11, an NMOS transistor Q11, a first PMOS transistor Q12, a second PMOS transistor Q13, a switch S11, a timing capacitor C11, a comparator I12, a pulse generating circuit I13, an inverter I14 and a 2-input NAND gate I15;

[0041] The positive input terminal of the amplifier I11 is connected to the reference input terminal VREF1, the negative input terminal is connected to the external resistor terminal ROVP and the source of the NMOS tube Q11, and the output terminal is connected to the gate of the NMOS tube Q11; the drain of the NMOS tube Q11 is connected to the drain and gate of the first PMOS tube Q12, and the source is connected to the negative input terminal of the amplifier I11 and the external resistor terminal ROVP; the drain of the first PMOS tube Q12 is connected to its gate, and the source is connected to the power supply voltage Vdd; the source of the second PMOS tube Q13 is connected to the power supply voltage Vdd, the drain is connected to the first end of the switch S11, the first end of the timing capacitor C11 and the positive input terminal of the comparator I12, and the gate is connected to the first PMOS tube Q12. The gate of the OS tube Q12; the control end of the switch S11 is connected to the switch signal input terminal DRVon1, and the second end is grounded; the first end of the timing capacitor C11 is connected to the first end of the switch S11, and the second end is grounded; the negative input end of the comparator I12 is connected to the peak current signal input terminal VPK1; the input end of the pulse generating circuit I13 is connected to the zero current state input terminal ZC1, and the output end is connected to the discharge pulse output terminal P11; the input end of the inverter I14 is connected to the output end of the comparator I12, and the output end is connected to the first input end of the 2-input NAND gate I15; the second input end of the 2-input NAND gate I15 is connected to the zero current state input terminal ZC1, and the output end is connected to the charging pulse output terminal P2.

[0042] The overvoltage detection circuit 201 sets an output overvoltage protection point by connecting an external resistor to the external resistor terminal ROVP, thereby avoiding the use of a dedicated output voltage detection and conversion circuit, simplifying the circuit and reducing costs.

[0043] In one embodiment, the charge pump circuit 202 includes: a constant current source I21, a first PMOS tube Q21, a second PMOS tube Q22, a third PMOS tube Q23, a fourth PMOS tube Q24, a first NMOS tube Q25, a second NMOS tube Q26, a third NMOS tube Q27 and a capacitor C21; wherein the drain of the first PMOS tube Q21 is connected to its gate and the first end of the constant current source I21, and the source is connected to the power supply Vdd; the second end of the constant current source I21 is grounded; the drain of the second PMOS tube Q22 is connected to the drain and gate of the first NMOS tube Q25, the gate is connected to the gate of the first PMOS tube Q21, and the source is connected to the power supply Vdd; the third PMOS The drain of the transistor Q23 is connected to the source of the fourth PMOS transistor Q24, the gate is connected to the charging pulse input terminal P2, and the source is connected to the power supply Vdd; the drain of the fourth PMOS transistor Q24 is connected to the first end of the capacitor C21 and to the control voltage output terminal VC1; the drain and the gate of the first NMOS transistor Q25 are connected together and connected to the drain of the second PMOS transistor Q22, and the source is grounded; the drain of the second NMOS transistor Q26 is connected to the drain of the fourth PMOS transistor Q24, the gate is connected to the gate of the first NMOS transistor Q25, and the source is connected to the drain of the third NMOS transistor Q27; the drain of the third NMOS transistor Q27 is connected to the source of the second NMOS transistor Q26, the gate is connected to the discharge pulse input terminal P11, and the source is grounded.

[0044] The charge pump circuit 202 generates a control voltage VC. This smooth voltage is used to adjust the output current of the constant current control circuit. When the output voltage of the constant current control circuit reaches the set overvoltage protection point, constant voltage operation can be achieved by adjusting the output current, thereby significantly improving the working stability in the overvoltage protection state.

[0045] In one embodiment, the constant current reference modulation circuit 203 includes: a first voltage buffer I31, a second voltage buffer I32, a first resistor R31, a second resistor R32, a first NMOS transistor Q31, and a second NMOS transistor Q32; wherein, the input end of the first voltage buffer I31 is connected to the constant current reference input end VI, and the output end is connected to the first end of the first resistor R31; the input end of the second voltage buffer I32 is connected to the control voltage input end VC2, and the output end is connected to the first end of the second resistor R32; the second end of the first resistor R31 is connected to the current reference output end VIREF1; the second end of the second resistor R32 is connected to the drain and gate of the first NMOS transistor Q31; the drain and gate of the first NMOS transistor Q31 are connected together and connected to the second end of the second resistor R32, and the source is grounded; the gate of the second NMOS transistor Q32 is connected to the gate of the first NMOS transistor Q31, the drain is connected to the second end of the first resistor R31, and the source is grounded.

[0046] In one embodiment, the overvoltage shutdown circuit 204 includes: a voltage buffer I41, a switch S41, and a comparator I42; wherein the input terminal of the voltage buffer I41 is connected to the second reference voltage input terminal Vov1, and the output terminal is connected to the first terminal of the switch S41; the second terminal of the switch S41 is connected to the control voltage input terminal VC3, and the control terminal is connected to the overvoltage shutdown signal input terminal OVSD1. The positive input terminal of the comparator I42 is connected to the control voltage input terminal VC3, the negative input terminal is connected to the first reference voltage input terminal Vovh, and the output terminal is connected to the overvoltage protection output terminal OVP1.

[0047] In one embodiment, the error amplifier circuit 205 includes: an amplifier I51, an error amplifier I52, a first NMOS transistor Q51, a second NMOS transistor Q52, a first resistor R51, a capacitor C51, a second resistor R52, and a switch S51; wherein the positive input terminal of the amplifier I51 is connected to the minimum peak current reference input terminal VPKmin, the negative input terminal is connected to the source of the first NMOS transistor Q51 and the peak current signal output terminal VPK2, and the output terminal is connected to the gate of the first NMOS transistor Q51; the drain of the first NMOS transistor Q51 is connected to the power supply voltage Vdd, the gate is connected to the output terminal of the amplifier I51, and the source is connected to the negative input terminal of the amplifier I51 and the peak current signal output terminal VPK2; the error amplifier I52 The positive input terminal is connected to the output current reference input terminal VIREF, the negative input terminal is connected to the second end of the first resistor R51 and the first end of the capacitor C51, and the output terminal is connected to the gate of the second NMOS tube Q52 and the second end of the capacitor C51; the drain of the second NMOS tube Q52 is connected to the power supply voltage Vdd, and the source is connected to the first end of the second resistor R52 and the peak current signal output terminal VPK2; the first end of the first resistor R51 is connected to the output current signal input terminal VIOUT, and the second end is connected to the first end of the capacitor C51 and the negative input terminal of the error amplifier I52; the second end of the capacitor C51 is connected to the first end of the switch S51; the second end of the switch S51 is grounded, and the control end is connected to the over-voltage shutdown signal input terminal OVSD2; the second end of the second resistor R52 is grounded.

[0048] In one embodiment, the first input terminal of the peak current comparator 209 is connected to the peak current signal output terminal VPK2 from the error amplifier circuit 205, the second input terminal is connected to the current signal output terminal VCS2 from the LEB circuit 211, and the output terminal is connected to the overcurrent signal input terminal OC of the logic control circuit 208.

[0049] In one embodiment, the driving output terminal GATE and the sampling current input terminal CS of the constant current control circuit are connected to a power MOS tube; the driving output terminal GATE of the constant current control circuit periodically outputs a high or low voltage to periodically turn on or off the power MOS to perform constant current control; the sampling current input terminal CS of the constant current control circuit is also connected to a current sampling resistor 4 to perform current sampling during the power MOS opening period.

[0050] like Figure 3 A structural schematic diagram of an LED constant current drive circuit in an embodiment of the present invention is shown.

[0051] The circuit is a commonly used single-winding inductor suspension step-down constant current drive circuit, which includes: an overvoltage setting resistor 1, a constant current control circuit 2 with charge pump overvoltage protection, a power MOS tube 3, a sampling resistor 4, a rectifier diode 5, a power inductor 6 and a load 7;

[0052] The first end of the overvoltage setting resistor 1 is connected to the external resistor end ROVP1 of the constant current control circuit 2, and the second end is grounded; the gate of the power MOS tube 3 is connected to the drive output end GATE of the constant current control circuit 2, the drain is connected to the first end of the power inductor 6 and the first end of the rectifier diode 5, and the source is connected to the first end of the sampling resistor 4; the first end of the sampling resistor 4 is connected to the sampling current input end CS of the constant current control circuit 2; the first end of the rectifier diode 5 is connected to the first end of the inductor 6, and the second end is connected to the input voltage VIN. The second end of the power inductor 6 is connected to the second end of the load 7. The first end of the load 7 is connected to the input voltage VIN, and the second end is connected to the second end of the power inductor. The first end of the load 7 is the positive output voltage VOUT+, and the second end is the negative output voltage VOUT-.

[0053] The driving output terminal GATE of the constant current control circuit 2 periodically outputs a high / low voltage, so that the power MOS tube 3 is periodically turned on and off. When the power MOS tube 3 is turned on, the input voltage VIN charges the power inductor 6 through the power MOS tube 3, and the inductor current gradually increases; at the same time, the constant current control circuit 2 is connected to the current sampling resistor 4 through the current sampling terminal CS to collect current information. When the power MOS tube 3 is turned off, the current in the power inductor 6 is continuously flowing through the rectifier diode 5, and the inductor current gradually decreases. The constant current control circuit 2 adjusts the duty cycle of the high / low voltage of the driving output terminal GATE according to the current information obtained by sampling, thereby controlling the average current flowing through the inductor 6, and finally achieving the current flowing from the input voltage source VIN through the load 7 to remain constant. The constant current control circuit 2 is connected to the overvoltage setting resistor 1 through the external resistor terminal ROVP1 to set the overvoltage protection point.

[0054] In one embodiment, the LEB circuit 211, the output current synthesis circuit 206, the error amplifier circuit 205, the peak current comparator 209, the logic control circuit 208 and the driving circuit 210 of the constant current control circuit 2 form a constant current control loop.

[0055] The LEB circuit 211 is used to remove the voltage spike on the current sampling terminal signal CS that appears at the moment when the power MOS tube 3 is turned on, and generate a clean current signal VCS. The output current synthesis circuit 206 is used to generate an output current signal VIOUT representing the output current size to the error amplifier circuit 205 according to the input current signal VCS, the switch signal DRVon and the zero current state signal ZC. The error amplifier circuit 205 is used to generate a peak current signal VPK to control the peak current when the power MOS tube 3 switch is turned on according to the input output current reference signal VIREF and the output current signal VIOUT, and finally achieve that the output current signal VIOUT is equal to the output current reference signal VIREF. The peak current comparator 209 is used to compare the peak current signal VPK with the current signal VCS during the turn-on period of the power MOS tube 3, and when VCS reaches VPK, the flip control logic control circuit 208 outputs a shutdown signal. The logic control circuit 208 is used to generate a switch control signal ON according to the overvoltage shutdown signal OVSD and the output signal OC of the peak current comparator 209 to control the drive circuit 210 to generate a drive voltage. The driving circuit 210 is used to generate a driving voltage GATE according to a switch control signal ON at the input end to drive the power MOS tube 3 to turn on and off. When the ON signal is a logic high level, GATE outputs a high voltage to drive the power MOS tube 3 to turn on. When the ON signal is a logic low level, GATE outputs a low voltage to drive the power MOS tube 3 to turn off.

[0056] When the LED constant current driving circuit is normal, the voltage of the output current signal VIOUT generated by the output current synthesis circuit 206 reflects the output current flowing through the load 7. The output current of the load 7 is written as Iout, and the resistance value of the resistance sampling resistor 4 is written as Rcs. The voltage of the output current signal VIOUT can be expressed as:

[0057] VIOUT=K*Iout*Rcs (1)

[0058] The VIOUT signal is output to the output current signal input terminal VIOUT1 of the error amplifier circuit 205 and compared with the output current reference VIREF voltage. When the VIOUT signal voltage is greater than VIREF, the output voltage of the error amplifier I52 of the error amplifier circuit 205 decreases. After passing through the buffer circuit composed of the second NMOS tube Q52 and the second resistor R52, the output peak current signal VPK voltage decreases, thereby controlling the peak current to decrease when the power MOS tube 3 is turned on, so that Iout decreases. When the VIOUT voltage is lower than VIREF, the VPK voltage increases, thereby controlling the peak current to increase when the power MOS tube 3 is turned on, so that Iout increases. When stable, Iout is equal to a stable value so that the VIOUT signal voltage is equal to the VIREF voltage. The output current Iout can be expressed as:

[0059]

[0060] Among them, the coefficient K is fixed, the Rcs resistance is also fixed, and the output current Iout is determined by the VIREF voltage when stable.

[0061] VIREF is generated by the reference modulation circuit 203. When the output voltage is lower than the set overvoltage protection point, the VIREF is equal to the reference voltage VI of the constant current reference voltage input terminal VI of the constant current reference modulation circuit 203. The normal output current Iout is determined by VI, K and Rcs. When the output voltage reaches the set overvoltage protection point, the control voltage VC increases, the output current reference voltage signal VIREF output from the constant current reference modulation circuit 203 decreases, and the output current Iout is controlled to decrease.

[0062] In the LED constant current drive circuit, the constant current control circuit 2 operates in the critical mode or discontinuous mode of the inductor current. In each switching cycle, the current passing through the inductor 6 is 0 when the power MOS tube 3 is turned on. When the constant current control circuit 2 detects that the voltage at the current sampling input terminal CS reaches the value set by VPK, the power MOS tube 3 is turned off. After the power MOS tube 3 is turned off, the current of the inductor 6 begins to decrease. If it works in the critical mode, the power MOS tube 3 is turned on again after the inductor current decreases to zero. If it works in the discontinuous mode, the power MOS tube 3 is turned on again after a delay period after the inductor current decreases to zero. In each switching cycle during normal operation, the inductor current will experience a process of decreasing from peak to zero. In each switching cycle, the maximum voltage on the sampling resistor during the opening of the power MOS tube 3 is written as CSpk, the resistance value of the current sampling resistor 4 is Rcs, the inductance value of the inductor 6 is L, the voltage across the load 7 is VOUT, and the time for the inductor current to decrease from the peak to 0 is Tdis. Ignoring the forward conduction voltage drop of the rectifier diode 5, Tdis can be calculated and expressed as:

[0063]

[0064] It can be seen from the above formula (3) that the inductor discharge time Tdis can reflect the output voltage VOUT. The VOUT can be indirectly detected by detecting Tdis to achieve output overvoltage protection.

[0065] In one embodiment, the amplifier I11, the NMOS transistor Q11, the first PMOS transistor Q12, the second PMOS transistor Q13 of the overvoltage detection circuit 201 and the overvoltage setting resistor 1 connected between the external resistor terminal ROVP1 and the ground form a current source circuit.

[0066] A fixed reference voltage VREF inputted by the reference input terminal VREF1 sets the working voltage of the external resistor terminal ROVP1. The negative feedback circuit is formed by the amplifier I11 and the NMOS tube Q11, so that the voltage of the external resistor terminal ROVP1 is stabilized at a value equal to the fixed reference voltage VREF. The fixed reference voltage VREF and the voltage of the external resistor terminal ROVP1 set a current of a fixed magnitude, which is connected to the current mirror circuit composed of the first PMOS tube Q12 and the second PMOS tube Q13 through the drain of the NMOS tube Q11, and the proportionally reduced timing charging current Ichg is outputted at the drain of the second PMOS tube Q13. When the switch signal DRVon inputted by the switch signal input terminal DRVon1 is at a logic high level, the switch S11 is closed, and the timing capacitor C11 is discharged to 0; when the switch signal DRVon inputted by the switch signal input terminal DRVon1 is at a logic low level, the switch S11 is disconnected, and the timing charging current Ichg charges the timing capacitor C11, and the voltage at the first end of the timing capacitor C11 increases; the voltage is connected to the positive input terminal of the comparator I12, and the negative input terminal of the comparator I12 is connected to the peak current signal voltage VPK, and when the voltage at the first end of the timing capacitor C11 reaches the peak current signal input terminal VPK1, the comparator I12 flips to complete the timing;

[0067] If the overvoltage setting resistor connected between the external resistor terminal ROVP1 and the ground is ROVP, the current mirror ratio between the second PMOS transistor Q13 and the first PMOS transistor Q12 is M, and the capacitance of the timing capacitor C11 is C11, then the time Tout required from the moment when the switch signal DRVon flips from the logic high level to the logic low level to the time when the comparator I12 flips can be expressed as:

[0068]

[0069] The peak current signal voltage VPK controls the maximum value of the current signal VCS during the opening of the power MOS tube 3 in each switching cycle, which is also the maximum value CSpk of the current sampling input terminal CS of the constant current control circuit. VPK and CSpk are in a fixed proportional relationship, that is, VPK=A*CSpk. Formula (1) can be re-expressed as:

[0070]

[0071] If Tout is used as the threshold of the output overvoltage value, and the overvoltage protection is activated when Tdis reaches Tout, then formula (3) is equal to formula (5). After adjustment, the output voltage VOUT can be expressed as:

[0072]

[0073] Formula (6) shows that VOUT and ROVP have a definite relationship, which is only related to L, Rcs, C11, A, VREF and M. VREF, M, C11 and A are circuit parameters that remain fixed. Therefore, after Rcs is determined, the VOUT overvoltage protection voltage can be set by ROVP.

[0074] The pulse generating circuit I13, the inverter I14 and the 2-input NAND gate I15 in the output overvoltage detection circuit 201 are used to generate a discharge pulse signal P1 and a charge pulse signal P2 to control the discharge and charge of the capacitor of the charge pump circuit 202 respectively.

[0075] Figure 4 , Figure 5 The working waveforms when the output voltage VOUT does not reach the set overvoltage protection point and reaches the set overvoltage protection point are shown respectively. Figure 4 In the waveform diagram shown, IL is the inductor current waveform in the drive circuit, DRVon is the switch signal waveform, VC11 is the voltage waveform of the first terminal of the timing capacitor C11 of the output overvoltage detection circuit 201, VPK is the peak current signal waveform, I12 output is the output waveform of the comparator I12 of the overvoltage detection circuit 201, ZC is the zero current state signal waveform, P1 is the discharge pulse waveform, and P2 is the charging pulse waveform. When the output voltage does not reach the set overvoltage protection point, the power MOS tube 3 is turned off at t2, IL starts to decrease from the peak value, and VC11 starts to increase from 0 voltage. At t3, VC11 reaches the VPK level, and I12 flips from a logic low level to a logic high level. At t4, the inductor current IL decreases to 0, and the ZC signal flips from a low level to a high level. When the ZC signal flips, the pulse generating circuit I13 generates a high-level short pulse and outputs it through P1. When Tdis is greater than Tout, the output of comparator I12 and ZC generated by inverter I14 and 2-input NAND gate I15 generate P2 output which is always at logic high level.

[0076] Figure 5 The waveform diagram shown shows the working waveform when the output voltage VOUT reaches the set overvoltage protection point. At t2, the inductor starts to discharge and IL starts to decrease. At the same time, VC11 starts to increase from 0 voltage. At t3, the IL current is reduced to 0, and the ZC signal flips from low level to high level. At t4, VC11 reaches VPK to flip I12 from logic low level to logic high level. Since Tdis is shorter than Tout, from t3 to t4, I12 output and ZC generate a low level pulse through combination logic I14 and I15 and output through P2. At the same time, when the ZC signal flips from low level to high level, I13 generates a high level short pulse and outputs through P1.

[0077] In one embodiment, the constant current source I21 in the charge pump circuit 202 sets the charge and discharge currents. The constant current source I21 mirrors two currents through the first PMOS tube Q21. One current flows out through the fourth PMOS tube Q24 as a charging current connected to the capacitor C21, and the other current flows out through the second PMOS tube Q22 connected to the first NMOS tube Q25 and the second NMOS tube Q26. After the current mirror circuit mirrors, the current flows out from the drain of the second NMOS tube Q26 as a discharge current connected to the capacitor C21.

[0078] The third PMOS transistor Q23 is connected to the charging current path as a charging control switch. When P2 is at a low level, the third PMOS transistor Q23 is turned on to connect the charging current path to charge the capacitor C21. The third NMOS transistor Q27 is connected to the discharging current path as a discharging control switch. When P1 is at a high level, the third NMOS transistor Q27 is turned on to connect the discharging current path to discharge the capacitor C21. The capacitor C21 is a holding capacitor used to generate a smooth control voltage VC. The stability of the constant voltage control loop can be adjusted by appropriately adjusting the size of the capacitor C21.

[0079] The control voltage VC generated by the charge pump circuit 202 is output to the control end of the reference modulation circuit 203 to adjust the constant current reference voltage VIREF. In the constant current reference modulation circuit 203, the control voltage VC is added between the second resistor R32 and the first NMOS transistor Q31 after passing through the voltage buffer I32. When the voltage at the control voltage output end VC1 is higher than the threshold voltage of the first NMOS transistor Q31, the first NMOS transistor Q31 starts to conduct. After conducting, the drain voltage of the first NMOS transistor Q31 is limited to the vicinity of its turn-on voltage. The current flowing through the first NMOS transistor Q31 is mainly determined by the voltage difference between the control voltage output end VC1 and the drain of the first NMOS transistor Q31 and the second resistor R32. The current of the first NMOS transistor Q31 is mirrored by the second NMOS transistor Q32, flows out through the drain of the second NMOS transistor Q32, and is added to the first resistor R31, thereby forming a voltage drop on the first resistor R31 so that the current reference output voltage VIREF is lower than the constant current reference input voltage VI. The increase of the VC voltage increases the current of Q31, thereby increasing the drain current of the second NMOS transistor Q32, and forming a larger voltage drop on the first resistor R31. The adjustment range of the control VC can be adjusted by adjusting the size ratio of the first resistor R31 and the second resistor R32 and the size ratio of the first NMOS transistor Q31 and the second NMOS transistor Q32.

[0080] Figure 6 The waveform diagram of constant voltage control is shown. When the output voltage is lower than the set overvoltage protection point, the charging control signal P2 maintains a high level, and the control voltage VC is discharged to 0 by the P1 pulse. When the output voltage reaches the set overvoltage protection point, the charging control signal P2 begins to have charging control pulses. When the P2 pulse width increases so that the charging current of the charge pump circuit is greater than the discharging current, the control voltage VC begins to rise. After the control voltage VC rises, the output current reference voltage VIREF output by the control reference modulation circuit 203 decreases, so that the output current decreases. After the output current is balanced with the load current, the output voltage stabilizes to the preset overvoltage protection point.

[0081] In one embodiment, the overvoltage shutdown circuit 204 and the timing control circuit 207 implement overvoltage shutdown / restart control. The input reference voltages Vovh and Vovl of the overvoltage shutdown circuit 204 are used to set the maximum working voltage of the control voltage VC and the maintenance voltage during the overvoltage shutdown period, respectively. The first reference voltage input terminal Vovh is connected to the negative input terminal of the comparator I42 to set the VC shutdown voltage. VC is connected to the positive input terminal of the comparator I42 to compare with Vovh. When VC reaches Vovh, the comparator I42 flips to make the OVP terminal output a high-level signal. When OVP becomes high, the overvoltage shutdown signal output terminal OVSD3 of the timing control circuit 207 outputs a high-level shutdown signal OVSD to shut down the output. When OVSD is high, the switch S41 in the overvoltage shutdown circuit 204 is closed, and the VC voltage is set to Vovl. Vovl is slightly lower than Vovh, so that it will not immediately enter the shutdown protection again after restarting. When OVSD is high, the switch S51 in the error amplifier circuit 205 is closed to set the output terminal of the error amplifier I52 to 0 voltage, so that the peak current signal VPK voltage is set to the minimum value VPKmin. When the OVSD high level ends and restarts, the switch current is controlled to be minimum, so that when VC works near the overvoltage shutdown threshold, the energy transmitted to the load in each switching cycle is minimized.

[0082] Figure 7 The waveform diagram of the overvoltage shutdown control working process is shown. If the output current is reduced to the minimum and the output voltage cannot be maintained stable, such as when no-load, VC will continue to rise. When VC rises to Vovh, OVSD flips to high and the GATE drive pulse stops. During the period when OVSD is continuously high, VC is set to Vovl. After a delay of Tovsd, OVSD flips to low level to allow the output drive signal again. If the control voltage VC rises again from Vovl after reopening, it will reach Vovh and re-enter the shutdown and restart process.

[0083] Compared with the prior art, the present invention has the following advantages:

[0084] 1. The constant current control circuit of the present invention uses a resistor to set the output overvoltage protection point. The overvoltage detection circuit uses the method of detecting the discharge time of the inductor current and comparing it with the time set by the set resistor to generate a charge / discharge pulse signal to control the charge and discharge of the charge pump. This design does not require direct detection of the output voltage. For application circuits that are not easy to directly detect the output voltage, the dedicated output voltage detection circuit can be omitted, saving circuit costs.

[0085] 2. The constant current control circuit of the present invention uses a charge pump circuit to generate a control voltage VC. This smooth voltage is used to adjust the output current of the constant current circuit, so that when the output voltage of the constant current circuit reaches the set overvoltage protection point, constant voltage operation can be achieved by adjusting the output current. The charge pump circuit has the advantages of simple structure and low cost. By adjusting the charge pump capacitor, the stable operation of the constant voltage control loop can be easily achieved. Under the constant voltage working state, the output current remains continuous. When the circuit is used to drive the LED, even if the output voltage fluctuates near the overvoltage point, the visible flicker phenomenon can be effectively avoided, which significantly improves the redundancy of the circuit and the user's product experience.

[0086] 3. The overall structure of the constant current control circuit of the present invention is concise and clear, which enables it to be easily integrated into a constant current control chip. This highly integrated feature is not only conducive to reducing the volume of the circuit, but also improves the reliability and stability of the circuit, providing strong support for the miniaturization and high performance of the product.

[0087] In summary, the constant current control circuit with charge pump overvoltage protection and the LED constant current drive circuit of the present invention realize the output overvoltage protection setting by connecting the overvoltage detection circuit to an external resistor, avoiding the use of a special output voltage detection and conversion circuit, simplifying the circuit and reducing the cost; in addition, the present invention also adds a charge pump circuit, so that the constant current control circuit can continuously adjust the output current to realize constant voltage control when reaching the set overvoltage protection point, thereby significantly improving the working stability under the overvoltage protection state. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A constant current control circuit with charge pump overvoltage protection, characterized in that: The circuit includes: an output overvoltage detection circuit, a charge pump circuit, a constant current reference modulation circuit, an overvoltage shutdown circuit, an error amplification circuit, an output current synthesis circuit, a timing control circuit, a logic control circuit, a peak current comparator, a drive circuit and an LEB circuit; Wherein, the output overvoltage detection circuit is provided with an external resistor terminal, and an overvoltage setting resistor is connected between the external resistor terminal and the ground; the drive circuit is provided with a drive output terminal; the LEB circuit is provided with a current sampling input terminal, and a current sampling resistor is connected between the current sampling input terminal and the ground; The input end of the output overvoltage detection circuit is connected to the output end of the drive circuit and the output end of the error amplifier circuit, and the output end is connected to the input end of the charge pump circuit; the output end of the charge pump circuit is connected to the input end of the constant current reference modulation circuit and the input end of the overvoltage shutdown circuit; the output end of the constant current reference modulation circuit is connected to the error amplifier circuit; the input end and the output end of the overvoltage shutdown circuit are connected to the timing control circuit; the input end of the error amplifier circuit is connected to the output end of the output current synthesis circuit and the output end of the timing control circuit, and the output end is connected to the input end of the peak current comparator; the input end of the output current synthesis circuit is connected to the output end of the drive circuit and the output end of the LEB circuit; the output end of the timing control circuit is connected to the input end of the logic control circuit; the input end of the logic control circuit is connected to the output end of the peak current comparator, and the output end is connected to the input end of the drive circuit; the output end of the drive circuit is connected to the output end of the LEB circuit; the output end of the LEB circuit is connected to the input end of the peak current comparator.

2. The constant current control circuit with charge pump overvoltage protection according to claim 1, characterized in that: The output overvoltage detection circuit includes: a reference input terminal, an external resistor terminal, a switch signal input terminal, a peak current signal input terminal, a zero current state input terminal, a discharge pulse output terminal and a charge pulse output terminal; the charge pump circuit includes: A discharge pulse input terminal, a charge pulse input terminal and a control voltage output terminal; the constant current reference modulation circuit comprises: A constant current reference input terminal, a control voltage input terminal and an output current reference output terminal; the overvoltage shutdown circuit comprises: A first reference voltage input terminal, a second reference voltage input terminal, an overvoltage shutdown signal input terminal, a control voltage input terminal and an overvoltage protection output terminal; the error amplifier circuit includes: a minimum peak current reference input terminal, an output current reference input terminal, an output current signal input terminal, an overvoltage shutdown signal input terminal and a peak current signal output terminal; the output current synthesis circuit includes: a current signal input terminal, a zero current state input terminal, a switch signal input terminal and an output current signal output terminal; the timing control circuit includes: an overvoltage protection input terminal and an overvoltage shutdown signal output terminal; the logic control circuit includes: an overcurrent signal input terminal, an overvoltage shutdown signal input terminal and a switch control output terminal; the drive circuit includes: an input terminal, a drive output terminal, a zero current state output terminal, and a switch state output terminal; the LEB circuit includes: a sampling current input terminal, a switch signal input terminal and a current signal output terminal; The reference input terminal of the output overvoltage detection circuit is connected to a fixed reference voltage, an overvoltage setting resistor is connected between the external resistance terminal and the ground to set the overvoltage protection point, the switch signal input terminal is connected to the switch state output terminal of the drive circuit, the peak current signal input terminal is connected to the peak current signal output terminal of the error amplifier circuit, the zero current state input terminal is the zero current state output terminal of the drive circuit, the discharge pulse output terminal is connected to the discharge pulse input terminal of the charge pump circuit, and the charge pulse output terminal is connected to the charge pulse input terminal of the charge pump circuit; the control voltage output terminal of the charge pump circuit is connected to the control voltage input terminal of the constant current reference modulation circuit and the control voltage input terminal of the overvoltage shutdown circuit; the constant current reference input terminal of the constant current reference modulation circuit is connected to a fixed reference voltage, and the output current reference output terminal is connected to the output current reference input terminal of the error amplifier circuit; the first reference input terminal and the second reference input terminal of the overvoltage shutdown circuit are respectively connected to two fixed reference voltage signals, the overvoltage shutdown signal input terminal is connected to the overvoltage shutdown signal output terminal of the timing control circuit, and the overvoltage protection output terminal is connected to the fixed The overvoltage protection input terminal of the timing control circuit is connected to the overvoltage protection input terminal of the timing control circuit; the minimum peak current reference input terminal of the error amplifier circuit is connected to a fixed reference voltage, the output current signal input terminal is connected to the output current signal output terminal of the output current synthesis circuit, the overvoltage shutdown signal input terminal is connected to the overvoltage shutdown signal output terminal of the timing control circuit, and the peak current signal output terminal is connected to the first input terminal of the peak current comparator; the current signal input terminal of the output current synthesis circuit is connected to the current signal output terminal of the LEB circuit, the zero-electric state input terminal is connected to the zero-current state output terminal of the drive circuit, and the switch signal input terminal is connected to the switch state output terminal of the drive circuit; the overvoltage shutdown signal output terminal of the timing control circuit is connected to the overvoltage shutdown signal input terminal of the logic control circuit; the overcurrent signal input terminal of the logic control circuit is connected to the output terminal of the overcurrent comparator, and the switch control output terminal is connected to the input terminal of the drive circuit; the switch state output terminal of the drive circuit is connected to the switch signal input terminal of the LEB circuit; the current signal output terminal of the LEB circuit is connected to the second input terminal of the peak current comparator.

3. The constant current control circuit with charge pump overvoltage protection according to claim 2, characterized in that: The LEB circuit is used to remove the voltage spike on the sampling current input terminal and output a clean current signal through the current signal output terminal; The output current synthesis circuit is used to output an output current signal indicating the magnitude of the output current to the output current signal input terminal of the error amplifier circuit through the output current signal output terminal according to the input current signal from the current signal output terminal of the LEB circuit, the zero current state signal from the zero current state output terminal of the drive circuit, and the switch signal from the switch state output terminal of the drive circuit; The error amplifier circuit is used to output a peak current signal through a peak current signal output terminal according to an output current reference signal from an output current reference output terminal of a constant current reference modulation circuit and an output current signal from an output current signal output terminal of an output current synthesis circuit, so that the output current signal is equal to the output current reference signal; The peak current comparator is used to compare the peak current signal of the peak current signal output end of the error amplifier circuit with the current signal outputted from the current signal output end of the LEB circuit, and when the current signal reaches the peak current signal, the control logic control circuit is flipped to output a shutdown signal; The logic control circuit is used to output a switch control signal through a switch control output terminal according to an overvoltage shutdown signal at an overvoltage shutdown signal output terminal of the timing control circuit and a signal output from an output terminal of a peak current comparator; the drive circuit is used to output a switch control signal according to a switch control output terminal of the logic control circuit and output a drive voltage through a drive output terminal; the overvoltage detection circuit is used to generate a timing signal according to a voltage at an external resistor terminal, and output a charge pump discharge pulse signal through a discharge pulse output terminal and a charge pulse signal through a charge pulse output terminal according to a zero current state signal from a zero current state output terminal of the drive circuit and the generated timing signal; The charge pump circuit is used to output a control voltage signal through the control voltage output terminal according to the discharge pulse signal and the charge pulse signal from the discharge pulse output terminal and the charge pulse output terminal of the overvoltage detection circuit; the constant current reference modulation circuit is used to adjust the output current signal output from the output current reference output terminal according to the magnitude of the control voltage from the control voltage output terminal of the charge pump circuit, so as to perform constant voltage control by adjusting the magnitude of the output current; the overvoltage shutdown circuit is used to control the control voltage signal from the control voltage output terminal of the charge pump circuit to rise to the fixed reference voltage connected to the first reference input terminal when the output current drops to an extremely low level when the application circuit of the constant current control circuit is unloaded, and the output voltage cannot be stabilized at the set value, and output an overvoltage shutdown signal through the overvoltage protection output terminal to control the drive circuit to be completely shut down; The timing control circuit is used to output a shutdown signal through the overvoltage shutdown signal output terminal to stop the drive circuit from outputting the drive signal when the overvoltage shutdown signal from the overvoltage shutdown output terminal of the overvoltage shutdown circuit is valid.

4. The constant current control circuit with charge pump overvoltage protection according to claim 3, characterized in that: The overvoltage detection circuit comprises: an amplifier, an NMOS tube, a first PMOS tube, a second PMOS tube, a switch, a timing capacitor, a comparator, a pulse generating circuit, an inverter and a 2-input NAND gate; The amplifier, the NMOS tube, the first PMOS tube, the second PMOS tube, the switch and the overvoltage setting resistor form a current source circuit; the positive input terminal of the amplifier is connected to the reference input terminal, the negative input terminal is connected to the external resistor terminal and the source of the NMOS tube, and the output terminal is connected to the gate of the NMOS tube; the drain of the NMOS tube is connected to the drain and gate of the first PMOS tube, and the source is connected to the negative input terminal of the amplifier and the external resistor terminal; the drain of the first PMOS tube is connected to its gate, and the source is connected to the power supply voltage; the source of the second PMOS tube is connected to the power supply voltage, and the drain is connected to the first terminal of the switch, the timing circuit The first end of the capacitor is connected to the positive input end of the comparator, and the gate is connected to the gate of the first PMOS tube; the control end of the switch is connected to the switch signal input end, and the second end is grounded; the first end of the timing capacitor is connected to the first end of the switch, and the second end is grounded; the negative input end of the comparator is connected to the peak current signal input end; the input end of the pulse generating circuit is connected to the zero current state input end, and the output end is connected to the discharge pulse output end; the input end of the inverter is connected to the output end of the comparator, and the output end is connected to the first input end of the 2-input NAND gate; the second input end of the 2-input NAND gate is connected to the zero current state input end, and the output end is connected to the charging pulse output end.

5. The constant current control circuit with charge pump overvoltage protection according to claim 3, characterized in that: The charge pump circuit comprises: a constant current source, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a capacitor; wherein the drain of the first PMOS tube is connected to its gate and the first end of the constant current source, and the source is connected to the power supply; the second end of the constant current source is grounded; the drain of the second PMOS tube is connected to the drain and the gate of the first NMOS tube, the gate is connected to the gate of the first PMOS tube, and the source is connected to the power supply; the drain of the third PMOS tube is connected to the source of the fourth PMOS tube, the gate is connected to the charging pulse input end, and the source is connected to the power supply; the drain of the fourth PMOS tube is connected to the first end of the capacitor and to the control voltage output end; the drain and the gate of the first NMOS tube are connected together and connected to the drain of the second PMOS tube, and the source is grounded; the drain of the second NMOS tube is connected to the drain of the fourth PMOS tube, the gate is connected to the gate of the first NMOS tube, and the source is connected to the drain of the third NMOS tube; the drain of the third NMOS tube is connected to the source of the second NMOS tube, the gate is connected to the discharge pulse input end, and the source is grounded.

6. The constant current control circuit with charge pump overvoltage protection according to claim 3, characterized in that: The constant current reference modulation circuit comprises: a first voltage buffer, a second voltage buffer, a first resistor, a second resistor, a first NMOS tube, and a second NMOS tube; wherein, the input end of the first voltage buffer is connected to the constant current reference input end, and the output end is connected to the first end of the first resistor; the input end of the second voltage buffer is connected to the control voltage input end, and the output end is connected to the first end of the second resistor; the second end of the first resistor is connected to the current reference output end; the second end of the second resistor is connected to the drain and the gate of the first NMOS tube; the drain and the gate of the first NMOS tube are connected together and connected to the second end of the second resistor, and the source is grounded; the gate of the second NMOS tube is connected to the gate of the first NMOS tube, the drain is connected to the second end of the first resistor, and the source is grounded.

7. The constant current control circuit with charge pump overvoltage protection according to claim 3, characterized in that: The overvoltage shutdown circuit includes: a voltage buffer, a switch, and a comparator; wherein the input end of the voltage buffer is connected to the second reference voltage input end, and the output end is connected to the first end of the switch; the second end of the switch is connected to the control voltage input end, and the control end is connected to the overvoltage shutdown signal input end; the positive input end of the comparator is connected to the control voltage input end, the negative input end is connected to the first reference voltage input end, and the output end is connected to the overvoltage protection output end.

8. The constant current control circuit with charge pump overvoltage protection according to claim 3, characterized in that: The error amplifier circuit comprises: an amplifier, an error amplifier, a first NMOS tube, a second NMOS tube, a first resistor, a capacitor, a second resistor, and a switch; wherein the positive input terminal of the amplifier is connected to the minimum peak current reference input terminal, the negative input terminal is connected to the source of the first NMOS tube and the peak current signal output terminal, and the output terminal is connected to the gate of the first NMOS tube; the drain of the first NMOS tube is connected to the power supply voltage, the gate is connected to the output terminal of the amplifier, and the source is connected to the negative input terminal of the amplifier and the peak current signal output terminal; the positive input terminal of the error amplifier is connected to the output current reference input terminal, the negative input terminal is connected to the second terminal of the first resistor and the first terminal of the capacitor, and the output terminal is connected to the gate of the second NMOS tube and the second terminal of the capacitor; the drain of the second NMOS tube is connected to the power supply voltage, and the source is connected to the first terminal of the second resistor and the peak current signal output terminal; the first terminal of the first resistor is connected to the output current signal input terminal, and the second terminal is connected to the first terminal of the capacitor and the negative input terminal of the error amplifier; the second terminal of the capacitor is connected to the first terminal of the switch; the second terminal of the switch is grounded, and the control terminal is connected to the overvoltage shutdown signal input terminal; the second terminal of the second resistor is grounded.

9. The constant current control circuit with charge pump overvoltage protection according to claim 1, characterized in that: The driving output end and the sampling current input end are connected to the power MOS tube; the driving output end periodically outputs a high or low voltage to periodically turn on or off the power MOS tube to perform current constant control; the sampling current input end is also connected to a current sampling resistor to perform current sampling during the opening of the power MOS tube.

10. An LED constant current drive circuit, characterized in that: The circuit comprises: an overvoltage setting resistor, a power MOS tube, a current sampling resistor, a rectifier diode, a power inductor, a load, and a constant current control circuit with charge pump overvoltage protection according to any one of claims 1 to 9; Among them, the first end of the overvoltage setting resistor is connected to the external resistor end of the constant current control circuit, and the second end is grounded; the gate of the power MOS tube is connected to the driving output end of the constant current control circuit, the drain is connected to the first end of the power inductor and the first end of the rectifier diode, and the source is connected to the first end of the current sampling resistor; the first end of the current sampling resistor is connected to the sampling current input end of the constant current control circuit; the first end of the rectifier diode is connected to the first end of the inductor, and the second end is connected to the input voltage; the second end of the power inductor is connected to the second end of the load; the first end of the load is connected to the input voltage, and the second end is connected to the second end of the power inductor.

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