Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, a first source-drain electrode layer, a first type semiconductor layer, a first gate layer, a first gate oxide layer, a second gate oxide layer, a second type semiconductor layer, and a second source-drain electrode layer. The first source-drain electrode layer comprises a first source, a first drain, a second source, and a second drain. The first type semiconductor layer comprises a first channel layer and a second channel layer. The first gate layer comprises a first gate, a second gate, and a third gate. The first gate oxide layer is arranged between the first gate layer and the second gate oxide layer. The second gate oxide layer is arranged between the second type semiconductor layer and the second source-drain electrode layer. The second gate oxide layer is provided with a first via hole, and the first via hole exposes the first gate. The second type semiconductor layer comprises a third channel layer and a fourth channel layer. The second source-drain electrode layer comprises a third source, a third drain, a fourth source, and a fourth drain. The technical scheme provided by the application can make the process of preparing a capacitorless dynamic random access memory compatible with the process of preparing a vertical complementary field effect transistor.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor technology, and particularly relates to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] In modern memory and computing architectures, memory devices play an increasingly important role. At present, most large-capacity memories are dynamic random access memories (DRAM) with one transistor and one capacitor, namely 1T1C DRAM. The special requirements of the preparation process for capacitors and transistors make it difficult to match the advanced preparation process of current logic circuits, and the von Neumann memory and computing architecture often separates DRAM from the central control processing unit CPU, and the data interaction needs long-distance communication. Therefore, the data transmission speed between memory and computing gradually mismatches. In this background, 2T0C memory devices, also known as capacitorless DRAM, provide a good solution because they do not need to prepare capacitors and therefore have better size scalability.

[0003] A complementary field effect transistor (CFET) is a kind of transistor that stacks P-type and N-type field effect transistors in the vertical direction, so that the two share a gate electrode as a signal input, and the drain is connected as a signal output. The two sources are connected to ground and power supply respectively. This design allows the size of N-type CFET and P-type CFET to be adjusted according to performance requirements, and the channels of N-type CFET and P-type CFET can use different semiconductor materials to match the mobility, thereby improving the drive current. In addition, the vertically stacked structure helps to reduce the size of the device and improve the integration of the chip.

[0004] The arrangement of CFET can effectively integrate multiple functional devices and reduce their power consumption. However, for the CFET prepared in the later stage, the process is a vertical process, which requires vertical stacking of two transistors in a unit area, which requires a top-gate transistor and a back-gate transistor. In the preparation of 2T0C DRAM, both transistors use a common transistor structure, either top-gate or back-gate, which is difficult to effectively compatible with the process of CFET prepared in the later stage. SUMMARY

[0005] The present application provides a semiconductor device and a preparation method thereof, which aims to make the process of preparing capacitorless DRAM compatible with the process of preparing CFET in the later stage.

[0006] In a first aspect, embodiments of the present application provide a semiconductor device, which is divided into a first region and a second region, the first region is used to form a capacitorless dynamic random access memory, and the second region is used to form a vertical complementary field effect transistor, the device comprises:

[0007] a substrate substrate;

[0008] a first source-drain electrode layer formed on the substrate substrate, the first source-drain electrode layer comprises a first source and a first drain formed in the first region, and a second source and a second drain formed in the second region;

[0009] a first type semiconductor layer formed on a side of the first source-drain electrode layer away from the substrate substrate, the first type semiconductor layer comprises a first channel layer formed in the first region and a second channel layer formed in the second region, two ends of the first channel layer are electrically connected to the first source and the first drain respectively, and two ends of the second channel layer are electrically connected to the second source and the second drain respectively;

[0010] a first gate layer, the first gate layer comprises a first gate located on a side of the first channel layer away from the substrate substrate, a second gate located on a side of the second channel layer away from the substrate substrate, and a third gate located in the first region, a first gate oxide layer is formed on a side of the first gate layer close to the substrate substrate, and a second gate oxide layer is formed on a side of the first gate layer away from the substrate substrate, a first via hole is formed on the second gate oxide layer, and the first via hole exposes the first gate;

[0011] a second type semiconductor layer formed on a side of the second gate oxide layer away from the substrate substrate, the second type semiconductor layer comprises a third channel layer and a fourth channel layer, the third channel layer is formed on a side of the third gate away from the substrate substrate, and the fourth channel layer is formed on a side of the second gate away from the substrate substrate;

[0012] a second source-drain electrode layer formed on a side of the second gate oxide layer away from the substrate substrate, the second source-drain electrode layer comprises a third source and a third drain, and a fourth source and a fourth drain, the third source and the third drain are electrically connected to two ends of the third channel layer respectively, the fourth source and the fourth drain are electrically connected to two ends of the fourth channel layer respectively, and the third drain is electrically connected to the first gate through the first via hole.

[0013] In some embodiments, the semiconductor device further comprises a second via hole, the second via hole penetrates the first gate oxide layer and the second gate oxide layer, and the second drain is electrically connected to the fourth drain through the second via hole.

[0014] In some embodiments, the second via includes a first sub-via and a second sub-via, the first sub-via penetrates the first gate oxide layer, the second sub-via penetrates the second gate oxide layer, and a projection of the first sub-via and the second sub-via on the substrate substrate at least partially overlaps.

[0015] In some embodiments, the first type semiconductor layer is an N-type semiconductor material layer, and the second type semiconductor layer is a P-type semiconductor material layer; or, the first type semiconductor layer is a P-type semiconductor material layer, and the second type semiconductor layer is an N-type semiconductor material layer.

[0016] In some embodiments, the N-type semiconductor material layer is at least one of IGZO, IWO, ITO, and other oxide semiconductor materials, and the P-type semiconductor material layer is at least one of TeOx, SnO, P-type oxide semiconductor materials, P-type two-dimensional materials, P-type carbon nanotubes, and the like.

[0017] In a second aspect, the embodiments of the present application further provide a preparation method of a flat panel detector substrate, including:

[0018] providing a substrate substrate;

[0019] forming a first source-drain electrode layer on the substrate substrate, the first source-drain electrode layer including a first source and a first drain formed in a first region, and a second source and a second drain formed in a second region;

[0020] forming a first type semiconductor layer on a side of the first source-drain electrode layer away from the substrate substrate, the first type semiconductor layer including a first channel layer formed in the first region and a second channel layer formed in the second region, two ends of the first channel layer being electrically connected to the first source and the first drain, respectively, and two ends of the second channel layer being electrically connected to the second source and the second drain, respectively;

[0021] forming a first gate layer, the first gate layer including a first gate located on a side of the first channel layer away from the substrate substrate, a second gate located on a side of the second channel layer away from the substrate substrate, and a third gate located in the first region, and forming a first gate oxide layer on a side of the first gate layer close to the substrate substrate, and forming a second gate oxide layer on a side of the first gate layer away from the substrate substrate, forming a first via on the second gate oxide layer, and the first via exposing the first gate;

[0022] The second type semiconductor layer is formed on the side of the second gate oxide layer away from the substrate, and includes a third channel layer and a fourth channel layer, the third channel layer is formed on the side of the third gate away from the substrate, and the fourth channel layer is formed on the side of the second gate away from the substrate.

[0023] The second source-drain electrode layer is formed on the side of the second gate oxide layer away from the substrate, and includes a third source electrode and a third drain electrode, and a fourth source electrode and a fourth drain electrode, the third source electrode and the third drain electrode are respectively electrically connected to both ends of the third channel layer, the fourth source electrode and the fourth drain electrode are respectively electrically connected to both ends of the fourth channel layer, and the third drain electrode is electrically connected to the first gate through the first via hole.

[0024] In some embodiments, before the fourth drain electrode is formed, the method further includes:

[0025] The second via hole is formed, the second via hole penetrates the first gate oxide layer and the second gate oxide layer, and the second drain electrode is electrically connected to the fourth drain electrode through the second via hole.

[0026] In some embodiments, the second via hole includes a first sub-via hole and a second sub-via hole, and the forming of the second via hole includes:

[0027] The first sub-via hole is formed after the first gate oxide layer is formed, and the first sub-via hole penetrates the first gate oxide layer.

[0028] The second sub-via hole is formed after the second gate oxide layer is formed, and the second sub-via hole penetrates the second gate oxide layer; the projections of the first sub-via hole and the second sub-via hole on the substrate at least partially overlap.

[0029] In some embodiments, the first type semiconductor layer is an N-type semiconductor material layer, and the second type semiconductor layer is a P-type semiconductor material layer; or, the first type semiconductor layer is a P-type semiconductor material layer, and the second type semiconductor layer is an N-type semiconductor material layer.

[0030] In some embodiments, the N-type semiconductor material layer is at least one of IGZO, IWO, ITO, and other oxide semiconductor materials, and the P-type semiconductor material layer is at least one of TeOx, SnO, P-type oxide semiconductor material, P-type two-dimensional material, P-type carbon nanotube, and the like.

[0031] The technical scheme provided in the embodiment of the application, the semiconductor device comprises a first region and a second region, the first region is formed with a back-end complementary capacitorless DRAM, and the second region is formed with a CFET, so that the capacitorless DRAM and the CFET are simultaneously arranged in the same semiconductor device, and the capacitorless DRAM and the CFET correspond to each other in the layer structure, so that the capacitorless DRAM and the CFET can be prepared by using one set of process flow, and the top-gate transistor and the back-gate transistor of the capacitorless DRAM can be prepared simultaneously. The back-end CFET can be compatible with different channel materials, and can be used to prepare functional modules with different requirements, so as to realize multifunctional integration of the back-end CFET.

[0032] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and / or by practice of the application. BRIEF DESCRIPTION OF DRAWINGS

[0033] The above and / or additional aspects and advantages of the application will become apparent and be readily appreciated from the following description, including the appended drawings, wherein:

[0034] Figure 1 A semiconductor device structure schematic diagram provided by an embodiment of the application;

[0035] Figure 2 Another semiconductor device structure schematic diagram provided by an embodiment of the application;

[0036] Figure 3 A flowchart of a preparation method of a semiconductor device provided by an embodiment of the application;

[0037] Figures 4 to 9 For Figure 3 The structure schematic diagram corresponding to each step in the preparation method shown. DETAILED DESCRIPTION

[0038] The embodiments of the application are described in detail below, and examples of the embodiments are shown in the drawings, wherein the same or similar reference signs represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below are exemplary and are only used to explain the application, and cannot be understood as a limitation on the application.

[0039] The terms "first", "second", and the like in the description and in the claims of this application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the use of such terms as "first" and "second" are arbitrary labels and are used merely for purposes of nomenclature. Unless specifically stated otherwise, it is appreciated that the same element can be labeled with a different numeric designation and / or not contain a numeric designation in different views. Further, the description and claims can refer to "and / or" where nomenclature such as "associated with" or "associated therewith" is used. Such nomenclature is used in this disclosure in the normal, rather than in the exclusive, sense.

[0040] In the description of the present application, the meaning of "a plurality" is two or more.

[0041] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "certain embodiments", "an example", "a specific example", or "some examples" and the like is intended to indicate that a particular feature, structure, material, or characteristic that follows the term is included in at least one embodiment or example of the present application. Such terms in the description are not necessarily all referring to the same embodiment or example. Furthermore, the described features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0042] In describing some embodiments, the use of "connection" and / or "coupling" and / or "connected" and / or "coupled" along with their derivatives can be used. These terms are intended to mean the joining of two or more elements in a manner that allows the elements to function cooperatively. In some embodiments, the joining can be through fixed connections, detachable connections, or integrally formed connections. In some embodiments, the joining can be direct as through a direct physical or electrical connection, or indirect such as through an intermediary medium. The embodiments disclosed herein are not necessarily limited in terms of the manner in which the connections are made.

[0043] In addition, the use of "based on" can mean "based, at least in part, on" which permits for openness and flexibility in the processes, steps, calculations, and other actions based on one or more recited conditions or values.

[0044] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate or intervening layers can also be present.

[0045] Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result from, for example, manufacturing. The regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0046] Examples of the embodiments are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements or elements with same or similar functions throughout. The embodiments described below by reference to the drawings are exemplary only, and are merely intended to explain the present application, and should not be construed as limiting the present application.

[0047] Most of the existing semiconductor preparation processes are based on silicon, which inevitably introduces high-temperature steps in transistors; further, the preparation of multilayer transistors is restricted by high temperature, which causes the lower transistor to fail, so the traditional process is mainly single-layer devices. The transistors prepared by using the back-compatible channel (such as oxide semiconductor) have lower preparation temperature and the potential for large-scale preparation; therefore, multilayer stacked transistors are possible.

[0048] In addition, the NP complementary transistor arrangement can effectively integrate various functional devices and reduce power consumption. However, for the vertically complementary transistor CFET prepared in the later stage, the process is a vertical process, which requires vertically stacking two transistors in a unit area, which requires a top gate transistor and a back gate transistor; in the preparation of today's capacitorless DRAM, both transistors use a transistor structure, but usually all use top gate or all use back gate, making it difficult to effectively compatible with the later CFET process.

[0049] To solve the above problems in the related art, the embodiments of the present application provide a semiconductor device, Figure 1 A semiconductor device structure schematic diagram is provided for the embodiments of the present application.

[0050] As Figure 1As shown, the semiconductor device 10 provided in the embodiments of the present application can be divided into a first region and a second region, the first region is used for forming a capacitorless DRAM, and the second region is used for forming a CFET. In the embodiments of the present application, the capacitorless DRAM includes a top-gate transistor and a back-gate transistor, the gates of the two are arranged in the same layer and can be prepared cooperatively, and the CFET includes a top-gate transistor and a back-gate transistor and shares the same gate; in addition, other film layers of the capacitorless DRAM and the CFET can also be arranged in the same layer and obtained in the same preparation step. Specifically, the semiconductor device provided in the embodiments of the present application can include:

[0051] a substrate 101;

[0052] a first source-drain electrode layer 102 formed on the substrate 101, the first source-drain electrode layer 102 includes a first source 1021 and a first drain 1022 formed in the first region, the first source 1021 and the first drain 1022 are the source and the drain of the top-gate transistor of the capacitorless DRAM, and a second source 1023 and a second drain 1024 formed in the second region, the second source 1023 and the second drain 1024 are the source and the drain of the top-gate transistor of the CFET;

[0053] a first type semiconductor layer 103 formed on the side of the first source-drain electrode layer 102 away from the substrate 101, the first type semiconductor layer 103 includes a first channel layer 1031 formed in the first region and a second channel layer 1032 formed in the second region, the two ends of the first channel layer are electrically connected with the first source 1021 and the first drain 1022 respectively, serving as the channel layer of the top-gate transistor of the capacitorless DRAM, and the two ends of the second channel layer 1032 are electrically connected with the second source 1023 and the second drain 1024 respectively, serving as the channel layer of the top-gate transistor of the CFET;

[0054] a first gate layer 104, the first gate layer 104 includes a first gate 1041 located on the side of the first channel layer 1031 away from the substrate 101, serving as the gate of the top-gate transistor of the capacitorless DRAM, a second gate 1042 located on the side of the second channel layer 1032 away from the substrate 101, serving as the gate of the top-gate transistor of the CFET, and a third gate 1043 located in the first region, serving as the gate of the back-gate transistor of the capacitorless DRAM;

[0055] In addition, to achieve gate insulation, a first gate oxide layer 105 may be further formed on the side of the first gate layer 104 close to the base substrate 101, and a second gate oxide layer 106 may be formed on the side of the first gate layer 104 away from the base substrate 101. A first via hole 109 is formed in the second gate oxide layer 106, and the first via hole 109 exposes the first gate 1041.

[0056] A second-type semiconductor layer 107 is formed on a side of the second gate oxide layer 106 away from the substrate 101. The second-type semiconductor layer 107 includes a third channel layer 1071 and a fourth channel layer 1072. The third channel layer 1071 is formed on a side of the third gate away from the substrate 101 and serves as a channel layer of the back-gate transistor of the capacitor-less DRAM. The fourth channel layer 1072 is formed on a side of the second gate 1042 away from the substrate 101 and serves as a channel layer of the back-gate transistor of the CFET.

[0057] A second source-drain electrode layer 108 is formed on the side of the second gate oxide layer 106 away from the base substrate 101. The second source-drain electrode layer 108 includes a third source 1081 and a third drain 1082, as well as a fourth source 1083 and a fourth drain 1084. The third source 1081 and the third drain 1082 are electrically connected to the two ends of the third channel layer 1071, respectively, and serve as the source and drain of the back-gate transistor of the above-mentioned capacitor-less DRAM, and the third drain 1082 is electrically connected to the first gate 1041 through the first via 109. The fourth source 1083 and the fourth drain 1084 are electrically connected to the two ends of the fourth channel layer 1072, respectively, and serve as the source and drain of the back-gate transistor of the CFET.

[0058] The capacitor-free DRAM provided in the above embodiment of the present application has a drain of the back-gate transistor, i.e., the third drain 1082, electrically connected to the gate of the top-gate transistor, i.e., the first gate 1041, through the first via 109. The above-mentioned back-gate transistor and top-gate transistor can be used as a write tube and a read tube respectively.

[0059] The CFET located in the second region of the semiconductor device includes a back-gate transistor and a top-gate transistor, such as Figure 1 As shown, the top-gate transistor and the back-gate transistor are stacked vertically. By adjusting the order of the process steps, the upper and lower positions of the two transistors can be interchanged without affecting the function of the back-end CFET device. The CFET is equivalent to an independent N transistor and an independent P transistor. Through lead interconnection, they can each achieve their required functions while occupying only one unit area.

[0060] The technical solution provided by the embodiment of the present application includes a semiconductor device comprising a first region and a second region, wherein the first region forms a back-end complementary capacitor-less DRAM, and the second region forms a CFET, thereby achieving the simultaneous provision of capacitor-less DRAM and CFET in the same semiconductor device, and the two are also corresponding in each layer structure, thereby enabling the preparation of both through a set of process flows, and for the capacitor-less DRAM, its top-gate transistor and back-gate transistor can also be prepared in coordination. Such a back-end CFET can be compatible with the integration of different channel materials, prepare functional modules with different requirements, and realize the multifunctional integration of the back-end CFET.

[0061] In some embodiments, as Figure 2 As shown, the semiconductor device also has a second via 110 formed therein. The second via 110 penetrates the first gate oxide layer 105 and the second gate oxide layer 1032, and the second drain 1024 is electrically connected to the fourth drain 1084 through the second via. When the CFET is opened through the via process, the back-gate transistor and the top-gate transistor share the second gate 1042 as the signal input terminal. When the input signal is high, the back-gate transistor connected to the power supply terminal is turned off, and the top-gate transistor connected to the ground line is turned on. The fourth drain 1084 and the second drain 1024 are interconnected as the output terminal. At this time, the back-gate transistor pulls the output terminal voltage down to the low level of the ground terminal. Conversely, when the input terminal is low, the top-gate transistor is turned on, the back-gate transistor is turned off, and the top-gate transistor pulls the output terminal voltage up to the high level of the power supply terminal, realizing the inverter function.

[0062] In some embodiments, the second via 110 includes a first sub-via 1101 and a second sub-via 1102, the first sub-via 1101 penetrates the first gate oxide layer 105, and the second sub-via 1102 penetrates the second gate oxide layer 106, and the projections of the first sub-via 1101 and the second sub-via 1102 on the base substrate 101 at least partially overlap. Therefore, in the preparation process of the semiconductor device, the first sub-via 1101 can be prepared after the first gate oxide layer 105 is prepared, and then the second sub-via 1101 can be prepared after the second gate oxide layer 106 is prepared.

[0063] In some embodiments, the first type semiconductor layer 103 is an N-type semiconductor material layer, and the second type semiconductor layer 107 is a P-type semiconductor material layer; or, the first type semiconductor layer 103 is a P-type semiconductor material layer, and the second type semiconductor layer 107 is an N-type semiconductor material layer.

[0064] The N transistor is a back-gate transistor, and the P transistor is a top-gate transistor. The top gate or back gate of the two can be interchangeable, but it should be noted that materials with lower leakage (usually N transistors) need to be used as write transistors of 2T0C DRAM memory to ensure sufficiently good storage retention characteristics.

[0065] In some embodiments, the N-type semiconductor material layer can be made of any low-leakage, post-processable, and uniform material. Examples include IGZO, IWO, ITO, and other oxide semiconductor materials. The P-type semiconductor material layer can be made of any post-processable, scalable, and uniform material. Examples include P-type oxide semiconductor materials such as TeOx and SnO, P-type two-dimensional materials, and P-type carbon nanotubes.

[0066] In some embodiments, a capless DRAM located in the first region of the semiconductor device can be composed of a top-gate P-type read transistor and a back-gate N-type write transistor. The third drain 1082 of the N-type write transistor is connected to the write transistor bit line, the third gate 1043 is connected to the write transistor word line, and the third source 1081 is connected to the first gate 1041 of the P-type read transistor. When data needs to be written, the data is supplied to the write transistor bit line in the form of a voltage. A high voltage is set at the end of the write transistor word line to turn on the N-type write transistor, and the voltage at the storage node (SN) is pulled low or high by the write transistor bit line. When data is not needed to be written to this cell, the write transistor word line is grounded or set to a negative voltage, turning the write transistor off and retaining the data in the SN. The two ends of the read transistor are respectively connected to the read transistor word line and the bit line. When not selected, they are grounded, keeping the P-type read transistor in the off state. When selected to read data, the read transistor bit line is given a higher voltage and the read transistor word line is given a lower voltage. The current is read to determine the potential at the storage node, thereby realizing the memory function.

[0067] The present invention also provides a method for preparing a semiconductor device, which can be used to prepare the above-mentioned Figure 1 The semiconductor device 10 in the illustrated embodiment. Figure 3 A schematic diagram of a process for preparing a semiconductor device provided in an embodiment of the present application, wherein the specific structure can be referred to Figure 1 As shown, the semiconductor device 10 can be divided into a first region and a second region, the first region is used to form a capacitor-less DRAM, and the second region is used to form a CFET. In the embodiment of the present application, the capacitor-less DRAM includes a top-gate transistor and a back-gate transistor, the gates of the two are arranged in the same layer and can be prepared in collaboration, and the CFET includes a top-gate transistor and a back-gate transistor, and they share the same gate; in addition, the other film layers of the capacitor-less DRAM and the CFET can also be arranged in the same layer and obtained in the same preparation step. The specific preparation process is as follows Figure 3 As shown, the preparation method comprises the following steps:

[0068] Step 301: providing a substrate 101, which can be a single crystal silicon wafer.

[0069] Step 302: forming a first source-drain electrode layer 102, which includes a first source 1021 and a first drain 1022 formed in a first region, and a second source 1023 and a second drain 1024 formed in a second region, wherein the first source 1021 and the first drain 1022 are the source and the drain of the top-gate transistor of the above-mentioned capacitorless DRAM, and the second source 1023 and the second drain 1024 are the source and the drain of the top-gate transistor of the above-mentioned CFET.

[0070] In this step, the first source-drain electrode layer 102 can be made of various metal materials, for example, it can be palladium (Pd), as shown in Figure 4 The first source-drain electrode layer 102 can be formed by depositing palladium (Pd) on the substrate 101 by electron beam evaporation, as shown in

[0071] Step 303: forming a first type semiconductor layer 103, which includes a first channel layer 1031 formed in the first region and a second channel layer 1032 formed in the second region, the two ends of the first channel layer 1031 are electrically connected to the first source 1021 and the first drain 1022 respectively, and the two ends of the second channel layer 1032 are electrically connected to the second source 1023 and the second drain 1024 respectively, wherein the first channel layer 1031 can be used as the channel layer of the top-gate transistor of the above-mentioned capacitorless DRAM, and the second channel layer 1032 can be used as the channel layer of the top-gate transistor of the above-mentioned CFET.

[0072] In this step, according to the type of the top-gate transistor to be prepared, the above-mentioned first type semiconductor layer 103 can be a P-type semiconductor material layer or an N-type semiconductor material layer, for example, it can be a P-type semiconductor material layer, which can be TeO x At this time, as shown in Figure 5 TeO x The Te:O composition ratio in TeO x The region where the channel layer is located can be defined by dry etching using Cl2 and BCl3.

[0073] Step 304: forming a first gate oxide layer 105;

[0074] As shown in Figure 6As shown, aluminum oxide Al2O3 and hafnium oxide HfO2 are stacked as a first gate oxide layer 105 by atomic layer deposition (ALD) on the side of the first type semiconductor layer 103 away from the substrate 101. In this step, the ambient temperature during deposition can be set to 150°C.

[0075] Step 305: forming a first gate layer 104, the first gate layer 104 including a first gate 1041 located on a side of the first channel layer 1031 away from the substrate 101, a second gate 1042 located on a side of the second channel layer 1032 away from the substrate 101, and a third gate 1043 located in the first region.

[0076] like Figure 7 As shown, the material of the first gate layer can be a metal material. In the embodiment of the present application, titanium Ti / palladium Pd is deposited on the side of the first gate oxide layer 105 away from the base substrate 101 to form a first gate layer 104, wherein the first gate layer 104 includes a first gate 1041 located on the side of the first channel layer 1031 away from the base substrate 101, and the first gate 1041 serves as the top gate of the capacitor-less DRAM; a second gate 1042 located on the side of the second channel layer 1032 away from the base substrate 101, and the second gate 1042 serves as the top gate of the CFET and is also used as the common gate of the CFET; a third gate 1043 located in the first region serves as the back gate of the capacitor-less DRAM.

[0077] Step 306: forming a second gate oxide layer 106 and a first via hole 109; forming a first gate oxide layer 105 on the side of the first gate layer 104 close to the base substrate 101, and forming a second gate oxide layer 106 on the side of the first gate layer 104 away from the base substrate 101, and forming a first via hole 109 on the second gate oxide layer 106, wherein the first via hole 109 exposes the first gate 1041;

[0078] like Figure 8 As shown, hafnium oxide (HfO2) is grown as a second gate oxide layer 106 by ALD at 150°C on the side of the first gate layer 104 near the substrate 101. Simultaneously, this step also opens a hole in the second gate oxide layer 106 deposited on the first gate 1041 of the capless DRAM, forming a first via 109, exposing the metal of the first gate 1041 for easy interconnection with the third drain 1082.

[0079] Step 307: forming a second-type semiconductor layer 107, the second-type semiconductor layer 107 including a third channel layer 1071 and a fourth channel layer 1072, the third channel layer 1071 being formed on a side of the third gate 1043 away from the substrate 101, and the fourth channel layer 1072 being formed on a side of the second gate 1042 away from the substrate 101; wherein the third channel layer 1071 can serve as a channel layer of a back-gate transistor of the aforementioned capacitor-less DRAM, and the fourth channel layer 1072 can serve as a channel layer of a back-gate transistor of a CFET;

[0080] like Figure 9 As shown, a second type semiconductor layer 107 is formed on the side of the second gate oxide layer 106 away from the substrate 101 by atomic layer deposition. The second type semiconductor layer 107 can be a P-type semiconductor material layer, or an N-type semiconductor material layer, for example, an N-type semiconductor material layer, which can be IGZO;

[0081] Step 308: forming a second source-drain electrode layer 108, the second source-drain electrode layer 108 including a third source 1081 and a third drain 1082, and a fourth source 1083 and a fourth drain 1084. The third source 1081 and the third drain 1082 are electrically connected to two ends of the third channel layer 1071, respectively. The fourth source 1083 and the fourth drain 1084 are electrically connected to two ends of the fourth channel layer 1072, respectively. The third drain 1082 is electrically connected to the first gate 1041 through the first via 109. The third source 1081 and the third drain 1082 serve as the source and drain of the back-gate transistor of the capacitor-less DRAM, respectively. The fourth source 1083 and the fourth drain 1084 serve as the source and drain of the back-gate transistor of the CFET, respectively.

[0082] In this step, chemical vapor deposition can be used to form a second source-drain electrode layer 108 on the side of the second type semiconductor layer 107 away from the substrate 101. Through this step, the above-mentioned Figure 1 The semiconductor device in the illustrated embodiment.

[0083] Finally, palladium (Pd) can be deposited by chemical vapor deposition to serve as contact points connecting the second source and drain electrode layer 108 to the external circuit. Unnecessary palladium layers and possible other material layers are removed by wet etching to define the channel layer region of the second type semiconductor layer 107.

[0084] In some embodiments, as Figure 2As shown, the second via hole 110 is formed by etching the first gate insulating layer 105 and the second gate insulating layer 106 using inductively coupled plasma before forming the fourth drain electrode 1084, the second via hole 110 penetrates the first gate insulating layer 105 and the second gate insulating layer 106, and the second drain electrode 1024 is electrically connected to the fourth drain electrode 1084 through the second via hole 110; the second via hole 110 can be formed at one time or in two times.

[0085] For example, the second via hole 110 includes a first sub-via hole 1101 and a second sub-via hole 1102, and is formed in two steps, for example, after forming the first gate insulating layer 105, the first sub-via hole 1101 is formed by etching the first gate insulating layer 105 using inductively coupled plasma, the first sub-via hole 1101 penetrates the first gate insulating layer 105;

[0086] After forming the second gate insulating layer 106, the second sub-via hole 1102 is formed by etching the second gate insulating layer 106 using inductively coupled plasma, the second sub-via hole 1102 penetrates the second gate insulating layer 106; the projection of the first sub-via hole 1101 and the second sub-via hole 1102 on the substrate 101 at least partially overlaps.

[0087] In the embodiments of the present application, the N-type channel material can be any low-leakage, post-preparable, and well-uniform material. For example, IGZO, IWO, ITO, and other oxide semiconductor materials. The P-type channel material can be any post-preparable, large-scale-preparable, and well-uniform material. For example, TeOx, SnO, P-type oxide semiconductor material, P-type two-dimensional material, P-type carbon nanotube, and the like.

[0088] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: The semiconductor device is divided into a first region and a second region, the first region is used to form a capacitor-free dynamic random access memory, and the second region is used to form a vertical complementary field effect transistor. The device includes: substrate; A first source-drain electrode layer is formed on the base substrate, wherein the first source-drain electrode layer includes a first source and a first drain formed in a first region, and a second source and a second drain formed in the second region; a first-type semiconductor layer formed on a side of the first source-drain electrode layer away from the substrate, the first-type semiconductor layer comprising a first channel layer formed in a first region and a second channel layer formed in a second region, two ends of the first channel layer being electrically connected to the first source and the first drain, respectively, and two ends of the second channel layer being electrically connected to the second source and the second drain, respectively; a first gate layer, the first gate layer including a first gate located on a side of the first channel layer away from the base substrate, a second gate located on a side of the second channel layer away from the base substrate, and a third gate located in the first region, a first gate oxide layer formed on a side of the first gate layer close to the base substrate, and a second gate oxide layer formed on a side of the first gate layer away from the base substrate, a first via hole formed in the second gate oxide layer, the first via hole exposing the first gate; a second-type semiconductor layer formed on a side of the second gate oxide layer away from the base substrate, the second-type semiconductor layer comprising a third channel layer and a fourth channel layer, the third channel layer being formed on a side of the third gate away from the base substrate, and the fourth channel layer being formed on a side of the second gate away from the base substrate; A second source-drain electrode layer is formed on the side of the second gate oxide layer away from the base substrate, the second source-drain electrode layer includes a third source and a third drain, and a fourth source and a fourth drain, the third source and the third drain are electrically connected to the two ends of the third channel layer respectively, the fourth source and the fourth drain are electrically connected to the two ends of the fourth channel layer respectively, and the third drain is electrically connected to the first gate through the first via hole.

2. The semiconductor device according to claim 1, wherein A second via hole is also formed, the second via hole passes through the first gate oxide layer and the second gate oxide layer, and the second drain electrode is electrically connected to the fourth drain electrode through the second via hole.

3. The semiconductor device according to claim 2, wherein The second via includes a first sub-via and a second sub-via, the first sub-via passes through the first gate oxide layer, the second sub-via passes through the second gate oxide layer, and projections of the first sub-via and the second sub-via on the substrate at least partially overlap.

4. The semiconductor device according to claim 1, wherein The first type semiconductor layer is an N-type semiconductor material layer, and the second type semiconductor layer is a P-type semiconductor material layer; Alternatively, the first type semiconductor layer is a P-type semiconductor material layer, and the second type semiconductor layer is an N-type semiconductor material layer.

5. The semiconductor device according to claim 4, wherein The N-type semiconductor material layer is at least one of IGZO, IWO and ITO, and the P-type semiconductor material layer is at least one of TeOx, SnO, P-type two-dimensional material and P-type carbon nanotube.

6. A method for preparing a semiconductor device, characterized in that: The semiconductor device is divided into a first region and a second region, the first region is used to form a capacitor-free dynamic random access memory, and the second region is used to form a vertical complementary field effect transistor. The preparation method includes: providing a substrate; forming a first source-drain electrode layer on the base substrate, wherein the first source-drain electrode layer includes a first source and a first drain formed in a first region, and a second source and a second drain formed in the second region; forming a first-type semiconductor layer on a side of the first source-drain electrode layer away from the substrate, the first-type semiconductor layer comprising a first channel layer formed in a first region and a second channel layer formed in a second region, two ends of the first channel layer being electrically connected to the first source electrode and the first drain electrode, respectively, and two ends of the second channel layer being electrically connected to the second source electrode and the second drain electrode, respectively; forming a first gate layer, the first gate layer including a first gate located on a side of the first channel layer away from the base substrate, a second gate located on a side of the second channel layer away from the base substrate, and a third gate located in the first region, a first gate oxide layer formed on a side of the first gate layer close to the base substrate, and a second gate oxide layer formed on a side of the first gate layer away from the base substrate, a first via hole formed in the second gate oxide layer, the first via hole exposing the first gate; forming a second-type semiconductor layer on a side of the second gate oxide layer away from the substrate, the second-type semiconductor layer comprising a third channel layer and a fourth channel layer, the third channel layer being formed on a side of the third gate away from the substrate, and the fourth channel layer being formed on a side of the second gate away from the substrate; A second source-drain electrode layer is formed on the side of the second gate oxide layer away from the base substrate, and the second source-drain electrode layer includes a third source and a third drain, and a fourth source and a fourth drain. The third source and the third drain are electrically connected to the two ends of the third channel layer, respectively, and the fourth source and the fourth drain are electrically connected to the two ends of the fourth channel layer, respectively, and the third drain is electrically connected to the first gate through the first via hole.

7. The preparation method according to claim 6, characterized in that Before forming the fourth drain, the method further includes: A second via hole is formed, the second via hole penetrates the first gate oxide layer and the second gate oxide layer, and the second drain electrode is electrically connected to the fourth drain electrode through the second via hole.

8. The preparation method according to claim 7, characterized in that The second via hole includes a first sub-via hole and a second sub-via hole, and forming the second via hole includes: After forming the first gate oxide layer, forming the first sub-via hole, wherein the first sub-via hole penetrates the first gate oxide layer; After forming the second gate oxide layer, the second sub-via is formed, and the second sub-via passes through the second gate oxide layer; the projections of the first sub-via and the second sub-via on the base substrate at least partially overlap.

9. The preparation method according to claim 6, characterized in that The first type semiconductor layer is an N-type semiconductor material layer, and the second type semiconductor layer is a P-type semiconductor material layer; Alternatively, the first type semiconductor layer is a P-type semiconductor material layer, and the second type semiconductor layer is an N-type semiconductor material layer.

10. The preparation method according to claim 9, characterized in that The N-type semiconductor material layer is at least one of IGZO, IWO and ITO, and the P-type semiconductor material layer is at least one of TeOx, SnO, P-type two-dimensional material and P-type carbon nanotube.

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