Memory and preparation method thereof

Abstract

The embodiment of the invention discloses a memory and a preparation method thereof, the memory comprises a plurality of memory units, each memory unit comprises a charge storage area and a vertical transfer transistor located on the charge storage area, and the doping concentration of a source end, a drain end and a channel area of the vertical transfer transistor is controlled, so that the vertical transfer transistor is formed. The interface of the source end and the channel region is easy to generate band-to-band tunneling so as to realize lower sub-threshold swing and larger on-state current, so that the read-write speed is improved; furthermore, a lightly doped concentration region which comprises lightly doped and is opposite to the doping type of the drain end is formed between the drain end and the channel region, so that the leakage current is reduced, the refreshing frequency is reduced, and the power consumption is reduced. The preparation method of the memory can be completed only by simple doping concentration control, can be compatible with the manufacturing of a CMOS image sensor, and can reduce the process manufacturing difficulty.

Description

Technical Field

[0001] The present invention relates to the field of storage processing of image sensors, and in particular to a memory and a preparation method thereof Background Art

[0002] As the density of pixel arrays in image sensors increases, the storage requirements for image signals are also increasing, which makes the cache occupy a very large area in the image sensor chip and consumes a lot of energy during fast reading and writing. In order to further improve the energy efficiency of the cache system, we have previously proposed a process method for preparing high-density multi-value cache using etching and epitaxial processes to effectively increase the storage density of signals and reduce the cache area. However, under traditional transistor design, reading and writing large amounts of data still requires a lot of energy.

[0003] like Figure 1 As shown in FIG. 1 , it is a schematic example of the design of an existing memory. The doping concentration of the source terminal S, the channel region CL, and the drain terminal D of the existing vertical transfer transistor Tx is rarely designed. Sometimes, only the drain terminal is set to be heavily doped to reduce the leakage current, but such a design has very limited performance improvement on the memory. The existing memories need to consume a lot of energy when using traditional transistor designs. The transfer of charge in the existing design is completed by thermionic emission in the traditional MOSFET. Therefore, the minimum value of the subthreshold swing (the subthreshold swing is a performance indicator for measuring the mutual conversion rate between the on and off states of the transistor. It represents the change in gate voltage required for the leakage current to change tenfold) will not be lower than the lower limit of 60mV / dec. In this case, the switching ratio (I on / I off ) is difficult to improve, so the reading speed of the memory charge is difficult to further increase; and due to the influence of the short channel effect, as the memory density increases, the capacitor leakage becomes increasingly obvious, the memory time is limited, and the refresh frequency is forced to increase, resulting in difficulty in reducing power consumption. Summary of the invention

[0004] Based on the above problems, the purpose of the present invention is to provide a memory and a method for preparing the same. The memory of the present invention utilizes the process flow of the existing pixel area of ​​the CMOS image sensor. It only needs to change the doping distribution to prepare a transfer transistor that is easy to tunnel between the source end and the channel area interface as the switch of the memory. The doping concentration distribution design of the source end and the channel area realizes a lower subthreshold swing and a larger on-state current, thereby improving the read and write speed. Furthermore, a lightly doped concentration area including lightly doped and the doping type opposite to the doping type of the drain end is controlled to be formed between the drain end and the channel area to reduce leakage current, reduce refresh times, and reduce power consumption. The preparation method of the memory only needs simple doping concentration control to complete, is compatible with the manufacture of CMOS image sensors, and can reduce the difficulty of process manufacturing.

[0005] The present invention provides a method for preparing a memory, wherein the memory comprises a plurality of memory cells, each of the memory cells comprises a charge storage region and a vertical transfer transistor located on the charge storage region, and is characterized in that the preparation method comprises providing a substrate, preparing a charge storage region on the substrate, and preparing a vertical transfer transistor on the charge storage region; wherein, by controlling the doping concentration of a source terminal, a drain terminal, and a channel region of the vertical transfer transistor, band-to-band tunneling is easily caused at the interface between the source terminal and the channel region.

[0006] In some embodiments, the source end of the vertical transfer transistor includes a heavily doped first doping type region, the drain end includes a heavily doped second doping type region, and the channel region includes an intrinsic doping region, or a first lightly doped region, wherein the first doping type is opposite to the second doping type.

[0007] In some embodiments, after the vertical transfer transistor is etched, the first doping type region is formed by self-aligned implantation to form a first doping type region including a ring-shaped region, or to form a first doping type region including a U-shaped region, or to form a first doping type region including independently spaced first sub-regions and second sub-regions.

[0008] In some embodiments, the first doping type region is formed by well implantation.

[0009] In some embodiments, on a plane perpendicular to the length direction of the channel, the gate of the vertical transfer transistor is in a flat ring shape surrounding the channel region.

[0010] In some embodiments, on a plane perpendicular to the length direction of the channel, the gate includes a ring-shaped or U-shaped gate around the channel region, or the gate includes a first sub-gate and a second sub-gate located on both sides of the channel region.

[0011] In some embodiments, a second lightly doped region is further included between the drain terminal and the channel region, and the doping type of the second lightly doped region is opposite to the doping type of the second doping type region.

[0012] In some embodiments, both sides of the channel region further include heavily doped second doping type sub-regions adjacent thereto.

[0013] In some embodiments, a cross-sectional width of the second doping type sub-region is smaller than a width of the channel region.

[0014] In some embodiments, one end of the second doping type sub-region is adjacent to the second lightly doped region, and the other end is adjacent to the first doping type region.

[0015] In some embodiments, a doping concentration of the second lightly doped region is greater than a doping concentration of the channel region.

[0016] In some embodiments, a depth dimension of the second lightly doped region is smaller than a depth dimension of the channel region.

[0017] In some embodiments, the width dimension of the first doping type region is greater than the width dimension of the second doping type region.

[0018] In some embodiments, the charge type of the charge storage region is the same as the doping type of the source terminal and opposite to the doping type of the drain terminal.

[0019] In some embodiments, the substrate includes a first sub-substrate of a first doping type, a second sub-substrate of a second doping type located on the first sub-substrate, and a third sub-substrate of the first doping type located on the second sub-substrate.

[0020] In some embodiments, preparing a charge storage region on the substrate comprises the steps of: S1: etching the substrate to form a plurality of first grooves; S2: forming a first dielectric layer in the trench; S3: Filling a first polysilicon material on the surface of the first dielectric layer, and forming a lateral PN junction with the first polysilicon material and the second sub-substrate portion between the adjacent first trenches as the charge storage area.

[0021] In some embodiments, fabricating the vertical transfer transistor on the charge storage region comprises the steps of: S4: performing a first doping type heavy doping implantation, with the implantation depth being lower than the bottom of the vertical transfer transistor to form a source terminal of the vertical transfer transistor; S5: etching the third sub-substrate of the substrate to form a plurality of second grooves; S6: forming a second dielectric layer in the second trench; S7: Filling a second polysilicon material on the surface of the second dielectric layer.

[0022] In some embodiments, preparing the vertical transfer transistor on the charge storage region further comprises the step of: heavily doping the drain end of the vertical transfer transistor with a second doping type.

[0023] In some embodiments, preparing the vertical transfer transistor on the charge storage region includes the steps of: using chemical mechanical polishing to flatten the second polysilicon material remaining above the silicon surface; and then using an etching process to etch the second polysilicon material below the silicon surface, so that the gates of the multiple transfer transistors are separated from each other.

[0024] In some embodiments, the process step of etching the second polysilicon material below the silicon surface is performed simultaneously with the step of etching back the transistors in the pixel area.

[0025] In some embodiments, the preparing the vertical transfer transistor on the charge storage region comprises the step of: doping the gate of the vertical transfer transistor.

[0026] In some embodiments, the process step of doping the gate of the vertical transfer transistor is performed simultaneously with the process step of doping the gate of the transistor in the pixel area.

[0027] In some embodiments, the vertical transfer transistor is located in a region between the two adjacent first trenches.

[0028] In some embodiments, preparing the vertical transfer transistor on the charge storage region further comprises the step of: doping the channel region, the doping type comprising a first doping type or a second doping type.

[0029] In some embodiments, the first doping type includes P type or N type, and the second doping type includes N type or P type.

[0030] The present invention also provides a memory, which is prepared according to the method described in any of the above embodiments.

[0031] Compared with the prior art, the present invention has the following beneficial effects: (1) By controlling the doping concentration of the source, drain, and channel regions of the vertical transfer transistor, band-to-band tunneling is easily generated at the interface between the source and channel regions to achieve a lower subthreshold swing and a larger on-state current, thereby improving the read and write speed. By controlling the source to include a heavily doped region and the channel region to be an intrinsic region or a lightly doped region, when the transistor is turned off, due to the low channel doping concentration, depletion occurs under the action of the gate work function, and the long and narrow depletion channel presents a large resistance, thereby inhibiting the charge in the capacitor from leaking to the drain, and ensuring sufficient memory time without the need for a negative operating voltage. When performing read and write operations, when the transistor is turned on, the gate of the transistor applies a gate voltage, and when the channel and the source form a reverse PN junction, the interface energy band between the channel and the source is greatly bent, and band-to-band tunneling occurs at the interface between the channel and the source. Since the tunneling transistor does not rely on carrier thermal diffusion for charge transport, the subthreshold swing of the vertical transfer transistor can break through the thermodynamic limit, achieving a higher on-state current at a lower operating voltage, and faster read and write speeds. When the channel and the source end form a forward-biased PN junction, the entire channel cross section is used for charge transfer. The charge transfer cross section in this state is significantly larger than the corresponding on state of the conventional transfer transistor. The traditional MOSFET reading and writing relies on the channel inversion layer, which is only formed on the surface, with a small cross-sectional area and a large channel resistance. Therefore, the tunneling transistor in this state still has a better writing performance. In summary, the present invention can realize high-speed storage of multi-value memory, thereby reducing storage power consumption.

[0032] (2) Furthermore, the drain terminal is controlled to form a second doping type region including a heavily doped region, and a second lightly doped type region is set between the channel region and the drain terminal. The concentration of the second lightly doped type region is greater than the doping concentration of the channel region, which can further reduce the leakage current of the depletion region when turned off, reduce the number of refresh times, and reduce storage power consumption.

[0033] (3) Furthermore, a heavily doped region having a doping type opposite to that of the source end is formed on the side of the channel region and the surface of the first doping type region to connect the source end and the second lightly doped type region, thereby further reducing power consumption.

[0034] (4) The preparation method of the memory can be completed by simply setting the concentration, which is compatible with the production of CMOS image sensors and can reduce the difficulty of the production process. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The present invention will be further described in the form of exemplary embodiments, which will be described in detail by way of the accompanying drawings. These embodiments are not restrictive, and in these embodiments, the same number represents the same structure, wherein: Figure 1 It is a partial cross-sectional schematic diagram of a memory in the prior art.

[0036] Figure 2 FIG. 4 is a schematic cross-sectional view of a memory device according to an embodiment.

[0037] Figure 3 FIG. 4 is a schematic cross-sectional view of a memory device according to another embodiment.

[0038] Figure 4 FIG. 4 is a schematic cross-sectional view of a memory according to another embodiment.

[0039] Figure 5 FIG. 4 is a schematic cross-sectional view of a memory device according to yet another embodiment.

[0040] Figure 6-1 to Figure 6-5 The present invention is a schematic diagram of an embodiment of the process of the memory manufacturing method of the present invention.

[0041] Figure 7 The present invention is a schematic diagram of another embodiment of the process of the method for preparing the memory of the present invention.

[0042] Figure 8 A cross-sectional view of a memory device including specific doping types according to an embodiment is shown.

[0043] Fig. 9 Schematic diagram of the XZ cross-sectional shape of the gate and channel regions of a vertical transfer transistor. DETAILED DESCRIPTION

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present invention. For ordinary technicians in this field, the present invention can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0045] The problems mentioned in the background technology are described below in conjunction with specific embodiments.

[0046] Figure 2 1 is a cross-sectional schematic diagram of a memory of an embodiment, wherein the memory 1 comprises a plurality of memory cells Cs fabricated on a substrate 100, each memory cell Cs comprising a charge storage region and a vertical transfer transistor Tx located on the charge storage region Cs, the vertical transfer transistor Tx comprising a drain terminal D, a source terminal S and a channel region CL, wherein the drain terminal D, the channel region CL and the source terminal S are sequentially arranged in the Y direction. The charge type of the charge storage region Cs is the same as the doping type of the source terminal S and is opposite to the doping type of the drain terminal D.

[0047] The doping concentrations of the source terminal S, the drain terminal D, and the channel region CL of the vertical transfer transistor are controlled, and the source terminal S is set to include a heavily doped first doping type region 106, and the drain terminal D includes a heavily doped second doping type region 109 of a doping type opposite to the first doping type region. The channel region CL is set as an intrinsic doping region or as a first lightly doped type region, and the doping type of the first lightly doped type region can be the first doping type or the second doping type. By setting the source terminal S to include a heavily doped first doping type region 106 and the channel region CL to be intrinsically doped or lightly doped (i.e., the doping concentration of the first doping type region is much greater than the doping concentration of the channel region CL), after the gate is pressurized, the interface energy band between the first doping type region 106 and the channel region CL is greatly bent, and band-to-band tunneling occurs at the interface between the first doping type region 106 and the channel region CL. Since the tunneling transistor does not rely on carrier thermal diffusion for charge transport, the subthreshold swing of the vertical transfer transistor can break through the thermodynamic limit, achieve a higher on-state current under lower operating voltage conditions, improve the read and write speed, and can reduce the operating voltage of the integrated circuit and reduce power consumption.

[0048] In a preferred embodiment, if Figure 3 As shown, a second lightly doped region 111 is further provided between the heavily doped second doping type region 109 and the channel region CL, the doping concentration of the second lightly doped region 111 is greater than the doping concentration of the channel region CL, but less than the doping concentration of the second doping type region 109, and the doping type of the second lightly doped region 111 is opposite to the doping type of the second doping type region 109. The channel region CL may include intrinsic doping or light doping. If the doping type of the channel region CL is the same as the doping type of the second lightly doped region, the doping concentration of the channel region CL is required to be less than the second lightly doped region 111, otherwise the channel region is provided as an intrinsic doping or a lightly doped region opposite to the doping type of the second lightly doped region 111. In addition, the depth dimension (i.e., the dimension in the Y direction) of the second lightly doped region 111 is less than the depth dimension of the channel region CL. Controlling the formation of a region including a decreasing doping concentration at the drain terminal and the channel region can reduce leakage current, reduce the number of refreshes, and further reduce power consumption. In addition, by controlling the doping concentration of the source terminal S and the channel region CL to increase the probability of band-to-band tunneling at the interface, and controlling the drain terminal D and the channel region CL to form a region with decreasing doping concentration, the on-state current of the transistor can be increased while reducing the leakage current, thereby further improving the switching ratio.

[0049] like Figure 2 or Figure 3 As shown, the first doping type region 106 may be formed by well implantation or remote implantation to include a width dimension greater than the width dimension of the second doping type region 109. Figure 2As shown, the width of the first doping type region 106 in the X direction is approximately equal to the sum of the width of the channel region CL and the width of the gates G on both sides, that is, the first doping type region 106 not only has the width of the second doping type region 109, but also extends to both sides. The shape of the first doping type region 106 in the XZ cross section can form a combination of one or more shapes including block, circular ring, flat circular ring, U-shape, etc. Among them, the shape of the first doping type region 106 in the XZ cross section can also form independent first sub-regions and second sub-regions including blocks, the first sub-regions and the second sub-regions are symmetrically formed on both sides of the channel region CL relative to the channel region CL, and the first sub-regions and the second sub-regions form contact interfaces with the channel region CL. The shape formed by the first doping type region 106 can be substantially consistent with the shape of the gate G in the XZ cross section, such as Fig. 9 As shown, the shape of the gate G in the XZ cross section can be formed into a combination of one or more shapes including a block (as shown in (a)), a ring (as shown in (c)-(e)), a circular ring (as shown in (e)), an oblate ring (as shown in (d)), a U-shape (as shown in (b)), etc., and can also form a gate G including an independent first block and a second block, that is, a dual-gate transistor, as shown in Fig. 9 Preferably, the shape of the gate G in the XZ section is preferably formed into a flat circular ring (as shown in (d)), which can ensure that the channel can be fully depleted when the transistor is turned on, enhance the control ability of the gate over the channel, and at the same time, the flat ring area is smaller, ensuring a certain isolation distance from the surrounding area.

[0050] In a preferred embodiment, the first doping type region 106 is preferably formed by self-aligned implantation of the vertical transfer transistor Tx, so as to facilitate compatibility with the process of the CMOS image sensor and simplify the manufacturing process. Figure 4 As shown, it is a cross-sectional example of an embodiment of the memory disclosed in the present invention, wherein the first doping type region 106 is formed based on the self-aligned injection of the vertical transfer transistor Tx. Two separate regions can be seen in the XY cross section, but the first doping type region 106 in the XZ cross section can be formed into doping regions including annular, oblate, U-shaped, etc. based on the self-aligned injection of the vertical transfer transistor Tx, and can also form independent first sub-regions and second sub-regions including blocks. Specifically, the self-aligned ion injection of the transfer transistor can be performed after the transfer transistor shape Tx is engraved and before the gate polysilicon material G is filled, and the heavily doped first doping type region 106 is formed based on the self-aligned doping injection of the transfer transistor shape Tx.

[0051] In a preferred embodiment, when the heavily doped first doping type region 106 is formed based on the self-aligned implantation of the vertical transfer transistor Tx, in order to further reduce the threshold voltage, thereby further reducing the operating voltage, which is beneficial to reducing power consumption, a heavily doped second doping type sub-region 112 may be formed at the side interface of the channel region CL and the upper interface of the first doping type region 106, such as Figure 5 As shown. The cross-sectional width of the second doping type sub-region 112 (cross-sectional width, specifically refers to the width of one side of the parts located on both sides of the channel region CL in the X direction, and the part located on the upper interface of the first doping type region 106 is the width in the Y direction) is smaller than the width of the channel region CL, and one end of the second doping type sub-region 112 is adjacent to the second lightly doped region 111 to form an interface, and the other end is adjacent to the first doping type region 106 to form an interface. Figure 5 As shown, the second doping type sub-region 112 forms a positive and negative “L” shape in the XY cross section, and the bottom side of the “L” forms a contact interface with the upper surface of the first doping type region 106 .

[0052] In any embodiment of the present disclosure, the first doping type may include P type or N type, and the second doping type may include N type or P type. Specifically, when the first doping type is P type, the second doping type includes N type; when the first doping type is N type, the second doping type is P type. The first lightly doped region may be N type lightly doped or P type lightly doped.

[0053] Take the N-type tunneling transistor as an example to introduce it in detail. Figure 8As shown, in the process, the drain terminal D is made together with the floating diffusion area FD of the pixel area of ​​the CMOS image sensor to include a heavily doped N+ type area, the control source terminal S is a heavily doped P+ area, the second lightly doped type area 111 is a lightly doped P- area, the channel area CL of the transfer transistor is an N- (N-type lightly doped) area (or an intrinsic doping, or a P-- area (P-- refers to a P-type lightly doped area with a lower doping concentration than the second lightly doped type area 111 is a P- area), which can be selected according to the required threshold voltage), and the gate G of the vertical transfer transistor Tx is made together with the gate of the pixel area transistor into an N-type doped gate G, thereby forming an N-type tunneling transistor. During the read and write operations, when the gate G is positively charged, the channel region CL is N-type, and the drain terminal D is charged with high voltage (write 1). The N-type of the channel region CL and the P+ type of the source terminal S form a reverse biased PN junction, which controls the carrier concentration of the P+ region of the source terminal S and the N-region of the channel region CL, so that the probability of band-to-band tunneling at the interface of the first doping type region 106 (or the source terminal S) and the channel region CL increases. Since the tunneling transistor does not rely on carrier thermal diffusion for charge transport, the subthreshold swing of the vertical transfer transistor Tx can break through the thermodynamic limit. A higher on-state current is achieved under lower operating voltage conditions, and the writing (writing 1) speed is faster. On the other hand, when the drain terminal D is charged with low voltage (write 0), the N-type of the channel region CL and the P+ type of the source terminal S form a forward biased PN junction. The forward biased PN junction can use the entire channel cross section to transfer charge. The transmission current cross section in this state is significantly larger than the corresponding on state of the conventional transfer transistor. Compared with the traditional field effect transistor, writing "0" relies on the channel inversion layer, the inversion layer is only formed on the channel surface, the cross-sectional area is small, and the channel resistance is large. Under the same conditions, the tunneling transistor disclosed in the present invention has better writing performance. When turned off, the tunneling transistor disclosed in the present invention is depleted under the action of the gate work function due to the low doping concentration of the channel region CL, and the long and narrow depletion channel presents a large resistance, thereby suppressing the leakage of charge in the capacitor to the drain terminal D, and sufficient memory time can be guaranteed without the need for a negative operating voltage. Therefore, the memory disclosed in the present invention can reduce the power consumption of the memory while realizing high-speed storage of multi-value memory. In addition, on this basis, a second lightly doped region 111 is added near the drain terminal, that is, a second lightly doped region 111 is set between the drain terminal and the channel region, and the concentration of the second lightly doped region 111 is greater than the concentration of the channel region CL and less than the doping concentration of the drain terminal. When turned on, band-to-band tunneling easily occurs at the interface between the source terminal S and the channel region CL. When turned off, due to the existence of the second lightly doped region 111, the resistance of the channel depletion region is larger, so that the turn-off current is lower, and a higher switching ratio can be achieved.

[0054] The present disclosure also provides a method for preparing the memory of any of the foregoing embodiments. The structure of the memory of the present disclosure is compatible with the existing CMOS image sensor process. It only needs to control the doping concentration of the source end and the etching depth of the vertical transfer transistor to form a tunneling transistor, and utilize the interface between the source end and the channel region to facilitate band-to-band tunneling to improve the performance of the memory.

[0055] The memory includes multiple storage units, each storage unit includes a charge storage area and a vertical transfer transistor located on the charge storage area, and its preparation method includes providing a substrate, preparing a charge storage area on the substrate, and preparing a vertical transfer transistor on the charge storage area; the process flow of the preparation method of the memory disclosed in the present invention is introduced below in combination with specific embodiments.

[0056] like Figure 6-1 As shown in the process (a), a semiconductor substrate 100 is provided. Any material containing silicon can be used as a material for making a semiconductor substrate, such as silicon, single crystal or polycrystalline silicon, amorphous silicon, carbon-doped silicon, and a combination thereof or a multilayer of two or more thereof. The semiconductor substrate 100 can also be germanium, germanium silicon, or silicon on an insulator. The provided substrate 100 includes a first sub-substrate 101 of a first doping type, a second sub-substrate 102 of a second doping type located on the first sub-substrate, and a third sub-substrate 103 of a first doping type located on the second sub-substrate. For example, the first sub-substrate 101 located at the bottom layer may include a P-type substrate, the second sub-substrate 102 in the middle may include an N-type region as a charge storage region (or a photodiode region), and the third sub-substrate 103 at the top may include a P-type epitaxial layer for use as a functional tube (such as a vertical transfer transistor, etc.) substrate. The steps of preparing a charge storage region Cs on the substrate 100 and preparing a vertical transfer transistor Tx on the charge storage region Cs are described in detail below.

[0057] The preparation of the charge storage region Cs on the substrate 100 includes the following steps: S1: etching the substrate 100 to form a plurality of first grooves 104; Figure 6-1 The vertical transfer transistor Tx prepared later is located in the area between the two adjacent first trenches 104 .

[0058] S2: forming a buffer layer and a first dielectric layer (the buffer layer and the dielectric layer are not shown) in the trench 104; the material of the dielectric layer may be silicon oxide.

[0059] S3: Filling the first polysilicon material 105 on the surface of the first dielectric layer, the remaining second sub-substrate (eg, N-type) region between adjacent first trenches 104 forms a lateral PN junction with the first polysilicon material 105 to serve as a charge storage region Cs; Figure 6-2Here, after etching the substrate 100 to form the isolation trench 104, a smaller portion of the substrate that has not been etched remains. When the isolation trench 104 is filled with a buffer layer, a dielectric layer, and polysilicon material, the remaining portion of the substrate is compensated by the P-type buffer layer, so the unetched portion of the substrate finally presents a P-type region with less doping (i.e., a P-type lightly doped region (P-)). Figure 8 shown.

[0060] The preparation of a vertical transfer transistor Tx on a charge storage region Cs comprises the following steps: S4: performing heavy doping implantation of the first doping type, with the implantation depth being lower than the bottom of the vertical transfer transistor, so as to form a source terminal S including a first doping type region 106; Figure 6-2 For example, a remote P-type heavy doping implant is performed, and the implantation depth is lower than the bottom of the vertical transfer transistor to form a block-shaped first doping type region 106 with a width larger than the width of the second doping type region 109 (the first doping type of this step can be doped by EPI growth, and it is also easy to form this Figure 6-2 The first doping type region 106 of the shape shown in the process (d) shown in the figure). The doping concentration of the first doping type (e.g., P-type) region 106 of the source terminal S and the etching depth of the vertical transistor Tx have certain requirements, which must meet the requirement that the energy band bending of the depletion region after the PN junction is reverse biased at the interface between the source terminal S and the channel region CL when the transistor is turned on is large enough, which is more conducive to the occurrence of band-to-band tunneling. For example, a semiconductor element with a narrower bandgap (e.g., Ge) can be implanted at the source terminal S to reduce the bandgap width on this side, thereby enhancing the probability of band-to-band tunneling (BTBT) and further improving the device switching ratio.

[0061] S5: etching the third sub-substrate 103 of the substrate 100 to form a plurality of second grooves 110; Figure 6-3 The process shown is (e).

[0062] S6: forming a second dielectric layer (not shown) in the second trench 110; S7: Filling the second polysilicon material 108 on the surface of the second dielectric layer; Figure 6-3 The process shown is (f).

[0063] S8: planarizing the second polysilicon material 108 remaining on the surface of the third sub-substrate 103 by chemical mechanical polishing; Figure 6-4 The process shown is (g).

[0064] S9: The drain end of the vertical transfer transistor Tx is heavily doped with the second doping type to form a second doping type region 109. The second doping type region 109 can be completed together with the second doping type doping injection of the floating diffusion region of the pixel region. Figure 6-4 The process shown (h).

[0065] S10: Etch the second polysilicon material 108 below the silicon surface using an etching process, such as Figure 6-4 The process (i) shown in the figure ensures that the gates G of multiple transfer transistors are separated from each other. On a plane perpendicular to the length direction of the channel CL, the gate G may include a circular ring, an oblate ring or a U-shaped formation on the side of the channel region, or the gate G may include a first sub-gate and a second sub-gate located on both sides of the channel CL to form a dual-gate transistor. Preferably, on a plane perpendicular to the length direction of the channel CL, the gate of the vertical transfer transistor is in a flat ring shape surrounding the channel region, so that the channel can be fully depleted when the transistor is turned on, and the control ability of the gate over the channel is enhanced. At the same time, the flat ring area is smaller, ensuring a certain isolation distance from the surrounding area.

[0066] In addition, the preparation method of the vertical transfer transistor Tx may further include a gate doping step, and the gate etching and gate doping of the vertical transfer transistor Tx may be performed together with the gate etching and doping of the pixel region to reduce the process steps. The preparation method may further include a step of doping the channel region, and the doping type of the channel region may include a light doping of the first doping type or the second doping type.

[0067] In a preferred embodiment, the steps of the process (d)-(e) can be replaced by steps including (d')-(e'), such as Figure 7 As shown, the third sub-substrate 103 is etched to form a trench 110 of the vertical transfer transistor. As shown in process (d'), the vertical transfer transistor 107 is self-aligned to perform a first doping type (e.g., P-type) doping injection to form a heavily doped first doping type region 106. In this way, the injection depth can be naturally lower than the bottom of the vertical transfer transistor to form the source terminal S of the vertical transfer transistor, which greatly simplifies the process and improves the injection accuracy. The first doping type region formed in this way can form a first doping type region including an annular region, or a first doping type region including a U-shaped region, or a first doping type region including an independently spaced first sub-region and a second sub-region. Further preferably, the first doping type region 106 can form a first doping type region including a flat annular region.

[0068] In a preferred embodiment, the method for preparing the vertical transfer transistor Tx may further include a step of setting a second lightly doped region 111, and controlling the doping concentration of the second lightly doped region 111 to be greater than the doping concentration of the channel region CL and less than the doping concentration of the second doping type region 109. The doping implantation involved in this step may be performed by well implantation after the trench 110 is formed as shown in the process (e) (or the processes (d') and (e')), and before the second polysilicon material 108 is filled.

[0069] In a preferred embodiment, the preparation method of the vertical transfer transistor Tx may further include an implantation step of a heavily doped second doping type sub-region 112, forming a heavily doped second doping type sub-region 112 on the side surface of the channel region CL and the upper surface of the first doping type region 106. The doping implantation involved in this step may be completed by well implantation and self-aligned implantation after the formation of the trench 110 as shown in the process (e) diagram (or the process (d'), (e') diagrams) and before the second polysilicon material 108 is filled.

[0070] In a preferred embodiment, the portion of the first polysilicon material 105 filled in the first trench 104 located in the vertical transfer transistor Tx will be etched back to a certain depth (not shown in the drawings) in a subsequent process. The etching depth can be slightly higher than the bottom of the vertical transfer transistor Tx, or slightly lower than the bottom of the vertical transfer transistor Tx. After etching back, a dielectric layer is filled for isolation.

[0071] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present invention. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and corrections to the present invention. Such modifications, improvements and corrections are suggested in the present invention, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present invention.

[0072] It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, as examples and not limitations, alternative configurations of the embodiments of the present invention may be considered consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.

Claims

1. A method for preparing a memory, wherein the memory comprises a plurality of memory cells, each of the memory cells comprises a charge storage region and a vertical transfer transistor located on the charge storage region, characterized in that: The preparation method comprises: Providing a substrate, preparing a charge storage region on the substrate, and preparing a vertical transfer transistor on the charge storage region; Wherein, by controlling the doping concentration of the source terminal, the drain terminal, and the channel region of the vertical transfer transistor, band-to-band tunneling is easily caused at the interface between the source terminal and the channel region.

2. The method according to claim 1, characterized in that: The source end of the vertical transfer transistor includes a heavily doped first doping type region, the drain end includes a heavily doped second doping type region, and the channel region includes an intrinsic doping region, or a first lightly doped region, wherein the first doping type is opposite to the second doping type.

3. The method according to claim 2, characterized in that After the vertical transfer transistor is etched, the first doping type region is formed by self-aligned implantation to form a first doping type region including a ring region, or to form a first doping type region including a U-shaped region, or to form a first doping type region including independently spaced first sub-regions and second sub-regions.

4. The method according to claim 2, characterized in that: The first doping type region is formed by well implantation.

5. The method according to claim 1, characterized in that On a plane perpendicular to the length direction of the channel, the gate of the vertical transfer transistor is in a flat ring shape surrounding the channel region.

6. The method according to claim 1, characterized in that On a plane perpendicular to the length direction of the channel, the gate includes a ring-shaped or U-shaped gate around the channel region, or the gate includes a first sub-gate and a second sub-gate located on both sides of the channel region.

7. The method according to claim 2, characterized in that A second lightly doped region is further included between the drain terminal and the channel region, and the doping type of the second lightly doped region is opposite to the doping type of the second doping type region.

8. The method according to claim 7, characterized in that A second doping type sub-region including heavy doping is further formed on the surface side of the channel region and the surface side of the first doping type region.

9. The method according to claim 8, characterized in that A cross-sectional width of the second doping type sub-region is smaller than a width of the channel region.

10. The method according to claim 8, characterized in that One end of the second doping type sub-region is adjacent to the second lightly doped region, and the other end is adjacent to the first doping type region.

11. The method according to claim 7, characterized in that The doping concentration of the second lightly doped region is greater than the doping concentration of the channel region.

12. The method according to claim 2, characterized in that: The depth of the second lightly doped region is smaller than the depth of the channel region.

13. The method according to claim 2, characterized in that The width of the first doping type region is greater than the width of the second doping type region.

14. The method according to any one of claims 1 to 13, characterized in that: The charge type of the charge storage region is the same as the doping type of the source terminal and opposite to the doping type of the drain terminal.

15. The method according to any one of claims 1 to 14, characterized in that: The substrate includes a first sub-substrate of a first doping type, a second sub-substrate of a second doping type located on the first sub-substrate, and a third sub-substrate of the first doping type located on the second sub-substrate.

16. The method according to claim 15, characterized in that Preparing a charge storage region on the substrate comprises the steps of: S1: etching the substrate to form a plurality of first grooves; S2: forming a first dielectric layer in the trench; S3: filling a first polysilicon material on the surface of the first dielectric layer, and forming a lateral PN junction with the first polysilicon material as the charge storage area through a portion of the second substrate region between the adjacent first trenches.

17. The method according to claim 15 or 16, characterized in that The process of preparing the vertical transfer transistor on the charge storage region comprises the following steps: S4: performing a first doping type heavy doping implantation, with the implantation depth being lower than the bottom of the vertical transfer transistor to form a source terminal of the vertical transfer transistor; S5: etching the third sub-substrate of the substrate to form a plurality of second grooves; S6: forming a second dielectric layer in the second trench; S7: Filling a second polysilicon material on the surface of the second dielectric layer.

18. The method according to claim 17, characterized in that The preparation of the vertical transfer transistor on the charge storage region further comprises the step of: heavily doping the drain end of the vertical transfer transistor with a second doping type.

19. The method according to claim 17, characterized in that The preparation of the vertical transfer transistor on the charge storage area includes the following steps: using chemical mechanical polishing to flatten the second polysilicon material remaining above the silicon surface; and then using an etching process to etch the second polysilicon material below the silicon surface, so that the gates of the multiple transfer transistors are separated from each other.

20. The method according to claim 19, characterized in that The process step of etching the second polysilicon material below the silicon surface is performed simultaneously with the step of etching back the transistors in the pixel area.

21. The method according to claim 17, characterized in that The step of preparing the vertical transfer transistor on the charge storage region includes: doping the gate of the vertical transfer transistor.

22. The method according to claim 21, characterized in that The process step of doping the gate of the vertical transfer transistor is performed synchronously with the process step of doping the gate of the transistor in the pixel area.

23. The method according to claim 17, characterized in that The vertical transfer transistor is located in a region between the two adjacent first trenches.

24. The method according to claim 16, characterized in that The preparation of the vertical transfer transistor on the charge storage region further includes the step of: doping the channel region, wherein the doping type includes a first doping type or a second doping type.

25. The method according to any one of claims 1 to 24, characterized in that The first doping type includes P type or N type, and the second doping type includes N type or P type.

26. A memory prepared according to the method according to any one of claims 1 to 25.

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