MIM capacitor structure and preparation method thereof

Abstract

This application provides a MIM capacitor structure and its fabrication method. In the fabrication method, a trench is first formed in a first insulating layer. Then, a second metal layer, a second insulating layer, a third metal layer, a third insulating layer, an Nth metal layer, an Nth insulating layer, and an N+1th metal layer are stacked in the trench, where N is an integer greater than or equal to 4. Next, a top dielectric layer is deposited on the N+1th metal layer at the top of the trench. Then, first to Nth conductive plugs are formed. Finally, the patterned metal layer on the top layer enables the parallel connection of multiple MIM capacitors at the bottom of the trench and within the trench, thereby forming a trench-type MIM capacitor structure with at least two parallel connections. Compared with traditional planar MIM capacitors, the MIM capacitor structure fabricated in this application is not only a trench-type capacitor structure but also a parallel capacitor structure, which can effectively improve the capacitance density per unit area.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, specifically to a MIM capacitor structure and its fabrication method. Background Technology

[0002] MIM (Metal-Insulator-Metal) capacitors, also known as plate capacitors, have precise capacitance values ​​that do not change with bias voltage. In semiconductor devices, MIM capacitor structures are typically formed by a lower metal layer, an insulating dielectric layer, and an upper metal layer.

[0003] Although MIM capacitors have precise capacitance values, their capacitance per unit area is small, approximately one-third that of MOM (Metal-Oxide-Metal) capacitors. Currently, semiconductor devices typically use single-layer planar MIM capacitor structures, but it is difficult to increase capacitance density in single-layer planar MIM capacitor structures by reducing the dielectric layer thickness. Summary of the Invention

[0004] This application provides a MIM capacitor structure and its fabrication method, which can solve the problem of low capacitance density in current MIM capacitor structures in semiconductor devices.

[0005] On one hand, embodiments of this application provide a method for fabricating a MIM capacitor structure, including:

[0006] A semiconductor structure is provided, wherein the top layer of the semiconductor structure is a first metal layer;

[0007] A first insulating layer is formed, which covers the first metal layer;

[0008] The first insulating layer is etched down to the surface of the first metal layer to form a trench;

[0009] A second metal layer is formed, which covers the sidewalls and bottom wall of the trench and the first insulating layer;

[0010] A second insulating layer is formed, which covers the second metal layer;

[0011] A third metal layer is formed, which covers the second insulating layer;

[0012] A third insulating layer is formed, which covers the third metal layer;

[0013] An Nth metal layer is formed, which covers the third insulating layer, wherein N is an integer greater than or equal to 4;

[0014] An Nth insulating layer is formed, the Nth insulating layer covering the Nth metal layer;

[0015] An N+1th metal layer is formed, which covers the Nth insulating layer and fills the remaining space of the trench;

[0016] Grinding removes the second metal layer to the (N+1)th metal layer and the second insulating layer to the Nth insulating layer that extend beyond the surface of the first insulating layer;

[0017] A top dielectric layer is formed, which covers the second metal layer to the (N+1)th metal layer and the first insulating layer to the Nth insulating layer;

[0018] A first conductive plug, a second conductive plug to an Nth conductive plug are formed. The first conductive plug penetrates the top dielectric layer and the first insulating layer and is connected to the first metal layer. The second conductive plug penetrates the top dielectric layer and is connected to the third metal layer. The Nth conductive plug penetrates the top dielectric layer and is connected to the N+1th metal layer.

[0019] A patterned metal layer is formed, which covers the first conductive plug, the second conductive plug to the Nth conductive plug respectively, to form at least two parallel MIM capacitor structures.

[0020] Optionally, in the method for fabricating the MIM capacitor structure, the material of the first metal layer and the material of the second metal layer are both copper.

[0021] Optionally, in the method for fabricating the MIM capacitor structure, the materials of the third metal layer, the Nth metal layer, and the N+1th metal layer are all titanium nitride.

[0022] Optionally, in the method for fabricating the MIM capacitor structure, the patterned metal layer is made of aluminum.

[0023] Optionally, in the method for preparing the MIM capacitor structure, the material of the first insulating layer is silicon dioxide.

[0024] Optionally, in the method for fabricating the MIM capacitor structure, the materials of the second insulating layer, the third insulating layer, and the Nth insulating layer are all silicon nitride.

[0025] Optionally, in the method for fabricating the MIM capacitor structure, the thickness of the second insulating layer is 300 angstroms to 700 angstroms; the thickness of the third insulating layer is 300 angstroms to 700 angstroms; and the thickness of the Nth insulating layer is 300 angstroms to 700 angstroms.

[0026] Optionally, in the method for fabricating the MIM capacitor structure, the top dielectric layer includes: a stacked SiON layer and an undoped silicon glass layer, wherein the SiON layer covers a second metal layer to an N+1th metal layer and a first insulating layer to an Nth insulating layer, and the undoped silicon glass layer covers the SiON layer.

[0027] Optionally, in the method for preparing the MIM capacitor structure, a chemical mechanical polishing process is used to remove the second metal layer to the N+1th metal layer and the second insulating layer to the Nth insulating layer that extend beyond the surface of the first insulating layer.

[0028] On the other hand, embodiments of this application also provide a MIM capacitor structure, including:

[0029] A semiconductor structure, wherein the top layer of the semiconductor structure is a first metal layer;

[0030] A first insulating layer, the first insulating layer covering the first metal layer;

[0031] A trench located in the first insulating layer and exposing the bottom of the first metal layer;

[0032] A second metal layer covers the sidewalls and bottom wall of the trench;

[0033] A second insulating layer, which covers the second metal layer;

[0034] A third metal layer, the third metal layer covering the second insulating layer;

[0035] A third insulating layer, the third insulating layer covering the third metal layer;

[0036] The Nth metal layer covers the third insulating layer, wherein N is an integer greater than or equal to 4;

[0037] The Nth insulating layer covers the Nth metal layer;

[0038] The (N+1)th metal layer covers the Nth insulating layer and fills the remaining space of the trench;

[0039] A top dielectric layer, which covers the second metal layer to the (N+1)th metal layer and the first insulating layer to the Nth insulating layer;

[0040] The first conductive plug, the second conductive plug to the Nth conductive plug, wherein the first conductive plug penetrates the top dielectric layer and the first insulating layer and is connected to the first metal layer, the second conductive plug penetrates the top dielectric layer and is connected to the third metal layer, and the Nth conductive plug penetrates the top dielectric layer and is connected to the N+1th metal layer;

[0041] A patterned metal layer covers the first conductive plug, the second conductive plug to the Nth conductive plug, respectively, to form at least two parallel MIM capacitor structures.

[0042] The technical solution of this application has at least the following advantages:

[0043] In the method for fabricating the MIM capacitor structure provided in this application, a trench is first formed in the first insulating layer. Then, a second metal layer, a second insulating layer, a third metal layer, a third insulating layer, an Nth metal layer, an Nth insulating layer, and an N+1th metal layer are stacked in the trench, where N is an integer greater than or equal to 4. Next, a top dielectric layer is deposited on the N+1th metal layer at the top of the trench. Then, first to Nth conductive plugs are formed. Finally, the patterned metal layer on the top layer enables the parallel connection of multiple MIM capacitors at the bottom of the trench and in the trench, thereby forming a trench-type MIM capacitor structure with at least two parallel connections. Compared with traditional planar capacitors, the MIM capacitor structure prepared in this application is not only a trench-type capacitor structure but also a parallel capacitor structure, which can effectively improve the capacitance density per unit area. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0045] Figure 1 This is a flowchart of the method for preparing the MIM capacitor structure according to an embodiment of the present invention;

[0046] Figures 2-9 This is a schematic diagram of the semiconductor structure in each process step of the fabrication of the MIM capacitor structure according to an embodiment of the present invention;

[0047] The reference numerals in the attached figures are explained as follows:

[0048] 10 - Semiconductor structure; 21 - First metal layer; 22 - Second metal layer; 23 - Third metal layer; 24 - Fourth metal layer; 25 - Fifth metal layer; 31 - First insulating layer; 32 - Second insulating layer; 33 - Third insulating layer; 34 - Fourth insulating layer; 40 - Trench; 50 - Top dielectric layer; 61 - First conductive plug; 62 - Second conductive plug; 63 - Third conductive plug; 64 - Fourth conductive plug; 70 - Patterned metal layer. Detailed Implementation

[0049] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0051] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0052] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0053] This application provides a method for fabricating a MIM capacitor structure, referencing... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a MIM capacitor structure according to an embodiment of the present invention. The method for fabricating the MIM capacitor structure includes:

[0054] First, perform step S1: Refer to Figure 2 , Figure 2 This is a schematic diagram of the semiconductor structure after trench formation according to an embodiment of this application. A semiconductor structure 10 is provided, wherein the top layer of the semiconductor structure 10 is a first metal layer 21.

[0055] In this embodiment, the first metal layer 21 is made of copper.

[0056] Then, proceed to step S2: Continue to refer to Figure 2 A first insulating layer 31 is formed, which covers the first metal layer 21.

[0057] In this embodiment, the first insulating layer 31 is made of silicon dioxide.

[0058] Next, proceed to step S3: Continue to refer to Figure 2 The first insulating layer 31 is etched to the surface of the first metal layer 21 to form a trench 40.

[0059] Further, proceed to step S4: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the formation of the second metal layer according to an embodiment of this application. The second metal layer 22 is formed, and the second metal layer 22 covers the sidewalls and bottom wall of the trench 40 and the first insulating layer 31.

[0060] In this embodiment, the material of the second metal layer 22 is copper.

[0061] Next, proceed to step S5: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the formation of the fourth insulating layer in an embodiment of this application. A second insulating layer 32 is formed, and the second insulating layer 32 covers the second metal layer 22.

[0062] In this embodiment, the second insulating layer 32 is made of silicon nitride.

[0063] Preferably, the thickness of the second insulating layer 32 is 300 angstroms to 700 angstroms.

[0064] Further, proceed to step S6: Continue to refer to Figure 4 A third metal layer 23 is formed, which covers the second insulating layer 32.

[0065] In this embodiment, the third metal layer 23 is made of titanium nitride.

[0066] Next, proceed to step S7: Continue to refer to Figure 4 A third insulating layer 33 is formed, which covers the third metal layer 23.

[0067] In this embodiment, the third insulating layer 33 is made of silicon nitride.

[0068] Preferably, the thickness of the third insulating layer 33 is 300 angstroms to 700 angstroms.

[0069] Further, proceed to step S8: Continue to refer to... Figure 4 The Nth metal layer is formed, which covers the third insulating layer, wherein N is an integer greater than or equal to 4.

[0070] In this embodiment, taking N as 4 as an example, a fourth metal layer 24 is formed, which covers the third insulating layer 33.

[0071] In this embodiment, the fourth metal layer 24 is made of titanium nitride.

[0072] Next, proceed to step S9: Continue to refer to Figure 4 A fourth insulating layer 34 is formed, which covers the fourth metal layer 24.

[0073] In this embodiment, the fourth insulating layer 34 is made of silicon nitride.

[0074] Preferably, the thickness of the fourth insulating layer 34 is 300 angstroms to 700 angstroms.

[0075] Further, proceed to step S10: Refer to Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the fifth metal layer according to an embodiment of this application. The fifth metal layer 25 is formed, which covers the fourth insulating layer 34 and fills the remaining space of the trench 40.

[0076] In this embodiment, the fifth metal layer 25 is made of titanium nitride.

[0077] Next, proceed to step S11: (Refer to...) Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the second to fifth metal layers and the second to fourth insulating layers beyond the surface of the first insulating layer are removed by grinding according to an embodiment of this application. The second to fifth metal layers 22 to 25 and the second to fourth insulating layers 32 to 34 beyond the surface of the first insulating layer 31 are removed by grinding.

[0078] Preferably, a chemical mechanical polishing process is used to remove the second metal layer 22 to the fifth metal layer 25, as well as the second insulating layer 32 to the fourth insulating layer 34, which extend beyond the surface of the first insulating layer 31.

[0079] Further, proceed to step S12: Refer to Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the formation of the top dielectric layer in an embodiment of this application. The top dielectric layer 50 is formed, which covers the second metal layer 22 to the fifth metal layer 25, and the second insulating layer 32 to the fourth insulating layer 34.

[0080] Preferably, the top dielectric layer 50 includes: a stacked SiON layer and an undoped silicon glass layer (USG film), the SiON layer covering a second metal layer to an N+1th metal layer and a first insulating layer to an Nth insulating layer, and the undoped silicon glass layer covering the SiON layer.

[0081] Next, proceed to step S13: (Refer to...) Figure 8 , Figure 8 This is a schematic diagram of the semiconductor structure after the formation of the first conductive plug, the second conductive plug, and the fourth conductive plug according to an embodiment of this application. The first conductive plug 61, the second conductive plug 62, the third conductive plug 63, and the fourth conductive plug 64 are formed. The first conductive plug 61 penetrates the top dielectric layer 50 and the first insulating layer 31 and is connected to the first metal layer 21. The second conductive plug 62 penetrates the top dielectric layer 50 and is connected to the third metal layer 23. The third conductive plug 63 penetrates the top dielectric layer 50 and is connected to the fourth metal layer 24. The fourth conductive plug 64 penetrates the top dielectric layer 50 and is connected to the fifth metal layer 25.

[0082] Finally, perform step S14: (Refer to...) Figure 9 , Figure 9 This is a schematic diagram of the semiconductor structure after the formation of a patterned metal layer according to an embodiment of this application. A patterned metal layer 70 is formed, which covers the first conductive plug 61, the second conductive plug 62, the third conductive plug 63, and the fourth conductive plug 64 respectively. The first conductive plug 61, the second conductive plug 62, the third conductive plug 63, and the fourth conductive plug 64 after the formation of the patterned metal layer 70 are not connected to each other.

[0083] In this embodiment, N=4 is used as an example. Therefore, the first metal layer 21, the second metal layer 22, the second insulating layer 32 and the third metal layer 23 constitute a MIM capacitor; the fourth metal layer 24, the fourth insulating layer 34 and the fifth metal layer 25 constitute a MIM capacitor.

[0084] The two MIM capacitors are connected in parallel through a patterned metal layer 70, thereby forming a two-way parallel MIM capacitor structure.

[0085] In other embodiments, when N is 6, three MIM capacitors can be obtained: the first metal layer 21 / the second metal layer 22, the second insulating layer 32, and the third metal layer 23 constitute one MIM capacitor; the fourth metal layer 24, the fourth insulating layer 34, and the fifth metal layer 25 constitute one MIM capacitor; and the sixth metal layer, the sixth insulating layer, and the seventh metal layer constitute one MIM capacitor. The three MIM capacitors can be connected in parallel using the patterned metal layer 70, thereby forming a three-way parallel trench-type MIM capacitor structure. In summary, in the MIM capacitor structure provided in this application, N is greater than or equal to 4 and is a multiple of 2. Through the patterned metal layer 70 and the first to Nth conductive plugs, an N / 2-way parallel trench-type MIM capacitor structure is formed.

[0086] In this application, the actual value of N is selected according to the actual capacitance density requirement, thereby designing the lateral opening size of the trench 40 to deposit the second metal layer, the second insulating layer, the third metal layer, the third insulating layer, ..., the Nth metal layer, the Nth insulating layer and the N+1th metal layer in the trench 40.

[0087] In this embodiment, the patterned metal layer 70 is made of aluminum.

[0088] In this application, a trench is first formed in the first insulating layer. Then, a second metal layer, a second insulating layer, a third metal layer, a third insulating layer, an Nth metal layer, an Nth insulating layer, and an N+1th metal layer are stacked in the trench, where N is an integer greater than or equal to 4. Next, a top dielectric layer is deposited on the N+1th metal layer at the top of the trench. Then, first to Nth conductive plugs are formed. Finally, the patterned metal layer on the top layer enables the parallel connection of multiple MIM capacitors at the bottom of the trench and in the trench, thereby forming a trench-type MIM capacitor structure with at least two parallel connections. Compared with traditional planar capacitors, the MIM capacitor structure prepared in this application is not only a trench-type capacitor structure but also a parallel capacitor structure, which can effectively improve the capacitance density per unit area.

[0089] Based on the same inventive concept, this application also provides a MIM capacitor structure, see reference. Figure 9 The MIM capacitor structure includes:

[0090] A semiconductor structure 10, wherein the top layer of the semiconductor structure 10 is a first metal layer 21;

[0091] A first insulating layer 31 covers the first metal layer 21;

[0092] The trench 40 is located in the first insulating layer 31 and exposes the bottom of the first metal layer 21;

[0093] A second metal layer 22 covers the sidewalls and bottom wall of the trench 40;

[0094] The second insulating layer 32 covers the second metal layer 22;

[0095] A third metal layer 23 covers the second insulating layer 32;

[0096] A third insulating layer 33 covers the third metal layer 23;

[0097] A fourth metal layer 24 covers the third insulating layer 33;

[0098] A fourth insulating layer 34 covers the fourth metal layer 24;

[0099] A fifth metal layer 25, which covers the fourth insulating layer 34 and fills the remaining space of the trench 40;

[0100] A top dielectric layer 50 covers a second metal layer 22 to a fifth metal layer 25, and a first insulating layer 31 to a fourth insulating layer 34.

[0101] The first conductive plug 61, the second conductive plug 62 to the fourth conductive plug 64, wherein the first conductive plug 61 penetrates the top dielectric layer 50 and the first insulating layer 31 and is connected to the first metal layer 21; the second conductive plug 62 penetrates the top dielectric layer 50 and is connected to the third metal layer 23; the third conductive plug 63 penetrates the top dielectric layer 50 and is connected to the fourth metal layer 24; and the fourth conductive plug 64 penetrates the top dielectric layer 50 and is connected to the fifth metal layer 25.

[0102] A patterned metal layer 70 covers the first conductive plug 61, the second conductive plug 62 to the fourth conductive plug 64 respectively, to form a two-way parallel MIM capacitor structure.

[0103] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a MIM capacitor structure, characterized in that, include: A semiconductor structure is provided, wherein the top layer of the semiconductor structure is a first metal layer; A first insulating layer is formed, which covers the first metal layer; The first insulating layer is etched down to the surface of the first metal layer to form a trench; A second metal layer is formed, which covers the sidewalls and bottom wall of the trench and the first insulating layer; A second insulating layer is formed, which covers the second metal layer; A third metal layer is formed, which covers the second insulating layer; A third insulating layer is formed, which covers the third metal layer; An Nth metal layer is formed, which covers the third insulating layer, wherein N is an integer greater than or equal to 4; An Nth insulating layer is formed, the Nth insulating layer covering the Nth metal layer; An N+1th metal layer is formed, which covers the Nth insulating layer and fills the remaining space of the trench; Grinding removes the second metal layer to the (N+1)th metal layer and the second insulating layer to the Nth insulating layer that extend beyond the surface of the first insulating layer; A top dielectric layer is formed, which covers the second metal layer to the (N+1)th metal layer and the first insulating layer to the Nth insulating layer; A first conductive plug, a second conductive plug to an Nth conductive plug are formed. The first conductive plug penetrates the top dielectric layer and the first insulating layer and is connected to the first metal layer. The second conductive plug penetrates the top dielectric layer and is connected to the third metal layer. The Nth conductive plug penetrates the top dielectric layer and is connected to the N+1th metal layer. A patterned metal layer is formed, which covers the first conductive plug, the second conductive plug to the Nth conductive plug respectively, to form at least two parallel MIM capacitor structures.

2. The method for preparing the MIM capacitor structure according to claim 1, characterized in that, The first metal layer and the second metal layer are both made of copper.

3. The method for fabricating a MIM capacitor structure according to claim 1, characterized in that, The materials of the third metal layer, the Nth metal layer, and the N+1th metal layer are all titanium nitride.

4. The method for preparing the MIM capacitor structure according to claim 1, characterized in that, The patterned metal layer is made of aluminum.

5. The method for fabricating a MIM capacitor structure according to claim 1, characterized in that, The first insulating layer is made of silicon dioxide.

6. The method for preparing the MIM capacitor structure according to claim 1, characterized in that, The materials of the second insulating layer, the third insulating layer, and the Nth insulating layer are all silicon nitride.

7. The method for fabricating a MIM capacitor structure according to claim 1, characterized in that, The thickness of the second insulating layer is 300 angstroms to 700 angstroms; the thickness of the third insulating layer is 300 angstroms to 700 angstroms; and the thickness of the Nth insulating layer is 300 angstroms to 700 angstroms.

8. The method for preparing the MIM capacitor structure according to claim 1, characterized in that, The top dielectric layer comprises: a stacked SiON layer and an undoped silicon glass layer, wherein the SiON layer covers a second metal layer to an N+1th metal layer and a first insulating layer to an Nth insulating layer, and the undoped silicon glass layer covers the SiON layer.

9. The method for preparing the MIM capacitor structure according to claim 1, characterized in that, The second to N+1 metal layers and the second to N insulating layers that extend beyond the surface of the first insulating layer are removed by chemical mechanical polishing.

10. A MIM capacitor structure, characterized in that, include: A semiconductor structure, wherein the top layer of the semiconductor structure is a first metal layer; A first insulating layer, the first insulating layer covering the first metal layer; A trench located in the first insulating layer and exposing the bottom of the first metal layer; A second metal layer covers the sidewalls and bottom wall of the trench; A second insulating layer, which covers the second metal layer; A third metal layer, the third metal layer covering the second insulating layer; A third insulating layer, the third insulating layer covering the third metal layer; The Nth metal layer covers the third insulating layer, wherein N is an integer greater than or equal to 4; The Nth insulating layer covers the Nth metal layer; The (N+1)th metal layer covers the Nth insulating layer and fills the remaining space of the trench; A top dielectric layer, which covers the second metal layer to the (N+1)th metal layer and the first insulating layer to the Nth insulating layer; The first conductive plug, the second conductive plug to the Nth conductive plug, wherein the first conductive plug penetrates the top dielectric layer and the first insulating layer and is connected to the first metal layer, the second conductive plug penetrates the top dielectric layer and is connected to the third metal layer, and the Nth conductive plug penetrates the top dielectric layer and is connected to the N+1th metal layer; A patterned metal layer covers the first conductive plug, the second conductive plug to the Nth conductive plug, respectively, to form at least two parallel MIM capacitor structures.

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