Semiconductor structure for adjusting the withstand voltage of isolation ring and preparation method thereof

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and provides a semiconductor structure for adjusting the withstand voltage of an isolation ring and a preparation method thereof. The semiconductor structure comprises: a silicon substrate, the silicon substrate having a first conductivity type, and the silicon substrate having a front side and a back side that are arranged oppositely; an isolation ring, extending from the front side of the silicon substrate into the silicon substrate and having a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type; a gate structure, formed on the front side of the silicon substrate, and the orthographic projection of the gate structure on the silicon substrate falls into the isolation ring; a dielectric layer, the dielectric layer covers the front side of the silicon substrate and the gate structure; a deep trench isolation field plate, extending from the back side of the silicon substrate to the outer side wall of the isolation ring, the deep trench isolation field plate surrounds the outer side wall of the isolation ring and does not contact the isolation ring.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure for adjusting the withstand voltage of an isolation ring and a preparation method thereof. Background Art

[0002] In high voltage (drain voltage greater than 20V) or even ultra-high voltage (drain voltage greater than 400V) laterally diffused metal oxide semiconductor (LDMOS) devices, a long drift region is usually formed in the channel region to increase the breakdown voltage of the device. When voltage is applied to the drain, the drift region will be completely depleted and become a space charge region. This region will be in a high resistance state, thus playing a role in withstanding voltage.

[0003] At present, high-voltage LDMOS devices often use an isolation ring (Iso-ring) formed in a P-type substrate including a deep N-well to isolate different potentials and prevent latch-up effects. The breakdown leakage from the isolation ring to the P-type substrate will limit the internal withstand voltage of the device. As the requirements for isolation rings in high-voltage LDMOS devices become higher and higher, there are currently methods to increase the breakdown voltage from the isolation ring to the P-type substrate through front deep trench isolation (Deep Trench Isolation, DTI for short) and Silicon-On-Insulator (Silicon-On-Insulator, SOI for short), but it can only increase the withstand voltage between the isolation ring and the P-type substrate to a certain extent.

[0004] The impact ionization simulation results of the high-voltage LDMOS device without DTI are shown in Figure 2. Figure 1 As shown in Figure 2, the impact ionization simulation results of the high-voltage LDMOS device with front-side DTI are shown in Figure 2. Figure 2 From the simulation results, it can be seen that no matter whether there is a front DTI structure in the high-voltage LDMOS device, the probability of the breakdown leakage between the isolation ring and the P-type substrate occurring at the bottom tip of the isolation ring is very high. Summary of the invention

[0005] The purpose of the present invention is to provide a semiconductor structure for adjusting the withstand voltage of an isolation ring and a preparation method thereof, by introducing a back DTI type field plate in the device, the withstand voltage from the isolation ring to the P-type substrate is improved, and the limitation of the leakage from the isolation ring to the P-type substrate on the withstand voltage inside the device is reduced.

[0006] To achieve the above-mentioned purpose, the present invention provides a method for preparing a semiconductor structure for adjusting the withstand voltage of an isolation ring, comprising the following steps: forming a substrate, the substrate comprising a silicon substrate having a first conductivity type, the silicon substrate having a front side and a back side arranged opposite to each other, the substrate also comprising an isolation ring extending from the front side of the silicon substrate into the silicon substrate and having a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type; forming a gate structure and a dielectric layer on the front side of the silicon substrate, the orthographic projection of the gate structure on the silicon substrate falls into the isolation ring, and the dielectric layer covers the front side of the silicon substrate and the gate structure; and forming a deep trench isolation field plate extending to the outer side wall of the isolation ring on the back side of the silicon substrate, the deep trench isolation field plate surrounding the outer side wall of the isolation ring and not contacting the isolation ring.

[0007] In some embodiments, the step of forming a substrate specifically includes: providing the silicon substrate having the first conductivity type; forming a buried layer having the second conductivity type in the silicon substrate, an annular first deep well contacting the buried layer and having the second conductivity type, an annular second deep well contacting the side of the first deep well away from the buried layer and having the second conductivity type, an annular second well region contacting the side of the second deep well away from the first deep well and having the second conductivity type, and an annular second doped region contacting the side of the second well region away from the second deep well and having the second conductivity type, wherein the buried layer, the first deep well, the second deep well, the second well region and the second doped region form the isolation ring.

[0008] In some embodiments, the step of forming a substrate also includes: forming an annular first well region having the first conductivity type in the silicon substrate, an annular body region contacting the first well region and having the first conductivity type, and an annular first doped region contacting a side of the body region away from the first well region and having the first conductivity type, wherein the first well region, the body region and the first doped region are all located on the outer wall of the isolation ring and are not in contact with the isolation ring.

[0009] In some embodiments, a surface of the first doped region facing away from the body region is flush with the front surface of the silicon substrate, and a surface of the second doped region facing away from the second well region is flush with the front surface of the silicon substrate.

[0010] In some embodiments, the step of forming a gate structure and a dielectric layer on the front side of the silicon substrate further includes: forming a deep trench isolation mark extending into the silicon substrate on the front side of the silicon substrate, wherein a first distance between the bottom of the deep trench isolation mark and the back side of the silicon substrate is less than a second distance between the bottom of the isolation ring and the back side of the silicon substrate; the step of forming a gate structure and a dielectric layer on the front side of the silicon substrate specifically includes: forming a gate structure on the front side of the silicon substrate and forming a dielectric material layer covering the front side of the silicon substrate and the gate structure; flattening the dielectric material layer to a first thickness; performing a back side thinning process on the back side of the silicon substrate until the deep trench isolation mark is exposed; flattening the dielectric material layer to a target thickness to form the dielectric layer, wherein the target thickness is less than the first thickness; the step of forming a deep trench isolation field plate extending to the outer wall of the isolation ring on the back side of the silicon substrate further includes: determining an etching position of the deep trench isolation field plate on the back side of the silicon substrate according to the deep trench isolation mark.

[0011] In some embodiments, the step of forming a deep trench isolation field plate extending to the outer wall of the isolation ring on the back side of the silicon substrate specifically includes: etching a deep trench extending to the outer wall of the isolation ring on the back side of the silicon substrate, the deep trench surrounding the outer wall of the isolation ring and not contacting the isolation ring; forming an oxide layer on the inner wall of the deep trench; filling the surface of the oxide layer on the inner wall of the deep trench to form an isolation layer, the oxide layer and the isolation layer constitute the deep trench isolation field plate.

[0012] In some embodiments, the oxide layer is also formed on the back side of the silicon substrate, and the step of filling the surface of the oxide layer on the inner wall of the deep trench to form an isolation layer specifically includes: depositing to form an isolation material layer, the isolation material layer fills the deep trench and covers the surface of the oxide layer on the back side of the silicon substrate; using the oxide layer on the back side of the silicon substrate as a stop layer, flattening the isolation material layer, and the remaining isolation material layer in the deep trench forms the isolation layer.

[0013] In some embodiments, the method also includes: forming a back side routing on the back side of the silicon substrate that contacts the deep trench isolation field plate, and voltage can be applied to the deep trench isolation field plate through the back side routing to increase the withstand voltage of the isolation ring; forming an isolation passivation layer covering the back side of the silicon substrate and the back side routing, the isolation passivation layer having a through hole exposing the back side routing.

[0014] In some embodiments, the first conductivity type is P type, and the second conductivity type is N type; or, the first conductivity type is N type, and the second conductivity type is P type.

[0015] To achieve the above-mentioned purpose, the present invention also provides a semiconductor structure for adjusting the withstand voltage of an isolation ring, comprising a silicon substrate, the silicon substrate having a first conductivity type, the silicon substrate having a front side and a back side arranged opposite to each other; an isolation ring, extending from the front side of the silicon substrate into the silicon substrate and having a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type; a gate structure, formed on the front side of the silicon substrate, the orthographic projection of the gate structure on the silicon substrate falls into the isolation ring; a dielectric layer, the dielectric layer covering the front side of the silicon substrate and the gate structure; and a deep trench isolation field plate, extending from the back side of the silicon substrate to the outer side wall of the isolation ring, the deep trench isolation field plate surrounding the outer side wall of the isolation ring and not in contact with the isolation ring.

[0016] In some embodiments, the isolation ring includes: a buried layer formed in the silicon substrate and having the second conductivity type; an annular first deep well in contact with the buried layer and having the second conductivity type; an annular second deep well in contact with a side of the first deep well away from the buried layer and having the second conductivity type; an annular second well region in contact with a side of the second deep well away from the first deep well and having the second conductivity type; and an annular second doped region in contact with a side of the second well region away from the second deep well and having the second conductivity type.

[0017] In some embodiments, the semiconductor structure for adjusting the isolation ring withstand voltage also includes: a deep trench isolation mark, which runs from the front side of the silicon substrate to the back side of the silicon substrate, and the deep trench isolation mark is used to determine the etching position of the deep trench isolation field plate on the back side of the silicon substrate.

[0018] In some embodiments, the deep trench isolation field plate includes: an oxide layer formed on the inner wall of a deep trench extending from the back side of the silicon substrate to the outer wall of the isolation ring; an isolation layer filling the surface of the oxide layer on the inner wall of the deep trench, and the material of the isolation layer includes metal tungsten.

[0019] In some embodiments, the semiconductor structure for adjusting the withstand voltage of the isolation ring also includes: a back side routing formed on the back side of the silicon substrate and in contact with the deep trench isolation field plate, through which a voltage can be applied to the deep trench isolation field plate to increase the withstand voltage of the isolation ring; an isolation passivation layer covering the back side of the silicon substrate and the back side routing, the isolation passivation layer having a through hole exposing the back side routing.

[0020] In some embodiments, the backside wiring adopts a composite laminated structure of an adhesive layer and a metal layer, and the material of the adhesive layer is titanium or titanium nitride; the isolation passivation layer adopts a composite laminated structure of an undoped silicate glass layer and a silicon nitride layer.

[0021] The above technical solution, by adding a deep trench isolation field plate on the back side of the silicon substrate, weakens the electric lines between the negative charges of a part of the silicon substrate and the positive charges of the isolation ring, thereby reducing the electric field peak in the bottom tip area of ​​the isolation ring, alleviating the phenomenon of electric field concentration, and at the same time widening the depletion region, thereby improving the withstand voltage. The withstand voltage of the isolation ring can also be further improved by applying voltage to the deep trench isolation field plate through back wiring. By adding a deep trench isolation mark, the etching position of the deep trench isolation field plate can be determined according to the deep trench isolation mark on the back side of the silicon substrate, and the etching position of the deep trench isolation field plate can be accurately determined, so that the formed deep trench isolation field plate surrounds the outer side wall of the isolation ring and does not contact the isolation ring. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 It is a schematic diagram of the impact ionization simulation results of a high-voltage LDMOS device without DTI;

[0024] Figure 2 Schematic diagram of the impact ionization simulation results of a high-voltage LDMOS device with front-side DTI;

[0025] Figure 3 A flow chart of a method for preparing a semiconductor structure for adjusting the withstand voltage of an isolation ring provided in one embodiment of the present invention;

[0026] Figure 4 It is a schematic diagram of a device structure after forming a substrate according to an embodiment of the present invention;

[0027] Figure 5 It is a schematic diagram of a device structure after forming a gate structure and a dielectric layer according to an embodiment of the present invention;

[0028] Fig. 6A A schematic diagram of a device structure after forming a deep trench according to an embodiment of the present invention;

[0029] Figure 6B A schematic diagram of a device structure after an oxide layer is formed on the inner wall of a deep trench according to an embodiment of the present invention;

[0030] Figure 6C It is a schematic diagram of a device structure after forming an isolation material layer according to an embodiment of the present invention;

[0031] Fig.6DIt is a schematic diagram of a device structure after forming a deep trench isolation field plate according to an embodiment of the present invention;

[0032] Figure 7 It is a schematic diagram of the device structure after the backside wiring is formed according to an embodiment of the present invention;

[0033] Figure 8 It is a schematic diagram of the device structure after forming an isolation passivation layer according to an embodiment of the present invention;

[0034] Fig. 9 A schematic diagram of a device structure after forming a deep trench isolation mark according to another embodiment of the present invention;

[0035] Fig. 10A It is a schematic diagram of a device structure after forming a gate structure and a dielectric material layer according to another embodiment of the present invention;

[0036] Fig. 10B This is a schematic diagram of a device structure after the dielectric material layer is planarized according to another embodiment of the present invention;

[0037] Fig. 10C A schematic diagram of a device structure after a backside thinning process is performed according to another embodiment of the present invention;

[0038] Fig. 10D It is a schematic diagram of a device structure after a dielectric layer is formed according to another embodiment of the present invention;

[0039] Fig.11A It is a schematic diagram of a device structure after forming a deep trench according to another embodiment of the present invention;

[0040] Fig. 11B It is a schematic diagram of a device structure after an oxide layer is formed on the inner wall of a deep trench according to another embodiment of the present invention;

[0041] Fig. 11C It is a schematic diagram of a device structure after forming an isolation material layer according to another embodiment of the present invention;

[0042] Fig.11D It is a schematic diagram of a device structure after forming a deep trench isolation field plate according to another embodiment of the present invention;

[0043] Fig.12 It is a schematic diagram of the device structure after backside wiring is formed according to another embodiment of the present invention;

[0044] Fig.13 It is a schematic diagram of the device structure after forming an isolation passivation layer according to another embodiment of the present invention.

[0045] Description of reference numerals:

[0046] 40. Silicon substrate;

[0047] 401, positive;

[0048] 402, back;

[0049] 41. Isolation ring;

[0050] 411, buried layer;

[0051] 412. The First Deep Trap;

[0052] 413. The Second Deep Trap;

[0053] 414, second well region;

[0054] 415, a second doped region;

[0055] 421, first well region;

[0056] 422, body area;

[0057] 423, a first doped region;

[0058] 43. Isolation structure;

[0059] 51. Gate structure;

[0060] 52. Dielectric layer;

[0061] 520, dielectric material layer;

[0062] 61. Deep trench isolation field plate;

[0063] 600, deep groove;

[0064] 611, oxide layer;

[0065] 612, isolation layer;

[0066] 6120, insulating material layer;

[0067] 71. Back wiring;

[0068] 711, adhesive layer;

[0069] 712, metal layer;

[0070] 81. Isolation passivation layer;

[0071] 811. Undoped silicate glass layer;

[0072] 812, silicon nitride layer;

[0073] 800, through hole;

[0074] 91. Deep groove isolation mark. DETAILED DESCRIPTION

[0075] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0076] Please also read Figure 3~Figure 8 ,in, Figure 3 A flow chart of a method for preparing a semiconductor structure for adjusting the withstand voltage of an isolation ring provided in one embodiment of the present invention; Figure 4 It is a schematic diagram of a device structure after forming a substrate according to an embodiment of the present invention; Figure 5 It is a schematic diagram of a device structure after forming a gate structure and a dielectric layer according to an embodiment of the present invention; Fig. 6A A schematic diagram of a device structure after forming a deep trench according to an embodiment of the present invention; Figure 6B A schematic diagram of a device structure after an oxide layer is formed on the inner wall of a deep trench according to an embodiment of the present invention; Figure 6C It is a schematic diagram of a device structure after forming an isolation material layer according to an embodiment of the present invention; Fig.6D It is a schematic diagram of a device structure after forming a deep trench isolation field plate according to an embodiment of the present invention; Figure 7 It is a schematic diagram of the device structure after the backside wiring is formed according to an embodiment of the present invention; Figure 8 It is a schematic diagram of the device structure after forming an isolation passivation layer according to an embodiment of the present invention.

[0077] like Figure 3 As shown, the preparation method of the semiconductor structure for adjusting the withstand voltage of the isolation ring described in this embodiment includes the following steps: S1, forming a base, the base including a silicon substrate with a first conductivity type, the silicon substrate having a front side and a back side arranged oppositely, and the base also including an isolation ring extending from the front side of the silicon substrate into the silicon substrate and having a second conductivity type; S2, forming a gate structure and a dielectric layer on the front side of the silicon substrate, the orthographic projection of the gate structure on the silicon substrate falls into the isolation ring, and the dielectric layer covers the front side of the silicon substrate and the gate structure; and S3, forming a deep trench isolation field plate extending to the outer side wall of the isolation ring on the back side of the silicon substrate, the deep trench isolation field plate surrounds the outer side wall of the isolation ring and does not contact the isolation ring.

[0078] Please refer to step S1 and Figure 4, forming a substrate, the substrate comprising a silicon substrate 40 having a first conductivity type, the silicon substrate 40 having a front side 401 and a back side 402 arranged opposite to each other, and the substrate further comprising an isolation ring 41 extending from the front side 401 of the silicon substrate 40 into the silicon substrate 40 and having a second conductivity type. The first conductivity type is opposite to the second conductivity type. Specifically, the first conductivity type is P type and the second conductivity type is N type; or, the first conductivity type is N type and the second conductivity type is P type.

[0079] In this embodiment, the step of forming a substrate described in step S1 specifically includes: (1) providing the silicon substrate 40 having the first conductivity type; (2) forming a buried layer 411 having the second conductivity type in the silicon substrate 40, a first annular deep well 412 having the second conductivity type and contacting the buried layer 411, a second annular deep well 413 having the second conductivity type and contacting the first deep well 412 on a side away from the buried layer 411, a second annular well region 414 having the second conductivity type and contacting the second deep well 413 on a side away from the first deep well 412, and a second annular doped region 415 having the second conductivity type and contacting the second well region 414 on a side away from the second deep well 413. The buried layer 411, the first deep well 412, the second deep well 413, the second well region 414, and the second doped region 415 form the isolation ring 41. In this embodiment, the surface of the second doped region 415 away from the second well region 414 is flush with the front surface 401 of the silicon substrate 40.

[0080] The following is an example in which the first conductivity type is P type and the second conductivity type is N type. An N type buried layer 411 (NBL), a high voltage N type well (HNW, i.e., a first deep well 412), a deep N type well (DNW, i.e., a second deep well 413), an N well region (NWL, i.e., a second well region 414) and an N+ region (i.e., a second doped region 415) are formed in the P type silicon substrate 40. Among them, the HNW is used to adjust the concentration of the implanted ions and to play a connecting role in the isolation ring. For high voltage LDMOS devices, the breakdown leakage from the isolation ring 41 to the P type silicon substrate 40 will limit the internal withstand voltage of the device, so it is necessary to increase the withstand voltage between the isolation ring 41 and the P type silicon substrate 40.

[0081] In this embodiment, the step of forming a substrate described in step S1 further includes: forming an annular first well region 421 (for example, PWL) having the first conductivity type in the silicon substrate 40, an annular body region 422 (for example, PBD) having the first conductivity type in contact with the first well region 421, and an annular first doping region 423 (for example, P+) having the first conductivity type in contact with the side of the body region 422 away from the first well region 421. The first well region 421, the body region 422, and the first doping region 423 are all located on the outer side wall of the isolation ring 41 and are not in contact with the isolation ring 41. Further, the first doping region 423 is also isolated from the second doping region 415 by an isolation structure 43 (for example, a shallow trench isolation structure STI). In this embodiment, the surface of the first doping region 423 away from the body region 422 is flush with the front surface 401 of the silicon substrate 40.

[0082] In this embodiment, the components formed in the silicon substrate 40 serve as corresponding components constituting two parallel transistors (two gate structures GTAE will be formed later), and the two parallel transistors form a device high-voltage LDMOS device. In the figure, the isolation ring 41 is an N-type semiconductor, and the silicon substrate 40 is a P-type semiconductor. When the P-type semiconductor and the N-type semiconductor are in contact, a special area called a depletion area will be formed between them. The PN junction is formed by the close contact between the P-type semiconductor and the N-type semiconductor in the figure, and the bottom tip area of ​​the isolation ring 41 (i.e., the left and right end areas of the NBL) is the main junction position that is easy to break down.

[0083] Please refer to step S2 and Figure 5 A gate structure 51 and a dielectric layer 52 are formed on the front side 401 of the silicon substrate 40 , wherein the orthographic projection of the gate structure 51 on the silicon substrate 40 falls within the isolation ring 41 , and the dielectric layer 52 covers the front side 401 of the silicon substrate 40 and the gate structure 51 .

[0084] In this embodiment, two gate structures 51 are formed on the front side 401 of the silicon substrate 40 . The two gate structures 51 and corresponding components in the silicon substrate 40 constitute two parallel transistors. The two parallel transistors form a high-voltage LDMOS device.

[0085] Please refer to step S3 and Fig.6D A deep trench isolation field plate 61 extending to the outer side wall of the isolation ring 41 is formed on the back side 402 of the silicon substrate 40 . The deep trench isolation field plate 61 surrounds the outer side wall of the isolation ring 41 and does not contact the isolation ring 41 .

[0086] In this embodiment, the step of forming a deep trench isolation field plate 61 extending to the outer side wall of the isolation ring 41 on the back side 402 of the silicon substrate 40 described in step S3 specifically includes: (1) etching a deep trench 600 extending to the outer side wall of the isolation ring 41 on the back side 402 of the silicon substrate 40, wherein the deep trench 600 surrounds the outer side wall of the isolation ring 41 and does not contact the isolation ring, such as Fig. 6A (2) forming an oxide layer 611 on the inner wall of the deep trench 600, as shown in FIG. 6B ; (3) filling the surface of the oxide layer 611 on the inner wall of the deep trench 600 with an isolation layer 612, the oxide layer 611 and the isolation layer 612 forming the deep trench isolation field plate 61, as shown in FIG. Fig.6D In this embodiment, the material of the oxide layer 611 includes silicon oxide, and the material of the isolation layer 612 includes metal tungsten (W).

[0087] Specifically, in this embodiment, the oxide layer 611 is also formed on the back side 402 of the silicon substrate 40, and the step of filling the surface of the oxide layer 611 on the inner wall of the deep trench 600 with the isolation layer 612 specifically includes: (31) depositing an isolation material layer 6120, wherein the isolation material layer 6120 fills the deep trench 600 and covers the surface of the oxide layer 611 on the back side 402 of the silicon substrate 40, as shown in FIG. Figure 6C As shown; (32) the oxide layer 611 on the back side 402 of the silicon substrate 40 is used as a stop layer, the isolation material layer 6120 is planarized, and the remaining isolation material layer 6120 in the deep trench 600 forms the isolation layer 612, as shown Fig.6D The planarization can be achieved by using a chemical mechanical polishing (CMP) process.

[0088] The method for preparing a semiconductor structure for adjusting the withstand voltage of an isolation ring provided in this embodiment, by adding a deep trench isolation field plate 61 on the back side 402 of the silicon substrate 40, weakens the electric lines between the negative charge of a portion of the silicon substrate 40 (P-type depletion region) and the positive charge of the isolation ring 41 (N-type depletion region), thereby reducing the electric field peak value of the bottom tip region of the isolation ring 41 (i.e., the main junction position), and alleviating the phenomenon of electric field concentration; at the same time, the depletion region is widened (the deep trench isolation field plate 61 is equivalent to a negative charge, and the negative charge pushes away the majority carriers in the N-well in the isolation ring 41), thereby improving the withstand voltage.

[0089] Specifically, in this embodiment, the deep trench isolation field plate 61 extends to the buried layer 411 and the second deep well 413 (ie, between NBL and DNW) to fully reduce the electric field peak at the bottom tip region of the isolation ring 41 and improve the withstand voltage.

[0090] The withstand voltage of the isolation ring can also be further improved by applying a voltage to the deep trench isolation field plate. Specifically, the method further includes: S4, forming a back wiring in contact with the deep trench isolation field plate on the back side of the silicon substrate; and S5, forming an isolation passivation layer covering the back side of the silicon substrate and the back wiring, the isolation passivation layer having a through hole exposing the back wiring.

[0091] Please refer to step S4 and Figure 7 , a back wiring 71 in contact with the deep trench isolation field plate 61 is formed on the back side 402 of the silicon substrate 40. Specifically, a voltage can be applied to the deep trench isolation field plate 61 through the back wiring 71 to improve the withstand voltage of the isolation ring 41. In this embodiment, the back wiring 71 adopts a composite laminated structure of an adhesive layer 711 and a metal layer 712, and the material of the adhesive layer 711 is titanium or titanium nitride. A layer of adhesive layer 711 can also be formed on the side of the metal layer 712 away from the adhesive layer 711 to facilitate bonding with subsequent components. The back wiring 71 described in step S4 can be prepared in a manner similar to the top metal process.

[0092] Please refer to step S5 and Figure 8 , forming an isolation passivation layer 81 covering the back side 402 of the silicon substrate 40 and the back side wiring 71, and the isolation passivation layer 81 has a through hole 800 exposing the back side wiring 71. In this embodiment, the isolation passivation layer 81 adopts a composite laminated structure of an undoped silicate glass layer 811 and a silicon nitride layer 812. Specifically, the undoped silicate glass layer 811 covers the back side 402 of the silicon substrate 40 and the back side wiring 71, and the undoped silicate glass layer 811 has the through hole 800 exposing the back side wiring 71. Undoped silicate glass (USG) can be used for isolation between two transistors. The silicon nitride layer 812 covers the surface of the undoped silicate glass layer 811 away from the back side 402 of the silicon substrate 40. Silicon nitride (SiN) has high stress, high hardness, and good corrosion resistance, and can protect the internal circuit of the device.

[0093] By exposing the through hole 800 of the back wiring 71, a voltage can be applied to the deep trench isolation field plate 61 to further improve the withstand voltage of the isolation ring 41. Within a certain range, the higher the pressure, the higher the withstand voltage; if the voltage is increased beyond a certain range, the main junction withstand voltage will not be greatly affected. Positive or negative voltage can be applied to the deep trench isolation field plate 61, depending on the device situation.

[0094] In order to determine the etching position of the deep trench isolation field plate so that the deep trench isolation field plate surrounds the outer side wall of the isolation ring and does not contact the isolation ring, another embodiment of the present invention provides a deep trench isolation mark to determine the etching position of the deep trench isolation field plate on the back side of the silicon substrate according to the deep trench isolation mark. In this embodiment, the silicon substrate 40 has a relatively thick initial thickness so that after the back side thinning process is performed, the silicon substrate 40 still has enough thickness for preparing the deep trench isolation field plate 61.

[0095] Please also read Figure 9~Figure 13 ,in, Fig. 9 A schematic diagram of a device structure after forming a deep trench isolation mark according to another embodiment of the present invention; Fig. 10A It is a schematic diagram of a device structure after forming a gate structure and a dielectric material layer according to another embodiment of the present invention; Fig. 10B This is a schematic diagram of a device structure after the dielectric material layer is planarized according to another embodiment of the present invention; Fig. 10C A schematic diagram of a device structure after a backside thinning process is performed according to another embodiment of the present invention; Fig. 10D It is a schematic diagram of a device structure after a dielectric layer is formed according to another embodiment of the present invention; Fig.11A It is a schematic diagram of a device structure after forming a deep trench according to another embodiment of the present invention; Fig. 11B It is a schematic diagram of a device structure after an oxide layer is formed on the inner wall of a deep trench according to another embodiment of the present invention; Fig. 11C It is a schematic diagram of a device structure after forming an isolation material layer according to another embodiment of the present invention; Fig.11D It is a schematic diagram of a device structure after forming a deep trench isolation field plate according to another embodiment of the present invention; Fig.12 It is a schematic diagram of the device structure after backside wiring is formed according to another embodiment of the present invention; Fig.13 It is a schematic diagram of the device structure after forming an isolation passivation layer according to another embodiment of the present invention.

[0096] Specifically, before the step of forming the gate structure 51 and the dielectric layer 52 on the front side 401 of the silicon substrate 40 described in step S2, the step further includes: forming a deep trench isolation mark 91 extending into the silicon substrate 40 on the front side 401 of the silicon substrate 40, wherein a first distance H1 between the bottom of the deep trench isolation mark 91 and the back side 402 of the silicon substrate 40 is smaller than a second distance H2 between the bottom of the isolation ring 41 and the back side 402 of the silicon substrate 40, so that when a back side thinning process is subsequently performed to expose the deep trench isolation mark 91, the isolation ring 41 will not be exposed. Fig. 9As shown. The silicon substrate 40 can be formed by epitaxial growth. In order not to affect the epitaxial growth of the silicon substrate 40, after the epitaxial growth of the silicon substrate 40 is completed, the deep trench isolation mark 91 is etched and filled on the front side 401 of the silicon substrate 40. The deep trench isolation mark 91 can be prepared by using the existing through-silicon via (TSV) technology. TSV technology can reach a depth of 250um.

[0097] Specifically, the step of forming the gate structure 51 and the dielectric layer 52 on the front surface 401 of the silicon substrate 40 in step S2 includes: (1) forming the gate structure 51 on the front surface 401 of the silicon substrate 40 and forming a dielectric material layer 520 covering the front surface 401 of the silicon substrate 40 and the gate structure 51, such as Fig. 10A As shown; (2) planarizing the dielectric material layer 520 to a first thickness W1, as shown Fig. 10B (3) performing a backside thinning process on the back side 402 of the silicon substrate 40 until the deep trench isolation mark 91 is exposed, as shown in FIG. Fig. 10C (4) planarizing the dielectric material layer 520 to a target thickness W2 to form the dielectric layer 52, wherein the target thickness W2 is less than the first thickness W1, as shown in FIG. Fig. 10D Specifically, the planarization may be achieved by using a chemical mechanical polishing (CMP) process; the material of the dielectric layer 52 may be an interlayer dielectric (ILD).

[0098] That is, in this embodiment, after the dielectric material layer 520 is deposited (ILD DEP), two planarization processes are performed; after the first planarization process (ILD CMP), a backside thinning process is performed to thin the backside 402 of the silicon substrate 40 until the deep trench isolation mark 91 is exposed, and then a second planarization process (ILD CMP) is performed to obtain a dielectric layer 52 with a flat surface. Specifically, the first ILD CMP leaves a margin (the difference between the first thickness W1 and the target thickness W2 is the margin), which can offset the consumption of the ILD by the backside thinning process and prevent the surface of the ILD from being contaminated or scratched by the backside thinning process; after the backside thinning process is completed, CMP is performed to remove the margin, thereby obtaining an ILD with a flat surface.

[0099] Specifically, before the step of forming a deep trench isolation field plate 61 extending to the outer wall of the isolation ring 41 on the back side 402 of the silicon substrate 40 described in step S3, it also includes: determining the etching position of the deep trench isolation field plate 61 on the back side 402 of the silicon substrate 40 according to the deep trench isolation mark 91.

[0100] Specifically, the step of forming a deep trench isolation field plate 61 extending to the outer side wall of the isolation ring 41 on the back side 402 of the silicon substrate 40 described in step S3 specifically includes: (1) etching a deep trench 600 extending to the outer side wall of the isolation ring 41 on the back side 402 of the silicon substrate 40 according to the etching position determined by the deep trench isolation mark 91, wherein the deep trench 600 surrounds the outer side wall of the isolation ring 41 and does not contact the isolation ring, such as Fig.11A (2) forming an oxide layer 611 on the inner wall of the deep trench 600, and the oxide layer 611 is also formed on the back side 402 of the silicon substrate 40, as shown in FIG. Fig. 11B (3) depositing an isolation material layer 6120, wherein the isolation material layer 6120 fills the deep trench 600 and covers the surface of the oxide layer 611 on the back side 402 of the silicon substrate 40, as shown in FIG. Fig. 11C (4) using the oxide layer 611 on the back side 402 of the silicon substrate 40 as a stop layer, planarizing the isolation material layer 6120, and the remaining isolation material layer 6120 in the deep trench 600 forms the isolation layer 612, as shown in FIG. Fig.11D The planarization can be achieved by using a chemical mechanical polishing (CMP) process.

[0101] exist Fig.11D On the basis of the above, a backside wiring 71 in contact with the deep trench isolation field plate 61 is formed on the backside 402 of the silicon substrate 40, such as Fig.12 As shown. Fig.12 On the basis of, forming an isolation passivation layer 81 covering the back side 402 of the silicon substrate 40 and the back side wiring 71, the isolation passivation layer 81 has a through hole 800 exposing the back side wiring 71, such as Fig.13 shown.

[0102] Based on the same inventive concept, the present invention further provides a semiconductor structure for adjusting the withstand voltage of an isolation ring, which can be prepared by the method for preparing the semiconductor structure for adjusting the withstand voltage of an isolation ring of the present invention.

[0103] See also Figure 4~Figure 8 A semiconductor structure for adjusting the withstand voltage of an isolation ring provided in an embodiment of the present invention includes: a silicon substrate 40 , an isolation ring 41 , a gate structure 51 , a dielectric layer 52 , and a deep trench isolation field plate 61 .

[0104] Specifically, the silicon substrate 40 has a first conductivity type, and the silicon substrate 40 has a front side 401 and a back side 402 that are arranged opposite to each other. The isolation ring 41 extends from the front side 401 of the silicon substrate 40 to the inside of the silicon substrate 40 and has a second conductivity type; the gate structure 51 is formed on the front side 401 of the silicon substrate 40, and the orthographic projection of the gate structure 51 on the silicon substrate 40 falls into the isolation ring 41; the dielectric layer 52 covers the front side 401 of the silicon substrate 40 and the gate structure 51; the deep trench isolation field plate 61 extends from the back side 402 of the silicon substrate 40 to the outer side wall of the isolation ring 41, and the deep trench isolation field plate 61 surrounds the outer side wall of the isolation ring 41 and does not contact the isolation ring 41.

[0105] In this embodiment, the isolation ring 41 includes: a buried layer 411 formed in the silicon substrate 40 and having the second conductivity type, an annular first deep well 412 contacting the buried layer 411 and having the second conductivity type, an annular second deep well 413 contacting a side of the first deep well 412 away from the buried layer 411 and having the second conductivity type, an annular second well region 414 contacting a side of the second deep well 413 away from the first deep well 412 and having the second conductivity type, and an annular second doped region 415 contacting a side of the second well region 414 away from the second deep well 413 and having the second conductivity type. In this embodiment, the surface of the second doped region 415 away from the second well region 414 is flush with the front surface 401 of the silicon substrate 40.

[0106] In this embodiment, the deep trench isolation field plate 61 includes: an oxide layer 611 formed on the inner wall of the deep trench 600 extending from the back surface 402 of the silicon substrate 40 to the outer side wall of the isolation ring 41; and an isolation layer 612 filled on the surface of the oxide layer 611 on the inner wall of the deep trench 600. In this embodiment, the material of the oxide layer 611 includes silicon oxide, and the material of the isolation layer 612 includes metal tungsten (W).

[0107] In this embodiment, the deep trench isolation field plate 61 extends to the buried layer 411 and the second deep well 413 (ie, between NBL and DNW) to fully reduce the electric field peak at the bottom tip region of the isolation ring 41 and improve the withstand voltage.

[0108] The withstand voltage of the isolation ring can also be further improved by applying a voltage to the deep trench isolation field plate. Specifically, the semiconductor structure for adjusting the withstand voltage of the isolation ring also includes: a back wiring 71, formed on the back side 402 of the silicon substrate 40 and in contact with the deep trench isolation field plate 61, through which a voltage can be applied to the deep trench isolation field plate 61 to improve the withstand voltage of the isolation ring 41; an isolation passivation layer 81, covering the back side 402 of the silicon substrate 40 and the back wiring 71, and the isolation passivation layer 81 has a through hole 800 exposing the back wiring 71.

[0109] In this embodiment, the backside wiring 71 adopts a composite laminated structure of an adhesive layer 711 and a metal layer 712, and the material of the adhesive layer 711 is titanium or titanium nitride. The isolation passivation layer 81 adopts a composite laminated structure of an undoped silicate glass layer 811 and a silicon nitride layer 812.

[0110] See also Figure 4 , Figure 9~Figure 13 , which schematically illustrates a semiconductor structure for adjusting the withstand voltage of an isolation ring provided by another embodiment of the present invention. Figure 5~Figure 8 The difference of the provided semiconductor structure for adjusting the withstand voltage of the isolation ring is that, in this embodiment, the semiconductor structure for adjusting the withstand voltage of the isolation ring further includes: a deep trench isolation mark 91. The deep trench isolation mark 91 runs through from the front surface 401 of the silicon substrate 40 to the back surface 402 of the silicon substrate 40, and the deep trench isolation mark 91 is used to determine the etching position of the deep trench isolation field plate 61 on the back surface 402 of the silicon substrate 40.

[0111] The semiconductor structure for adjusting the withstand voltage of the isolation ring and the preparation method thereof provided in this embodiment, by adding a deep trench isolation field plate on the back side of the silicon substrate, the electric lines between the negative charges of a part of the silicon substrate and the positive charges of the isolation ring are weakened, thereby reducing the electric field peak in the bottom tip area of ​​the isolation ring, alleviating the phenomenon of electric field concentration, and at the same time widening the depletion region, thereby improving the withstand voltage. The withstand voltage of the isolation ring can also be further improved by applying voltage to the deep trench isolation field plate through back wiring. By adding a deep trench isolation mark, the etching position of the deep trench isolation field plate can be determined according to the deep trench isolation mark on the back side of the silicon substrate, and the etching position of the deep trench isolation field plate can be accurately determined, so that the formed deep trench isolation field plate surrounds the outer side wall of the isolation ring and does not contact the isolation ring.

[0112] It should be noted that, in the above-mentioned embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0113] The terms "including" and "having" and their variations involved in the documents of the present invention are intended to cover non-exclusive inclusions. The terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless the context clearly indicates, and it should be understood that the data used in this way can be interchanged where appropriate. The term "one or more" depends at least in part on the context and can be used to describe features, structures or characteristics in a singular sense, or can be used to describe a combination of features, structures or features in a plural sense. The term "based on" can be understood as not necessarily intended to express a set of exclusive factors, but can alternatively, also at least in part depending on the context, allow the presence of other factors that are not necessarily explicitly described. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict. In addition, in the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concepts of the present invention.

[0114] The above is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. It should be noted that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor structure for adjusting the withstand voltage of an isolation ring, characterized in that: The invention comprises the following steps: forming a base, the base comprising a silicon substrate having a first conductivity type, the silicon substrate having a front side and a back side arranged opposite to each other, the base also comprising an isolation ring extending from the front side of the silicon substrate into the silicon substrate and having a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type; forming a gate structure and a dielectric layer on the front side of the silicon substrate, the orthographic projection of the gate structure on the silicon substrate falls into the isolation ring, the dielectric layer covers the front side of the silicon substrate and the gate structure; and forming a deep trench isolation field plate extending to the outer side wall of the isolation ring on the back side of the silicon substrate, the deep trench isolation field plate surrounds the outer side wall of the isolation ring and does not contact the isolation ring.

2. The method according to claim 1, characterized in that The step of forming a substrate specifically includes: providing the silicon substrate having the first conductivity type; forming a buried layer having the second conductivity type in the silicon substrate, an annular first deep well having the second conductivity type in contact with the buried layer, an annular second deep well having the second conductivity type in contact with a side of the first deep well away from the buried layer, an annular second well having the second conductivity type in contact with a side of the second deep well away from the first deep well, and an annular second well region having the second conductivity type in contact with a side of the second well away from the first deep well, and an annular second doped region having the second conductivity type in contact with a side of the second well region away from the second deep well, wherein the buried layer, the first deep well, the second deep well, the second well region and the second doped region form the isolation ring.

3. The method according to claim 2, characterized in that The step of forming a substrate also includes: forming an annular first well region having the first conductivity type in the silicon substrate, an annular body region contacting the first well region and having the first conductivity type, and an annular first doped region contacting a side of the body region away from the first well region and having the first conductivity type, wherein the first well region, the body region and the first doped region are all located on the outer wall of the isolation ring and are not in contact with the isolation ring.

4. The method according to claim 3, characterized in that A surface of the first doped region facing away from the body region is flush with the front surface of the silicon substrate, and a surface of the second doped region facing away from the second well region is flush with the front surface of the silicon substrate.

5. The method according to claim 1, characterized in that Before the step of forming a gate structure and a dielectric layer on the front side of the silicon substrate, the step further includes: forming a deep trench isolation mark extending into the silicon substrate on the front side of the silicon substrate, wherein a first distance between the bottom of the deep trench isolation mark and the back side of the silicon substrate is less than a second distance between the bottom of the isolation ring and the back side of the silicon substrate; the step of forming a gate structure and a dielectric layer on the front side of the silicon substrate specifically includes: forming a gate structure on the front side of the silicon substrate and forming a dielectric material layer covering the front side of the silicon substrate and the gate structure; flattening the dielectric material layer to a first thickness; performing a back side thinning process on the back side of the silicon substrate until the deep trench isolation mark is exposed; flattening the dielectric material layer to a target thickness to form the dielectric layer, wherein the target thickness is less than the first thickness; before the step of forming a deep trench isolation field plate extending to the outer side wall of the isolation ring on the back side of the silicon substrate, the step further includes: determining an etching position of the deep trench isolation field plate on the back side of the silicon substrate according to the deep trench isolation mark.

6. The method according to claim 1, characterized in that The step of forming a deep trench isolation field plate extending to the outer wall of the isolation ring on the back side of the silicon substrate specifically includes: etching a deep trench extending to the outer wall of the isolation ring on the back side of the silicon substrate, the deep trench surrounding the outer wall of the isolation ring and not contacting the isolation ring; forming an oxide layer on the inner wall of the deep trench; filling the surface of the oxide layer on the inner wall of the deep trench to form an isolation layer, the oxide layer and the isolation layer constitute the deep trench isolation field plate.

7. The method according to claim 6, characterized in that The oxide layer is also formed on the back side of the silicon substrate, and the step of filling the surface of the oxide layer on the inner wall of the deep trench to form an isolation layer specifically includes: depositing to form an isolation material layer, the isolation material layer fills the deep trench and covers the surface of the oxide layer on the back side of the silicon substrate; using the oxide layer on the back side of the silicon substrate as a stop layer, flattening the isolation material layer, and the remaining isolation material layer in the deep trench forms the isolation layer.

8. The method according to claim 1, characterized in that The method also includes: forming a backside routing on the backside of the silicon substrate that contacts the deep trench isolation field plate, and applying a voltage to the deep trench isolation field plate through the backside routing to increase the withstand voltage of the isolation ring; forming an isolation passivation layer covering the backside of the silicon substrate and the backside routing, the isolation passivation layer having a through hole exposing the backside routing.

9. The method according to claim 1, characterized in that The first conductivity type is P type, and the second conductivity type is N type; or, the first conductivity type is N type, and the second conductivity type is P type.

10. A semiconductor structure for adjusting the withstand voltage of an isolation ring, characterized in that: include: A silicon substrate, wherein the silicon substrate has a first conductivity type and has a front side and a back side that are oppositely disposed; An isolation ring extending from the front side of the silicon substrate into the silicon substrate and having a second conductivity type, wherein the first conductivity type is opposite to the second conductivity type; a gate structure formed on the front side of the silicon substrate, wherein the orthographic projection of the gate structure on the silicon substrate falls into the isolation ring; a dielectric layer, wherein the dielectric layer covers the front side of the silicon substrate and the gate structure; and a deep trench isolation field plate extending from the back side of the silicon substrate to the outer side wall of the isolation ring, wherein the deep trench isolation field plate surrounds the outer side wall of the isolation ring and does not contact the isolation ring.

11. The semiconductor structure for adjusting the withstand voltage of the isolation ring according to claim 10, characterized in that: The isolation ring includes: a buried layer formed in the silicon substrate and having the second conductivity type; an annular first deep well in contact with the buried layer and having the second conductivity type; an annular second deep well in contact with a side of the first deep well away from the buried layer and having the second conductivity type; an annular second well region in contact with a side of the second deep well away from the first deep well and having the second conductivity type; and an annular second doped region in contact with a side of the second well region away from the second deep well and having the second conductivity type.

12. The semiconductor structure for adjusting the withstand voltage of the isolation ring according to claim 10, characterized in that: Also includes: A deep trench isolation mark runs from the front side of the silicon substrate to the back side of the silicon substrate, and the deep trench isolation mark is used to determine the etching position of the deep trench isolation field plate on the back side of the silicon substrate.

13. The semiconductor structure for adjusting the withstand voltage of the isolation ring according to claim 10, characterized in that: The deep trench isolation field plate includes: an oxide layer formed on the inner wall of a deep trench extending from the back of the silicon substrate to the outer wall of the isolation ring; an isolation layer filling the surface of the oxide layer on the inner wall of the deep trench, wherein the material of the isolation layer includes metal tungsten.

14. The semiconductor structure for adjusting the withstand voltage of the isolation ring according to claim 10, characterized in that: Also includes: A backside wiring is formed on the backside of the silicon substrate and contacts the deep trench isolation field plate, and a voltage can be applied to the deep trench isolation field plate through the backside wiring to improve the withstand voltage of the isolation ring; An isolation passivation layer covers the back side of the silicon substrate and the back side wiring, and the isolation passivation layer has a through hole exposing the back side wiring.

15. The semiconductor structure for adjusting the withstand voltage of the isolation ring according to claim 14, characterized in that: The backside wiring adopts a composite laminated structure of an adhesive layer and a metal layer, and the material of the adhesive layer is titanium or titanium nitride; the isolation passivation layer adopts a composite laminated structure of an undoped silicate glass layer and a silicon nitride layer.

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