Semiconductor structure and forming method of semiconductor structure

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises a device region and a non-device region and comprises a first substrate, a second substrate and an insulating layer located between the first substrate and the second substrate, the insulating layer comprises a first insulating part located in a device area and a second insulating part located in a non-device area, the first insulating part and the second insulating part are made of different materials, and the heat conductivity coefficient of the first insulating part is larger than that of the second insulating part; the device structure is located in the device area, and the device structure is formed on the face, back on to the insulating layer, of the first substrate and corresponds to the first insulating part up and down. The heat dissipation problem of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] In an era of rapid development of the information technology industry, 5G applications are becoming increasingly widespread, and research investment in 6G continues to increase, and the requirements for integrated circuits are also increasing. Continuous improvements in process technology and innovations in device structure have led to a continuous reduction in device feature size, continuous improvement in integration, continuous reduction in power consumption, and continuous improvement in performance. However, as feature size decreases, the interaction between devices within and between devices through the substrate in bulk silicon technology becomes increasingly serious, and a series of new problems in materials, device physics, device structure, and process technology have emerged. For devices formed based on bulk silicon materials, there is a substrate effect between devices, that is, there is a latch effect, which affects the performance of the device.

[0003] In order to solve the latch-up effect, silicon-on-insulator wafers are often used as substrates in the prior art. However, the self-heating effect is easily generated during the use of silicon-on-insulator wafers as substrates, which will also affect the performance of the device. There are currently three main methods to improve the self-heating effect: the first is to increase the area of ​​the device; the second is to increase the thickness of the top layer of the second base silicon or reduce the thickness of the buried silicon dioxide; the third is to set up body contacts to provide a heat dissipation path. However, the improvement degree of these three methods is limited, which is not conducive to improving the performance of the chip.

[0004] Therefore, how to solve the self-heating effect of silicon-on-insulator is a technical problem that continues to need to be solved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure, which solves the self-heating effect of silicon on an insulator.

[0006] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including a device area and a non-device area, the substrate including a first base, a second base and an insulating layer located between the first base and the second base stacked in sequence, the insulating layer including a first insulating portion located in the device area and a second insulating portion located in the non-device area, wherein the first insulating portion and the second insulating portion are made of different materials and the thermal conductivity of the first insulating portion is greater than the thermal conductivity of the second insulating portion; a device structure, the device structure is located in the device area, the device structure is formed on a side of the first base facing away from the insulating layer, and corresponds to the first insulating portion up and down.

[0007] Optionally, the resistivity of the first insulating portion is greater than the resistivity of the second insulating portion.

[0008] Optionally, the material of the first insulating part includes aluminum nitride or silicon nitride; and the material of the second insulating part includes silicon oxide.

[0009] Optionally, the thickness of the first insulating portion is the same as the thickness of the second insulating portion.

[0010] Optionally, the thickness of the second substrate is smaller than the thickness of the first substrate.

[0011] Optionally, the device structure includes a transistor, a diode or a triode; the transistor includes: a gate structure located on a first substrate and source and drain doped regions located in the first substrate on both sides of the gate structure.

[0012] Accordingly, the technical solution of the present invention also provides a method for forming the semiconductor structure, comprising:

[0013] Step S1: forming a substrate, the forming of the substrate comprising: providing a first base; forming an insulating layer on one surface of the first base, the insulating layer comprising a first insulating portion and a second insulating portion, wherein the material of the first insulating portion is different from that of the second insulating portion and the thermal conductivity of the first insulating portion is greater than that of the second insulating portion; providing a second base; bonding the second base to the insulating layer; thinning the first base on a surface facing away from the insulating layer to form the substrate; wherein the substrate comprises a device area and a non-device area, the first insulating portion is located in the device area, and the second insulating portion is located in the non-device area;

[0014] Step S2: forming a device structure in the device region, wherein the device structure is formed on a surface of the first substrate facing away from the insulating layer, and the device structure corresponds to the first insulating portion in a vertical direction.

[0015] Optionally, an insulating layer is formed on a first substrate, including: forming a second insulating part material layer on the first substrate; removing the second insulating part material layer in the device area, and forming a second insulating part in the non-device area; forming a first insulating part material layer, wherein the first insulating part material layer covers the device area and the second insulating part; flattening the first insulating part material layer until the surface of the second insulating part is exposed, and forming the first insulating part on the first substrate in the device area.

[0016] Optionally, before forming the insulating layer on the first substrate, the method further includes: forming an alignment mark groove in a non-device area of ​​the first substrate, and when forming the second insulating portion on the first substrate, the alignment mark groove is also filled with the second insulating portion.

[0017] Optionally, thinning the first substrate on a side facing away from the insulating layer specifically includes: thinning the first substrate on a side facing away from the insulating layer until the second insulating portion in the alignment mark groove is exposed to form the substrate.

[0018] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0019] In the semiconductor structure of the technical solution of the present invention, the first insulating part is located in the device area, the first insulating part is located at the bottom of the device structure, the material of the first insulating part is different from the material of the second insulating part, and the thermal conductivity of the first insulating part is greater than the thermal conductivity of the second insulating part. Therefore, the first insulating part can easily conduct the heat generated by the device structure and conduct it out through the second substrate, thereby fundamentally improving the self-heating effect of the substrate and thereby improving the performance of the semiconductor structure.

[0020] Furthermore, the resistivity of the first insulating portion is greater than that of the second insulating portion. The first insulating portion has a larger resistivity, and the first insulating portion can maintain the insulation effect between the first substrate and the second substrate, maintain the isolation between the device regions, and eliminate the latch effect.

[0021] In the formation method of the technical solution of the present invention, the first insulating part is formed in the device area, the first insulating part is formed at the bottom of the device structure, the material of the first insulating part is different from the material of the second insulating part, and the thermal conductivity of the first insulating part is greater than the thermal conductivity of the second insulating part. Therefore, the first insulating part can easily conduct the heat generated by the device structure and conduct it out through the second substrate, thereby fundamentally improving the self-heating effect of the substrate and thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic structural diagram of a semiconductor structure in an embodiment;

[0023] Figures 2 to 8 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] As described in the background art, there are still many problems to be solved in using silicon on insulator as a substrate, which will be described in detail below with reference to the accompanying drawings.

[0025] Figure 1The schematic diagram of the structure of a semiconductor structure in an embodiment is shown. The substrate of the semiconductor structure is a silicon-on-insulator wafer, and the silicon-on-insulator wafer has a three-layer structure, namely, a first substrate 100, a second substrate 102, and an insulating layer 101 between the first substrate 100 and the second substrate 102. The second substrate 102 on the top layer is the area for making devices, the middle insulating layer 101 is a buried silicon dioxide layer, and the bottom first substrate 100 is substrate silicon. Due to the isolation effect of the insulating layer 101 of silicon dioxide and the isolation structure 105, there is no substrate effect between the device area and the device area, that is, there is no latch effect, which can effectively improve the performance of the device. However, due to the poor thermal conductivity of the buried oxide layer silicon dioxide, the heat generated during the operation of the device is not easy to conduct away, forming a temperature accumulation, resulting in a self-heating effect. The self-heating effect causes the temperature of the second substrate 102 on the top layer to rise. As the temperature of the silicon device area of ​​the second substrate 102 on the top layer rises sharply, the lattice scattering is enhanced, the electron carrier mobility decreases, and the output characteristic curve of the device shows that when the drain voltage is large, the negative conductivity effect occurs, in which the drain current decreases as the voltage increases.

[0026] In order to solve the above problems, an embodiment of the present invention provides a semiconductor structure and a method for forming a semiconductor structure, by setting a first insulating part in the device area and setting the first insulating part at the bottom of the device structure, the material of the first insulating part is different from the material of the second insulating part, and the thermal conductivity of the first insulating part is greater than the thermal conductivity of the second insulating part. Therefore, the first insulating part can easily conduct the heat generated by the device structure and conduct it out through the second substrate, thereby fundamentally improving the self-heating effect of the substrate, thereby improving the performance of the semiconductor structure.

[0027] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0028] Figures 2 to 8 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0029] The method for forming the semiconductor structure comprises:

[0030] Perform step S1: form a substrate, forming the substrate includes: providing a first base; forming an insulating layer on one surface of the first base, the insulating layer including a first insulating part and a second insulating part, wherein the material of the first insulating part is different from that of the second insulating part and the thermal conductivity of the first insulating part is greater than the thermal conductivity of the second insulating part; providing a second base; bonding the second base to the insulating layer; thinning the first base on a side facing away from the insulating layer to form the substrate; wherein the substrate includes a device area I and a non-device area II, the first insulating part is located in the device area I, and the second insulating part is located in the non-device area II.

[0031] Perform step S2: forming a device structure in the device area, wherein the device structure is formed on a surface of the first substrate facing away from the insulating layer, and the device structure corresponds to the first insulating portion in a vertical direction.

[0032] Among them, the device area I is the area where the device structure is formed. As a specific implementation, the device structure includes a transistor, a diode or a triode, etc.; the non-device area II is the area where other non-devices are formed, such as circuit connections, resistors, capacitors, inductors, etc.

[0033] The formation process of the substrate can be found in Figures 2 to 6 .

[0034] Please refer to Figure 2 , providing a first substrate 200 ; etching the first substrate 200 in the non-device area II, and forming an alignment mark groove 201 in the first substrate 200 .

[0035] In this embodiment, the material of the first substrate 200 is silicon.

[0036] In other embodiments, the material of the first substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0037] A method for etching the first substrate 200 in the non-device area II to form an alignment mark groove 201 in the first substrate 200 includes: forming a patterned mask layer (not shown) on the first substrate 200, wherein the patterned mask layer exposes a portion of the surface of the first substrate 200 in the non-device area II; etching the first substrate 200 using the patterned mask layer as a mask to form an alignment mark groove 201 in the first substrate 200.

[0038] The process of etching the first substrate 200 in the non-device region II includes a dry etching process.

[0039] Please refer to Figure 3 , a second insulating portion 203 is formed on the first substrate 200 .

[0040] The method for forming the second insulating part 203 includes: forming a second insulating part material layer (not shown) on the first substrate 200 and in the alignment mark groove 201; removing the second insulating part material layer in the device area I, and forming a second insulating part 203 on the first substrate 200 in the non-device area II and in the alignment mark groove 201, wherein the second insulating part 203 has an opening 204 exposing the surface of the first substrate 200 in the device area I.

[0041] The material of the second insulating portion 203 includes an insulating material. Preferably, the material of the second insulating portion 203 includes silicon oxide.

[0042] The process of forming the second insulating portion includes a chemical vapor deposition process or a physical vapor deposition process.

[0043] Please refer to Figure 4 , a first insulating portion 205 is formed on the first substrate 200 in the device region I.

[0044] The method for forming the first insulating part 205 includes: forming a first insulating part material layer (not shown) in the opening 204 of the device area I and on the second insulating part 203, the first insulating part material layer covering the device area I and the second insulating part 203; flattening the first insulating part material layer until the surface of the second insulating part 203 is exposed, and forming the first insulating part 205 on the first substrate 200 of the device area I.

[0045] In this embodiment, the top surface of the first insulating material layer in the opening 204 is higher than the depth of the opening 204 , so the first insulating portion 205 is formed after the first insulating material layer is planarized.

[0046] The first insulating portion 205 and the second insulating portion 203 constitute an insulating layer between the first substrate 200 and a subsequent second substrate.

[0047] In this embodiment, the material of the first insulating portion 205 is different from the material of the second insulating portion 203 .

[0048] In this embodiment, the thermal conductivity of the first insulating part 205 is greater than the thermal conductivity of the second insulating part 203, so that the first insulating part 205 has better thermal conductivity and stronger heat conduction capability, and can easily conduct away the heat generated by the device structure formed in the device area I from the first substrate 200, so as to avoid temperature accumulation and self-heating effect.

[0049] As an embodiment, when the second insulating portion is preferably silicon oxide, the thermal conductivity of the first insulating portion 205 is greater than 1.4 W·m -1 ℃ -1 .

[0050] In this embodiment, the resistivity of the first insulating portion 205 is greater than the resistivity of the second insulating portion 203. The resistivity of the first insulating portion 205 is relatively large, and the first insulating portion 205 can maintain the insulation effect between the first substrate 200 and the second substrate 300, maintain the isolation effect between the device region I and the second substrate, and eliminate the latch effect. Preferably, the resistivity of the first insulating portion 205 is greater than 10 4 Ω·cm, and greater than the resistivity of the second insulating portion.

[0051] As a specific implementation, the material of the first insulating part 205 includes aluminum nitride or silicon nitride. The material of the first insulating part 205 includes aluminum nitride. The materials of the first insulating part and the second insulating part are different, and the resistivity and thermal conductivity of the first insulating part material are greater than those of the second insulating part material. For the specific materials of the first insulating part and the second insulating part, those skilled in the art can select them according to actual conditions, and no limitation is made here.

[0052] In this embodiment, the thickness of the first insulating portion 205 is the same as the thickness of the second insulating portion 203 .

[0053] Preferably, the thickness of the first insulating portion 205 and the thickness of the second insulating portion 203 are 2000 angstroms, that is, the thickness of the insulating layer is 2000 angstroms. For the specific thickness of the insulating layer, those skilled in the art can set a suitable thickness according to actual conditions, which is not limited here.

[0054] In this embodiment, the insulating layer includes a first insulating portion 205 located in the device area I and a second insulating portion 203 located in the non-device area II. The insulating layer is composed of two parts, and the second insulating portion 203 is not required to have a high thermal conductivity, so the material cost of the second insulating portion 203 is low. The insulating layer can have a low cost while having good thermal conductivity to the device area I.

[0055] In other embodiments, the insulating layer can be formed solely of the material of the first insulating portion, so that both the device region and the non-device region have good thermal conductivity, effectively improving the self-heating effect of the substrate.

[0056] Please refer to Figure 5 , providing a second substrate 300; bonding the second substrate 300 to the insulating layer, wherein the insulating layer is located between the first substrate 200 and the second substrate 300.

[0057] In this embodiment, the material of the second substrate 300 is silicon.

[0058] In other embodiments, the material of the second substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0059] Bonding the second substrate 300 to the insulating layer includes: polishing the surface of the insulating layer and the surface of the second substrate 300; bonding the second substrate 300 to the insulating layer after polishing the surface of the insulating layer and the surface of the second substrate 300; heat treating the bonded second substrate 300 and the insulating layer to complete the bonding of the second substrate 300 and the insulating layer.

[0060] In this embodiment, the thickness of the first insulating portion 205 is the same as that of the second insulating portion 203. Therefore, the insulating layer can provide a surface with high flatness during bonding, so as to form a chemical bond with high bonding force when bonding with the second substrate 300.

[0061] Please refer to Figure 6 After bonding the second substrate 300 to the insulating layer, the first substrate 200 is thinned on a side facing away from the insulating layer until the second insulating portion 203 in the alignment mark groove 201 is exposed, and the first substrate 200 is formed into a substrate. The substrate includes: a first substrate 200, an insulating layer, and a second substrate 300 stacked in sequence, wherein the insulating layer is located between the first substrate 200 and the second substrate 300.

[0062] It should be noted that the thinned surface of the first substrate 200 is the side facing away from the insulating layer, and the thinning of the first substrate 200 exposes the surface of the second insulating portion 203 at the bottom of the alignment mark groove 201 .

[0063] The process of thinning the first substrate 200 includes a chemical mechanical polishing process or an etching process.

[0064] In this embodiment, the thickness of the second substrate 300 is greater than the thickness of the first substrate 200 .

[0065] The thickness of the second substrate 300 is at the millimeter level. The second substrate 300 is relatively thick and provides structural support for forming a device structure on the first substrate 200. The first substrate 200 is used to form a device structure. The thickness of the first substrate 200 is relatively thin. The thickness range of the first substrate 200 is at the micron level. The corresponding thickness is selected within the range of 0.01 microns to 10 microns according to the device requirements of the chip.

[0066] Please refer to Figure 7 , an isolation structure 208 is formed in the thinned first substrate 200, the isolation structure penetrates the first substrate 200 and contacts the insulating layer, and the isolation structure 208 surrounds the first substrate 200 in the device area I.

[0067] In this embodiment, the first insulating portion 205 extends to the bottom of the isolation structure 208 .

[0068] The method for forming the isolation structure 208 includes: forming a patterned mask layer (not shown) on the first substrate 200, wherein the patterned mask layer exposes a portion of the surface of the first substrate 200 around the device area I; etching the first substrate 200 using the patterned mask layer as a mask to expose the surface of the insulating layer and form an isolation opening in the first substrate 200; and forming the isolation structure 208 in the isolation opening.

[0069] In this embodiment, the material of the isolation structure 208 includes silicon oxide.

[0070] Please refer to Figure 8 , performing step S2: forming a device structure in the device area I, wherein the device structure is formed on a side of the first substrate 200 facing away from the insulating layer, and the device structure corresponds to the first insulating portion 205 in a vertical direction.

[0071] The device structure includes a transistor, a diode or a triode.

[0072] In this embodiment, the device structure includes a transistor, and the transistor includes: a gate structure 206 located on a first substrate 200 and source / drain doped regions 207 located in the first substrate 200 on both sides of the gate structure 206 .

[0073] The gate structure 206 includes a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0074] In one embodiment, the material of the gate dielectric layer includes silicon oxide or a low-K (K is less than 3.9) material; and the material of the gate layer includes polysilicon.

[0075] In another embodiment, the material of the gate dielectric layer includes a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, the material of the gate dielectric layer is a high-K (K greater than 3.9) dielectric material, the material of the gate dielectric layer includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide; LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Al2O3, Si3N4, nitride oxide or other suitable materials; the material of the gate layer includes metal, and the metal includes tungsten.

[0076] The first insulating part 205 is located in the device area I, and the first insulating part 205 is located at the bottom of the device structure. The material of the first insulating part 205 is different from the material of the second insulating part 203, and the thermal conductivity of the first insulating part 205 is greater than the thermal conductivity of the second insulating part 203. Therefore, the first insulating part 205 can easily conduct the heat generated by the device structure and conduct it out through the second substrate 300, thereby fundamentally improving the self-heating effect of the substrate, thereby improving the performance of the semiconductor structure.

[0077] Accordingly, the technical solution of the present invention also provides a semiconductor structure, please continue to refer to Figure 7 ,include:

[0078] A substrate, the substrate comprising a device region I and a non-device region II, the substrate comprising a first substrate 200, a second substrate 300 stacked in sequence, and an insulating layer located between the first substrate 200 and the second substrate 300, the insulating layer comprising a first insulating portion 205 located in the device region I and a second insulating portion 203 located in the non-device region II, wherein the first insulating portion 205 and the second insulating portion 203 are made of different materials and the thermal conductivity of the first insulating portion 205 is greater than the thermal conductivity of the second insulating portion 203;

[0079] The device structure is located in the device area I. The device structure is formed on a side of the first substrate 200 facing away from the insulating layer and corresponds to the first insulating portion 205 up and down.

[0080] In this embodiment, the resistivity of the first insulating portion 205 is greater than the resistivity of the second insulating portion 203 .

[0081] In this embodiment, the material of the first insulating portion 205 includes aluminum nitride or silicon nitride; the material of the second insulating portion 203 includes silicon oxide.

[0082] In this embodiment, the thickness of the first insulating portion 205 is the same as the thickness of the second insulating portion 203 .

[0083] In this embodiment, the thickness of the second substrate 300 is greater than the thickness of the first substrate 200 .

[0084] In this embodiment, the device structure includes a transistor, a diode or a triode; the transistor includes: a gate structure 206 located on a first substrate 200 and source-drain doped regions 207 located in the first substrate 200 on both sides of the gate structure 206 .

[0085] The first insulating part 205 is located in the device area I, and the first insulating part 205 is located at the bottom of the device structure. The thermal conductivity of the first insulating part 205 is greater than the thermal conductivity of the second insulating part 203. Therefore, the first insulating part 205 can easily conduct the heat generated by the device structure and conduct it out through the second substrate 300, thereby fundamentally improving the self-heating effect of the substrate and thereby improving the performance of the semiconductor structure.

[0086] The materials, formation process, working principle, specific implementation method and beneficial effects involved in the semiconductor structure in the embodiment of the present invention can all be found in the method for forming the semiconductor structure in the embodiment of the present invention, and will not be described in detail here.

[0087] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a device area and a non-device area, the substrate comprising a first base, a second base and an insulating layer located between the first base and the second base stacked in sequence, the insulating layer comprising a first insulating portion located in the device area and a second insulating portion located in the non-device area, wherein the first insulating portion and the second insulating portion are made of different materials and the thermal conductivity of the first insulating portion is greater than the thermal conductivity of the second insulating portion; A device structure, wherein the device structure is located in the device region, and the device structure is formed on a side of the first substrate facing away from the insulating layer, and corresponds to the first insulating portion up and down.

2. The semiconductor structure according to claim 1, wherein: The resistivity of the first insulating portion is greater than the resistivity of the second insulating portion.

3. The semiconductor structure according to claim 1, wherein: The material of the first insulating portion includes aluminum nitride or silicon nitride; the material of the second insulating portion includes silicon oxide.

4. The semiconductor structure according to claim 1, wherein: The thickness of the first insulating portion is the same as the thickness of the second insulating portion.

5. The semiconductor structure according to claim 1, wherein: The thickness of the second substrate is smaller than the thickness of the first substrate.

6. The semiconductor structure according to claim 1, wherein: The device structure includes a transistor, a diode or a triode; the transistor includes: a gate structure located on a first substrate and source-drain doped regions located in the first substrate on both sides of the gate structure.

7. A method for forming a semiconductor structure according to any one of claims 1 to 6, characterized in that: include: Step S1: forming a substrate, wherein forming the substrate comprises: providing a first substrate; forming an insulating layer on one surface of the first substrate, the insulating layer comprising a first insulating portion and a second insulating portion, wherein the material of the first insulating portion is different from that of the second insulating portion and the thermal conductivity of the first insulating portion is greater than the thermal conductivity of the second insulating portion; providing a second substrate; bonding the second substrate to the insulating layer; Thinning the first base on a side facing away from the insulating layer to form the substrate, wherein the substrate includes a device area and a non-device area, the first insulating portion is located in the device area, and the second insulating portion is located in the non-device area; Step S2: forming a device structure in the device region, wherein the device structure is formed on a surface of the first substrate facing away from the insulating layer, and the device structure corresponds to the first insulating portion in a vertical direction.

8. The method for forming a semiconductor structure according to claim 7, wherein: An insulating layer is formed on a first substrate, comprising: Forming a second insulating material layer on the first substrate; removing the second insulating material layer in the device area, and forming a second insulating part in the non-device area; forming a first insulating material layer, wherein the first insulating material layer covers the device region and the second insulating portion; The first insulating part material layer is planarized until a surface of the second insulating part is exposed, and the first insulating part is formed on the first substrate in the device region.

9. The method for forming a semiconductor structure according to claim 8, wherein: Before forming the insulating layer on the first substrate, the method further includes: forming an alignment mark groove in the non-device area of ​​the first substrate, and when forming the second insulating part on the first substrate, the alignment mark groove is also filled with the second insulating part.

10. The method for forming a semiconductor structure according to claim 9, wherein: Thinning the first substrate on a side facing away from the insulating layer specifically includes: thinning the first substrate on a side facing away from the insulating layer until the second insulating portion in the alignment mark groove is exposed to form the substrate.

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