Semiconductor structure

Abstract

A semiconductor structure includes semiconductor stacks over a substrate, where each of the semiconductor stacks extends in a first direction, and adjacent semiconductor stacks are spaced apart from each other in a second direction different from the first direction, where each of the semiconductor stacks includes a channel layer, a first electrode, a second electrode, and a third electrode. The first and second electrodes are located above the substrate and are spaced apart from each other in a third direction, and the third direction is perpendicular to the first and second directions; and a gate structure comprising: a gate dielectric layer surrounding a corresponding channel layer; and a gate electrode along sidewalls of the gate dielectric layers and a top surface of an uppermost one of the gate dielectric layers, in which a pitch between two lowermost one of the channel layers in the third direction is greater than a pitch between two uppermost one of the channel layers in the third direction. This makes it possible to obtain a more uniform threshold voltage of a nanosheet transistor comprising a channel layer in each semiconductor stack.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Art

[0002] In recent years, advanced integrated circuit (IC) devices have become increasingly versatile and have shrunk in size. Although scaling down processes generally improves production efficiency and reduces associated costs, it also increases the complexity of processing and manufacturing IC devices. For example, Fin Field-Effect Transistor (FinFET) has been introduced to replace planar transistors. Among these FinFETs, gate-all-around (GAA) structures such as nanosheet metal-oxide-semiconductor field-effect transistors (MOSFET) have been developed to have excellent electrical characteristics, such as improved power performance and area scaling (area reduction) compared to current FinFET technology current.

[0003] Although existing semiconductor structures including nanosheet transistors and methods for manufacturing the same are sufficient to meet their intended purposes, they are not completely satisfactory in all aspects. For example, in a semiconductor structure including a nanosheet transistor, each multilayer fin includes several channel layers stacked on a substrate, and the channel layers in one of the multilayer fins are separated from each other in a direction perpendicular to the substrate. These multilayer fins are relatively high (high in height), and it is difficult to fill the empty space in the deeper position of the fin with the required material, such as filling the empty space near the bottom of the multilayer fin with a gate electrode layer material. The thickness of the gate electrode layer between nanosheet transistors controlled by the same gate stack is uneven. Therefore, the threshold voltage between nanosheet transistors controlled by the same gate stack will be different, which will affect the electrical performance of the semiconductor structure during operation. Therefore, there are still some problems to be overcome with respect to semiconductor structures including nanosheet transistors in semiconductor integrated circuits and technologies. Summary of the invention

[0004] In view of this, the present invention provides a semiconductor device which can greatly reduce power consumption compared with conventional designs.

[0005] In view of this, the present invention provides a semiconductor structure, which can obtain a uniform threshold voltage of the nanosheet transistors in each semiconductor stack, thereby improving the electrical performance of the semiconductor structure.

[0006] According to a first aspect of the present invention, a semiconductor structure is disclosed, comprising:

[0007] Semiconductor stacks are provided above the substrate, wherein each of the semiconductor stacks extends in a first direction and adjacent semiconductor stacks are spaced apart from each other in a second direction different from the first direction, wherein each of the semiconductor stacks comprises:

[0008] channel layers located above the substrate and spaced apart from each other in a third direction, wherein the third direction is perpendicular to the first direction and the second direction; and

[0009] A gate structure comprising: a gate dielectric layer surrounding the corresponding channel layer; and a gate electrode along the sidewalls of the gate dielectric layer and the top surface of the uppermost gate dielectric layer of the gate dielectric layer,

[0010] Wherein, a distance between two lowermost channel layers of the channel layer along the third direction is greater than a distance between two uppermost channel layers of the channel layer along the third direction.

[0011] According to a second aspect of the present invention, a semiconductor structure is disclosed, comprising:

[0012] Semiconductor stacks are provided above the substrate, wherein each of the semiconductor stacks extends in a first direction and adjacent semiconductor stacks are spaced apart from each other in a second direction different from the first direction, wherein each of the semiconductor stacks comprises:

[0013] channel layers, located above the substrate and spaced apart from each other in a third direction, wherein the third direction is perpendicular to the first direction and the second direction;

[0014] A gate structure, comprising: a gate dielectric layer surrounding the corresponding channel layer; and a gate electrode along the sidewalls of the gate dielectric layer and the top surface of the uppermost gate dielectric layer of the gate dielectric layer;

[0015] The channel layer includes: a first channel layer, which is above the substrate; a second channel layer, which is above the first channel layer, wherein a distance between the first channel layer and the second channel layer in a first direction is defined as a first spacing; and a third channel layer, which is above the second channel layer, wherein a distance between the second channel layer and the third channel layer in the first direction is defined as a second spacing;

[0016] The first spacing is greater than the second spacing.

[0017] According to a third aspect of the present invention, a semiconductor structure is disclosed, comprising:

[0018] Semiconductor stacks are provided above the substrate, wherein each of the semiconductor stacks extends in a first direction and adjacent semiconductor stacks are spaced apart from each other in a second direction different from the first direction, wherein each of the semiconductor stacks comprises:

[0019] channel layers located above the substrate and spaced apart from each other in the third direction, wherein the third direction is perpendicular to the first direction and the second direction; and

[0020] A gate structure comprising: a gate dielectric layer surrounding the corresponding channel layer; and a gate electrode along the sidewalls of the gate dielectric layer and the top surface of the uppermost gate dielectric layer of the gate dielectric layer,

[0021] Wherein a lowermost channel layer of the channel layers in the semiconductor stack comprises a higher germanium content than germanium contents in other corresponding channel layers in the semiconductor stack.

[0022] According to a fourth aspect of the present invention, a semiconductor structure is disclosed, comprising:

[0023] Semiconductor stacks are provided above the substrate, wherein each of the semiconductor stacks extends in a first direction and adjacent semiconductor stacks are spaced apart from each other in a second direction different from the first direction, wherein each of the semiconductor stacks comprises:

[0024] channel layers, located above the substrate and spaced apart from each other in a third direction, wherein the third direction is perpendicular to the first direction and the second direction;

[0025] A gate structure, comprising: a gate dielectric layer surrounding the corresponding channel layer; and a gate electrode along the sidewalls of the gate dielectric layer and the top surface of the uppermost gate dielectric layer of the gate dielectric layer;

[0026] Wherein, the channel layer includes: a first channel layer, which is above the substrate; a second channel layer, which is above the first channel layer;

[0027] The germanium content in the first channel layer is greater than the germanium content in the second channel layer.

[0028] The semiconductor structure of the present invention has a spacing between the two bottom channel layers of the channel layer along the third direction greater than the spacing between the two top channel layers of the channel layer along the third direction. This makes it easier to deposit the gate material around the bottom channel layer, avoiding the problem of less or insufficient gate material being deposited around the bottom channel layer, so that enough gate material can be deposited around the bottom channel layer, thereby significantly reducing the difference in electrical performance between the nanosheet transistors in each semiconductor stack, and obtaining a more uniform threshold voltage of the nanosheet transistors including the channel layer in each semiconductor stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a top view of the semiconductor structure above the substrate.

[0030] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B is a cross-sectional view of an intermediate stage in a method for forming a semiconductor structure according to some embodiments.

[0031] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig.9A It is along Figure 1 A cross-sectional view of the semiconductor structure taken along section line AA.

[0032] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Fig. 9B is along Figure 1 A cross-sectional view of the semiconductor structure taken along section line BB in FIG.

[0033] Fig.10 is a cross-sectional view of a semiconductor structure according to some embodiments.

[0034] Fig.11A The IV (drain current versus gate voltage) characteristics of a semiconductor stack including nanosheet transistors with non-uniform threshold voltage are schematically shown.

[0035] Fig. 11B Schematically illustrated are IV (drain current versus gate voltage) characteristics of a semiconductor stack including nanosheet transistors with uniform threshold voltage, according to some embodiments.

[0036] Fig.12 is a cross-sectional view of a semiconductor structure according to some embodiments.

[0037] Fig.13 is a cross-sectional view of a semiconductor structure according to some embodiments. DETAILED DESCRIPTION

[0038] The following description is the best conceived mode of implementing the present invention. This description is made to illustrate the general principles of the present invention and should not be considered as limiting. The scope of the present invention is determined by the appended claims.

[0039] The inventive concept is fully described below with reference to the accompanying drawings, in which exemplary embodiments of the inventive concept are shown. The advantages and features of the inventive concept and the methods for achieving these advantages and features will become apparent from the following exemplary embodiments, which will be described in more detail with reference to the accompanying drawings. However, it should be noted that the inventive concept is not limited to the following exemplary embodiments and can be implemented in various forms. Therefore, exemplary embodiments are provided only to disclose the inventive concept and to make those skilled in the art aware of the categories of the inventive concept. Moreover, the drawings shown are only schematic and non-restrictive. In the drawings, for illustrative purposes, the sizes of some elements may be enlarged and not drawn to scale. In the practice of the present invention, the sizes and relative sizes do not correspond to the actual sizes.

[0040] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. As used herein, the singular terms "a", "an" and "the" are also intended to include plural forms unless the context clearly indicates otherwise. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. It should be understood that when an element is referred to as being "connected" or "contacting" another element, it can be directly connected or contacting the other element, or there can be intermediate elements.

[0041] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there can be intervening elements. In contrast, the term "directly" means that there are no intervening elements. It should be understood that when used herein, the terms "include" and / or "comprise" specify the presence of the features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0042] In addition, for ease of description, spatial relative terms, such as "below ... ", "below ... ", "below ", "above ... ", "above ", etc., may be used herein to describe the relationship between an element or feature as shown in the figure and another one or more elements or features. In addition to the orientation described in the figure, spatial relative terms are also intended to cover different orientations of the device in use or operation. It should be understood that although the terms first, second, third, etc. can be used here to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present invention, the first element in some embodiments may be referred to as the second element in other embodiments. Exemplary embodiments of various aspects of the inventive concept explained and illustrated herein include their complementary equivalents. Throughout the specification, the same or similar figure numerals or reference numerals represent the same or similar elements.

[0043] Figure 1 is a top view of a semiconductor structure above a substrate. In some embodiments, the semiconductor structure is a three-dimensional or non-planar transistor. In some embodiments, the semiconductor structure is a field-effect transistor (FET) structure including a nanosheet transistor.

[0044] Reference Figure 1 The semiconductor structure 1 includes several multi-layer fins M1 and M2 on a substrate 10, and a gate structure GE spanning the multi-layer fins M1 and M2 to form a semiconductor stack M1. G and M2 G In order to simplify the figure, only two multilayer fins M1 and M2 are shown here. The multilayer fins M1 and M2 may extend in a first direction D1 (such as the X direction) (that is, the length direction of the multilayer fins M1 and M2 extends along the first direction D1), and the gate structure GE may extend in a second direction D2 (such as the Y direction) (that is, the length direction of the gate structure GE extends along the second direction D2). In some embodiments, the semiconductor stack M1 G and M2 G is a nanosheet stack, and each semiconductor stack includes a nanosheet transistor. Figure 1 As shown, adjacent multi-layer fins M1 and M2 (or adjacent semiconductor stacks M1 G and M2 G ) are spaced apart from each other in a second direction D2 (eg, Y direction) (the multilayer fins M1 and M2 have a spacing along the second direction D2), wherein the second direction D2 is different from the first direction D1. For example, the second direction D2 is perpendicular to the first direction D1.

[0045] According to some embodiments of the present invention, each semiconductor stack (such as M1) in the semiconductor structure G and M2 G ) includes nanosheet transistors, and the channel layer of each semiconductor stack is designed to improve electrical performance. Examples of the design include changing the spacing between adjacent channel layers in each semiconductor stack, changing the composition of the channel layer in each semiconductor stack, or a combination of the above changes. Thus, improved electrical performance including uniform threshold voltage of the nanosheet transistors in each semiconductor stack can be obtained.

[0046] The following describes a method for forming a semiconductor structure having a semiconductor stack, wherein the space between adjacent channel layers in each semiconductor stack is designed to improve the electrical performance of the nanosheet transistor. However, the present invention is not limited to the method provided herein. Those steps provided herein are only described as an example of fabrication.

[0047] Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B is a cross-sectional view of an intermediate stage in a method for forming a semiconductor structure according to some embodiments. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A and Fig.9A It is along Figure 1 A cross-sectional view of the semiconductor structure taken along section line AA. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Fig. 9B It is along Figure 1 A cross-sectional view of the semiconductor structure taken along section line BB in FIG.

[0048] Reference Figure 2A and Figure 2B, a substrate 10 is provided, and several semiconductor strips S1 and S2 are formed on the substrate 10, wherein adjacent semiconductor strips S1 and S2 are spaced apart from each other in a second direction D2 (eg, Y direction) (having a spacing (first groove 15) along the second direction D2), such as Figure 2B The lateral spacing between the semiconductor strips S1 and S2 shown). In some embodiments, each of the semiconductor strips S1 and S2 may include several sacrificial layers 11 and several channel layers 12 on the substrate 10. According to some embodiments of the present invention, the distance or space between the two lowest channel layers in the third direction D3 (e.g., Z direction) is greater than the distance or space between the two uppermost channel layers in the third direction D3 (e.g., Z direction), for example, the spacing (distance or space) between the channel layer 12-1 and the channel layer 12-2 is greater than the spacing (distance or space) between the channel layer 12-2 and the channel layer 12-3. The concepts of upper and lower in this embodiment can be based on the substrate 10 as a reference, for example, the one relatively close to the substrate is the lower, and the one relatively far away from the substrate is the upper.

[0049] In some embodiments, substrate 10 is a bulk semiconductor substrate, such as a semiconductor wafer. For example, substrate 10 includes silicon or other basic semiconductor materials such as germanium. Substrate 100 can be undoped or doped (e.g., p-type, n-type or a combination thereof). In some embodiments, substrate 10 includes an epitaxially grown semiconductor layer on a dielectric layer. The epitaxially grown semiconductor layer can be made of silicon germanium, silicon, germanium, one or more other suitable materials or a combination thereof. In some other embodiments, substrate 10 includes a multilayer structure. For example, substrate 10 includes a silicon germanium layer formed on a bulk silicon layer.

[0050] The semiconductor strips S1 and S2 may be formed / patterned by any suitable method. The following steps are provided to describe an applicable method for forming the semiconductor strips S1 and S2. In some embodiments, several sacrificial layers 11 and several channel layers 12 are alternately deposited above the substrate 10, and then a patterned hard mask layer 14 is deposited on the uppermost sacrificial layer. The sacrificial layer 11 and the channel layer 12 are then patterned using the patterned hard mask layer 14, thereby forming the semiconductor strips S1 and S2 on the substrate 10. The patterned hard mask layer 14 may be a silicon nitride layer or a patterned layer formed by one or more other suitable materials. The semiconductor strips S1 and S2 are separated by a first trench 15. In some embodiments, the semiconductor strips S1 and S2 extend in a first direction D1 (e.g., an X direction), such as Figure 2A In addition, Figure 2BAs shown, the semiconductor strips S1 and S2 are arranged along the second direction D2 (eg, the Y direction). That is, the semiconductor strips S1 and S2 are spaced apart from each other in the second direction D2 (spaced apart by the first trenches 15).

[0051] In order to simplify the figure, three channel layers 12 (e.g., a first channel layer 12-1, a second channel layer 12-2, and a third channel layer 12-3) and four sacrificial layers 11 (e.g., a first sacrificial layer 11-1, a second sacrificial layer 11-2, a third sacrificial layer 11-3, and a fourth sacrificial layer 11-4) are depicted here to show the material layers of each semiconductor strip S1 and S2, however, the number of sacrificial layers and channel layers is only for illustrative purposes, and the number of sacrificial layers and channel layers can be freely set as needed. Moreover, although two semiconductor strips S1 and S2 are shown here to simplify the illustration of the embodiment, more semiconductor strips can be formed on the substrate 10, and two adjacent semiconductor strips are separated by the first trench 15.

[0052] In addition, if Figure 2B As shown, in each semiconductor strip S1 and S2, the channel layers 12 (e.g., the first channel layer 12-1, the second channel layer 12-2, and the third channel layer 12-3) are spaced apart from each other along a third direction D3 (e.g., the Z direction) above the substrate 10. The third direction D3 is perpendicular to the first direction D1 and the second direction D2. In some embodiments of the present invention, the space (or distance, spacing) between the first channel layer 12-1 and the second channel layer 12-2 is greater than the space (or distance, spacing) between the second channel layer 12-2 and the third channel layer 12-3.

[0053] Specifically, Figure 2A and Figure 2BAs shown, the first sacrificial layer 11-1, the second sacrificial layer 11-2, the third sacrificial layer 11-3 and the fourth sacrificial layer 11-4 have thicknesses t1, t2, t3 and t4, respectively. The distance between the first channel layer 12-1 and the second channel layer 12-2 in the third direction D3 (for example, the two lowermost channel layers in this example) is defined as a first spacing, and the first spacing is equal to the thickness t2 of the second sacrificial layer 11-2. The distance between the second channel layer 12-2 and the third channel layer 12-3 (for example, the two uppermost channel layers in this example) in the third direction D3 is defined as a second spacing, and the second spacing is equal to the thickness t3 of the third sacrificial layer 11-3. According to some embodiments of the present invention, the first spacing (for example, equal to the thickness t2) is greater than the second spacing (for example, equal to the thickness t3) (t2>t3). In addition, the thickness t1 of the first sacrificial layer 11-1 may be equal to or greater than the thickness t2 of the second sacrificial layer 11-2, and the thickness t4 of the fourth sacrificial layer 11-4 may be equal to or greater than the thickness t3 of the third sacrificial layer 11-3. In addition, the thickness t1 of the first sacrificial layer 11-1 may be less than the thickness t2 of the second sacrificial layer 11-2, and the thickness t4 of the fourth sacrificial layer 11-4 may be less than the thickness t3 of the third sacrificial layer 11-3. Of course, when the thickness t1 of the first sacrificial layer 11-1 is equal to or greater than the thickness t2 of the second sacrificial layer 11-2, it will be easier to deposit the gate material between the channel layer 12-1 and the substrate 10, and it will be easier to allow the gate material to fill the space between the channel layer 12-1 and the substrate 10. In addition, when there are more than three channel layers, the thickness t2 of the second sacrificial layer 11-2 can be greater than, for example, the thickness of the fourth sacrificial layer (for example, there is also a fourth channel layer on the fourth sacrificial layer), or the thickness t2 of the second sacrificial layer 11-2 can also be greater than, for example, the thickness of the fifth sacrificial layer (for example, there are also a fifth sacrificial layer and a fifth channel layer on the fourth channel layer), and so on.

[0054] In some embodiments, the channel layer 12 includes one or more elements selected from Group IV semiconductor materials, such as Si (intrinsic Si or lightly doped Si), Ge (intrinsic Ge or lightly doped Ge), SiGe, or compounds including tin or lead. In some embodiments, the channel layer 12 includes a compound formed by elements selected from Group III-V semiconductor materials, such as GaAs, InAs, or InSb. It should be noted that the channel layer 12 of the present invention is not limited to including the aforementioned materials, but may also be other materials or include other materials.

[0055] In addition, the channel layer 12 in one of the semiconductor strips is made of the same material or the same compound of two or more elements having the same molar ratio. In some embodiments, the channel layer 12 in one of the semiconductor strips is made of silicon (Si). In some other embodiments, the channel layer 12 in one of the semiconductor strips is made of silicon germanium, wherein the molar ratio of silicon to germanium in each channel layer 12 is the same. For example, the channel layers 12 in one of the semiconductor strips are respectively made of Si and Ge. (1-Z) Ge Z 、Si (1-Y) Ge Y 、Si (1-X) Ge X The channel layer 12 is formed by a plurality of channels 12 and a plurality of channels 12 formed by a plurality of channels 12. The channel layer 12 is formed by a plurality of channels 12 and a plurality of channels 12 are ...

[0056] Next, refer to Figure 3A and Figure 3B In some embodiments, an insulating layer 16 is deposited over the semiconductor strips S1 and S2 and fills the first trench 15 between the semiconductor strips S1 and S2. A planarization process such as a chemical mechanical polishing (CMP) process is performed to remove excess portions of the insulating layer 16 over the patterned hard mask layer 14 ( Figure 3A and 3B The insulating layer 16 above the semiconductor strips (strips) S1 and S2 has been removed). Then, a patterned mask 18 can be formed on the patterned hard mask layer 14, and the semiconductor strips S1 and S2 can be (optionally) patterned to form second trenches 19, thereby defining several multi-layer fins covered by the patterned mask 18. The number of multi-layer fins depends on the design requirements in the application. Figure 3A As shown, two second trenches 19 extending in the second direction D2 define three multi-layer fins, and in order to simplify the illustration of the embodiment, one multi-layer fin M1 having a full width in the first direction D1 is shown. Figure 3B As shown, a patterned mask 18 is formed on the multi-layer fins M1 and M2 , wherein the multi-layer fins M1 and M2 are spaced apart from each other in a second direction D2 (eg, the Y direction).

[0057] In some embodiments, the patterned mask 18 may include an organic planarization layer, an anti-reflective coating (ARC) film, a photoresist layer, or other suitable materials. The patterned mask 18 may be applied in different layout configurations to define the number and length of the multilayer fins M1 and M2. The length L1 of the multilayer fin M1 in the first direction D1 is Figure 3A Shown in.

[0058] To form a nanosheet transistor of a semiconductor structure according to some embodiments of the present invention, the sacrificial layer 11 in the multi-layer fin must be removed, and then a gate structure is formed across the selected multi-layer fin and around the channel layer of the selected multi-layer fin.

[0059] The following is an applicable process (i.e., Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A and Figure 6B ) is used to illustrate the removal of the sacrificial layer 11 in the multi-layer fin.

[0060] refer to Figure 4A and Figure 4B In some embodiments, the patterned mask 18 is removed, and the material of the patterned hard mask layer 14 is deposited on the multi-layer fins M1 and M2 and fills the second trench 19. A step such as a chemical mechanical polishing (CMP) process may be performed to remove an excess portion of the insulating layer 16 above the insulating layer 16, thereby exposing the insulating layer 16. Figure 4A As shown, the material of the patterned hard mask layer 14 fills the second trench 19 between the multi-layer fins arranged separately along the first direction D1. Figure 4B As shown, the insulating layer 16 filling the first trench 15 is exposed between the multi-layer fins M1 and M2 separately arranged along the second direction D2.

[0061] Next, refer to Figure 5A and Figure 5B In some embodiments, the insulating layer 16 is removed from the first trench 15. After the insulating layer 16 is removed, the multi-layer fins M1 and M2 on two opposite sidewalls of the sacrificial layer 11 and the channel layer 12 are exposed in the first trench 15 ( Figure 5B ), and the other two opposite sidewalls of the sacrificial layer 11 and the channel layer 12 of the multi-layer fins M1 and M2 are covered by the material of the patterned hard mask layer 14 filled in the second trench 19.

[0062] Specifically, in Figure 5BIn the multi-layer fins M1 and M2 shown, the sidewall 11-1S of the first sacrificial layer 11-1, the sidewall 12-1S of the first channel layer 12-1, the sidewall 11-2S of the second sacrificial layer 11-2, the sidewall 12-2S of the second channel layer 12-2, the sidewall 11-3S of the third sacrificial layer 11-3, the sidewall 12-3S of the third channel layer 12-, the sidewall 11-4S of the fourth sacrificial layer 11-4, and the sidewall 14-S of the patterned hard mask layer 14 are exposed through the first groove 15. In addition, taking the multi-layer fin M1 as an example, the sidewall 11-1E of the first sacrificial layer 11-1, the sidewall 12-1E of the first channel layer 12-1, the sidewall 11-2E of the second sacrificial layer 11-2, the sidewall 12-2E of the second channel layer 12-2, the sidewall 11-3E of the third sacrificial layer 11-3, the sidewall 12-3E of the third channel layer 12-3, and the sidewall 11-4E of the fourth sacrificial layer 11-4 are covered by the material of the patterned hard mask layer 14 filled in the second trench 19. That is, two opposite sidewalls (e.g., sidewalls 12-1E, 12-2E, and 12-3E) of the channel layer 12 of the multi-layer fins M1 and M2 are fixed (or anchored) by the material of the patterned hard mask layer 14 in the second trench 19. The sidewalls 11 -S include a sidewall 11 - 1S of the first sacrificial layer 11 - 1 , a sidewall 11 - 2S of the second sacrificial layer 11 - 2 , a sidewall 11 - 3S of the third sacrificial layer 11 - 3 , and a sidewall 11 - 4S of the fourth sacrificial layer 11 - 4 .

[0063] Next, refer to Fig. 6A and Figure 6B In some embodiments, the sacrificial layer 11 (including the first sacrificial layer 11-1, the second sacrificial layer 11-2, the third sacrificial layer 11-3 and the fourth sacrificial layer 11-4) is removed from the multi-layer fins M1 and M2 to form the empty spaces 1110, 1120, 1130 and 1140 (such as Fig. 6A As shown). The sacrificial layer 11 may be removed using an isotropic dry or wet etching process that is selective to the channel layer 12. Figure 6B In the embodiment, the channel layer 12 in the multi-layer fins M1 and M2 appears to be floating. However, the material of the patterned hard mask layer 14 in the second trench 19 fixes both ends of the channel layer 12. Fig. 6A As clearly shown, two opposing sidewalls (eg, sidewalls 12 - 1E, 12 - 2E, and 12 - 3E) of the channel layer 12 of the multi-layer fins M1 and M2 are fixed to the material of the patterned hard mask layer 14 in the second trench 19 .

[0064] After removing the sacrificial layer 11 (eg, SiGe layer), a gate structure is formed across the selected multi-layer fin and around the channel layer of the selected multi-layer fin. A suitable process (eg, Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A and Fig. 9B ), to illustrate the formation of a gate structure in a multi-layer fin.

[0065] Reference Fig. 7A and Figure 7B , according to some embodiments, a portion of the patterned hard mask layer 14 above the third channel layer 12-3 (including a portion of the material of the patterned hard mask layer 14 and the second trench 19) is removed. Then, a dummy gate stack 23 is formed on the selected multi-layer fin, and then a spacer 24 is formed on the sidewall of the dummy gate stack 23, thereby defining an area for forming a nanosheet stack. In some embodiments, the dummy gate stack 23 may include silicon (such as polysilicon) or other suitable materials. The dummy gate stack 23 may be a single-layer or multi-layer structure. The spacer 24 may include a low-k (low dielectric constant) dielectric material, such as silicon carbon nitride (SiBCN), silicon oxycarbonitride (SiOCN), or silicon oxynitride (SiON). The spacer 24 may be a single-layer or multi-layer structure.

[0066] In addition, if Fig. 7A As shown, in this embodiment, as an example, three regions for forming three nanosheet stacks arranged along the first direction D1 are shown. Figure 7B As shown, for the sake of example, each dummy gate stack 23 extending in the second direction D2 and crossing over two multi-layer fins M1 and M2 is shown. Fig. 7A and Figure 7B The regions for forming the nanosheet stack and the two multi-layer fins intersected by the dummy gate stack 23 are shown for illustration only. It should be noted that the present invention is not limited to Fig. 7A and Figure 7B The intermediate structure in .

[0067] Next, refer to Fig. 8A and Figure 8B , remove the dummy gate stack 23. The remaining spacers 24 define an area for forming a gate structure surrounding the channel layer 12. In some embodiments, each gate structure includes a gate dielectric layer 21 and a gate electrode GE (refer to Fig.9A and Fig. 9B ). After removing the dummy gate stack 23, a gate dielectric layer 21 is formed to surround the corresponding channel layer 12. Specifically, as Fig. 8A and Figure 8BAs shown, gate dielectric layers 211, 212 and 213 are formed on two opposite sidewalls, the top surface and the bottom surface of the channel layers 12-1, 12-2 and 12-3, respectively. Moreover, in some embodiments, the gate dielectric layer 21 includes one or more high-k (high-k, high dielectric constant) dielectric materials, such as dielectric materials with a dielectric constant (k) greater than the dielectric constant of silicon dioxide, wherein the dielectric constant of silicon dioxide is about 3.7 to 3.9. The thickness of the gate dielectric layers 211, 212 and 213 can be the same or different, for example, slightly different. The gate electrode is also called a gate.

[0068] Next, refer to Fig.9A and Fig. 9B , the gate electrode GE fills the area defined by the spacer 24. Each gate electrode GE is formed at least on the sidewalls of the gate dielectric layer 21 and the top surface of the uppermost gate dielectric layer 213 of the gate dielectric layer 21. After the gate electrode GE is formed, in the following description, the multi-layer fins M1 and M2 and the portion of the gate electrode GE above the multi-layer fins M1 and M2 may be referred to as a semiconductor stack M1. G and M2 G Furthermore, after the gate electrode GE is formed, the spacer 24 may be removed.

[0069] In some embodiments, Fig.9A and Fig. 9B As shown, in the defined area, the gate electrode GE completely fills the empty space between the gate dielectric layer 21 and the empty space between the bottom channel layer 12-1 and the substrate 10. However, the present invention is not limited to the intermediate structure herein. In some other embodiments, the gate electrode GE may not completely fill the empty space around the bottom channel layer 12-1.

[0070] According to an embodiment of the present invention, each gate structure may include a gate dielectric layer 21 and a gate electrode GE. In some embodiments described above, the gate electrode GE of the gate structure may not include a work function tuning layer. However, in some other embodiments, the gate electrode GE may include a work function tuning layer 26 and a metal filling layer 27.

[0071] Fig.10 is a cross-sectional view of a semiconductor structure according to some embodiments, which depicts a work function tuning layer 26 surrounding a gate dielectric layer 21 and a metal filling layer 27 surrounding the work function tuning layer 26. In some embodiments, the gate dielectric layer 21 may electrically insulate the channel layer 12 from the gate electrode GE, wherein the gate electrode GE may include the metal filling layer 27, or a combination of the work function tuning metal layer 26 and the metal filling layer 27.

[0072] The work function tuning layer 26 of the gate electrode GE can be used to provide the desired work function for the nanosheet transistor to enhance electrical performance including improved threshold voltage. In some embodiments, the work function tuning layer 26 includes titanium nitride, tantalum, tantalum nitride, one or more other suitable materials or combinations thereof. Moreover, in some other embodiments, the work function tuning layer 26 is an aluminum-containing layer. For example, the aluminum-containing layer includes TiAlC, TiAlO, TiAlN, one or more other suitable materials or combinations thereof. In addition, in some embodiments, the work function tuning layer 26 may include metals, metal carbides, metal nitrides, other suitable materials or combinations thereof. For example, the work function tuning layer 26 includes tantalum nitride, tungsten nitride, titanium, titanium nitride, other suitable materials or combinations thereof. The work function tuning layer 26 can be deposited using an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an electroplating process, an electroless plating process, one or more other applicable processes or combinations thereof.

[0073] In some embodiments, the metal filling layer 27 may fill the space between adjacent work function tuning layers 261, 262, and 263. Fig.9A , Fig. 9B and Fig.10 However, the present invention is not limited to those configurations of the metal filling layer 27. The thicknesses of the work function tuning layers 261, 262, and 263 may be the same or different, for example, slightly different. In some other embodiments, the semiconductor stack (e.g., M1 ) is completely filled with the metal filling layer 27. G and M2 G ), but the semiconductor stack (e.g., M1 G and M2 G ) may not be completely filled with the metal filling layer 27 (not shown). As long as the thickness of the work function tuning layer and the metal filling layer surrounding the lower channel layer (e.g., the lowest channel layer) is similar to the thickness surrounding the other channel layers, the nanosheet transistor (e.g., M1) in the semiconductor stack can be improved. G or M2 G ) of the electrical properties (e.g., uniform threshold voltage of the nanosheet transistor). In this embodiment, in one of the semiconductor stacks (e.g., semiconductor stack M1 G) in the semiconductor stack (e.g., the space between the adjacent work function tuning layers (e.g., the work function tuning layer 261 of the channel layer 12-1 and the work function tuning layer 262 of the channel layer 12-2) is filled with a metal filling layer (e.g., the metal filling layer 27 between the work function tuning layer 261 and the work function tuning layer 261); or / and, in one of the semiconductor stacks (e.g., the semiconductor stack M1 G ) is filled with two gate dielectric layers (e.g., gate dielectric layer 213 of channel layer 12-3 and gate dielectric layer 212 of channel layer 12-2) and two work function tuning layers (e.g., work function tuning layer 263 of channel layer 12-3 and work function tuning layer 262 of channel layer 12-2). That is, both methods can be used at the same time, or any one of them can be selected.

[0074] In addition, in some embodiments, the metal filling layer 27 may be made of or include tungsten, aluminum, copper, cobalt, one or more other suitable materials, or a combination thereof. The metal filling layer 27 may be deposited using an ALD process, a PVD process, a CVD process, an electroplating process, an electroless plating process, one or more other suitable processes, or a combination thereof.

[0075] In the formation of Fig.9A , Fig. 9B and Fig.10 After the structure shown, subsequent processes are performed to complete the FET structure including the nanosheet transistor. For example, according to some embodiments of the present invention, a source / drain feature (not shown) is formed to contact the semiconductor stack M1. G and M2 G The channel layer 12 is then formed, and source / drain contacts and gate contacts are then formed. The details of the subsequent processes for forming a FET structure including a nanosheet transistor are not described herein.

[0076] In the current manufacturing process for forming a FET nanosheet stack, high multilayered fins (e.g., M1 and M2) are formed, and it is difficult to fill the empty space at a deeper position with the required material (e.g., one or more), such as filling the empty space near the bottom of the multilayer fin with the material of the gate electrode. After the gate electrode GE is formed, this will lead to significant differences in electrical performance between the nanosheet transistors in each semiconductor stack. Specifically, during the deposition of the gate electrode GE, the GE material layer (e.g., a metal filling layer, or a combination of a work function tuning layer and a metal filling layer, which may also be referred to as a gate material or gate material layer) around the bottommost channel layer will be much thinner than the layers around the other communication layers, and may not even completely surround the bottommost channel layer. The thinner the GE material layer, the greater the threshold voltage of the nanosheet transistor. Therefore, the thinner GE material layer surrounding the bottommost channel layer results in a higher threshold voltage of the bottommost nanosheet transistor, thereby causing significant differences in threshold voltage between the nanosheet transistors in each semiconductor stack. According to some embodiments of the present invention, at least the space around the bottom channel layer is expanded to solve the difficulty of depositing the GE material layer (such as a metal layer, or a combination of a work function tuning layer and a metal layer) around the bottom channel layer. Therefore, the difference in electrical performance between the nanosheet transistors in each semiconductor stack can be significantly reduced. For example, according to some embodiments, a more uniform threshold voltage of the nanosheet transistors including the channel layers 12-1, 12-2, and 12-3 in each semiconductor stack can be obtained.

[0077] Fig.11A The IV (drain current versus gate voltage) characteristics of a semiconductor stack including nanosheet transistors with non-uniform threshold voltage are schematically shown. Fig.11A The circled area on the IV curve 11-I in FIG. 1 may be caused by the higher threshold voltage of the lowest nanosheet transistor in the semiconductor stack. For example, the first nanosheet transistor (including the lowest channel layer in the semiconductor stack) has a threshold voltage of about 25 V, and the other nanosheet transistors (including other channel layers) have a threshold voltage of about 20 V. When the voltage applied to the gate electrode increases, a flat portion is shown in the middle of the IV curve 11-I, such as Fig.11A The circled flat part of the Fig. 11B Schematically illustrates IV (drain current versus gate voltage) characteristics of a semiconductor stack including nanosheet transistors with uniform threshold voltage according to some embodiments. Fig.11A Compared with the IV curve shown in 11-I, Fig. 11B The drain current of the IV curve 11 -II shown gradually and smoothly increases with the increase in the voltage applied to the gate electrode, and no flat portion is shown in the middle of the IV curve 11 -II.

[0078] In addition, if Fig. 9B and Fig.10 As shown, in some embodiments, the first spacing SP1 (along the third direction D3) between the two lowest channel layers (e.g., the channel layers 12-1 and 12-2) is greater than the second spacing SP2 (SP1>SP2) between the two highest channel layers (e.g., the channel layers 12-2 and 12-3), thereby reducing the spacing between each semiconductor stack (M1 G or M2 G ) includes a threshold voltage difference (value) between the nanosheet transistors of the channel layer. Therefore, according to some embodiments, each semiconductor stack (M1) can be obtained. G or M2 G ) includes a more uniform threshold voltage of a nanosheet transistor including channel layers 12-1, 12-2, and 12-3. In some embodiments, the difference between the first spacing SP1 and the second spacing SP2 is greater than 5 nm. In some embodiments, the difference between the first spacing SP1 and the second spacing SP2 is in a range of about 5 nm to about 30 nm (greater than or equal to 5 nm and less than or equal to 30 nm). The difference within this range can ensure that the threshold voltage remains uniform while minimizing the increase in the height of the semiconductor structure.

[0079] In addition to changing the spacing between adjacent channel layers in each semiconductor stack as described in the above embodiments, the spacing between adjacent channel layers in each semiconductor stack (M1) can also be changed. G or M2 G ) to improve the electrical performance of nanosheet transistors in semiconductor stacks.

[0080] Fig.12 1 is a cross-sectional view of a semiconductor structure according to some embodiments. Each of the multi-layer fins M1 and M2 (extending in the first direction D1) includes several channel layers alternating on the substrate 10. In addition, the gate dielectric layer 21 surrounds the corresponding channel layer 12, and the gate electrode GE extends in the second direction D2 and crosses the multi-layer fins M1 and M2 to form a semiconductor stack M1. G and M2 G In one example, if Fig.12 As shown, the first channel layer 12-1, the second channel layer 12-2 and the third channel layer 12-3 are alternately arranged above the substrate 10, and the gate dielectric layers 211, 212 and the gate dielectric layer 213 surround the first channel layer 12-1, the second channel layer 12-2 and the third channel layer 12-3 respectively. Moreover, the work function tuning layers 261, 262 and 263 of the gate electrode GE surround the corresponding gate dielectric layers 211, 212 and 213, and the metal filling layer 27 is filled between the work function tuning layers 261, 262 and 263.

[0081] exist Fig.10and Fig.12 In the embodiment, the same or similar reference numerals or reference signs represent the same or similar elements. It should be noted that for the aforementioned embodiments, Fig.12 The structure and materials of the components in Fig.10 Therefore, the details of the components are not repeated here. Fig.12 The method for the semiconductor structure in is similar to the method for the previously described embodiments and the details will not be repeated here.

[0082] In some embodiments, Fig.9A , 9B As shown in 10, the semiconductor stack M1 G and M2 G The channel layer 12 in one of the semiconductor stacks is made of the same material or compound including elements having the same molar ratio, wherein the space between adjacent channel layers in each semiconductor stack is changed (e.g., SP1>SP2) to improve the electrical performance of the nanosheet transistor in the semiconductor stack. However, the present invention is not limited thereto. The electrical performance of the nanosheet transistor can be improved by modifying the composition of the channel layer in each semiconductor stack without changing the spacing (interval, space or distance) between adjacent channel layers.

[0083] In some embodiments, Fig.12 As shown, the spacing between adjacent channel layers 12 in each semiconductor stack is the same (eg, SP1=SP2). G and M2 G The channel layer 12 in one of them may include a compound formed by at least two elements having different molar ratios. In some embodiments, the channel layer 12 includes a compound formed by at least two elements selected from Group IV semiconductor materials, such as Si, Ge, SiGe, or a compound including Sn or Pb. In some embodiments, the channel layer 12 includes a compound formed by an element selected from Group III-V semiconductor materials, such as GaAs, InAs, or InSb. It should be noted that the channel layer 12 of the present invention is not limited to the above materials. Several channel layers 12 can be roughly aligned up and down, for example, have roughly the same size, and their projections on the substrate 10 roughly overlap.

[0084] In some embodiments, the semiconductor stack M1 G and M2 GThe bottom channel layer (such as channel layer 12-1) in one of the channels has a higher germanium content than the germanium content in any other channel layer (such as channel layer 12-2 and channel layer 12-3). In some embodiments, the bottom channel layer (such as channel layer 12-1) contains no more than 0.7 molar ratio of germanium. In some other embodiments, the germanium content of the channel layer 12 decreases (gradually) as the distance (also referred to as the vertical distance) between the channel layer 12 and the substrate 10 in the third direction D3 (e.g., Z direction) increases (i.e., the germanium content of the channel layer 12 is smaller the farther away from the substrate 10).

[0085] In addition, in some embodiments, the channel layer 12 is made of silicon germanium, and the molar ratio of silicon to germanium is different in each channel layer 12. For example, the semiconductor stack M1 G and M2 G The channel layers 12-1, 12-2 and 12-3 in one of the channels are respectively made of Si (1-Z) Ge Z 、Si (1-Y) Ge Y 、Si (1-X) Ge X composition, wherein Z>Y>X. In some embodiments, Z is greater than Y and less than 0.7 (0.7>Z>Y), Y is greater than 0 and less than Z (Z>Y>0), and X is greater than 0 (Y>X>0). In some embodiments, the difference between Z and Y is in the range of about 0.05 to about 0.5 (including 0.05 and 0.5), and the difference between Y and X is in the range of about 0.05 to about 0.5 (including 0.05 and 0.5). This arrangement can make the material ratio in each channel layer appropriate to ensure the electrical properties of the semiconductor, while making the composition between each channel layer different, ensuring the uniformity of the threshold voltage when the first spacing is equal to the second spacing. According to some embodiments of the present invention, the higher the germanium content of the channel layer, the lower the threshold voltage of the nanosheet transistor. For example, the molar ratio of Ge to Si in the channel layer 12-1 is Z: (1-Z), where Z can be greater than (1-Z). In the embodiment of the present invention, for example, the germanium content of the channel layer 12-1 may be greater than the germanium content of the channel layer 12-2, and the germanium content of the channel layer 12-1 may be greater than the germanium content of the channel layer 12-3; the germanium content of the channel layer 12-2 may be greater than the germanium content of the channel layer 12-3.

[0086] Therefore, according to some of the above embodiments, the bottom channel layer (e.g., channel layer 12-1) in a semiconductor stack has a higher germanium content than any other channel layer (e.g., channel layers 12-2 and 12-3). As described above, since it is difficult to fill the empty space near the bottom of the multi-layer fin, and the lowest channel layer will be surrounded by a thinner GE material layer (which will cause a higher threshold voltage), there is a defect of a threshold voltage difference between the two. The nanosheet transistor (e.g., M1) in the semiconductor stack can be compensated by increasing the germanium content of the bottom channel layer (e.g., the molar ratio of germanium to silicon in the SiGe channel layer) to reduce the threshold voltage. G or M2 G According to some embodiments, it is thus possible to obtain a semiconductor stack having one (eg, M1 G and M2 G ) includes a more uniform threshold voltage of a nanosheet transistor including channel layers 12-1, 12-2, and 12-3.

[0087] In addition, according to some embodiments of the present invention, the electrical performance of nanosheet transistors in a semiconductor stack (e.g., uniform threshold voltage of nanosheet transistors) can be improved by changing the spacing between adjacent channel layers in the semiconductor stack and changing the composition of the channel layers in the semiconductor stack.

[0088] Fig.13 is a cross-sectional view of a semiconductor structure according to some embodiments of the present invention. In some embodiments, one of the semiconductor stacks (eg, M1 G and M2 G ) includes a higher germanium content than other channel layers in the semiconductor stack, and a spacing between adjacent channel layers in one of the semiconductor stacks (e.g., M1 G and M2 G ) is also changed to expand the space around the lowest channel layer. For example, the spacing between the two lowest channel layers (along the third direction D3) is greater than the spacing between the two uppermost channel layers.

[0089] like Fig.13 As shown, semiconductor stack M1 G and M2 G The channel layers 12-1, 12-2 and 12-3 in one of the channels are respectively made of Si (1-Z) Ge Z 、Si (1-Y) Ge Y 、Si (1-X) Ge X, where Z>Y>X. Moreover, the first spacing SP1 between the first channel layer 12-1 and the second channel layer 12-2 (i.e., the two bottom channel layers) along the third direction D3 is greater than the second spacing SP2 between the second channel layer 12-2 and the third channel layer 12-3 (i.e., the two top channel layers) along the third direction D3 (SP1>SP2). Therefore, according to some embodiments of the present invention, a uniform threshold voltage of the nanosheet transistor including the channel layers 12-1, 12-2, and 12-3 in each semiconductor stack can be obtained. In this embodiment, either SP1>SP2 or the smaller germanium content of the channel layer 12 farther away from the substrate 10 can be used to achieve the purpose of the present invention, or the two can be used in combination to achieve the purpose of the present invention. Among them, the requirements for materials when using the scheme of SP1>SP2 are lower, and existing materials can be used for manufacturing. The scheme of using the smaller germanium content of the channel layer 12 farther away from the substrate 10 does not require special setting of the spacing between the channel layers, the process is simpler, and the height of the semiconductor structure will not increase, thereby reducing the size of the semiconductor structure. The solution of using both together can make the height increase relatively small and it is easier to obtain a uniform threshold voltage.

[0090] In the formation of Fig.12 and Fig.13 After the structure shown, subsequent processes are performed to complete the FET structure including the nanosheet transistor. For example, according to some embodiments of the present invention, a source / drain feature (not shown) is formed to contact the semiconductor stack M1. G and M2 G The channel layer 12 is then formed, and source / drain contacts and gate contacts are then formed. The details of the subsequent processes for forming a FET structure including a nanosheet transistor are not described herein.

[0091] It should be noted that the details of the structure of the embodiment are provided for example, and the details of the description of the embodiment are not intended to limit the present invention. It should be noted that not all embodiments of the present invention are shown. Modifications and variations can be made without departing from the spirit of the present invention to meet the requirements of practical applications. Therefore, there may be other embodiments of the present invention that are not specifically shown. In addition, the drawings are simplified to clearly illustrate the embodiments. The dimensions and proportions in the figures may not be proportional to the actual product. Therefore, the description and drawings should be considered illustrative rather than restrictive.

[0092] Those skilled in the art will readily observe that many modifications and variations of the apparatus and method can be made while maintaining the teachings of the present invention.Accordingly, the above disclosure should be interpreted as being limited only by the metes and bounds of the appended claims.

Claims

1. A semiconductor structure, characterized in that: include: Semiconductor stacks are provided above the substrate, wherein each of the semiconductor stacks extends in a first direction and adjacent semiconductor stacks are spaced apart from each other in a second direction different from the first direction, wherein each of the semiconductor stacks comprises: channel layers located above the substrate and spaced apart from each other in a third direction, wherein the third direction is perpendicular to the first direction and the second direction; and A gate structure, comprising: a gate dielectric layer surrounding the corresponding channel layer; and a gate electrode along the sidewalls of the gate dielectric layer and the top surface of the uppermost gate dielectric layer of the gate dielectric layer, the gate electrode comprising: a work function tuning layer surrounding the gate dielectric layer; and a metal filling layer surrounding the work function tuning layer; Wherein, a distance between two lowermost channel layers of the channel layer along the third direction is greater than a distance between two uppermost channel layers of the channel layer along the third direction.

2. The semiconductor structure according to claim 1, wherein: A first space between work function tuning layers around an upper channel layer in one of the semiconductor stacks is completely filled with the metal filling layer, and a second space between work function tuning layers around a lower channel layer in one of the semiconductor stacks is not completely filled with the metal filling layer.

3. The semiconductor structure according to claim 1, wherein: The spacing between the two lowermost channel layers along the third direction is defined as a first spacing, the spacing between the two uppermost channel layers along the third direction is defined as a second spacing, and the difference between the first spacing and the second spacing is in the range of 5nm to 30nm.

4. The semiconductor structure according to claim 1, wherein: The space between the two uppermost channel layers in one of the semiconductor stacks is filled with two of the gate dielectric layers and two of the work function tuning layers.

5. The semiconductor structure according to claim 2, wherein: The channel layer in one of the semiconductor stacks is formed of the same material or the same compound of two or more elements having the same molar ratio; or, the channel layer in one of the semiconductor stacks is formed of the same compound having two or more elements having different molar ratios.

6. The semiconductor structure according to claim 2, wherein: The channel layers in one of the semiconductor stacks include silicon germanium, and a lowermost one of the channel layers includes a higher germanium content than other channel layers in the semiconductor stack.

7. The semiconductor structure according to claim 2, wherein: The channel layer includes one or more elements from Group IV semiconductor materials; or, the channel layer includes one of Group III-V semiconductor materials.

8. The semiconductor structure according to claim 2, wherein: The channel layer includes: a first channel layer, over the substrate; a second channel layer, above the first channel layer, wherein a distance between the first channel layer and the second channel layer in a first direction is defined as a first spacing; and a third channel layer, above the second channel layer, wherein a distance between the second channel layer and the third channel layer in the first direction is defined as a second spacing, The first spacing is greater than the second spacing.

9. The semiconductor structure according to claim 8, characterized in that The first channel layer, the second channel layer, and the third channel layer are formed of silicon or a silicon-containing material having a same element molar ratio.

10. The semiconductor structure according to claim 8, wherein: The first channel layer, the second channel layer and the third channel layer include Si (1-Z) Ge Z 、Si (1-Y) Ge Y 、Si (1-X) Ge X A material wherein Z is greater than Y and less than 0.7, Y is greater than 0 and greater than X, and X is greater than 0.

11. The semiconductor structure according to claim 10, characterized in that The difference between Z and Y is in the range of 0.05 to 0.5, and the difference between Y and X is in the range of 0.05 to 0.

5.

12. The semiconductor structure according to claim 1, wherein: The gate dielectric layer includes a high-k dielectric material having a greater dielectric constant than silicon dioxide.

13. A semiconductor structure, characterized in that: include: Semiconductor stacks are provided above the substrate, wherein each of the semiconductor stacks extends in a first direction and adjacent semiconductor stacks are spaced apart from each other in a second direction different from the first direction, wherein each of the semiconductor stacks comprises: channel layers located above the substrate and spaced apart from each other in the third direction, wherein the third direction is perpendicular to the first direction and the second direction; and A gate structure, comprising: a gate dielectric layer surrounding the corresponding channel layer; and a gate electrode along the sidewalls of the gate dielectric layer and the top surface of the uppermost gate dielectric layer of the gate dielectric layer, wherein the gate electrode comprises: a work function tuning layer surrounding the gate dielectric layer; and a metal filling layer surrounding the work function tuning layer; wherein a first space between work function tuning layers around an upper channel layer in one of the semiconductor stacks is completely filled with the metal filling layer, and a second space between work function tuning layers around a lower channel layer in one of the semiconductor stacks is not completely filled with the metal filling layer; Wherein a lowermost channel layer of the channel layers in the semiconductor stack comprises a higher germanium content than germanium contents in other corresponding channel layers in the semiconductor stack.

14. A semiconductor structure, characterized in that: include: Semiconductor stacks are provided above the substrate, wherein each of the semiconductor stacks extends in a first direction and adjacent semiconductor stacks are spaced apart from each other in a second direction different from the first direction, wherein each of the semiconductor stacks comprises: channel layers located above the substrate and spaced apart from each other in a third direction, wherein the third direction is perpendicular to the first direction and the second direction; and A gate structure, comprising: a gate dielectric layer surrounding the corresponding channel layer; and a gate electrode along the sidewalls of the gate dielectric layer and the top surface of the uppermost gate dielectric layer of the gate dielectric layer; Among them, the spacing between the two bottom channel layers along the third direction is defined as a first spacing, and the spacing between the two top channel layers along the third direction is defined as a second spacing. The first spacing is greater than the second spacing, and the difference between the first spacing and the second spacing is in the range of 5nm to 30nm.

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