Semiconductor device structure and manufacturing method thereof

Abstract

A method of manufacturing a semiconductor device structure includes forming a plurality of semiconductor layer stacks, each stack including a plurality of first semiconductor layers and a plurality of second layers alternately stacked with each other. Then, gate electrode structures are formed on each of the semiconductor layer stacks, each of the gate electrode structures including a gate spacer. An epitaxial layer is formed in an opening between each pair of adjacent semiconductor layer stacks. After the epitaxial layer is formed, an oxygen ion beam is applied to the gate spacer at an oblique angle to form an oxidized material having an oblique angle on the gate spacer. The oxidized material is then removed with a diluted hydrofluoric acid (HF) solution.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor technology, and more particularly to a semiconductor device structure and a manufacturing method thereof. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in integrated circuit (IC) materials and design have produced successive generations of integrated circuits (ICs), each with smaller and more complex circuits than the previous generation. In the evolution of integrated circuits (ICs), functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or line) that can be formed using a manufacturing process) has shrunk. This process of miniaturization can generally bring benefits by increasing production efficiency and reducing associated costs. This miniaturization presents new challenges. For example, transistors using nanowire channels have been proposed to achieve increased device density, greater carrier mobility, and drive current in devices. As device size decreases, there is a need to continuously improve the process and manufacturing of integrated circuits (ICs). Summary of the invention

[0003] The present invention aims to provide a semiconductor device structure and a manufacturing method thereof to solve at least one of the above problems.

[0004] In some embodiments, a method for manufacturing a semiconductor device structure is provided, comprising: forming a plurality of semiconductor layer stacks, each of the semiconductor layer stacks comprising a plurality of first layers and a plurality of second layers alternately stacked with each other; forming a gate electrode structure on each of the semiconductor layer stacks, each of the gate electrode structures comprising a gate spacer; forming an epitaxial source / drain feature component in an opening between each pair of adjacent ones in the semiconductor layer stack; applying an oxygen ion beam to the gate spacer at an inclined angle to form an oxide material on the gate spacer; and removing the oxide material with a dilute hydrofluoric acid (HF) solution.

[0005] In some embodiments, a method for manufacturing a semiconductor device structure is provided, including: removing a plurality of nodules formed on a gate spacer during formation of an epitaxial source / drain (S / D) feature in the semiconductor device structure, the method comprising: applying a plurality of directional oxygen ion beams at an inclined angle to oxidize the nodules, wherein the inclined angle is adjusted to prevent the oxygen ions from being applied to the epitaxial source / drain (S / D) feature; and removing the nodules that have been oxidized by the oxygen ions using a dilute hydrofluoric acid (HF) solution.

[0006] In some embodiments, a semiconductor device structure is provided, comprising: a pair of epitaxial source / drain regions; a channel region located between the epitaxial source / drain regions; and a gate structure located on the channel region, the gate structure comprising a gate spacer having one or more surface portions that are oxidized and etched. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1-Figure 8 Schematic perspective views showing various stages of fabricating a semiconductor device structure according to some embodiments.

[0008] Figure 9-Figure 21 According to some embodiments, Figure 8 Schematic cross-sectional view of various stages of manufacturing a semiconductor device structure taken at section AA.

[0009] Fig. 22 Show Fig.21 Magnified view of the area within the dashed box.

[0010] Fig.23 A flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0011] The reference numerals are as follows:

[0012] 100:Semiconductor device structure

[0013] 101: Base

[0014] 104: Semiconductor layer stack

[0015] 106: first semiconductor layer

[0016] 108: Second semiconductor layer

[0017] 110,110b: Mask structure

[0018] 110a: cushion layer

[0019] 112: Fin structure

[0020] 114,123: cushion

[0021] 116: Well area

[0022] 117: Coating layer

[0023] 118: Insulation material

[0024] 119: Lining

[0025] 120: Isolation Area

[0026] 121,125: Dielectric materials

[0027] 123: Groove

[0028] 127: Dielectric feature components

[0029] 130: Sacrificial gate structure

[0030] 132: Sacrificial gate dielectric layer

[0031] 134: Sacrificial gate electrode layer

[0032] 136: mask layer

[0033] 138: first layer; gate spacer; gate dielectric spacer

[0034] 138a: Oxidation

[0035] 139: Groove

[0036] 139b: Bottom

[0037] 140: Double layer structure

[0038] 144: Dielectric spacer layer

[0039] 146: epitaxial layer; epitaxial source / drain (S / D) feature component

[0040] 148: granulation; n-type granulation; p-type granulation; epitaxial granulation

[0041] 148a: Oxidized grains; Oxidized n-type grains; Oxidized p-type grains

[0042] 150: oxygen ion beam; directional oxygen ion beam

[0043] 152:Hydrofluoric acid (HF) solution

[0044] 162: Contact Etch Stop Layer (CESL)

[0045] 162a: first surface

[0046] 162b: Second surface

[0047] 163: First Interface

[0048] 164: Interlayer dielectric (ILD) layer

[0049] 165: Second interface

[0050] 173: Self-aligned contact layer

[0051] 180: Gate dielectric layer

[0052] 182: Gate electrode layer

[0053] 184: Silicide layer

[0054] 186: Source / Drain (S / D) Contact

[0055] 190: Replacement gate structure

[0056] 1000:Method

[0057] 1002,1004,1006,1008,1010,1012,1014,1016,1018,1020,1022,1024,1026,1028,1030,1032,1034,1036: Step Block

[0058] D1: vertical distance

[0059] D2,D3: Distance

[0060] W1: Width DETAILED DESCRIPTION

[0061] The following disclosure provides many different embodiments or examples to implement different characteristic components of the present invention. The following disclosure describes specific examples of each component and its arrangement in order to simplify the present disclosure. Of course, these are only examples and are not used to define the present invention. For example, if the following disclosure describes that a first characteristic component is formed on or above a second characteristic component, it means that it includes an embodiment in which the first characteristic component formed is in direct contact with the second characteristic component, and also includes an embodiment in which an additional characteristic component can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the present disclosure will repeat numbers and / or text in various different examples. Repetition is for the purpose of simplification and clarification, rather than listing and specifying the relationship between the various different embodiments and / or configurations discussed.

[0062] Furthermore, spatially related terms such as "under", "below", "lower", "over", "upper", etc. are used herein to easily express the relationship between a device or feature in the drawings shown in this specification and another device or feature. These spatially related terms not only cover the orientation shown in the drawings, but also cover different orientations of the device during use or operation. The device can have different orientations (rotated 90 degrees or other orientations) and the spatially related symbols used herein are also interpreted accordingly.

[0063] The present disclosure relates to semiconductor devices, and in particular to field-effect transistors (FETs), such as planar FETs, three-dimensional fin-line FETs (FinFETs), gate-all-around (GAA) devices (e.g., horizontal GAA (HGAA) FETs, vertical GAA (VGAA) FETs), vertical FETs (FETs), forksheet FETs, or complementary FETs (CFETs). Although the embodiments of the present disclosure are described with reference to GAA devices, some forms of the present disclosure may be implemented in other processes and / or other devices. It is easy for a person skilled in the art to understand that other modifications may be made within the scope of the present disclosure.

[0064] Figure 1-Figure 21 FIG. 1 shows an exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. It should be understood that additional embodiments of the above method may be Figure 1-Figure 21 Additional operating steps are provided before, during, and after the processes shown, and some of the operating steps described below may be replaced or removed. The order of the operating steps / processes is not limited and may be interchanged.

[0065] Figure 1-Figure 8 Schematic perspective views of various stages of fabricating a semiconductor device structure 100 are shown in accordance with some embodiments. Fig.23 A flow chart of a method 1000 of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure is shown. Figure 9-Figure 21 The semiconductor device 100 is schematically illustrated at various stages of fabrication according to the method 1000. It should be understood that additional steps may be provided before, during and / or after the method 1000, and that some of the steps described may be replaced, removed and / or modified in additional embodiments of the method 1000.

[0066] At step block 1002, a semiconductor device structure 100 is provided, which includes a semiconductor layer stack 104 formed on a substrate 101, such as Figure 1As shown. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material, such as but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide / (GaAsSb) and indium phosphide (InP). In one embodiment, the material of the substrate 101 is silicon. In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers and used for strengthening. In one form, the insulating layer is an oxygen-containing layer.

[0067] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants having p-type or n-type impurities). Depending on the circuit design, for example, the dopant may be boron for a p-type field effect transistor (p-type FET) and phosphorus for an n-type field effect transistor (n-type FET).

[0068] The semiconductor layer stack 104 includes semiconductor layers made of different materials to facilitate the formation of nanosheet channels in the multi-gate device. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108, and the first semiconductor layers 106 and the second semiconductor layers 108 are arranged parallel to each other. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etching selectivities and / or oxidation rates. For example, the first semiconductor layer 106 can be made of Si, and the second semiconductor layer 108 can be made of SiGe. In some examples, the first semiconductor layer 106 can be made of SiGe, and the second semiconductor layer 108 can be made of Si. In some embodiments, the first semiconductor layer 106 can be made of SiGe having a first Ge concentration range, and the second semiconductor layer 108 can be made of SiGe having a second Ge concentration range lower than or greater than the first Ge concentration range. In any case, the second semiconductor layer 108 may have a Ge concentration in a range of approximately 20 at. % (atomic percent) to 30 at. %.

[0069] The thickness of the first semiconductor layer 106 and the second semiconductor layer 108 can be changed according to application and / or device performance considerations. In some embodiments, the first semiconductor layer 106 and the second semiconductor layer 108 can each have a thickness in the range of about 5nm to 30nm. Each second semiconductor layer 108 can have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each first semiconductor layer 106 has a thickness in the range of about 10nm to 30nm, and each second semiconductor layer 108 has a thickness in the range of about 5nm to 20nm. The second semiconductor layer 108 will eventually be removed and used to define the vertical distance D1 between two adjacent channels of the semiconductor device structure 100.

[0070] The first semiconductor layer 106 or a portion thereof may form a nanosheet channel of the semiconductor device structure 100 in a subsequent manufacturing stage. The term "nanosheet" is used herein to refer to any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of this portion. Therefore, the above term refers to elongated material portions of circular and substantially circular cross-sections and beam-shaped or rod-shaped material portions, for example, including cylindrical or substantially rectangular cross-sections. The nanosheet channel of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanosheet transistor. The nanosheet transistor may be referred to as a nanosheet transistor, a nanowire transistor, a gate all-around (GAA) transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate surrounding the channel. The use of the first semiconductor layer 106 to define the channel of the semiconductor device structure 100 is further described below.

[0071] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of the film layer of the semiconductor layer stack 104 may be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. Figure 1 As shown, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, but it is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, depending on the predetermined number of nanosheet channels of each field effect transistor (FET). For example, the number of first semiconductor layers 106 (i.e., the number of channels) can be between 2 and 8.

[0072] At step block 1004, if Figure 2 As shown, a fin structure 112 is formed by a semiconductor layer stack 104. Each fin structure 112 has an upper portion including a first semiconductor layer 106 and a second semiconductor layer 108 and a well portion 116 formed by a substrate. Before forming the fin structure 112, a mask structure 110 is formed on the semiconductor layer stack 104. The mask structure 110 may include a pad layer 110a and a hard mask 110b. The pad layer 110a may be an oxygen-containing layer, such as a SiO2 layer. The hard mask 110b may be a nitrogen-containing layer, such as a Si3N4 layer. The mask structure 110 may be formed by any suitable deposition process, such as a chemical vapor deposition (CVD) process.

[0073] The fin structure 112 may be formed by patterning the mask structure 110 using one or more photolithography processes and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process may include a double patterning or multiple patterning process. In general, the double patterning or multiple patterning process combines the photolithography process with a self-alignment process, thereby allowing the formation of a pattern having a smaller pitch than that obtainable using a single direct photolithography process, for example. In an example of a multiple patterning process, a sacrificial layer may be formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structure 112. In any case, one or more etching processes form trenches 114 in unprotected areas through the mask structure 110, through the semiconductor layer stack and into the substrate 101, thereby leaving a plurality of extended fin structures 112. The width W1 of the fin structure 112 along the Y direction may be in a range of about 1.5 nm to 44 nm, for example, about 2 nm to 6 nm. The trench 114 may be etched using dry etching (e.g., reactive ion etching (RIE)), wet etching, and / or a combination thereof. Although two fin structures 112 are shown, the number of fin structures is not limited to two.

[0074] Figure 2 The fin structures 112 are also shown to have substantially vertical sidewalls, such that the widths of the fin structures 112 are substantially similar, and the shapes of the first semiconductor layer 106 and the second semiconductor layer 108 in the fin structures 112 are each rectangular. In some embodiments, the fin structures 112 may have tapered sidewalls, such that the width of each fin structure 112 increases continuously in a direction toward the substrate 101. In this case, each fin structure 112 in the first semiconductor layer 106 and the second semiconductor layer 108 may have different widths and be trapezoidal in shape.

[0075] At step block 1006 , after forming the fin structures 112 , an insulating material 118 is formed in the trenches 114 between the fin structures 112 . Figure 3 As shown. The insulating material 118 fills the trench 114 between adjacent fin structures 112 until the fin structure 112 is buried in the insulating material 118. Then, a planarization operation, such as a chemical mechanical polishing (CMP) process and / or an etch back process, is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), a low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD).

[0076] Thereafter, the insulating material 118 is recessed to form an isolation region 120. After the recessing, a portion of the fin structure 112 (e.g., the semiconductor layer stack 104) may protrude between adjacent isolation regions 120. The upper surface of the isolation region 120 may have a planar, convex, concave, or a combination thereof upper surface as shown. The recessing of the insulating material 118 exposes the trench 114 between adjacent fin structures 112. The isolation region 120 may be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. In one embodiment, the isolation region 120 is formed using dilute hydrofluoric acid (dHF), which is selective to the insulating material 118 above the semiconductor layer stack 104. After the recessing is completed, the upper surface of the insulating material 118 may be flush with or lower than the surface of the second semiconductor layer 108 (which is in contact with the well region portion 116 formed by the substrate 101).

[0077] At step block 1008, if Figure 4As shown, a cladding layer 117 can be formed on the exposed portion of the fin structure 112 by an epitaxial process. In some embodiments, a semiconductor liner (not shown) can be first formed above the fin structure 112, and then a cladding layer 117 can be formed above the semiconductor liner. The semiconductor liner can diffuse into the cladding layer 117 during the formation of the cladding layer 117. In other cases, the cladding layer 117 is in contact with the semiconductor layer stack 104. In some embodiments, the cladding layer 117 and the second semiconductor layer 108 include the same material with the same etching selectivity. For example, the cladding layer 117 and the second semiconductor layer 108 may be or include SiGe. The cladding layer 117 and the second semiconductor layer 108 can then be removed to create space for the gate electrode layer formed subsequently.

[0078] At step block 1010, a liner 119 is formed on the upper surface of the cladding layer 117 and the insulating material 118, such as Figure 5 As shown. The liner 119 may include a material with a k value lower than 7, such as SiO2, SiN, SiCN, SiOC or SiOCN. The liner 119 may be formed by a conformal process (eg, an ALD process). Then, a dielectric material 121 is formed in the trench 114 ( Figure 4 ) and on the liner 119. The dielectric material 121 may be an oxygen-containing material, such as an oxide, formed by flow chemical vapor deposition (FCVD). The oxygen-containing material may have a k value less than about 7, for example, less than about 3. A planarization process (e.g., a chemical mechanical polishing (CMP process)) may be performed to remove a portion of the liner 119 and a portion of the dielectric material 121 formed over the fin. After the planarization process, a portion of the cladding layer 117 disposed on the hard mask 110b is exposed.

[0079] Next, the liner 119 and the dielectric material 121 are recessed to the height of the topmost first semiconductor layer 106. For example, in some embodiments, after the recessing process, the upper surfaces of the liner 119 and the dielectric material 121 may be flush with the upper surface of the topmost first semiconductor layer 106. The recessing process may be a selective etching process that does not substantially affect the semiconductor material constituting the cladding layer 117. Due to the recessing process, trenches 123 are formed between the fin structures 112.

[0080] At step block 1012, if Figure 6 As shown, a dielectric material 125 is formed in the trench 123 ( Figure 5) and on the dielectric material 121 and the liner 119. The dielectric material 125 may include SiO2, SiN, SiC, SiCN, SiON, SiOCN, Al2O, AlN, AlON, ZrO, ZrN, ZrAlO, HfO or other suitable dielectric materials. In some embodiments, the dielectric material 125 includes a high-k dielectric material (e.g., a material with a k value greater than 7). The dielectric material 125 may be formed by any suitable process, such as a CVD, PECVD, FCVD or ALD process. A planarization process (e.g., a chemical mechanical polishing (CMP process)) is performed until the hard mask 110b of the mask structure 110 is exposed. The planarization process removes a portion of the dielectric material 125 and a portion of the cladding layer 117 disposed above the mask structure 110. The liner 119, the dielectric material 121, and the dielectric material 125 may be collectively referred to as a dielectric feature 127 or a hybrid fin. The dielectric features 127 are used to separate subsequently formed source / drain (S / D) epitaxial features from the adjacent gate electrode layer.

[0081] At step block 1014, the cladding layer 117 is recessed and the mask structure 110 is removed, such as Figure 7 As shown. The cladding layer 117 may be recessed by any suitable process, such as dry etching, wet etching, or a combination thereof. The recessing process may be controlled so that the remaining cladding layer 117 is substantially at the same height as the upper surface of the topmost first semiconductor layer 106 in the semiconductor layer stack 104. The etching process may be a selective etching process that does not substantially affect the dielectric material 125. The removal of the mask structure 110 may be performed by any suitable process, such as dry etching, wet etching, or a combination thereof.

[0082] At step block 1016, one or more sacrificial gate structures 130 (only two are shown) are formed over the semiconductor device structure 100, such as Figure 8As shown. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, followed by a patterning and etching process. For example, the patterning process includes a photolithography process (e.g., photolithography or electron beam lithography) (which may also include photoresist coating (e.g., spin coating), soft baking, photomask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., reactive ion etching (RIE)), wet etching, other etching methods, and / or combinations thereof.

[0083] By patterning the sacrificial gate structure 130, the semiconductor layer stack 104 of the fin structure 112 is partially exposed on two opposite sides of the sacrificial gate structure 130. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor device structure 100. The fin structure 112 partially exposed on two opposite sides of the sacrificial gate structure 130 defines the source / drain (S / D) region structure 100 of the semiconductor device. In some cases, some source / drain (S / D) regions may be shared between different transistors. For example, different regions of the source / drain (S / D) region may be connected together and implemented as a multifunctional transistor. Although two sacrificial gate structures 130 are shown, in some embodiments, more or fewer sacrificial gate structures 130 may be arranged along the X direction.

[0084] Next, gate spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. The gate spacers 138 may be formed by first depositing a compliant layer and then etching back to form the gate spacers 138. For example, the spacer material may be conformally disposed on the exposed surface of the semiconductor device structure 100. The compliant isolation material layer may be formed by an ALD process. Subsequently, the spacer material layer is anisotropically etched using, for example, reactive ion etching (RIE). During the anisotropic etching process, a majority of the spacer material layer is removed from horizontal surfaces (e.g., the top of the fin structure 112, the cladding layer 117, and the dielectric material 125), while leaving the gate spacers 138 on vertical surfaces (e.g., the sidewalls of the sacrificial gate structure 130). The gate spacers 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0085] In some embodiments where the capping layer 117 and the dielectric features 127 are not present, portions of the sacrificial gate structure 130 and portions of the gate spacers 138 are formed on the insulating material 118 , and gaps are formed between the exposed portions of the fin structures 112 .

[0086] Figure 9-Figure 21 According to some embodiments, Figure 8 1 is a cross-sectional view of various stages of manufacturing the semiconductor device structure 100 of the cross section AA. The cross section AA is located in the plane of the fin structure 112 along the X direction. At step block 1018, the exposed portion of the semiconductor layer stack 104 of the fin structure 112, the exposed portion of the capping layer 117, and the exposed portion of the dielectric material 125 not covered by the sacrificial gate structure 130 and the gate spacer 138 are removed to form a recess 139 for a source / drain (S / D) feature component, such as Fig. 9 As shown. The removal of the film layer can be accomplished by using one or more suitable etching processes, such as dry etching, wet etching, or a combination thereof. One or more etching processes can be performed until the well portion 116 is exposed. The exposed portion of the fin structure 112 can be recessed to the height of the lower surface of the second semiconductor layer 108 in contact with the well portion 116 of the substrate 101. In some embodiments, the etching process is performed so that the height of the bottom 139b of the recess 139 is located below the interface defined by the bottom second semiconductor layer 108 and the well portion 116.

[0087] At step block 1020, edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are horizontally removed along the X direction. Removing the edge portions of the second semiconductor layer 108 forms a cavity. In some embodiments, the edge portions of the second semiconductor layer 108 are removed by a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon and / or SiGe (having a lower germanium concentration than the second semiconductor layer 108), a wet etchant may be used to selectively etch the second semiconductor layer 108. For example, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediaminepyrocatechol (EDP), or potassium hydroxide (KOH) solution.

[0088] After removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form a dielectric spacer layer (or so-called inner spacer layer) 144, such as Fig.10As shown. The dielectric spacer 144 may be made of SiON, SiCN, SiOC, SiOCN or SiN. The dielectric spacer 144 may be formed by first using a compliant deposition process (e.g., ALD) to form a compliant dielectric layer, and then performing anisotropic etching to remove the portion of the compliant dielectric layer except the dielectric spacer 144. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 covers between the dielectric spacer layers 144 along the X direction.

[0089] At step block 1022, source / drain (S / D) features are formed in source / drain (S / D) regions between adjacent semiconductor layer 104 stacks. The source / drain (S / D) features include epitaxial layer 146, such as Fig.11 As shown. The source / drain (S / D) feature component can be a source / drain (S / D) region, for example, one of a pair of source / drain (S / D) epitaxial feature components is located on one side of the sacrificial gate structure 130 and can be a source region. The other of the pair of source / drain (S / D) epitaxial feature components is located on the other side of the sacrificial gate structure 130 and can be a drain region. A pair of source / drain (S / D) epitaxial feature components includes a source epitaxial feature component and a drain epitaxial feature component connected by a channel layer (i.e., the first semiconductor layer 106). In the present disclosure, source and drain can be used interchangeably, and their structures are substantially the same.

[0090] Please refer back to Fig.11 , the epitaxial layer 146 is formed on the exposed surface of the groove 139 ( Fig.10 ). The epitaxial layer 146 is selectively formed on the semiconductor surface of the first semiconductor layer 106 and the well portion 116, while the dielectric surface of the sacrificial gate structure 130 (e.g., the mask layer 136 and the gate spacer 138) remains exposed. The growth of the epitaxial layer 146 can extend to fill the groove 139 and cover the surface of the dielectric spacer layer 144, such as Fig.12 shown.

[0091] The epitaxial layer 146 may include silicon, germanium, or silicon germanium. Depending on the conductivity type of the source / drain (S / D) features grown thereon, n-type or p-type dopants may be added. For example, the epitaxial layer 146 at the n-type device region may include silicon doped with n-type dopants (e.g., phosphorus, antimony, or arsenic), while the epitaxial layer 146 at the p-type device region may include silicon doped with p-type dopants, such as boron or gallium. Exemplary epitaxial layers 146 may include boron-doped silicon (Si:B), phosphorus-doped silicon (Si:P), gallium-doped silicon (Si:Ga), boron-doped germanium (Ge:B), boron-doped silicon germanium (SiGe:B), or gallium-doped silicon germanium (SiGe:Ga).

[0092] In the case of silicon germanium for p-type source / drain (S / D) features, the epitaxial bottom layer 146 may have a Ge atomic percentage in the range of about 0 at.% to 80 at.%, such as about 40 at.% to 60 at.%, for improving channel stress with quality. The epitaxial layer 146 may have a doping concentration of about 5E19 atoms / cm 3 To 5E21 atoms / cm 3 The epitaxial layer 146 used in the n-type source / drain (S / D) feature may have a thickness of about 5E 19 Atom / cm 3 To 5E 21 Atom / cm 3 In most cases, the dopant can be uniformly distributed in the epitaxial layer 146 (e.g., constant distribution) or gradually distributed along the thickness of the epitaxial layer 146 (e.g., gradient distribution). For example, the dopant in the epitaxial layer 146 can have a first dopant concentration at and / or near the surface, and a second dopant concentration at the interface of the epitaxial layer 146 and the first semiconductor layer 106, wherein the first dopant concentration is greater than the second dopant concentration. Alternatively, the dopant can be controlled so that the first dopant concentration is lower than the second dopant concentration.

[0093] In some embodiments, the epitaxial layer 146 may be deposited such that the top of the epitaxial layer 146 may be higher than or equal to the height of the top of the topmost first semiconductor layer 106. The epitaxial layer 146 may be deposited using any suitable deposition process, such as CVD, a cyclic deposition etch (CDE) epitaxial process, a selective epitaxial growth (SEG) process, ALD, PEALD, molecular beam epitaxy (MBE), or any combination thereof. In some embodiments, the first semiconductor layer 106 may be contacted with a silicon-containing precursor and an n-type or p-type dopant-containing precursor in a process chamber to form the epitaxial layer 146. Growth process conditions are configured based on the crystal planes of the first semiconductor layer 106 and the substrate 101 to promote the formation of the epitaxial layer 146. Dopants in the epitaxial layer 146 may be added during the formation of the epitaxial layer 146 and / or implanted after the formation of the epitaxial layer 146.

[0094] In an exemplary embodiment where epitaxial layer 146 includes boron-doped silicon germanium, epitaxial layer 146 may be formed by heating semiconductor device structure 100 to a temperature of about 400 degrees Celsius to 750 degrees Celsius (e.g., about 520 degrees Celsius to 620 degrees Celsius), maintaining a chamber pressure of about 10 Torr to 300 Torr (e.g., about 20 Torr to 80 Torr), and exposing the exposed surface of semiconductor device structure 100 to a gas mixture comprising at least: a silicon-containing precursor, a germanium-containing precursor, and a boron-containing precursor. Suitable silicon-containing precursors may include, but are not limited to, silane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H 10 ), dimethylsilane ((CH3)2SiH2), methylsilane (SiH(CH3)3), dichlorosilane (SiH2Cl2, DCS), trichlorosilane (SiHCl3, TCS) or the like. Suitable germanium-containing precursors may include, but are not limited to, germanium (GeH4), germanium tetrachloride (GeCl4), digermane (Ge e 2H6), trigermane (Ge3H8) or germanium silane (GeH6Si) or the like. Suitable gases for the boron-containing precursor may include, but are not limited to, borane (BH3), diborane (B2H6), boron trichloride (BCl3), triethylborate (TEB), cycloborazine (B3N3H6) or alkyl-substituted derivatives cycloborazine or the like. A diluent / carrier gas, such as hydrogen (H2) and / or argon (Ar), may be used with the precursor of the epitaxial layer 146. In one embodiment, the epitaxial layer 146 is formed of DCS, GeH4 and B2H6. In one embodiment, the epitaxial layer 146 is formed of DCS, GeH4 and BCl3. In some cases, the epitaxial layer 146 may be deposited by a deposition-etch-deposition process to improve void-free gap filling. In the above case, an etching gas (e.g., HCl or Cl2) may be further introduced into the reaction chamber. The epitaxial layer 146 may be formed in a CVD reaction chamber.

[0095] During the formation of the epitaxial layer 146, the precursors of the epitaxial growth process traveling toward the bottom 139b bombard the exposed surface of the gate spacer 138, causing epitaxial nodules 148 to grow on the gate spacer 138 above the source / drain (S / D) region, such as Fig.11 As shown. The nodules 148 can be removed by an in-situ cleaning process using HCl. The mechanism of removing epitaxial nodules can be represented by the following chemical formula:

[0096] HC l→H+Cl

[0097] Si+2C l2→S i C l4

[0098] Due to the composition between Cl and Si, not only on the nodules 148, but also on the epitaxial layer 146. Loss of source / drain (S / D) feature components may occur before the nodules 148 are completely removed. Other methods for removing nodules 148 include non-in-situ (hydrogen) H-radical cleaning processes. However, H-radical cleaning processes can generally effectively remove n-type nodules. P-type epitaxial layers (e.g., SiGeB layers) may not be effectively removed using H-radical cleaning processes, especially for epitaxial layers with higher Ge concentrations. Although relatively small n-type nodules can be removed by H-radical cleaning processes, hydrogen can easily penetrate into the epitaxial layer 146 and cause lattice distortion in the n-type epitaxial layer. The same problem occurs in epitaxial layers formed from other materials.

[0099] In order to effectively remove nodules 148 without causing loss of source / drain (S / D) features, a two-step cleaning process is provided according to some embodiments. Figure 12-Figure 21 A cross-sectional view of a semiconductor device structure 100 and Fig.23 The two-step cleaning process is illustrated in the flowchart of FIG. The first step of the two-step cleaning process includes an oxidation process for the granules 148, and the second step uses a solution to wash away the oxidized substances. Fig.12 As shown, in Fig.23 At step block 1024, a directed oxygen ion beam is applied to the nodules 148 to oxidize the nodules. The directed oxygen ion beam 150 may be generated by a CO source. For example, according to some embodiments, the oxygen beam may be generated by applying radio frequency (RF) or microwave radiation to release a plasma containing CO. The oxygen ion beam 150 is applied at an oblique angle relative to the surface of the gate spacer 138. The oblique angle may be adjusted depending on the aspect ratio of the opening between adjacent sacrificial gates 130 to avoid the oxygen ion beam from being incident on the epitaxial layer 146.

[0100] The oxidation process can be applied to both n-type and p-type junctions. Fig.12 As shown, the n-type junction 148 may be oxidized into an oxidized junction 148a (SiO), and the p-type junction 148 may be oxidized into an oxidized junction 148a (SiGeO). Fig.23 At step block 1026, the oxidized junctions 148a may then be washed away. The oxidized n-type junctions 148a are removed by a diluted hydrofluoric acid (HF) solution 152. For example, the hydrofluoric acid (HF) solution 152 may have a ratio of about 1:500 HF to water to remove the oxidized n-type junctions 148a. The hydrofluoric acid (HF) solution 152 may be further diluted to remove the oxidized p-type junctions 148a. In some embodiments, water may also be used to remove the oxidized p-type junctions 148a. Fig.13The semiconductor device 100 is shown after nodules 148 have been removed by a two-step cleaning process.

[0101] Figure 14A-Figure 14C According to different embodiments, Fig.12 The enlarged view of the part is shown in the dotted line frame. Fig.14A As shown, the nodules 148 are oxidized by applying an oxygen ion beam 150. Since a portion of the surface of the gate spacer 138 is also exposed to contact the oxygen ion beam 150, the exposed gate spacer 138 is also oxidized and converted into an oxidized portion 138a during the oxidation of the nodules 148. The oxidation depth of the oxidized portion 138a varies depending on the extraction energy of the oxygen ions generated from the ion beam source (e.g., a CO source). For example, the oxidation depth may be about to When the gate spacer 138 is made of SiON, the oxidation process increases the oxygen content of the SiON to a certain extent, so that the oxidized portion 138a can be subsequently removed or washed away by diluted HF or water to remove the oxidized nodules 148a.

[0102] In some embodiments, the gate spacer may include Figure 14B-Figure 14C The double-layer structure 140 is shown. The double-layer structure 140 includes: a first layer 138, i.e., an original gate spacer 138 formed on the sidewall of the sacrificial gate electrode layer 134; and a second layer 138b formed during the deposition of the dielectric spacer layer 144. The first layer 138 and the second layer 138b can each be made of a low-k dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN and / or a combination thereof. Fig. 14B As shown, the exposed portion of the second layer 138b in contact with the oxygen ion beam 150 can be oxidized while the oxidized nodules 148 are oxidized. The oxidized portion of the double-layer structure 140 (gate spacer) can be removed or washed away while cleaning the oxidized nodules 148a using a diluted HF solution or water, as shown in FIG. Fig. 15B shown.

[0103] In some embodiments, some exposed portions of the gate dielectric spacer 138 (or the second layer 138b) may be unoxidized or insufficiently oxidized to facilitate removal in a subsequent cleaning process using a dilute HF solution or water, such as Fig. 15C shown. Figure 15A-Figure 15C After removing the granules 148, the Figure 14A-Figure 14Cstage of the semiconductor device structure 100. It can be seen that when the portion of the gate dielectric spacer 138 (double-layer structure 140) not covered by the nodules 148 is removed, the surface of the gate dielectric spacer 138 (double-layer structure 140) becomes rough, while the portion of the gate dielectric spacer 138 (double-layer structure 140) located under the nodules 148 is not etched or is removed at a slower etching rate. In this way, a gate dielectric spacer 138 (double-layer structure 140) having a surface roughness is formed. The surface roughness can be regarded as the distance measured between the bottom of the recessed portion and the unremoved portion of the surface of the gate dielectric spacer 138 (double-layer structure 140). In some embodiments, the surface roughness is measured in angstroms and can have a value of approximately to range. Figure 16A-16C They are shown as Figure 15A-Figure 15C The semiconductor device structure 100 is shown with respect to the roughness of the gate dielectric spacer 138 (double-layer structure 140 ).

[0104] Figure 17-Figure 21 After removing the nodules 148, the Fig.16A The same process can be applied to the semiconductor device 100 having a gate spacer with a double-layer structure 140, such as Fig. 16B and Fig. 16C At step block 1028, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100, such as Fig.17 As shown. The contact etch stop layer (CESL) 162 covers the upper surfaces of the sacrificial gate structure 130, the insulating material 118, and the epitaxial source / drain (S / D) feature 146 and the exposed surface of the semiconductor layer stack 104. The contact etch stop layer (CESL) 162 may have a surface profile that conforms to the surface profile of the gate spacer 138 (double-layer structure 140). Fig. 22 The contact etch stop layer (CESL) 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbide nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, or the like or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, as Fig.18As shown, at step block 1030, an interlayer dielectric (ILD) layer 164 is formed on the contact etch stop layer (CESL) 162 above the semiconductor device structure 100. The material used for the interlayer dielectric (ILD) layer 164 may include compounds containing Si, O, C and / or H Si, such as silicon oxide, TEOS oxide, SiCOH and SiOC. Organic materials (e.g., polymers) may also be used for the interlayer dielectric (ILD) layer 164. The interlayer dielectric (ILD) layer 164 may be deposited by a PECVD process or other suitable deposition techniques. A planarization process (e.g., chemical mechanical polishing (CMP)) is performed until the gate electrode layer 134 is exposed.

[0105] At step 1032, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed in sequence. Fig.19 The removal of the sacrificial gate structure 130 and the second semiconductor layer 108 forms an opening 166 between the gate spacer 138 and the second semiconductor layer 108 and between adjacent first semiconductor layers 106 (see Fig.19 ). During the above removal process, the interlayer dielectric (ILD) layer 164 protects the epitaxial source / drain (S / D) feature 146. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be first removed by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer 132, which can also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof.

[0106] The removal of the sacrificial gate structure 130 exposes the first semiconductor layer 106 and the second semiconductor layer 108. Next, an etching process (which may be any suitable etching process, such as dry etching, wet etching, or a combination thereof) is performed to remove the second semiconductor layer 108 and expose the dielectric spacer layer 144. The etching process may be a selective etching process that removes the second semiconductor layer 108 but does not remove the gate spacer 138, the dielectric spacer layer 144, the interlayer dielectric (ILD) layer 164, the contact etch stop layer (CESL) 162, and the first semiconductor layer 106. In one embodiment, the second semiconductor layer 108 may be removed using a wet etchant, such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), a dry etchant, such as a fluorine-based gas (e.g., F2) or a chlorine-based gas (e.g., Cl2), or any suitable isotropic etchant. After the above-described etching process, the portion of the first semiconductor layer 106 not covered by the dielectric spacer layer 144 is exposed through the opening 166 .

[0107] At step block 1034, a replacement gate structure 190 is formed, such as Fig. 20 As shown. Each replacement gate structure 190 may include an interfacial layer (IL) 178, a gate dielectric layer 180, and a gate electrode layer 182. The interfacial layer (IL) 178 is formed to surround the exposed surface of the first semiconductor layer 106 along the channel region. The interfacial layer (IL) 178 may include an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride, silicon oxynitride, oxynitride, etc.) and / or a dielectric layer (e.g., hafnium silicate) formed by thermal oxidation or chemical oxidation of the first semiconductor layer 106 or made of the above materials. The interfacial layer (IL) 178 may be formed by CVD, ALD, a cleaning process, or any appropriate process. Next, a gate dielectric layer 180 is formed on the exposed surface of the semiconductor device structure 100 (e.g., on the interfacial layer (IL) 178, on the sidewalls of the gate spacer 138, and on the upper surface of the first interlayer dielectric (ILD) layer 164, the contact etch stop layer (CESL) 162, and the dielectric spacer 144). The gate dielectric layer 180 may include or be made of a high-k dielectric material, such as hafnium oxide (HfO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide (HfAlO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), lanthanum oxide (La2O), aluminum oxide (Al2O), aluminum silicon oxide (AlSiO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), silicon oxynitride (SiON), or other suitable high-k materials. The gate dielectric layer 180 may be a compliant layer formed by, for example, an ALD process, a PECVD process, a molecular-beam deposition (MBD) process, or the like, or a combination thereof.

[0108] After forming the interfacial layer (IL) 178 and the gate dielectric layer 180, a gate electrode layer 182 is formed on the gate dielectric layer 180. The gate electrode layer 182 fills the opening 166 and surrounds a portion of each of the first semiconductor layers 106. The gate electrode layer 182 includes one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials and / or combinations thereof. The gate electrode layer 182 can be formed by PVD, CVD, ALD, electroplating or other suitable methods. In some embodiments, one or more optional conformal layers (not shown) can be conformally (and sequentially, if more than one layer) deposited between the gate dielectric layer 180 and the gate electrode layer 182. The one or more optional compliant layers may include one or more barrier and / or capping layers and one or more work function adjustment layers. The one or more barrier and / or capping layers may include or be titanium and / or tantalum nitrides, silicon nitrides, carbon nitrides, and / or aluminum nitrides; tungsten nitrides, carbon nitrides, and / or carbides; the like; or combinations thereof. The one or more work function adjustment layers may include or be titanium and / or tantalum nitrides, silicon nitrides, carbon nitrides, aluminum nitrides, aluminum oxides, and / or aluminum carbides; tungsten nitrides, carbon nitrides, and / or carbides; cobalt; platinum; the like; or combinations thereof.

[0109] At step 1036, the gate electrode layer 182 is subjected to one or more metal gate etch back (MGEB) processes. The MGEB process is performed so that the upper surfaces of the gate electrode layer 182 and the gate dielectric layer 180 are recessed to a height below the upper surface of the gate spacer 138. In some embodiments, the gate spacer 138 is also recessed to a height below the upper surface of the interlayer dielectric (ILD) layer 164. Fig.21As shown, a self-aligned contact layer 173 is formed on the gate electrode layer 182 and on the gate dielectric layer 180 between the gate spacers 138. The self-aligned contact layer 173 can be a dielectric material having an etch selectivity relative to the interlayer dielectric (ILD) layer 164. In some embodiments, the self-aligned contact layer 173 includes silicon nitride. Next, a contact opening is formed through the interlayer dielectric (ILD) layer 164 and the contact etch stop layer (CESL) 162 to expose the epitaxial source / drain (S / D) feature 146. A silicide layer 184 is then formed on the source / drain (S / D) epitaxial feature 146, and on the silicide layer 184 within the contact opening on the source / drain (S / D) contact 186. The source / drain (S / D) contact 186 can include a conductive material, such as Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. The silicide layer 184 may include metal or metal alloy silicide, and the metal may include noble metal, refractory metal, rare earth metal, alloys thereof or combinations thereof. Next, a conductive material is formed in the contact opening to form source / drain (S / D) contacts 186, such as Fig.21 As shown. The conductive material may include Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN or TaN. Although not shown, before forming the source / drain (S / D) contacts 186, a barrier layer (e.g., TiN, TaN or the like) is formed on the sidewalls of the contact opening. Then, a planarization process (e.g., chemical mechanical polishing (CMP)) is performed to remove excess deposition of the contact material and expose the upper surface of the gate electrode layer 182.

[0110] Fig. 22 Show Fig.2114 is an enlarged view of the area within the dashed box in FIG. As shown in the figure, after removing the nodules 148, not only the gate spacer 138 has an uneven or rough surface, but the contact etch stop layer (CESL) 162 also has an uneven or rough surface on both sides conforming to the gate spacer 138. In some embodiments, the contact etch stop layer (CESL) 162 has a first surface 162a and a second surface 162b opposite to the first surface 162a. The first surface 162a contacts the gate spacer 138, and the second surface 162b contacts the source / drain (S / D) contact 186. In some embodiments, a portion of the first surface 162 and a portion of the gate spacer 138 define a first interface 163, and a portion of the first surface 162a and a portion of the gate spacer 138 define a second interface 165, and the second interface 165 is offset from the first interface 163 by a distance D2. Similarly, a portion of the second surface 162b and a portion of the source / drain (S / D) contact 186 define a third interface 167, and a portion of the second surface 162b and a portion of the source / drain (S / D) contact 186 define a fourth interface 169 that is offset from the third interface 167 by a distance D3.

[0111] The semiconductor device structure 100 may be subjected to subsequent processes to complete the fabrication of a semiconductor device made of desired materials. For example, the semiconductor device structure 100 may be subjected to further complementary metal oxide semiconductor (CMOS) and / or back-end-of-line (BEOL) processes to form various devices, such as transistors, contacts / vias, interconnect metal layers, dielectric layers. The semiconductor device structure 100 may also include backside contacts (not shown) on the backside of the substrate 101, such that the source or drain of the epitaxial source / drain (S / D) feature is connected to a backside power rail (e.g., positive voltage VDD or negative voltage VSS) through the backside contacts.

[0112] The present disclosure provides a method for manufacturing a semiconductor device structure for removing unnecessary nodules formed on a gate spacer during the formation of an epitaxial source / drain (S / D) feature component. The above method uses a directional oxygen ion beam to oxidize the nodules. The directional oxygen ion beam is applied at an angle of inclination relative to the surface of the gate spacer. The inclination angle can be controlled depending on the aspect ratio of the opening between adjacent gate structures to prevent the epitaxial source / drain (S / D) feature component from being oxidized by oxygen ions. Therefore, the loss of the epitaxial source / drain (S / D) feature component can be prevented. Depending on the conductivity type, the oxidized nodules can be easily removed or rinsed away by a dilute hydrofluoric acid (HF) solution or water. When a portion of the gate spacer is exposed to the oxygen ion beam, at least a portion of the exposed portion of the gate spacer is also oxidized and removed by the hydrofluoric acid (HF) solution. This causes the surface of the gate spacer to become rough. The roughness of the rough surface depends on the extraction energy used to generate the ion beam from the oxygen ion source.

[0113] According to some embodiments, a method for manufacturing a semiconductor device structure is provided. The method includes: forming a plurality of semiconductor layer stacks. Each of the semiconductor layer stacks includes a plurality of first layers and a plurality of second layers alternately stacked with each other. Then, a gate electrode structure is formed on each of the semiconductor layer stacks, and each of the gate electrode structures includes a gate spacer. An epitaxial source / drain feature is formed in an opening between each pair of adjacent ones in the semiconductor layer stack. An oxygen ion beam is applied to the gate spacer at an inclined angle to form an oxide material on the gate spacer. Then, the oxide material is removed with a dilute hydrofluoric acid (HF) solution.

[0114] In some embodiments, the oxidized material includes a plurality of nodules formed on the gate spacer and oxidized by an oxygen ion beam when forming epitaxial source / drain features. In some embodiments, the method removes the oxidized nodules with a diluted hydrofluoric acid (HF) solution. In some embodiments, the diluted hydrofluoric acid (HF) solution has a ratio of hydrofluoric acid (HF) to water of approximately 1:500. In some embodiments, the nodules include a plurality of n-type nodules and a plurality of p-type nodules. In some embodiments, the method further includes applying a diluted hydrofluoric acid (HF) solution to remove the oxidized n-type nodules; and applying water to remove the oxidized p-type nodules. In some embodiments, the oxidized material includes a plurality of portions of the gate spacer exposed between the nodules and oxidized by the oxygen ion beam. In some embodiments, the oxidation depth of the exposed portions is approximately to In some embodiments, the method further comprises removing the oxidized portion of the gate spacer by applying a dilute hydrofluoric acid (HF) solution. In some embodiments, the surface of the gate spacer is roughened by removing the oxidized portion of the gate spacer. In some embodiments, the roughness of the roughened surface is about to In some embodiments, the method further comprises generating an oxygen ion beam from a carbon monoxide (CO) source. In some embodiments, the method further comprises adjusting the tilt angle according to an aspect ratio of an opening between the gate structures.

[0115] According to another embodiment, a method for manufacturing a semiconductor device structure is provided for removing a plurality of nodules formed on a gate spacer during formation of an epitaxial source / drain (S / D) feature in the semiconductor device structure. The method includes: applying a plurality of directional oxygen ion beams at an inclined angle to oxidize the nodules, wherein the inclined angle is adjusted to prevent the oxygen ions from being applied to the epitaxial source / drain (S / D) feature; and removing the nodules oxidized by the oxygen ions using a dilute hydrofluoric acid (HF) solution.

[0116] In some embodiments, the method further comprises oxidizing portions of the gate spacer by an oxygen ion beam. In some embodiments, the method further comprises removing the oxidized portions of the gate spacer to form a rough surface of the gate spacer. In some embodiments, the dilute hydrofluoric acid (HF) solution has a ratio of hydrofluoric acid (HF) to water of no greater than about 1:500.

[0117] According to another embodiment, a semiconductor device structure is provided, comprising: a pair of epitaxial source / drain regions; a channel region located between the epitaxial source / drain regions; and a gate structure located on the channel region, the gate structure comprising a gate spacer having one or more surface portions that are oxidized and etched.

[0118] In some embodiments, the surface portion has about to In some embodiments, the surface roughness of the gate spacer is about to

[0119] The above briefly describes the characteristic components of several embodiments of the present invention, so that those skilled in the art can more easily understand the types of the present disclosure. Any person skilled in the art should understand that the present disclosure can be easily used as a basis for the change or design of other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Any person skilled in the art can also understand that structures equivalent to the above do not depart from the spirit and scope of protection of the present disclosure, and can be changed, replaced and modified without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device structure, comprising: forming a plurality of semiconductor layer stacks, each of the plurality of semiconductor layer stacks comprising a plurality of first layers and a plurality of second layers alternately stacked with each other; forming a gate electrode structure on each of the plurality of semiconductor layer stacks, wherein each of the plurality of gate electrode structures comprises a gate spacer; forming an epitaxial source / drain feature in an opening between each pair of adjacent ones of the plurality of semiconductor layer stacks; Applying an oxygen ion beam to the plurality of gate spacers at an inclined angle to form a plurality of oxide materials on the plurality of gate spacers; as well as The oxidized material is removed with a dilute hydrofluoric acid solution.

2. The method for fabricating a semiconductor device structure as claimed in claim 1, wherein the plurality of oxide materials comprise a plurality of nodules formed on the plurality of gate spacers and oxidized by the oxygen ion beam when forming the epitaxial source / drain feature.

3. The method for manufacturing a semiconductor device structure as claimed in claim 2, wherein the plurality of oxide materials include a plurality of portions of the plurality of gate spacers exposed between the plurality of nodules and oxidized by the oxygen ion beam.

4. The method for manufacturing a semiconductor device structure according to claim 3, wherein the oxidation depth of the exposed portions is to 5. The method for fabricating a semiconductor device structure as claimed in claim 1, further comprising generating the oxygen ion beam from an oxidized carbon source. 6 . The method for manufacturing a semiconductor device structure as claimed in claim 1 , further comprising adjusting the tilt angle according to an aspect ratio of an opening between the plurality of gate structures.

7. A method for manufacturing a semiconductor device structure, for removing a plurality of nodules formed on a gate spacer during formation of an epitaxial source / drain feature in the semiconductor device structure, comprising: applying a directed oxygen ion beam at a tilt angle to oxidize the plurality of nodules, wherein the tilt angle is adjusted to prevent oxygen ions from being applied to the epitaxial source / drain features; and A dilute hydrofluoric acid solution is used to remove the plurality of nodules that have been oxidized by oxygen ions.

8. The method for manufacturing a semiconductor device structure according to claim 7, further comprising: Portions of the gate spacer are oxidized by a plurality of the directional oxygen ion beams.

9. A semiconductor device structure, comprising: a pair of epitaxial source / drain regions; a channel region located between the pair of epitaxial source / drain regions; as well as A gate structure is located on the channel region, and the gate structure includes a gate spacer having one or more surface portions that are oxidized and etched.

10. The semiconductor device structure of claim 9, wherein the one or more upper surface portions have to Depth of oxidation.

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