Power integrated circuit with two VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) connected in series and manufacturing method thereof

Abstract

The embodiment of the invention provides a power integrated circuit with two VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) connected in series, which comprises a buried oxide layer extending along the transverse direction; the isolation column extends along the longitudinal direction, and the isolation column and the buried oxide layer form a spatial electrical isolation region; the first power MOS tube is located outside the electrical isolation region; the second power MOS tube is located in the electrical isolation region and comprises a second N + doped layer, a second N-type epitaxial layer, a second p-type substrate region, a second dielectric layer, a second source region, a second drain electrode, a second grid electrode and a second source electrode; the second drain electrode and the first source electrode are located on the same side of the horizontal plane where the second N + doping layer is located and are electrically connected. The embodiment of the invention further provides a manufacturing method of the power integrated circuit.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power integrated circuit having two VDMOS connected in series and a manufacturing method thereof. Background Art

[0002] Traditional electronic power circuits based on power MOS tubes, such as synchronous buck circuits, synchronous boost circuits, synchronous buck-boost circuits, and half-bridge circuits, all have power conversion functions. These circuits require the source and drain of high-side and low-side power MOS tubes to be connected in series. Since the power MOS tube needs to carry a large current, the general power MOS tube adopts VDMOS (Vertical Double Diffused MOSFET, vertical double diffused metal oxide semiconductor field effect transistor) devices. The entire back substrate of VDMOS is the drain, so the high-side and low-side VDMOS that need to be electrically separated from the drain are difficult to integrate on the same chip. The existing methods mostly use two VDMOS tubes to be set separately. The packaging wire bonding and PCB board-level interconnection of the discrete MOS lead to large parasitic RCL (resistance, capacitance and inductance), which increases the complexity of power electronic system design and reduces robustness. Summary of the invention

[0003] The technical problem to be solved by the embodiments of the present application is to provide a power integrated circuit with two VDMOS connected in series and a manufacturing method thereof in view of the deficiencies of the prior art. The two VDMOS are integrated on a single chip, thereby reducing packaging and interconnection parasitics and improving the robustness of the power electronic system.

[0004] In order to solve the above technical problems, a first aspect of an embodiment of the present application provides a power integrated circuit having two VDMOS connected in series, comprising:

[0005] a buried oxide layer extending in a lateral direction;

[0006] An isolation column extending in a longitudinal direction, wherein the isolation column and the buried oxide layer form a spatial electrical isolation region;

[0007] a first power MOS transistor, which is located outside the electrical isolation region, and comprises a first drain, a first gate and a first source, wherein the first drain is located below the first gate and the first source;

[0008] a second power MOS tube, which is located in the electrical isolation region, and comprises a second N+ doped layer, a second N-type epitaxial layer, a second p-type matrix region, a second dielectric layer, a second source region, a second drain, a second gate and a second source, wherein the second N+ doped layer is located on the buried oxide layer, the second N-type epitaxial layer is arranged on the second N+ doped layer, the second p-type matrix region is arranged on the second N-type epitaxial layer, the second dielectric layer is located in the second N-type epitaxial layer and the second p-type matrix region, a second gate is arranged in the second dielectric layer, the second source region is located on the second p-type matrix region, the second source region is connected to the second source, and the second N+ doped layer is connected to the second drain;

[0009] The second drain and the first source are located on the same side of the horizontal plane where the second N+ doped layer is located and the two are electrically connected

[0010] Optionally, the second power MOS tube also includes a third dielectric layer and a second drain connection portion, wherein the second drain connection portion extends downward from the upper surface of the second N-type epitaxial layer to contact the second N+ doped layer, the upper end of the second drain connection portion is connected to the second drain, and the third dielectric layer is arranged around the second drain connection portion to electrically insulate the second drain connection portion from the second N-type epitaxial layer.

[0011] Optionally, a longitudinal height of the third dielectric layer is smaller than a longitudinal height of the isolation column.

[0012] Optionally, a lower end of the second drain connection portion contacts an upper surface of the second N+ doped layer or extends into a portion of the second N+ doped layer.

[0013] Optionally, the second power MOS tube includes a first N+ substrate, a first N-type epitaxial layer, a first p-type matrix region, a first dielectric layer, and a first source region, wherein the first N-type epitaxial layer is arranged on the first N+ substrate, the first p-type matrix region is arranged on the first N-type epitaxial layer, the first drain is arranged below the first N+ substrate, the first dielectric layer is arranged in the first N-type epitaxial layer and the first p-type matrix region, the first gate is arranged in the first dielectric layer, the first source region is arranged on the first p-type matrix region, and the second source region is connected to the second source electrode;

[0014] Wherein, the buried oxide layer is located between the first N+ substrate and the second N+ doped layer.

[0015] Optionally, the lower surface of the buried oxide layer is in contact with the first N+ substrate, and the upper surface of the buried oxide layer is in contact with the second N+ doped layer; or,

[0016] The first N-type epitaxial layer includes a first-N-type epitaxial layer and a first-second N-type epitaxial layer, the first-N-type epitaxial layer is located on the first N+ substrate, the first-second N-type epitaxial layer is located on the first-N-type epitaxial layer, the lower surface of the buried oxide layer contacts the first-N-type epitaxial layer, and the upper surface of the buried oxide layer contacts the second N+ doped layer.

[0017] Optionally, the isolation column is located between the first N-type epitaxial layer and the second N-type epitaxial layer.

[0018] Optionally, the second N+ doped layer and the first N+ substrate belong to the same initial wafer substrate; or,

[0019] The second N+ doped layer is formed by doping the first N-type epitaxial layer with N-type impurities.

[0020] A second aspect of an embodiment of the present application provides a method for manufacturing a power integrated circuit, comprising:

[0021] Providing an N+ substrate;

[0022] Forming a buried oxide layer in the N+ substrate;

[0023] An N-type epitaxial layer is formed on an N+ substrate, and a third deep trench is dug in the N-type epitaxial layer, wherein the third deep trench extends downward to the buried oxide layer;

[0024] An isolation column is formed in the third deep trench, wherein the isolation column and the buried oxide layer form a spatial electrical isolation region, wherein the N+ substrate is separated into a first N+ substrate and a second N+ doped layer, and the N-type epitaxial layer is separated into a first N-type epitaxial layer and a second N-type epitaxial layer by the isolation column and the buried oxide layer;

[0025] Digging a first groove and a second groove in the N-type epitaxial layer;

[0026] forming a first dielectric layer and a first gate in the first groove, and forming a second dielectric layer and a second gate in the second groove,

[0027] Forming a first p-type base region, a first source region, and a first p-type contact region outside the electrical isolation region, and forming a second p-type base region, a second source region, and a second p-type contact region inside the electrical isolation region;

[0028] forming a fourth deep trench in the electrical isolation region, wherein the fourth deep trench extends from the upper surface of the second N-type epitaxial layer to the second N+ doped layer;

[0029] A third dielectric layer and a second drain connection portion are formed in the fourth deep trench, and a first drain is formed on the lower surface of the first N+ substrate.

[0030] A third aspect of an embodiment of the present application provides a method for manufacturing a power integrated circuit, comprising:

[0031] Providing a first N+ substrate, and forming a first N-type epitaxial layer on the first N+ substrate;

[0032] forming a buried oxide layer in the first N-type epitaxial layer;

[0033] The first N-type epitaxial layer above the buried oxide layer is heavily N-doped to form a second N+ doped layer;

[0034] An N-type epitaxial layer is formed on the first N-type epitaxial layer and the second N+ doped layer, and a third deep trench is dug in the N-type epitaxial layer, wherein the third deep trench extends downward to the buried oxide layer;

[0035] An isolation column is formed in the third deep trench, wherein the isolation column and the buried oxide layer form a spatial electrical isolation region, wherein the N-type epitaxial layer is separated into a first second N-type epitaxial layer and a second N-type epitaxial layer by the isolation column and the buried oxide layer, and the first N-type epitaxial layer includes the remaining first first N-type epitaxial layer and the first second N-type epitaxial layer;

[0036] Digging a first groove in the first N-type epitaxial layer and digging a second groove in the second N-type epitaxial layer;

[0037] forming a first dielectric layer and a first gate in the first groove, and forming a second dielectric layer and a second gate in the second groove;

[0038] Forming a first p-type base region, a first source region, and a first p-type contact region outside the electrical isolation region, and forming a second p-type base region, a second source region, and a second p-type contact region inside the electrical isolation region;

[0039] forming a fourth deep trench in the electrical isolation region, wherein the fourth deep trench extends from the upper surface of the second N-type epitaxial layer to the second N+ doped layer;

[0040] A third dielectric layer and a second drain connection portion are formed in the fourth deep trench.

[0041] In this embodiment, the first power MOS tube and the second power MOS tube are electrically isolated by the isolation column and the buried oxide layer, and the drains of the two are also electrically isolated, so that the first power MOS tube and the second power MOS tube can be made on the same chip, so that the parasitic RCL caused by the package wiring and the PCB board-level interconnection is reduced, which is conducive to reducing the complexity of circuit design and improving robustness. In addition, the isolation column and the buried oxide layer have good electrical isolation performance, and the first power MOS tube and the second power MOS tube are less affected by interference with each other. In addition, the first power MOS tube and the second MOS tube are both VDMOS, and the current flows in the longitudinal direction when flowing, and the area occupied by the chip in the horizontal plane is small, which is conducive to saving area and cost. In addition, the first source of the first power MOS tube and the second drain of the second power MOS tube are located on the same side of the horizontal plane where the second N+ doped layer of the second power MOS tube is located, and it is easier to electrically connect the two, reducing the complexity of the drain-source connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figure 1 is an application circuit diagram of the power integrated circuit of the first embodiment of the present application;

[0044] Figure 2 is a schematic diagram of the structure of a power integrated circuit according to the first embodiment of the present application;

[0045] Figure 3a It is a schematic diagram of the power integrated circuit applied to the Buck circuit in the first embodiment of the present application;

[0046] Figure 3b It is a schematic diagram of applying the power integrated circuit of the first embodiment of the present application to the Boost circuit;

[0047] Figure 4 is a flow chart of a method for manufacturing a power integrated circuit according to a first embodiment of the present application;

[0048] Figure 5a-5l is a schematic diagram of the manufacturing steps of the power integrated circuit of the first embodiment of the present application;

[0049] Figure 6 is a schematic diagram of the structure of a power integrated circuit according to a second embodiment of the present application;

[0050] Figure 7 is a flow chart of a method for manufacturing a power integrated circuit according to a second embodiment of the present application;

[0051] Figure 8a-8m It is a schematic diagram of the manufacturing steps of the power integrated circuit according to the second embodiment of the present application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0053] The terms "including" and "having" and any variations thereof that appear in the specification, claims and drawings of this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or modules is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices. In addition, the terms "first", "second" and "third" are used to distinguish different objects, not to describe a specific order. The connections of this application include direct connections and indirect connections. Indirect connection means that other electronic components, pins, etc. may exist between the two connected components.

[0054] First embodiment

[0055] See also Figure 1 and Figure 2 The embodiment of the present application provides a power integrated circuit (PIC), which is also called a power chip. The power integrated circuit includes at least a first power MOS tube and a second power MOS tube, that is, the first power MOS tube and the second power MOS tube are made on the same semiconductor substrate, and the source of the first power MOS tube is connected in series with the drain of the second power MOS tube. In this embodiment, the first power MOS tube and the second power MOS tube are both VDMOS, and the first power MOS tube and the second power MOS tube are made on a single chip, which is conducive to reducing packaging and interconnection parasitics. Figure 1 In the embodiment, the first power MOS tube is a high-side power MOS tube, the second power MOS tube is a low-side power MOS tube, the drain end of the high-side power MOS tube is connected to the high potential VCC, the source end of the high-side power MOS tube is connected to the drain end of the low-side power MOS tube, the source end of the low-side power MOS tube is connected to the low potential VSS, and the gate of the high-side power MOS tube and the gate of the low-side power MOS tube are both connected to the control circuit 320.

[0056] Please continue to see Figure 2 In this embodiment, the first power MOS tube includes a first drain 157, a first N+ substrate 111, a first N-type epitaxial layer 131, a first p-type base region 154, a first source region 155, a first p-type contact region 156, a first dielectric layer, a first source (not shown in the figure) and a first gate 152. Figure 2 The first power MOS tube is composed of a plurality of cells repeatedly connected in parallel, and the number of parallel connections is determined by the on-resistance required by the first power MOS tube. For the convenience of display, only one cell unit is included in the figure. This is a conventional technology in the art and will not be described here. Specifically, the first N+ substrate 111 is the substrate of the entire power integrated circuit, and is arranged at the bottom of the entire power integrated circuit. A first drain 157 is arranged on the lower surface of the first N+ substrate 111. The first drain 157 is the drain of the first power MOS tube. The first N-type epitaxial layer 131 is located on the first N+ substrate 111. A first p-type base region 154 and a first dielectric layer are arranged on the first epitaxial layer. A first gate 152 is arranged in the first dielectric layer. The first p-type base region 154 is arranged around the first dielectric layer. A first source region 155 and a first p-type contact region 156 are arranged on the first p-type base region 154. The first source region 155 and the first p-type contact region 156 are connected to the first source.

[0057] In this embodiment, the power integrated circuit also includes a buried oxide layer 120 and an isolation column 144. The buried oxide layer 120 is arranged on the first N+ substrate 111. The buried oxide layer 120 is an insulating layer. The material of the buried oxide layer 120 is, for example, SiO2. The isolation column 144 extends downward from the upper surface of the first N-type epitaxial layer 131 to contact the buried oxide layer 120. Here, the isolation column 144 is in contact with the upper surface of the buried oxide layer 120 or the isolation column 144 extends into part of the buried oxide layer 120. The isolation column 144 is also an insulating layer. The isolation column 144 is, for example, SiO2. In this embodiment, the buried oxide layer 120 extends to the edge of the power integrated circuit in the horizontal direction, so that the buried oxide layer 120 electrically isolates the area above it from the area below it, that is, the buried oxide layer 120 is used for longitudinal electrical isolation, and the isolation column 144 extends from the buried oxide layer 120 to the upper surface of the first N-type epitaxial layer 131, that is, the isolation column 144 extends longitudinally, so that the isolation column 144 electrically isolates the left area from the right area in the figure, that is, the isolation column 144 performs horizontal electrical isolation, and the isolation column 144 is combined with the buried oxide layer 120 to form a spatial electrical isolation area. The spatial electrical isolation area is a three-dimensional electrical isolation area, which can be a rectangular parallelepiped, a cube, a half cylinder, etc., wherein isolation is performed in the left and right directions by the isolation column 144, and isolation is performed in the longitudinal direction by the buried oxide layer 120.

[0058] In this embodiment, the second power MOS transistor is formed in the space electrical isolation region, and the second power MOS transistor includes a second N+ doped layer 112, a second N-type epitaxial layer 132, a second p-type base region 164, a second source region 165, a second p-type contact region 166, a second dielectric layer, a second source (not shown in the figure), a second gate 162 and a second drain (not shown in the figure). Figure 2 The second power MOS tube is composed of a plurality of cells repeatedly connected in parallel, and the number of parallel connections is determined by the on-resistance required by the second power MOS tube. For the convenience of display, only one cell unit is included in the figure. This is a conventional technology in the art and will not be described here. Among them, the second N+ doped layer 112 is formed on the buried oxide layer 120, and the second N+ doped layer 112 and the first N+ substrate 111 are made of the same material. The second N-type epitaxial layer 132 is located on the second N+ doped layer 112, and a second p-type base region 164 and a second dielectric layer are provided on the second N-type epitaxial layer 132. A second gate 162 is provided in the second dielectric layer, and the second p-type base region 164 is arranged around the second dielectric layer. A second source region 165 and a second p-type contact region 166 are provided on the second p-type base region 164, and the second source region 165 and the second p-type contact region 166 are both connected to the source.

[0059] In order to connect the electrical signal of the second N+ doped layer 112, in this embodiment, the second power MOS tube further includes a third dielectric layer 167 and a second drain connection portion 168. The second drain connection portion 168 is located in the third dielectric layer 167. The lower end of the second drain connection portion 168 contacts the second N+ doped layer 112. The second drain connection portion 168 extends upward to the upper surface of the second N-type epitaxial layer 132, so as to connect the electrical signal of the second N+ doped layer 112 through the second drain connection portion 168. The second drain connection portion 168 is connected to the second drain. The second drain and the first source are located on the same side of the first N+ substrate 111 and the same side of the horizontal plane where the second N+ doped layer 112 is located. The third dielectric layer 167 is used to isolate the second drain connection portion 168 from the second N+ epitaxial layer 132. The third dielectric layer 167 is an insulating layer. The third dielectric layer 167 is, for example, SiO2. In this embodiment, the first source of the first power MOS tube is connected to the second drain of the second power MOS tube. Due to the provision of the second drain connection portion 168, the first source and the second drain are located on the same side, thereby facilitating electrical connection between the two. In this embodiment, the longitudinal height of the third dielectric layer is less than the longitudinal height of the isolation column.

[0060] In this embodiment, the first power MOS tube and the second power MOS tube are electrically isolated by the isolation column 144 and the buried oxide layer 120, and the drains of the two are also electrically isolated, so that the first power MOS tube and the second power MOS tube can be made on the same chip, so that the parasitic RCL caused by the package wiring and the PCB board-level interconnection is reduced, which is conducive to reducing the complexity of circuit design and improving robustness. In addition, the isolation column 144 and the buried oxide layer 120 have good electrical isolation performance, and the first power MOS tube and the second power MOS tube are less affected by interference with each other. In addition, the first power MOS tube and the second power MOS tube are both VDMOS, and the current flows in the vertical direction when flowing, and the area occupied by the chip in the horizontal plane is small, which is conducive to saving area and cost. In addition, the power MOS tube located in the isolation column 144 and the buried oxide layer 120 is connected to the electrical signal of one of the power MOS tubes by setting the second drain connection part 168, so that the drain of one of the power MOS tubes and the source of the other power MOS tube are located on the same side, which is convenient for the electrical connection between the two and reduces the complexity of the drain-source connection.

[0061] See also Figure 3a , Figure 3a This is a typical schematic diagram of a Buck circuit. The two power MOS tubes M1 and M2 in the figure can be the first power MOS tube and the second power MOS tube of the present application. Figure 3b , Figure 3b This is a typical schematic diagram of a Boost circuit, in which the two power MOS tubes M1 and M2 in the figure can be the first power MOS tube and the second power MOS tube of the present application. In addition, the power integrated circuit of the present application can also be used in buck-boost circuits, half-bridge and full-bridge power supply circuits, which is a conventional technology in the art and will not be described in detail here.

[0062] The present application also provides a method for manufacturing a power integrated circuit. The manufacturing method corresponds to the above power integrated circuit structure. Please refer to Figure 1-Figure 5l , the manufacturing method comprises:

[0063] S110: providing an N+ substrate 110;

[0064] See also Figure 5a In this embodiment, the N+ substrate 110 is an initial wafer substrate.

[0065] S120: forming a buried oxide layer 120 in the N+ substrate 110;

[0066] See also Figure 5b, oxygen ions are implanted into the upper part of the N+ substrate 110, and then heated at a high temperature, the oxygen ions react with the N+ substrate 110 to form a buried oxide layer 120 in the N+ substrate 110, and the buried oxide layer 120 is an electrical insulating layer. In this embodiment, the number of the buried oxide layer 120 is one, and the buried oxide layer 120 does not penetrate the N+ substrate 110 in the left-right direction. In the figure, the left side of the buried oxide layer 120 extends to the middle of the N+ substrate 110 or near the middle.

[0067] S130: forming an N-type epitaxial layer 130 on the N+ substrate 110, and digging a third deep trench 143 in the N-type epitaxial layer 130, wherein the third deep trench 143 extends downward to the buried oxide layer 120;

[0068] See also Figure 5c In the present embodiment, the doping concentration of the N-type epitaxial layer 130 is less than the doping concentration of the N+ substrate 110, and the third deep trench 143 extends downward from the upper surface of the N-type epitaxial layer 130. The third deep trench 143 penetrates the N-type epitaxial layer 130, and the third deep trench 143 also enters the N-type substrate and extends to the buried oxide layer 120. The third deep trench 143 contacts the upper surface of the buried oxide layer 120 or enters part of the buried oxide layer 120. In this embodiment, the number of the third deep trenches 143 is one or more (shown as one in the figure, and can be set to multiple according to the electrical isolation requirements). In the figure, the lower side of the third deep trench 143 is in contact with one side (left side) of the buried oxide layer 120, and the other side (right side) of the buried oxide layer 120 extends to the edge of the N+ substrate 110. The buried oxide layer 120 electrically isolates the area above it from the area below it, that is, the buried oxide layer 120 performs vertical electrical isolation, and the third deep trench 143 electrically isolates the left area from the right area in the figure, that is, the third deep trench 143 performs horizontal electrical isolation, so that the third deep trench 143 and the second buried oxide layer 120 are combined to form an electrically isolated area. In this embodiment, the N+ substrate 110 located below the buried oxide layer 120 or on the left side of the third deep trench 143 is the first N+ substrate 111, and the N+ substrate 110 located above the buried oxide layer 120 and on the right side of the third deep trench 143 is the second N+ doped layer 112, that is, the second N+ doped layer 112 is in the electrical isolation region, and the first N+ substrate 111 is outside the electrical isolation region. The two are electrically isolated by the electrical isolation region. The second N+ doped layer 112 is arranged to facilitate the formation of the second power MOS tube in the electrical isolation region. The first N+ substrate 111 and the second N+ doped layer 112 are formed together to save process steps. The first N+ substrate 111 and the second N+ doped layer 112 belong to the same initial wafer substrate. Similarly, the N-type epitaxial layer 130 outside the electrical isolation region is the first N-type epitaxial layer 131, and the N-type epitaxial layer 130 in the electrical isolation region is the second N-type epitaxial layer 132.

[0069] S140: forming an isolation column 144 in the third deep trench 143, wherein the isolation column 144 and the buried oxide layer 120 form a spatial electrical isolation region;

[0070] See also Figure 5d In this embodiment, an insulating material is filled in the third deep groove 143 to form an isolation column 144, and the isolation column 144 is an insulating layer, and the isolation column 144 is, for example, an insulating material such as SiO2. In this embodiment, the isolation column 144 is in contact with the buried oxide layer 120, for example, in contact with the upper surface of the buried oxide layer 120, or the isolation column 144 is inserted into a part of the buried oxide layer 120, and the isolation column 144 and the buried oxide layer 120 work together to form a spatial electrical isolation area. Since the isolation column 144 and the buried oxide layer 120 are both insulating layers, the components in the electrical isolation area are less disturbed by the components outside the electrical isolation area.

[0071] S150: Digging a first groove 141 and a second groove 142 in the N-type epitaxial layer 130;

[0072] See also Figure 5e In this embodiment, the depths of the first groove 141 and the second groove 142 are the same, but they may be different. The depths of the first groove 141 and the second groove 142 are both less than the depth of the third deep groove 143. The first groove 141 and the second groove 142 extend downward from the upper surface of the N-type epitaxial layer 130, and the first groove 141 and the second groove 142 are located in the N-type epitaxial layer 130. In this embodiment, there are multiple first grooves 141 and second grooves 142 (shown as 2 in the figure), the first groove 141 is located outside the electrical isolation region, and the second groove 142 is located in the electrical isolation region.

[0073] S160: forming a first dielectric layer and a first gate 152 in the first groove 141 , and forming a second dielectric layer and a second gate 162 in the second groove 142 ;

[0074] See also Figure 5e-Figure 5h In this embodiment, the first dielectric layer includes a first gate oxide layer 151 and a first gate protection layer 153, and the second dielectric layer includes a second gate oxide layer 161 and a second gate protection layer 163. The first gate oxide layer 151, the second gate oxide layer 161, the first gate protection layer 153 and the second gate protection layer 163 are all electrical insulating layers, such as SiO2 (silicon dioxide). The first gate 152 is surrounded by the first dielectric layer, and the second gate 162 is surrounded by the second dielectric layer.

[0075] In this embodiment, step S160 specifically includes:

[0076] A first gate oxide layer 151 and a second gate oxide layer 161 are formed in the first groove 141 and the second groove 142;

[0077] See also Figure 5f , a first gate oxide layer 151 and a second gate oxide layer 161 are formed on the surfaces of the first groove 141 and the second groove 142 by oxidation and / or deposition. In this embodiment, the first gate oxide layer 151 and the second gate oxide layer 161 are insulating layers, and the first gate oxide layer 151 and the second gate oxide layer 161 are, for example, SiO2.

[0078] A first gate 152 is formed in the first groove 141 , and a second gate 162 is formed in the second groove 142 ;

[0079] See also Figure 5g , a conductive material such as polysilicon is deposited in the first groove 141 and the second groove 142 , and then etched to form a first gate 152 and a second gate 162 , respectively.

[0080] A first gate protection layer 153 is formed over the first gate electrode 152 , and a second gate protection layer 163 is formed over the second gate electrode 162 .

[0081] See also Figure 5h The first gate protection layer 153 and the second gate protection layer 163 are, for example, SiO 2 or other insulating materials.

[0082] S170: forming a first p-type base region 154, a first source region 155, and a first p-type contact region 156 outside the electrical isolation region, and forming a second p-type base region 164, a second source region 165, and a second p-type contact region 166 inside the electrical isolation region;

[0083] See also Figure 5i In this embodiment, a first p-type base region 154, a first source region 155, and a first p-type contact region 156 are formed outside the electrical isolation region, wherein the first p-type base region 154 is on the first N-type epitaxial layer 131, the first p-type contact region 156 and the first source region 155 are respectively on the first p-type base region 154, the first p-type base region 154 is connected to the first source based on the first p-type contact region 156, and the first source region 155 is also connected to the first source. A second p-type base region 164, a second source region 165, and a second p-type contact region 166 are formed in the electrical isolation region, wherein the second p-type base region 164 is on the second N-type epitaxial layer 132, the second p-type contact region 166 and the second source region 165 are respectively on the second p-type base region 164, the second p-type base region 164 is connected to the second source based on the second p-type contact region 166, and the second source region 165 is connected to the second source.

[0084] S180: forming a fourth deep trench 145 in the electrical isolation region, wherein the fourth deep trench 145 extends from the upper surface of the second N-type epitaxial layer 132 to the second N+ doped layer 112;

[0085] See also Figure 5j In the present embodiment, the bottom of the fourth deep trench 145 contacts the second N+ doped layer 112. Specifically, the fourth deep trench 145 penetrates the second N+ doped layer 132 from the upper surface of the second N-type epitaxial layer 132 and extends to the upper surface of the second N+ doped layer 112, or the fourth deep trench 145 enters part of the second N+ doped layer 112, that is, at this time, the second N+ doped layer 112 is exposed.

[0086] S190 : forming a third dielectric layer 167 and a second drain connection portion 168 in the fourth deep trench 145 , and forming a first drain 157 on the lower surface of the first N+ substrate 111 .

[0087] See also Figure 5k-5l In this embodiment, a third dielectric layer 167 is first formed in the fourth deep trench 145, and the third dielectric layer 167 is located on the peripheral wall of the fourth deep trench 145. Then, a conductive material is deposited in the fourth deep trench 145 to form a second drain connection portion 168. The second drain connection portion 168 passes through the fourth deep trench 145, and the second drain connection portion 168 is surrounded by the third dielectric layer 167. The third dielectric layer 167 is used to electrically insulate the second N-type epitaxial layer 132 from the second drain connection portion 168. The lower end of the second drain connection portion 168 is connected to the second N+ doped layer 112, and the upper end of the second drain connection portion is also connected to the second drain, so as to realize the connection between the second N+ doped layer 112 and the drain, thereby forming a second power MOS tube. In this embodiment, the second drain connection portion 168 is, for example, tungsten, aluminum, polysilicon, etc., and the third dielectric layer 167 is an insulating material, for example, SiO2, etc. In this embodiment, a first drain 157 is formed on the lower surface of the first N+ substrate 111 to form a first power MOS tube.

[0088] In this embodiment, in the first power MOS tube, the current flows in from the first drain 157, and sequentially passes through the first N+ substrate 111, the first N-type epitaxial layer 131, the first p-type body region 154, and the first source region 155 to reach the first source, or vice versa; in the second power MOS tube, the current flows in from the second drain, and sequentially passes through the second drain connection portion 168, the second N+ doped layer 112, the second N-type epitaxial layer 132, the second p-type body region 164, and the second source region 165 to reach the second source, or vice versa. That is, in this embodiment, the current flow direction of the first power MOS tube and the second power MOS tube is a vertical flow direction, and under the same on-resistance, they have a smaller area than LDMOS (Lateral Double Diffused Metal Oxide Semiconductor FET).

[0089] Second embodiment

[0090] See also Figure 6 , Figure 6 This is a partial cross-sectional film layer diagram of the power integrated circuit of the second embodiment of the present application. This embodiment is similar to the first embodiment, so the parts not described in this embodiment can refer to the first embodiment. The main difference between this embodiment and the first embodiment is that the second N+ doped layer is not formed together with the first N+ substrate.

[0091] See also Figure 6 The power integrated circuit includes a first power MOS tube and a second power MOS tube, that is, the first power MOS tube and the second power MOS tube are made on the same semiconductor substrate, and the first power MOS tube and the second power MOS tube are connected in series. Here, the series connection means that the source of one power MOS tube is connected to the drain of the other power MOS tube.

[0092] In this embodiment, the first power MOS transistor includes a first drain 157, a first N+ substrate 111, a first N-type epitaxial layer 131, a first p-type body region 154, a first source region 155, a first p-type contact region 156, a first dielectric layer, a first source (not shown in the figure) and a first gate 152. Specifically, the first N+ substrate 111 is the substrate of the entire power integrated circuit and is arranged at the bottom of the entire power integrated circuit. A first drain 157 is formed on the lower surface of the first N+ substrate 111. The first drain 157 is the source of the first power MOS tube. The first N-type epitaxial layer 131 is located on the first N+ substrate 111. In this embodiment, the first N-type epitaxial layer 131 is divided into two layers, including a first-N-type epitaxial layer 131a and a first-second N-type epitaxial layer 131b. The first-second N-type epitaxial layer 131b is located on the first-N-type epitaxial layer 131a. A first p-type base region 154 and a first dielectric layer are provided on the first N-type epitaxial layer 131. A first gate 152 is provided in the first dielectric layer. The first p-type base region 154 is arranged around the first dielectric layer. A first source region 155 and a first p-type contact region 156 are provided on the first p-type base region 154. The first source region 155 and the first p-type contact region 156 are connected to the source.

[0093] In this embodiment, the power integrated circuit further includes a buried oxide layer 120 and an isolation column 144. The buried oxide layer 120 is formed in the first N-type epitaxial layer 131. In order to make the buried oxide layer 120 located at the lower part of the first N-type epitaxial layer 131 and reduce the impact on the performance of the second power MOS tube, in this embodiment, the buried oxide layer 120 is located in the first-N-type epitaxial layer 131a, and the longitudinal height of the first-N-type epitaxial layer 131b is greater than the longitudinal height of the first-N-type epitaxial layer 131a. The isolation column 144 extends downward from the upper surface of the first N-type epitaxial layer 131 to contact the buried oxide layer 120. Here, the isolation column 144 contacts the upper surface of the buried oxide layer 120 or the isolation column 144 extends into part of the buried oxide layer 120. In this embodiment, the buried oxide layer 120 extends integrally to the edge of the power integrated circuit, so that the buried oxide layer 120 electrically isolates the area above it from the area below it, that is, the buried oxide layer 120 is used for longitudinal electrical isolation, and the isolation column 144 extends from the buried oxide layer 120 to the upper surface of the first N-type epitaxial layer 131, so that the isolation column 144 electrically isolates the left area from the right area in the figure, that is, the isolation column 144 performs horizontal electrical isolation, and the isolation column 144 is combined with the buried oxide layer 120 to form a spatial electrical isolation area. The spatial electrical isolation area is a three-dimensional electrical isolation area, which can be a rectangular parallelepiped, a cube, a half cylinder, etc., wherein isolation is performed in the left and right directions by the isolation column 144, and isolation is performed in the vertical direction by the buried oxide layer 120.

[0094] In the present embodiment, a second power MOS transistor is formed in the spatial electrical isolation region, and the second power MOS transistor includes a second N+ doped layer 112, a second N-type epitaxial layer 132, a second p-type base region 164, a second source region 165, a second p-type contact region 166, a second dielectric layer, a second source (not shown in the figure) and a second gate 162, wherein the second N+ doped layer 112 is formed on the buried oxide layer 120, and the second N+ doped layer 112 and the first N+ substrate 111 are formed by a non-through process, and the second N+ doped layer 112 is formed by heavily N-doping the first N-type epitaxial layer 131a above the buried oxide layer 120, that is, the first N-type epitaxial layer 131a in the electrical isolation region is heavily N-doped to form the second N+ doped layer 112, and there is no first N-type epitaxial layer 131a in the electrical isolation region thereafter. The second N-type epitaxial layer 132 is located on the second N+ doped layer 112. The second N-type epitaxial layer 132 is formed synchronously with the first second N-type epitaxial layer 131b, which is beneficial to reducing the process steps. A second p-type base region 164 and a second dielectric layer are provided on the second N-type epitaxial layer 132. A second gate 162 is provided in the second dielectric layer. The second p-type base region 164 is arranged around the second dielectric layer. A second source region 165 and a second p-type contact region 166 are provided on the second p-type base region 164. The second source region 165 and the second p-type contact region 166 are both connected to the source.

[0095] In order to connect the electrical signal of the second N+ doped layer 112, in this embodiment, the second power MOS tube further includes a third dielectric layer 167 and a second drain connection portion 168, the second drain connection portion 168 is located in the third dielectric layer 167, the lower end of the second drain connection portion 168 is in contact with the second N+ doped layer 112, and the second drain connection portion 168 extends upward to the upper surface of the second N-type epitaxial layer 132, so as to connect the electrical signal of the second N+ doped layer 112 through the second drain connection portion 168, and the second drain connection portion 168 is connected to the second drain. The third dielectric layer 167 is used to isolate the second drain connection portion 168 from the second N-type epitaxial layer 132.

[0096] The present application also provides a method for manufacturing a power integrated circuit. The manufacturing method corresponds to the above power integrated circuit structure. Please refer to Figure 6-Figure 8m , the manufacturing method comprises:

[0097] S210: providing an N+ substrate 110, and forming a first N-type epitaxial layer 131a on the N+ substrate 110;

[0098] See also Figure 8a The N+ substrate 110 is the first N+ substrate 111 . The first N-type epitaxial layer 131 a is located on the first N+ substrate 111 . The first N-type epitaxial layer 131 a is relatively thin.

[0099] S220: forming a buried oxide layer 120 in the first N-type epitaxial layer 131a;

[0100] See also Figure 8b , oxygen ions are implanted into the upper portion of the first N-type epitaxial layer 131a, and then heated at a high temperature, the oxygen ions react with the first N-type epitaxial layer 131a to form a buried oxide layer 120 in the first N-type epitaxial layer 131a, and the buried oxide layer 120 is an electrical insulating layer. In this embodiment, the number of the buried oxide layer 120 is one.

[0101] S230: heavily doping the first N-type epitaxial layer 131a above the buried oxide layer 120 with N-type to form a second N+ doped layer 112;

[0102] See also Figure 8c The second N+ doped layer 112 is not a part of the first N+ substrate 111. The concentration of electrons in the second N+ doped layer 112 is equal to or similar to the concentration of electrons in the first N+ substrate 111. The second N+ doped layer 112 is located above the buried oxide layer 120. The second N+ doped layer 112 is formed by heavily doping the first N-type epitaxial layer 131a above the buried oxide layer 120 with N-type impurities. For example, pentavalent elements such as phosphorus (P) or arsenic (As) are doped in the first N-type epitaxial layer 131a.

[0103] S240: forming an N-type epitaxial layer 130 on the first N-type epitaxial layer 131 a and the second N+ doped layer 112 , and digging a third deep trench 143 in the N-type epitaxial layer 130 , wherein the third deep trench 143 extends downward to the buried oxide layer 120 ;

[0104] See also Figure 8d In this embodiment, a first second N-type epitaxial layer 131b is formed on the first first N-type epitaxial layer 131a, and a second N-type epitaxial layer 132 is formed on the second N+ doped layer 112. In this embodiment, a third deep trench 143 is formed on the N-type epitaxial layer 130, and the third deep trench 143 extends downward from its upper surface to the buried oxide layer 120, for example, the third deep trench 143 extends to the surface of the buried oxide layer 120 or extends into the buried oxide layer 120, the N-type epitaxial layer 130 located on the left side of the third deep trench 143 is the first second N-type epitaxial layer 131b, the N-type epitaxial layer 130 located on the right side of the third deep trench 143 is the second N-type epitaxial layer 132, the first second N-type epitaxial layer 131b is located on the first first N-type epitaxial layer 131a, and the second N-type epitaxial layer 132 is located on the second N+ doped layer 112. In this embodiment, the right side of the third deep trench 143 is all the second N+ doped layer 112 , that is, there is no first N-type epitaxial layer 131 a , and there is no second N+ doped layer 112 on the left side of the third deep trench 143 .

[0105] S250: forming an isolation column 144 in the third deep trench 143, wherein the isolation column 144 and the buried oxide layer 120 form a spatial electrical isolation region, wherein the N-type epitaxial layer is separated into a first second N-type epitaxial layer and a second N-type epitaxial layer by the isolation column and the buried oxide layer, and the first N-type epitaxial layer includes the remaining first first N-type epitaxial layer and the first second N-type epitaxial layer;

[0106] S260: digging a first groove 141 in the first N-type epitaxial layer 131 b and digging a second groove 142 in the second N-type epitaxial layer 132 ;

[0107] In this embodiment, the first trench 141 is formed in the first second N-type epitaxial layer 131 b , and the second trench 142 is formed in the second N-type epitaxial layer 132 .

[0108] S270: forming a first dielectric layer and a first gate 152 in the first groove 141 , and forming a second dielectric layer and a second gate 162 in the second groove 142 ;

[0109] S280: forming a first p-type base region 154, a first source region 155, and a first p-type contact region 156 outside the electrical isolation region, and forming a second p-type base region 164, a second source region 165, and a second p-type contact region 166 inside the electrical isolation region;

[0110] S290: forming a fourth deep trench 145 in the electrical isolation region, wherein the fourth deep trench 145 extends from the upper surface of the second N-type epitaxial layer 132 to the second N+ doped layer 112;

[0111] S300 : forming a third dielectric layer 167 and a second drain connection portion 168 in the fourth deep trench 145 , and forming a first drain 157 on the lower surface of the first N+ substrate 111 .

[0112] In this embodiment, the specific steps of steps S250 - S300 refer to the corresponding steps S140 - S190 of the first embodiment, which will not be described in detail here.

[0113] In this embodiment, the first power MOS tube and the second power MOS tube are also electrically isolated by the isolation column 144 and the buried oxide layer 120, and the drains of the two are also electrically isolated, so that the first power MOS tube and the second power MOS tube can be made on the same chip, so that the parasitic RCL caused by the package wiring and the PCB board-level interconnection is reduced, which is conducive to reducing the complexity of circuit design and improving robustness. Moreover, the isolation column and the buried oxide layer have good electrical isolation performance, and the first power MOS tube and the second power MOS tube are less affected by interference with each other. In addition, the first power MOS tube and the second power MOS tube are both VDMOS, and the current flows in the vertical direction when flowing, and the chip occupies a smaller area in the horizontal plane, which is conducive to cost saving. In addition, the power MOS tube located in the isolation column 144 and the buried oxide layer 120 is connected to the electrical signal of the second power MOS tube by setting the second drain connection part 168 and the third dielectric layer 167.

[0114] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0115] It should be understood that the "plurality" mentioned in this article refers to two or more. Those skilled in the art will easily think of other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary technical means in the art that are not disclosed in the present application. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present application are indicated by the following claims.

[0116] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0117] The above disclosure is only the preferred embodiment of the present application, which certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A power integrated circuit having two VDMOS connected in series, characterized in that: include: a buried oxide layer extending in a lateral direction; An isolation column extending in a longitudinal direction, wherein the isolation column and the buried oxide layer form a spatial electrical isolation region; a first power MOS transistor, which is located outside the electrical isolation region, and comprises a first drain, a first gate and a first source, wherein the first drain is located below the first gate and the first source; a second power MOS tube, which is located in the electrical isolation region, and comprises a second N+ doped layer, a second N-type epitaxial layer, a second p-type matrix region, a second dielectric layer, a second source region, a second drain, a second gate and a second source, wherein the second N+ doped layer is located on the buried oxide layer, the second N-type epitaxial layer is arranged on the second N+ doped layer, the second p-type matrix region is arranged on the second N-type epitaxial layer, the second dielectric layer is located in the second N-type epitaxial layer and the second p-type matrix region, a second gate is arranged in the second dielectric layer, the second source region is located on the second p-type matrix region, the second source region is connected to the second source, and the second N+ doped layer is connected to the second drain; The second drain and the first source are located on the same side of the horizontal plane where the second N+ doped layer is located and are electrically connected.

2. The power integrated circuit according to claim 1, characterized in that: The second power MOS tube also includes a third dielectric layer and a second drain connection portion, wherein the second drain connection portion extends downward from the upper surface of the second N-type epitaxial layer to contact the second N+ doped layer, the upper end of the second drain connection portion is connected to the second drain, and the third dielectric layer is arranged around the second drain connection portion to electrically insulate the second drain connection portion from the second N-type epitaxial layer.

3. The power integrated circuit according to claim 2, characterized in that: The longitudinal height of the third dielectric layer is smaller than the longitudinal height of the isolation column.

4. The power integrated circuit according to claim 3, characterized in that: A lower end of the second drain connecting portion contacts an upper surface of the second N+ doped layer or extends into a portion of the second N+ doped layer.

5. The power integrated circuit according to any one of claims 1 to 4, characterized in that: The second power MOS tube includes a first N+ substrate, a first N-type epitaxial layer, a first p-type base region, a first dielectric layer, and a first source region, wherein the first N-type epitaxial layer is arranged on the first N+ substrate, the first p-type base region is arranged on the first N-type epitaxial layer, the first drain is arranged below the first N+ substrate, the first dielectric layer is arranged in the first N-type epitaxial layer and the first p-type base region, the first gate is arranged in the first dielectric layer, the first source region is arranged on the first p-type base region, and the second source region is connected to the second source electrode; Wherein, the buried oxide layer is located between the first N+ substrate and the second N+ doped layer.

6. The power integrated circuit according to claim 5, characterized in that: The lower surface of the buried oxide layer is in contact with the first N+ substrate, and the upper surface of the buried oxide layer is in contact with the second N+ doped layer; or, The first N-type epitaxial layer includes a first-N-type epitaxial layer and a first-second N-type epitaxial layer, the first-N-type epitaxial layer is located on the first N+ substrate, the first-second N-type epitaxial layer is located on the first-N-type epitaxial layer, the lower surface of the buried oxide layer contacts the first-N-type epitaxial layer, and the upper surface of the buried oxide layer contacts the second N+ doped layer.

7. The power integrated circuit according to claim 5, characterized in that: The isolation column is located between the first N-type epitaxial layer and the second N-type epitaxial layer.

8. The power integrated circuit according to claim 5, characterized in that: The second N+ doped layer and the first N+ substrate belong to the same initial wafer substrate; or, The second N+ doped layer is formed by doping the first N-type epitaxial layer with N-type impurities.

9. A method for manufacturing a power integrated circuit, characterized in that: include: Providing an N+ substrate; Forming a buried oxide layer in the N+ substrate; An N-type epitaxial layer is formed on an N+ substrate, and a third deep trench is dug in the N-type epitaxial layer, wherein the third deep trench extends downward to the buried oxide layer; An isolation column is formed in the third deep trench, wherein the isolation column and the buried oxide layer form a spatial electrical isolation region, wherein the N+ substrate is separated into a first N+ substrate and a second N+ doped layer, and the N-type epitaxial layer is separated into a first N-type epitaxial layer and a second N-type epitaxial layer by the isolation column and the buried oxide layer; Digging a first groove and a second groove in the N-type epitaxial layer; forming a first dielectric layer and a first gate in the first groove, and forming a second dielectric layer and a second gate in the second groove, Forming a first p-type base region, a first source region, and a first p-type contact region outside the electrical isolation region, and forming a second p-type base region, a second source region, and a second p-type contact region inside the electrical isolation region; forming a fourth deep trench in the electrical isolation region, wherein the fourth deep trench extends from the upper surface of the second N-type epitaxial layer to the second N+ doped layer; A third dielectric layer and a second drain connection portion are formed in the fourth deep trench, and a first drain is formed on the lower surface of the first N+ substrate.

10. A method for manufacturing a power integrated circuit, characterized in that: include: Providing a first N+ substrate, and forming a first N-type epitaxial layer on the first N+ substrate; forming a buried oxide layer in the first N-type epitaxial layer; The first N-type epitaxial layer above the buried oxide layer is heavily N-doped to form a second N+ doped layer; An N-type epitaxial layer is formed on the first N-type epitaxial layer and the second N+ doped layer, and a third deep trench is dug in the N-type epitaxial layer, wherein the third deep trench extends downward to the buried oxide layer; An isolation column is formed in the third deep trench, wherein the isolation column and the buried oxide layer form a spatial electrical isolation region, wherein the N-type epitaxial layer is separated into a first second N-type epitaxial layer and a second N-type epitaxial layer by the isolation column and the buried oxide layer, and the first N-type epitaxial layer includes the remaining first first N-type epitaxial layer and the first second N-type epitaxial layer; Digging a first groove in the first N-type epitaxial layer and digging a second groove in the second N-type epitaxial layer; forming a first dielectric layer and a first gate in the first groove, and forming a second dielectric layer and a second gate in the second groove; Forming a first p-type base region, a first source region, and a first p-type contact region outside the electrical isolation region, and forming a second p-type base region, a second source region, and a second p-type contact region inside the electrical isolation region; forming a fourth deep trench in the electrical isolation region, wherein the fourth deep trench extends from the upper surface of the second N-type epitaxial layer to the second N+ doped layer; A third dielectric layer and a second drain connection portion are formed in the fourth deep trench.

Images