Semiconductor device

Abstract

A semiconductor device includes channel layers on a substrate, the channel layers being spaced apart from each other and having first and second side surfaces opposite to each other in a first direction; a gate electrode surrounding the channel layer, the gate electrode having a first end portion and a second end portion opposite to each other in the first direction; and a source / drain layer on a first side of the gate electrode and in contact with the channel layer, a portion of the source / drain layer protruding in a first direction relative to a first end portion of the gate electrode, wherein a first distance from a first end portion of the gate electrode to a first side surface of the channel layer is shorter than a second distance from a second end portion of the gate electrode to a second side surface of the channel layer.

Description

[0001] This application is a divisional application of the Chinese patent application “Semiconductor Device” (application number: 201910757604.3) with an application date of August 15, 2019.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the priority of Korean Patent Application No. 10-2018-0100509, entitled “Semiconductor Device”, filed on August 27, 2018 in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0004] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device having a plurality of vertically stacked channel layers. Background Art

[0005] A gate-all-around transistor has been proposed as a component for implementing scaling technology to increase the density of semiconductor devices. The gate-all-around transistor may include a plurality of active patterns in the form of nanowires or nanosheets on a substrate and a gate electrode covering a surface of the active pattern. Summary of the invention

[0006] According to example embodiments, a semiconductor device may include: a plurality of channel layers stacked on a substrate, the plurality of channel layers being spaced apart from each other and having a first side surface and a second side surface opposite to each other in one direction; a gate electrode surrounding the plurality of channel layers, the gate electrode having a first end and a second end opposite to each other in the one direction; and a source / drain layer in contact with the plurality of channel layers on one side of the gate electrode. A portion of the source / drain layer extends out relative to the first end of the gate electrode in the one direction. In the one direction, a first distance from the first end of the gate electrode to the first side surface of the plurality of channel layers is shorter than a second distance from the second end of the gate electrode to the second side surface of the plurality of channel layers.

[0007] According to example embodiments, a semiconductor device may include: a gate electrode on a substrate, the gate electrode having a first end and a second end, the second end being opposite to the first end in one direction; a plurality of nanosheets spaced apart from each other on the substrate, the plurality of nanosheets penetrating the gate electrode and having a first side surface and a second side surface, the second side surface being opposite to the first side surface in the one direction; a source / drain layer in contact with the plurality of nanosheets on one side of the gate electrode; and a gate isolation portion adjacent to the first end of the gate electrode. A portion of the source / drain layer protrudes relative to the first end of the gate electrode in the one direction, and a portion of the gate isolation portion and a portion of the source / drain layer overlap each other horizontally. In the one direction, a first distance from the first end of the gate electrode to the first side surface of the plurality of nanosheets is shorter than a second distance from the second end of the gate electrode to the second side surface of the plurality of nanosheets.

[0008] According to example embodiments, a semiconductor device may include: a first active region extending in a first direction; a plurality of first channel layers stacked and spaced apart from each other on the first active region, the plurality of first channel layers having first and second side surfaces opposite to each other in a second direction perpendicular to the first direction; a first gate electrode surrounding the plurality of first channel layers, the first gate electrode having a first end and a second end, the second end being opposite to the first end in the second direction; a first source / drain layer in contact with the plurality of first channel layers on one side of the gate electrode; a second active region extending in the first direction; a plurality of second channel layers spaced apart from each other on the second active region, the plurality of second channel layers having a third and fourth side surfaces opposite to each other in the second direction; a second gate electrode surrounding the plurality of second channel layers, the second gate electrode having a third and fourth end, the fourth end being opposite to the third end in the second direction; and a second source / drain layer in contact with the plurality of second channel layers on one side of the second gate electrode. At least a portion of the first source / drain layer protrudes in the second direction relative to the first end of the first gate electrode, and at least a portion of the second source / drain layer protrudes in the second direction relative to the third end of the second gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 shows a layout of a semiconductor device according to an example embodiment;

[0011] Figures 2 to 4 shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0012] Figures 5 to 10 shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0013] Fig.11 shows a layout of a semiconductor device according to an example embodiment;

[0014] Fig.12 and Fig.13 shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0015] Fig.14 shows a layout of a semiconductor device according to an example embodiment;

[0016] Fig.15 and Fig.16 shows a cross-sectional view of a semiconductor device according to example embodiments; and

[0017] Fig.17 A graph showing simulation results of an example embodiment is shown. DETAILED DESCRIPTION

[0018] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0019] Figure 1 is a layout of a semiconductor device according to example embodiments. Figures 2 to 4 yes Figure 1 A cross-sectional view of a semiconductor device in FIG. Figure 2 is along Figure 1 A cross-sectional view taken along line II' in FIG. Figure 3 is along Figure 1 A cross-sectional view taken along line II-II' in FIG. Figure 4 Shown along Figure 1 A cross-sectional view taken along line III-III' and line IV-IV'.

[0020] Reference Figure 1 , a semiconductor device according to example embodiments may include logic standard cells C disposed on a substrate. Each logic standard cell C includes an N-type transistor TN and a P-type transistor TP.

[0021] The logic standard cell C may include a first active area AN extending in a first direction (e.g., in the x direction), a first gate electrode GN extending in a second direction (e.g., in the y direction) to intersect with the first active area AN, a first source / drain layer SD disposed between the first gate electrodes GN, a second active area AP extending in the first direction (e.g., in the x direction), a second gate electrode GP extending in the second direction (e.g., in the y direction) to intersect with the second active area AP, and a second source / drain layer SG disposed between the second gate electrodes GP.

[0022] The N-type transistor TN includes a first active area AN, a first gate electrode GN and a first source / drain layer SD. The P-type transistor TP includes a second active area AP, a second gate electrode GP and a second source / drain layer SG.

[0023] The semiconductor device may further include a gate isolation portion 180 disposed between the first gate electrodes GN (e.g., between the first gate electrodes GN adjacent to each other in the y direction) and between the second gate electrodes GP (e.g., between the second gate electrodes GP adjacent to each other in the y direction). The semiconductor device may further include a contact plug 190 connected to the first source / drain layer SD and the second source / drain layer SG.

[0024] The gate isolation portion 180 may be disposed adjacent to the first end GC1 of the first gate electrode GN, and adjacent to the third end GC3 of the second gate electrode GP. The first gate electrode GN may have a second end opposite to the first end GC1, and the second gate electrode GP may have a fourth end opposite to the third end GC3. The second end of the first gate electrode GN and the fourth end of the second gate electrode GP may contact each other to form a contact portion GC2. Therefore, it should be understood that the contact portion GC2 is the same as the second end and the fourth end.

[0025] Reference Figure 2 , the semiconductor device may further include a substrate 101, in which a first well region PW and a second well region NW are formed. In the substrate 101, a first active region AN protrudes from the first well region PW, a second active region AP protrudes from the second well region NW, and a device isolation layer 105 is between the first active region AN and the second active region AP, between adjacent first active regions AN, and between adjacent second active regions AP. In addition, a first channel layer CN may be disposed on the first active region AN at a predetermined interval, a second channel layer CP may be disposed on the second active region AP at a predetermined interval, a first gate electrode GN may be disposed to cover (e.g., surround) the first channel layer CN, a second gate electrode GP may be disposed to cover (e.g., surround) the second channel layer CP, and a gate insulating layer GI may be disposed between the first gate electrode GN and the first channel layer CN and between the second gate electrode GP and the second channel CP. A gate isolation portion 180 may be disposed to contact a first end portion GC1 of the first gate electrode GN and a third end portion GC3 of the second gate electrode GP. A gate capping layer 175 may be disposed on the first gate electrode GN and the second gate electrode GP.

[0026] The substrate 101 may include a semiconductor material such as silicon, germanium or silicon germanium, or a III-V compound such as GaAs, AlGaAs, InAs, InGaAs, InSb, GaSb, InGaSb, InP, GaP, InGaP, InN, GaN or InGaN. In some embodiments, the substrate 101 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0027] The first well region PW, the first active region AN, and the first channel layer CN may include a P-type dopant. The second well region NW, the second active region AP, and the second channel layer CP may include an N-type dopant.

[0028] The first channel layer CN and the second channel layer CP may be nanosheets, each nanosheet having a width in, for example, the x and y directions greater than its thickness in, for example, the z direction. Each of the first channel layer CN and the second channel layer CP may have a width in the second direction (for example, in the y direction) ranging from about 10 nm to about 50 nm. The first channel layer CN may have a first side surface and a second side surface opposite to each other in the second direction (for example, in the y direction), and the second channel layer CP may have a third side surface and a fourth side surface opposite to each other in the second direction (for example, in the y direction). The first side surface and the second side surface of the first channel layer CN may have a curved surface, and the third side surface and the fourth side surface of the second channel layer CP may have a curved surface.

[0029] The first channel layer CN and the second channel layer CP may include a semiconductor material, such as silicon, germanium, etc. The number of the first channel layers CN and the number of the second channel layers CP are not limited to the numbers shown in the drawings.

[0030] The first gate electrode GN may also be disposed between the first active area AN and the first channel layer CN. The second gate electrode GP may also be disposed between the second active area AP and the second channel layer CP. The first gate electrode GN and the second gate electrode GP may extend in the second direction (eg, in the y direction) to the device isolation layer 105. The first gate electrode GN and the second gate electrode GP may contact each other between the first active area AN and the second active area AP to form a contact portion GC2 ( Figure 2 The contact portion GC2 may be the second end portion of the first gate electrode GN or the fourth end portion of the second gate electrode GP.

[0031] The first gate electrode GN may have a first end GC1 and a second end opposite to each other in the second direction (eg, in the y direction). The second gate electrode GP may have a third end GC3 and a fourth end opposite to each other in the second direction (eg, in the y direction).

[0032] The first end portion GC1 of the first gate electrode GN may be disposed such that the first channel layer CN is completely covered by the first gate electrode GN. The third end portion GC3 of the second gate electrode GP may be disposed such that the second channel layer CP is completely covered by the second gate electrode GP.

[0033] A first distance D1 from the first end GC1 of the first gate electrode GN to the first side surface of the first channel layer CN may be shorter than a second distance D2 from the second end of the first gate electrode GN to the second side surface of the first channel layer CN. The first distance D1 may be less than half of the width of each first channel layer CN in the second direction (e.g., the y direction). A third distance D3 from the third end GC3 of the second gate electrode GP to the third side surface of the second channel layer CP may be shorter than a fourth distance D4 from the fourth end of the second gate electrode GP to the fourth side surface of the second channel layer CP. The third distance D3 may be less than half of the width of each second channel layer CP in the second direction (e.g., the y direction).

[0034] The first distance D1 may be about 3 nanometers (nm) or less. The first distance D1 and the third distance D3 may be equal to each other, and the second distance D2 and the fourth distance D4 may be equal to each other.

[0035] The first gate electrode GN and the second gate electrode GP may include work function materials different from each other to adjust the threshold voltages of the N-type transistor TN and the P-type transistor TP. The work function material may include, for example, at least one of titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), titanium aluminum carbide (TiAlC), and tungsten nitride (WN).

[0036] The gate insulating layer GI may also be disposed between the first gate electrode GN and the first active area AN, between the first gate electrode GN and the device isolation layer 105, and between the first end portion GC1 of the first gate electrode GN and the gate isolation portion 180. The gate insulating layer GI may also be disposed between the second gate electrode GP and the second active area AP, between the second gate electrode GP and the device isolation layer 105, and between the third end portion GC3 of the second gate electrode GP and the gate isolation portion 180.

[0037] The gate insulating layer GI may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. The high-k dielectric material may refer to a dielectric material having a dielectric constant higher than that of a silicon oxide layer (SiO 2 ) dielectric material. High-k dielectric materials may include, for example, aluminum oxide (Al 2 O 3 )、Tantalum oxide(Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y2 O 3 )、ZrO 2 )、ZrO2 silicon(ZrSi x O y )、HfO 2 )、HfSiO x O y )、Lanthanum oxide(La 2 O 3 )、Lanthanum Aluminum Oxide(LaAl x O y ), lanthanum hafnium oxide (LaHf x O y )、HfAl x O y ) and praseodymium oxide (Pr 2 O 3 ) at least one of the following.

[0038] An interface insulating layer may be disposed between the first channel layer CN and the gate insulating layer GI and between the second channel layer CP and the gate insulating layer GI. The interface insulating layer may include an oxide, for example, silicon oxide.

[0039] Reference Figure 3 and Figure 4 , the first source / drain layer SD may be disposed on the first active area AN extending along the first direction (e.g., the x direction), and the second source / drain layer SG may be disposed on the second active area AP extending along the first direction (e.g., the x direction). The first channel layer CN may be disposed between the first source / drain layers SD, and the first source / drain layer SD may be in contact with the first channel layer CN. The second channel layer CP may be disposed between the second source / drain layers SG, and the second source / drain layer SG may be in contact with the second channel layer CP.

[0040] The gate spacer GS may be disposed on the sidewalls of the first gate electrode GN and the second gate electrode GP. The gate spacer GS may be formed of an insulating material. The gate capping layer 175 disposed to cover the first gate electrode GN and the second gate electrode GP may include nitride, for example, silicon nitride.

[0041] The contact plug 190 may be disposed on the first source / drain layer SD and the second source / drain layer SG. The contact plug 190 may penetrate the interlayer dielectric 160 to contact the first source / drain layer SD and the second source / drain layer SG. The interlayer dielectric 160 may include, for example, silicon oxide, such as tetraethyl orthosilicate (TEOS).

[0042] A portion of the first source / drain layer SD may extend in the second direction (eg, y direction) relative to the first end portion GC1 of the first gate electrode GN. A portion of the second source / drain layer SG may extend in the second direction (eg, y direction) relative to the third end portion GC3 of the second gate electrode GP.

[0043] Figures 5 to 10 is a cross-sectional view according to an example embodiment of the present disclosure, corresponding to Figure 2 Since these semiconductor devices are similar to reference Figure 2 The semiconductor device described herein will therefore be omitted. Figure 2 Detailed description of elements identical to those shown in .

[0044] Reference Figure 5 , in the semiconductor device, the first end GC1 of the first gate electrode GN may be aligned with the first side surface of the first channel layer CN. For example, the first distance from the first end GC1 of the first gate electrode GN to the first side surface of the first channel layer CN is 0 nm. The third end GC3 of the second gate electrode GP may be aligned with the third side surface of the second channel layer CP. For example, the third distance from the third end GC3 of the second gate electrode GP to the third side wall of the second channel layer CP is 0 nm.

[0045] Reference Figure 6 In the semiconductor device, the first side surface of the first channel layer CN may extend relative to the first end GC1 of the first gate electrode GN, for example, the first side surface of the first channel layer CN may extend beyond the first gate electrode GN in the y direction into the gate isolation portion 180. For example, a first distance D1' (for example, within the gate isolation portion 180) from the first end GC1 of the first gate electrode GN to the first side surface of the first channel layer CN may be about 3 nm or less. The first distance D1' may be shorter than the second distance D2. The third side surface of the second channel layer CP may extend relative to the third end GC3 of the second gate electrode GP, for example, the third side surface of the second channel layer CP may extend beyond the second gate electrode GP in the y direction into the gate isolation portion 180. For example, a third distance D3' from the third end GC3 of the second gate electrode GP to the third side surface of the second channel layer CP may be about 3 nm or less. The third distance D3' may be shorter than the fourth distance D4.

[0046] A first side surface of the first channel layer CN extending relative to the first end portion GC1 of the first gate electrode GN may have a curved surface and may be in contact with the gate isolation portion 180. The gate isolation portion 180 may cover the first side surface of the first channel layer CN extending relative to the first end portion GC1 of the first gate electrode GN. A third side surface of the second channel layer CP extending relative to the third end portion GC3 of the second gate electrode GP may have a curved surface and may be in contact with the gate isolation portion 180. The gate isolation portion 180 may cover the third side surface of the second channel layer CP extending relative to the third end portion GC3 of the second gate electrode GP.

[0047] Reference Figure 7 In the semiconductor device, the first gate electrode GN may include a first lower electrode portion GNa and a first upper electrode portion GNb, the first upper electrode portion GNb being disposed on the first lower electrode portion GNa and extending less than the first lower electrode portion GNa in the second direction (eg, y direction). Figure 7 As shown in , the first upper electrode portion GNb may be aligned with the edge of the first channel layer CN, and the first lower electrode portion GNa may extend beyond the edge of the first channel layer CN in the y direction. The first upper electrode portion GNb may be configured to cover (e.g., overlap) a portion of the uppermost first channel layer CN in the first channel layers CN, and the first lower electrode portion GNa may be configured to cover the remaining channel layers CN. The first upper electrode portion GNb may not cover a portion of the first side surface of the uppermost first channel layer CN. The first end GC1 of the first upper electrode portion GNb may be aligned with the first side surface of the uppermost first channel layer CN. In the second direction (e.g., the y direction), the first distance D1 from the first end GC1 of the first lower electrode portion GNa to the first side surface of the first channel layer CN may be shorter than the second distance D2 from the second end GC2 of the first gate electrode GN to the second side surface of the first channel layer CN.

[0048] The second gate electrode GP may include a second lower electrode portion GPa and a second upper electrode portion GPb, the second upper electrode portion GPb being disposed on the second lower electrode portion GPa and extending less than the second lower electrode portion Gpa in the second direction (e.g., the y direction). The second upper electrode portion GPb may be disposed to cover a portion of the uppermost second channel layer CP in the second channel layer CP, and the second lower electrode portion GPa may be disposed to cover other second channel layers CP. The second upper electrode portion GPb may not cover a portion of the third side surface of the uppermost second channel layer CP. The third end GC3 of the second upper electrode portion GPb may be aligned with the third side surface of the uppermost second channel layer CP. In the second direction (e.g., the y direction), a third distance D3 from the third end GC3 of the second lower electrode portion GPa to the third side surface of the second channel layer CP may be shorter than a fourth distance D4 from the fourth end GC2 of the second gate electrode GP to the fourth side surface of the second channel layer CP.

[0049] The gate isolation portion 180 may include a lower gate isolation portion 180a and an upper gate isolation portion 180b, the upper gate isolation portion 180b being disposed on the lower gate isolation portion 180a and having a length in the second direction (e.g., in the y direction) greater than that of the lower gate isolation portion 180a. The first distance D1 may be equal to the length of a protrusion of the upper gate isolation portion 180b from the lower gate isolation portion 180a, for example, the first distance D1 may be equal to the length of a portion of the upper gate isolation portion 180b protruding beyond an edge of the lower gate isolation portion 180a in the second direction.

[0050] Reference Figure 8 In the semiconductor device, the first gate electrode GN may include a first lower electrode portion GNa and a first upper electrode portion GNb′, the first upper electrode portion GNb′ being disposed on the first lower electrode portion GNa and extending less than the first lower electrode portion GNa in the second direction (eg, the y direction). The first upper electrode portion GNb′ may extend less than Figure 7 The first side surface of the uppermost first channel layer CN may protrude relative to the first upper electrode portion GNb' of the first gate electrode GN, and a lower region of the first side surface of the uppermost first channel layer CN may be covered by the first lower electrode portion GNa.

[0051] The second gate electrode GP may include a second lower electrode portion GPa and a second upper electrode portion GPb′, the second upper electrode portion GPb′ being disposed on the second lower electrode portion GPa and extending less than the second lower electrode portion GPa in a second direction (eg, y direction). The second upper electrode portion GPb′ may extend less than Figure 7The third side surface of the uppermost second channel layer CP may protrude relative to the second upper electrode portion GPb′ of the second gate electrode GP, and a lower region of the third side surface of the uppermost second channel layer CP may be covered by the second lower electrode portion GPa.

[0052] The gate isolation portion 180 may include a lower gate isolation portion 180a and an upper gate isolation portion 180b', and the width of the upper gate isolation portion 180b' in the second direction (eg, the y direction) is greater than the width of the lower gate isolation portion 180a. The width of the upper gate isolation portion 180b' may be greater than Figure 7 The upper gate isolation portion 180b' of the gate isolation portion 180 may be in contact with a first side surface of the uppermost first channel layer CN and a third side surface of the uppermost second channel layer CP.

[0053] Reference Fig. 9 , a first side surface of the first channel layer CN may extend relative to the first end portion GC1 of the first gate electrode GN. A first distance D1' from the first end portion GC1 of the first gate electrode GN to the first side surface of the first channel layer CN may be substantially equal to the thickness of the gate insulating layer GI. The first distance D1' may be shorter than the second distance D2. A third side surface of the second channel layer CP may extend relative to the third end portion GC3 of the second gate electrode GP. A distance D3' from the third end portion GC3 of the second gate electrode GP to the third side surface of the second channel layer CP may be substantially equal to the thickness of the gate insulating layer GI. The third distance D3' may be shorter than the fourth distance D4.

[0054] A first side surface of the first channel layer CN protruding relative to the first end portion GC1 of the first gate electrode GN may be a plane (e.g., flat) and may be in contact with the gate isolation portion 180. A third side surface of the second channel layer CP protruding relative to the third end portion GC3 of the second gate electrode GP may be a plane (e.g., flat) and may be in contact with the gate isolation portion 180.

[0055] Reference Fig.10 , the gate isolation portion 180 may be biased to one side in the second direction (eg, the y direction). In order to form the gate isolation portion 180, a structure may be formed as a photolithography process to form an isolation hole, and the isolation hole is misaligned. Figure 2 The semiconductor devices in the Fig.10 The first distance D1 and the third distance D3 of the semiconductor device in the embodiment may be different from each other. Fig.10 In the case of a semiconductor device in FIG. 1 , the first distance D1 may be shorter and the third distance D3 may be longer.

[0056] Fig.11is a layout of a semiconductor device according to example embodiments. Fig.12 is along Fig.11 A cross-sectional view taken along line II' in FIG. Fig.13 is along Fig.11 The cross-sectional view is taken along the line II-II' in FIG. Figures 11 to 13 The semiconductor device in Figures 1 to 4 Therefore, the semiconductor devices in Figures 1 to 4 Detailed description of elements identical to those shown in .

[0057] Reference Figures 11 to 13 , a semiconductor device according to example embodiments may include a gate isolation portion 180 disposed between the first gate electrodes GN and a gate isolation portion 180' disposed between the second gate electrodes GP in a second direction (e.g., y direction). In the second direction (e.g., in the y direction), a length of the gate isolation portion 180' may be shorter than a length of the gate isolation portion 180. In the second direction (e.g., in the y direction), a length of the second gate electrode GP may be greater than a length of the first gate electrode GN.

[0058] Therefore, the first distance D1 from the first end GC1 of the first gate electrode GN to the first side surface of the first channel layer CN may not be equal to the third distance D3 from the third end GC3 of the second gate electrode GP to the third side surface of the second channel layer CP. The third distance D3 may be longer than the first distance D1. The first distance D1 may be less than half of the width of each first channel layer CN in the second direction (e.g., y direction). The first distance D1 may be about 3 nm or less.

[0059] A portion of the first source / drain layer SD may extend relative to the first end portion GC1 of the first gate electrode GN. For example, a horizontal edge of the first source / drain layer SD may extend beyond the first end portion GC1 of the first gate electrode GN. Fig.13 The second source / drain layer SG may not extend relative to the third end GC3 of the second gate electrode GP. For example, the horizontal edge of the second source / drain layer SG may not reach the third end GC3 of the second gate electrode GP ( Fig.13 For example, Fig.11 As shown in FIG. 1 , the gate isolation portion 180 may horizontally overlap a portion of the first source / drain layer SD (as seen in the top view), while the gate isolation portion 180 ′ may not horizontally overlap the second source / drain layer SG (as seen in the top view).

[0060] Fig.14 is a layout of a semiconductor device according to example embodiments. Fig.15 is along Fig.14 A cross-sectional view taken along line II' in FIG. Fig.16 is along Fig.14 The cross-sectional view is taken along the line II-II' in FIG. Figures 14 to 16 The semiconductor device in Figures 1 to 4 Therefore, the semiconductor devices in Figures 1 to 4 Detailed description of elements identical to those shown in .

[0061] Reference Figures 14 to 16 , a semiconductor device according to example embodiments may include a gate isolation portion 180" disposed between the first gate electrodes GN and a gate isolation portion 180 disposed between the second gate electrodes GP in a second direction (e.g., the y direction). In the second direction (e.g., the y direction), a length of the gate isolation portion 180" may be shorter than a length of the gate isolation portion 180. In the second direction (e.g., the y direction), a length of the first gate electrode GN may be greater than a length of the second gate electrode GP.

[0062] Therefore, the first distance D1 from the first end GC1 of the first gate electrode GN to the first side surface of the first channel layer CN may not be equal to the third distance D3 from the third end GC3 of the second gate electrode GP to the third side surface of the second channel layer CP. The first distance D1 may be longer than the third distance D3. The third distance D3 may be less than half of the width of each second channel layer CP in the second direction (e.g., y direction). The third distance D3 may be about 3 nm or less.

[0063] A portion of the second source / drain layer SG may extend relative to the third end portion GC3 of the second gate electrode GP, while the first source / drain layer SD may not extend relative to the first end portion GC1 of the first gate electrode GN. Fig.14 As shown in FIG. 1 , the gate isolation portion 180 may horizontally overlap a portion of the second source / drain layer SG (as seen in the top view), while the gate isolation portion 180″ may not horizontally overlap the first source / drain layer SD (as seen in the top view).

[0064] Fig.17 is a graph showing simulation results of an example embodiment.

[0065] Reference Fig.17 In the case of the example embodiment, it can be seen that the reduction in the length of the gate electrode extending from the side surface of the channel layer (nanosheet) leads to a higher operating speed. For example, it can be seen that when the length of the gate electrode extending from the side surface of the channel layer is 0 nm (in a structure in which the side surface of the channel layer and the end of the gate electrode are aligned with each other), the operating speed is the fastest. In this case, the operating speed is increased by about 6 percent (%) compared to the comparative example. The reduction in parasitic capacitance caused by the reduction in the length of the gate electrode extending from the side surface of the channel layer (nanosheet) leads to an increase in the operating speed.

[0066] In addition, it can be seen that when the length of the gate electrode extending from the side surface of the channel layer has a negative (-) value, the operating speed is reduced again. The negative (-) value of the extended gate electrode refers to a structure in which the side surface of the channel layer protrudes relative to the end of the gate electrode. Since the gate electrode does not cover the side surface of the channel layer, the leakage current caused by the short channel effect increases, thereby reducing the operating speed again.

[0067] As described above, in the semiconductor device according to the example embodiment, parasitic capacitance can be reduced and the operating speed can be increased, thereby improving electrical characteristics. That is, for example, when the gate does not extend beyond the source / drain, a semiconductor device (e.g., a multi-bridge channel (MBC)-FET device) having a large nanosheet width (e.g., 10 nm or more) can have an asymmetric gate, thereby reducing parasitic capacitance. The deviation between the gate edge and the channel edge can be in the range of about (-3) nm to (+3) nm.

[0068] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some cases, as known to those of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in conjunction with a specific embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise specifically noted. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: A first active fin and a second active fin protrude from the substrate in a vertical direction perpendicular to an upper surface of the substrate, and the first active fin and the second active fin extend in a first direction perpendicular to the vertical direction; a plurality of first channel layers vertically stacked on the first active fin to be spaced apart from each other in the vertical direction, the plurality of first channel layers having a first side surface and a second side surface, the second side surface being opposite to the first side surface in a second direction perpendicular to each of the first direction and the vertical direction; a plurality of second channel layers vertically stacked on the second active fin to be spaced apart from each other in the vertical direction, the plurality of second channel layers having a third side surface and a fourth side surface, the fourth side surface being opposite to the third side surface in the second direction; a first source / drain layer on the first active fin to contact the plurality of first channel layers; a second source / drain layer on the second active fin to contact the plurality of second channel layers; a first gate electrode extending in the second direction and surrounding the plurality of first channel layers and the plurality of second channel layers, the first gate electrode having a first end and a second end opposite to each other in the second direction, and the first gate electrode having a central portion located between the first end and the second end in the second direction at substantially the same distance from each of the first end and the second end; an interlayer dielectric layer, on the first source / drain layer and the second source / drain layer; as well as a gate isolation pattern, adjacent to the first end portion and the second end portion of the first gate electrode, respectively; wherein a first distance from the first end of the first gate electrode to the first side surface of the plurality of first channel layers in the second direction is shorter than a second distance from the center of the first gate electrode to the second side surface of the plurality of first channel layers in the second direction, and wherein a third distance from the second end of the first gate electrode to the third side surface of the plurality of second channel layers in the second direction is shorter than a fourth distance from the center of the first gate electrode to the fourth side surface of the plurality of second channel layers in the second direction.

2. The semiconductor device according to claim 1, further comprising: a third active fin protruding from the substrate in the vertical direction, the third active fin extending in the first direction; a plurality of third channel layers vertically stacked on the third active fin to be spaced apart from each other in the vertical direction, the plurality of third channel layers having a fifth side surface; as well as a second gate electrode extending in the second direction around the plurality of third channel layers, the second gate electrode having a third end facing the first end of the first gate electrode, and the second gate electrode being spaced apart from the first gate electrode by the gate isolation pattern, wherein the fifth side surfaces of the plurality of third channel layers face the first side surfaces of the plurality of first channel layers, and Wherein, a fifth distance from the third end of the second gate electrode to the fifth side surface of the plurality of third channel layers is shorter than the second distance.

3. The semiconductor device according to claim 1, wherein The first active fin includes impurities of a different conductivity type relative to impurities of the second active fin.

4. The semiconductor device according to claim 1, wherein: A width of each of the plurality of first channel layers and at least one of the plurality of second channel layers in the second direction is in a range of about 10 nm to about 50 nm.

5. The semiconductor device according to claim 1, wherein At least one of the first side surface, the second side surface, the third side surface, and the fourth side surface has a curved surface convex outward.

6. The semiconductor device according to claim 1, wherein The plurality of first channel layers or the plurality of second channel layers include germanium Ge.

7. The semiconductor device according to claim 1, wherein: At least one of the first side surfaces of the plurality of first channel layers is substantially flat, and At least one of the second side surfaces of the plurality of first channel layers has a curved surface convex outward.

8. The semiconductor device according to claim 7, wherein: The at least one substantially flat first side surface of the plurality of first channel layers contacts one of the gate isolation patterns adjacent to the first end portion of the first gate electrode.

9. The semiconductor device according to claim 7, wherein: The first gate electrode includes an inner portion at a level between the plurality of first channel layers, and The at least one substantially flat first side surface of the plurality of first channel layers protrudes relative to an end of the inner portion of the first gate electrode and contacts one of the gate isolation patterns adjacent to the first end of the first gate electrode.

10. The semiconductor device according to claim 1, wherein: One of the gate isolation patterns includes a lower isolation pattern and an upper isolation pattern on the lower isolation pattern, and A first length of the lower isolation pattern in the second direction is different from a second length of the upper isolation pattern in the second direction.

11. The semiconductor device according to claim 1, wherein The first gate electrode comprises: an inner portion at a level between the plurality of first channel layers; and an upper portion at a level higher than an uppermost first channel layer among the plurality of first channel layers, Wherein, in a cross-sectional view along the second direction, an end portion of the inner portion adjacent to the gate isolation pattern is not aligned with an end portion of the upper portion adjacent to the gate isolation pattern.

12. The semiconductor device according to claim 1, wherein: One of the gate isolation patterns has a side surface facing the first end portion of the first gate electrode, and The side surface of one of the gate isolation patterns includes a bent portion so that a length of an upper portion of one of the gate isolation patterns in the second direction is different from a length of a lower portion of one of the gate isolation patterns in the second direction.

13. The semiconductor device according to claim 1, wherein A bottom of the first gate electrode is at a lower level than a top of the first active fin and a top of the second active fin.

14. The semiconductor device according to claim 1, wherein At least a portion of the first source / drain layer protrudes in the second direction relative to the first end portion of the first gate electrode.

15. The semiconductor device according to claim 1, wherein The first distance is shorter than the fourth distance.

16. The semiconductor device according to claim 15, wherein: The fourth distance is shorter than the second distance.

17. The semiconductor device according to claim 1, wherein The first distance is less than half of a width of each of the plurality of first channel layers in the first direction.

18. The semiconductor device according to claim 1, wherein The first end portion of the first gate electrode covers the first side surfaces of the plurality of first channel layers, and the first distance is about 3 nm or less.

19. The semiconductor device according to claim 1, wherein The first side surfaces of the plurality of first channel layers are aligned with the first end portion of the first gate electrode.

20. The semiconductor device according to claim 1, wherein The first side surfaces of the plurality of first channel layers protrude relative to the first end portion of the first gate electrode, and the first side surfaces of the plurality of first channel layers protrude relative to the first end portion of the first gate electrode and have a curved surface convex outward.

21. A semiconductor device comprising: A first active fin, a second active fin, a third active fin and a fourth active fin protrude from the substrate in a vertical direction perpendicular to an upper surface of the substrate, and the first active fin, the second active fin, the third active fin and the fourth active fin extend in a first direction perpendicular to the vertical direction; a plurality of first channel layers, a plurality of second channel layers, a plurality of third channel layers, and a plurality of fourth channel layers, respectively vertically stacked on the first active fin, the second active fin, the third active fin, and the fourth active fin, wherein each of the plurality of first channel layers, the plurality of second channel layers, the plurality of third channel layers, and the plurality of fourth channel layers are spaced apart from each other in a vertical direction; A first gate electrode, a second gate electrode, a third gate electrode, and a fourth gate electrode extending in a second direction perpendicular to each of the first direction and the vertical direction, the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode respectively surrounding the plurality of first channel layers, the plurality of second channel layers, the plurality of third channel layers, and the plurality of fourth channel layers; a first gate isolation pattern between the first gate electrode and the second gate electrode; as well as a second gate isolation pattern, between the third gate electrode and the fourth gate electrode, wherein the first gate isolation pattern has a first length in the second direction, wherein the second gate isolation pattern has a second length in the second direction, and Wherein, the first length is different from the second length.

22. The semiconductor device according to claim 21, wherein The first length is longer than the second length.

23. The semiconductor device according to claim 21, wherein: Each of the first active fin and the second active fin includes N-type conductive impurities, and Each of the third active fin and the fourth active fin includes P-type conductive type impurities.

24. The semiconductor device according to claim 21, wherein: Each of the first active fin and the second active fin includes a P-type conductive impurity, and Each of the third active fin and the fourth active fin includes N-type conductive type impurities.

25. The semiconductor device according to claim 21, further comprising a source / drain layer on the first active fin to contact the plurality of first channel layers, at least a portion of the source / drain layer protruding in the second direction relative to an end of the first gate electrode contacting the first gate isolation pattern.

26. The semiconductor device according to claim 21, wherein: The plurality of second channel layers have a first side surface and a second side surface, the second side surface being opposite to the first side surface in the second direction, The plurality of third channel layers have a third side surface and a fourth side surface, the fourth side surface being opposite to the third side surface in the second direction, The second side surfaces of the plurality of second channel layers face the third side surfaces of the plurality of third channel layers in the second direction, The second gate electrode has a first end portion contacting the first gate isolation pattern in the second direction, The third gate electrode has a second end portion contacting the second gate isolation pattern in the second direction, and A first distance from the first end of the first gate electrode to the first side surface of the plurality of second channel layers in the second direction is shorter than a second distance from the second end of the third gate electrode to the fourth side surface of the plurality of third channel layers in the second direction.

27. The semiconductor device according to claim 26, wherein: The second gate electrode and the third gate electrode include a contact portion therebetween, the contact portion contacting each of the second gate electrode and the third gate electrode, and A third distance from the contact portion between the second gate electrode and the third gate electrode to the second side surfaces of the plurality of second channel layers is longer than the second distance.

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