Preparation method of PD-SOI device and device
By forming bumps and buried oxygen layers of a specific structure on the first substrate of the PD-SOI device, and forming device structure and body contact areas on the top silicon layer, the floating body effect and heat dissipation problems in the device are solved, and better performance and heat dissipation effects are achieved.
Patent Information
- Application Number
- CN202411999332.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-05-06
AI Technical Summary
The floating body effect in PD-SOI devices causes a sudden increase in drain-source current, affecting the performance of the analog circuit. At the same time, due to the low thermal conductivity of the buried oxygen layer, the device's heat dissipation is not good.
By forming several first bumps and at least three second bumps on the first surface of the first substrate, and thinning the top silicon layer of a preset thickness on the second surface of the first substrate, the gate structure of the device structure is located directly above the first bump and is in communication with the body contact area to release carriers and suppress the floating body effect. At the same time, several first bumps come into contact with the buried oxygen layer, enhancing the heat dissipation ability of the device.
It effectively suppresses the floating body effect of PD-SOI devices, improves the heat dissipation ability of the device, and improves the performance of the device in analog circuits.
Smart Images
Figure CN119947243A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor devices, and in particular to a preparation method and a PD-SOI device. Background Art
[0002] PD-SOI devices (Partially Depleted_Silicon-On-Insulator) have the advantages of low leakage current, high anti-interference ability, high integration, fast reaction rate, and complete elimination of latch-up effect due to the presence of the top silicon layer on SOI. However, the transistors in the PD-SOI device form a capacitor relative to the buried oxide layer in SOI, and the body potential and bias of the PD-SOI device are related to carrier recombination, which makes it easy for charges to accumulate on the surface of the buried oxide layer, i.e., the floating body effect, which in turn has an adverse effect on the application of PD-SOI devices in analog circuits. For example, the floating body effect of the PD-SOI device can cause the drain-source current of the device to suddenly increase, which affects the performance of the analog circuit. Therefore, it is very important to suppress the floating body effect of the PD-SOI device. At the same time, because the buried oxide layer in the SOI wafer is made of silicon oxide, its thermal conductivity is much lower than that of silicon, so there are also problems with the heat dissipation of the PD-SOI device.
[0003] Therefore, how to effectively suppress the floating body effect of PD-SOI devices has become a technical problem that the industry urgently needs to solve. Summary of the invention
[0004] The embodiment of the present invention provides a method for preparing a PD-SOI device and a device, so as to effectively suppress the floating body effect of the PD-SOI device.
[0005] In order to solve the above technical problems, the technical solution of the present invention provides a method for preparing a PD-SOI device, comprising:
[0006] providing a first substrate;
[0007] Forming a plurality of first bumps in a first preset area of the first surface of the first substrate, and forming at least three second bumps in a second preset area of the first surface of the first substrate; wherein the thickness of the first bump is less than the thickness of the second bump;
[0008] depositing a buried oxide layer on the first surface of the first substrate;
[0009] Providing a second substrate, and bonding the first surface of the second substrate to the buried oxide layer;
[0010] Thinning the second surface of the first substrate to form a top silicon layer of a preset thickness in the first preset area and expose the buried oxide layer;
[0011] forming a device structure on the top silicon layer, wherein a gate structure of the device structure is formed on a surface of the top silicon layer, and the gate structure is located directly above one of the first bumps;
[0012] A body contact region is formed in a preset position of the top silicon layer, and the preset position is located at the periphery of the device structure, and the body contact region is connected to the first bump.
[0013] Optionally, forming a plurality of first bumps in a first preset area on the first surface of the first substrate specifically includes:
[0014] depositing a first hard mask layer on the first surface of the first substrate;
[0015] Forming a patterned first mask on the surface of the first hard mask layer, wherein the first mask includes a plurality of first bump blocking regions, at least three third bump blocking regions, and a window region;
[0016] Using the patterned first mask as a mask, the first hard mask layer and the first substrate in the window area are etched in sequence, with the etching endpoint staying in the first substrate, so as to form the plurality of first bumps and at least three third bumps.
[0017] Optionally, forming at least three second bumps on the second preset area specifically includes:
[0018] After forming the first bump, depositing a second hard mask layer on the first surface of the first substrate;
[0019] The second hard mask layer and the first substrate in the third bump spacing region are sequentially etched, with the etching endpoint staying within the first substrate, to form at least three second bumps, wherein the thickness of the second bumps is greater than that of the third bumps.
[0020] Optionally, the plurality of first bumps are evenly distributed, and a width of the first bump is less than or equal to a width of the gate structure.
[0021] Optionally, the buried oxide layer has a thickness greater than a thickness of the second bump.
[0022] Optionally, the thickness of the buried oxide layer is between 100nm and 200nm, and the thickness of the second bump is between 80nm and 180nm.
[0023] Optionally, the preset thickness is between 50nm and 100nm.
[0024] Optionally, depositing a buried oxide layer on the first surface of the first substrate specifically includes:
[0025] depositing an oxide on the first surface of the first substrate;
[0026] The surface of the oxide is subjected to chemical mechanical polishing to form the buried oxide layer.
[0027] The technical solution of the present invention further provides a PD-SOI device, characterized in that it comprises:
[0028] substrate;
[0029] A buried oxide layer, located on the surface of the first substrate;
[0030] A top silicon layer is located on the surface of the buried oxide layer; a side of the top silicon layer facing the buried oxide layer includes a plurality of first bumps;
[0031] A device structure is located on a side of the top silicon layer facing away from the buried oxide layer, a gate structure of the device structure is located on a surface of the top silicon layer, and the gate structure is located directly above one of the first bumps;
[0032] A body contact region is located at a preset position of the top silicon layer and is connected to the first bump, and the preset position is located at the periphery of the device structure.
[0033] Optionally, the width of the first bump is less than or equal to the width of the gate structure.
[0034] Optionally, the spacing between the plurality of first protrusions meets a preset minimum design dimension.
[0035] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:
[0036] The preparation method of the PD-SOI device provided by the technical solution of the present invention forms a plurality of first bumps in a first preset area of the first surface of the first substrate, and thins the second surface of the first substrate to form a top silicon layer of a preset thickness. Therefore, the thickness of the top silicon layer at the first bump is greater than the thickness of the top silicon layer in other areas. When the device structure and the body contact area are subsequently formed on the top silicon layer, the gate structure of the device structure is located directly above the first bump, and the first bump is connected to the body contact area to release the carriers accumulated in the top silicon layer corresponding to the first bump through the body contact area, thereby effectively suppressing the floating body effect of the PD-SOI device. While forming the first bump, at least three second bumps are also formed on the second preset area of the first surface of the first substrate, and after the first substrate is thinned, the buried oxide layer located between the second bumps and exposed is used as a positioning mark, which can be used as an alignment mark for subsequent process steps. At the same time, the plurality of first bumps are in contact with the buried oxide layer, thereby enhancing the overall heat dissipation capacity of the PD-SOI device.
[0037] Furthermore, after forming the plurality of first bumps and at least three third bumps, the second hard mask layer is deposited and etched to form the at least three second bumps, thereby saving one photomask and thus reducing the manufacturing cost of the device.
[0038] Furthermore, since the plurality of first bumps are evenly distributed, not only can the buried oxide layer be formed more evenly and flatly, but the symmetry of the device structure can also be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Figure 1A-Figure 1C Top views of NMOS structures using body contact to suppress floating body effect provided in three implementations respectively;
[0040] Figure 1D for Figure 1A The top view of the actual structure of the NMOS structure prepared by the actual process;
[0041] Figure 2 A flow chart of the preparation of a PD-SOI device provided in an embodiment of the present invention;
[0042] Figures 3 to 14 They are schematic diagrams of simplified cross-sectional structures corresponding to the PD-SOI device provided by the embodiments of the present invention in different preparation processes;
[0043] Fig.15 It is a simplified cross-sectional schematic diagram of the PD-SOI device provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0045] The problems existing in the PD-SOI device of the prior art will be described below with reference to the accompanying drawings.
[0046] Figure 1A-Figure 1C The top views of NMOS structures using body contact to suppress floating body effect are provided in three implementation modes respectively; wherein, Figure 1A It is a top view of the T-gate PD-SOI device structure; Figure 1B It is a top view of the H-gate PD-SOI device structure; Figure 1C A top view of a BTS-gate PD-SOI device structure.
[0047] Please combine Figure 1A-Figure 1C In order to suppress the floating body effect of PD-SOI devices, the applicant has studied the structures of three body contact methods, that is, all three methods connect the well region to a fixed potential through the body contact region to release the accumulated carriers (such as holes). Figure 1A-Figure 1C The PD-SOI devices in the embodiment respectively include a source region 21, a drain region 22, a gate structure 23 and a body contact region 10, the difference being the structure of the gate structure 23 and the position of the body contact region 10; wherein, Figure 1A The gate structure is a T-type gate. Figure 1B The gate structure is an H-type gate. Figure 1C The gate structure in the circuit is a BTS (Body-Tied-to-Source) type gate. All three structures can connect the well region to control the change of body potential.
[0048] After in-depth research on the above three methods, the applicant found that the above three methods have at least the following problems:
[0049] 1) For Figure 1A For the T-type gate structure in FIG, the source and drain regions on both sides of the gate structure will have arc-shaped corners in the actual process (such as Figure 1D The body contact region 10 only exists at the top of the T-type gate structure, which causes asymmetry, resulting in poor uniformity of the device and edge effects. In addition, since the T-type gate has a lateral gate structure (such as Figure 1D The gate structure does not generate a channel, but forms a parasitic capacitor with the oxide layer and the active area below, thereby increasing the parasitic effect.
[0050] 2) For Figure 1B The H-type gate structure also has a lateral gate structure part, which will also cause an increase in parasitic effects.
[0051] 3) For Figure 1CAs for the BTS-type gate structure, due to its asymmetric structure, the source region and the drain region cannot be interchanged, resulting in inflexible circuit design.
[0052] In addition, since the body contact structures of the embodiments shown in Figures 1(a), 1(b) and 1(c) are all arranged in the top silicon layer where the source and drain regions are located, the PD-SOI devices corresponding to Figures 1(a), 1(b) and 1(c) also have heat dissipation problems because the thermal conductivity of the internal silicon dioxide is much lower than that of silicon.
[0053] In view of this, an embodiment of the present invention provides a method for preparing a PD-SOI device, which effectively solves the floating body effect and improves the heat dissipation capability. The method comprises:
[0054] providing a first substrate;
[0055] Forming a plurality of first bumps in a first preset area of the first surface of the first substrate, and forming at least three second bumps in a second preset area of the first surface of the first substrate; wherein the thickness of the first bump is less than the thickness of the second bump;
[0056] depositing a buried oxide layer on the first surface of the first substrate;
[0057] Providing a second substrate, and bonding the first surface of the second substrate to the buried oxide layer;
[0058] Thinning the second surface of the first substrate to form a top silicon layer of a preset thickness in the first preset area and expose the buried oxide layer;
[0059] forming a device structure on the top silicon layer, wherein a gate structure of the device structure is formed on a surface of the top silicon layer, and the gate structure is located directly above one of the first bumps;
[0060] A body contact region is formed in a preset position of the top silicon layer, and the preset position is located at the periphery of the device structure, and the body contact region is connected to the first bump.
[0061] The embodiment of the present invention forms a plurality of first bumps in a first preset area of the first surface of the first substrate, and thins the second surface of the first substrate to form a top silicon layer of a preset thickness. Therefore, the thickness of the top silicon layer at the first bump is greater than the thickness of the top silicon layer in other areas. When the device structure and the body contact area are subsequently formed on the top silicon layer, the gate structure of the device structure is located directly above the first bump. The first bump and the body contact area are connected, and the carriers accumulated in the well area of the PD-SOI device during operation can be released through the body contact area, thereby effectively suppressing the floating body effect of the PD-SOI device. While forming the first bump, at least three second bumps are also formed on the second preset area of the first surface of the first substrate, and after the second substrate is thinned, the buried oxide layer is exposed and used as an alignment mark. At the same time, because the plurality of first bumps are in contact with the buried oxide layer, the overall heat dissipation capacity of the PD-SOI device is enhanced.
[0062] The following Figure 2 Taking the embodiment shown as an example, the preparation method of the PD-SOI device provided by the embodiment of the present invention is introduced in detail:
[0063] in, Figure 2 A flow chart of the preparation of a PD-SOI device provided in an embodiment of the present invention. Figures 3 to 14 They are respectively schematic diagrams of simplified cross-sectional structures corresponding to the PD-SOI device provided by the embodiments of the present invention in different preparation processes.
[0064] Please refer to Figure 2 The method for preparing the PD-SOI device provided in the embodiment of the present invention specifically comprises the following steps:
[0065] S1: Provide a first substrate 403, such as Figure 3 shown.
[0066] S2: forming a plurality of first bumps in a first preset area on the first surface of the first substrate, and forming at least three second bumps in a second preset area on the first surface of the first substrate.
[0067] Wherein, the thickness of the first bump is smaller than the thickness of the second bump.
[0068] The step S2 of forming a plurality of first bumps in a first preset area on the first surface of the first substrate and forming at least three second bumps in a second preset area on the first surface of the first substrate specifically includes the following steps:
[0069] S211: depositing a first hard mask layer 408 on the first surface of the first substrate 403, such as Figure 4 shown.
[0070] The first hard mask layer 408 is made of silicon oxide, and the deposition process is to perform thermal oxidation on the first surface of the first substrate 403 through a furnace tube. The temperature of the thermal oxidation is between 800°C and 950°C.
[0071] S212: forming a patterned photolithography mask layer on the surface of the first hard mask layer 408. The patterned photolithography mask layer includes: three first bump blocking regions, three second bump blocking regions and a window region.
[0072] The plurality of first bump blocking regions are evenly distributed, thereby improving the integrity of bumps subsequently formed by etching using the photolithography mask layer as a mask. The second bump blocking region is located in the sawing road region of the first substrate.
[0073] The formation of the photolithography mask layer is specifically a photolithography process in the art, which will not be elaborated here.
[0074] S213: Using the patterned photolithography mask layer as a mask, the first hard mask layer 408 and the first substrate 403 in the window area are sequentially etched, and the etching end point stays in the first substrate 403 to form at least three first bumps 4031 and three third bumps 4071, such as Figure 5 shown.
[0075] in, Figure 5 The number of the first bumps 4031 and the number of the third bumps 4071 shown are only a specific implementation. The number of the first bumps 4031 and the number of the third bumps 4071 can be adaptively adjusted according to different requirements, and are not limited here. Among them, the thickness of the first bump 4031 and the third bump 4071 are both between 30nm and 100nm, and the size of the third bump is larger than the size of the first bump. Of course, the thickness of the first bump 4031 and the third bump 407 can be adjusted according to requirements, and are not limited here.
[0076] S214: depositing a second hard mask layer 408 on the surface of the first substrate 403 and the surface of the first hard mask layer 408 after etching, such as Figure 6 shown.
[0077] The material of the second hard mask layer 408 is the same as that of the first hard mask layer 408, which will not be described in detail. Since the spacing between the third bumps is greater than the spacing between the first bumps, the second hard mask layer 408 completely fills the grooves between the first bumps 4031, and covers the surface of the first hard mask layer 408 corresponding to the first bumps 4031 and the third bumps 4071, and covers the surface of the first substrate 403 between the third bumps 4071.
[0078] S215: The first substrate 403 in the area between the second hard mask layer 408 and the third bump 4071 is sequentially etched, and the etching end point stays in the first substrate 403 to form three second bumps 407, and the thickness of the second bump 407 is greater than the thickness of the third bump 4071. Figure 7 shown.
[0079] Because the embodiment of the present invention forms the second bump 407 by performing patternless etching on the second hard mask layer 408 and the substrate 403, one photomask is saved, thereby reducing the manufacturing cost of the device.
[0080] Among them, taking dry etching as an example, after the second hard mask layer 408 between the third bumps 4071 is etched and the first substrate 403 between the third bumps 4071 is exposed, the type and proportion of the etching gas are adjusted to etch silicon with a high etching selectivity ratio. After the first substrate 403 between the third bumps 4071 is etched to a preset depth, the preparation of the second bump 407 is completed. Since the preset depths of the second bumps 407 of different devices are different, the preset depth is not limited here. Among them, the thickness of the second bump 407 is between 80nm and 180nm. Of course, the second bump 407 can be adjusted according to demand and is not limited here.
[0081] The second hard mask layer and the first hard mask layer 408 are made of the same material and are formed in the same manner, which will not be described in detail herein.
[0082] It should be noted that Figure 6 It can be seen that the sidewall of the third bump also has the second hard mask layer 408. Therefore, when performing patternless etching, the first substrate opposite to the sidewall of the third bump will not be etched, so that the etched second bump 407 has a certain step structure (not shown in the figure).
[0083] S216: removing the remaining first hard mask layer 408 and the remaining second hard mask layer 408, such as Figure 8 shown.
[0084] The above is the preparation process of step S2. The remaining steps of the preparation method of the PD-SOI device provided in the embodiment of the present invention are described below:
[0085] S3: Depositing a buried oxide layer 402 on the first surface of the first substrate 403, such as Fig. 9 shown.
[0086] The material of the buried oxide layer 402 is specifically silicon oxide. Of course, in addition to silicon oxide, the buried oxide layer 402 may also include silicon nitride or polysilicon, etc., which is not limited here. The process of depositing the buried oxide layer 402 includes high-density plasma deposition or chemical vapor deposition, and the specific process can be selected according to demand. The thickness of the buried oxide layer is between 100nm and 200nm. Of course, as long as the thickness of the buried oxide layer is greater than the second bump, it can be adjusted according to actual needs, which is not limited here.
[0087] Since the first bumps 4031 are evenly distributed, when depositing the buried oxide layer 402 material, the buried oxide layer 402 material can be well filled in the grooves spaced by the first bumps 4031 , thereby improving the film uniformity of the buried oxide layer 402 .
[0088] S4: providing a second substrate 401, and bonding the first surface of the second substrate 401 to the buried oxide layer 402, such as Fig.10 shown.
[0089] S5: Thinning the second surface of the first substrate 403 to form a top silicon layer 403 of a preset thickness in the first preset region and exposing the buried oxide layer 402, such as Fig.11 shown.
[0090] The buried oxide layer 402 exposed between the second bumps 407 can be used as an alignment mark, so that in the subsequent process of preparing semiconductor devices, the photolithography machine can accurately locate the position of the active area and the shallow trench isolation structure (STI) through the alignment mark, and perform exposure and development to etch the STI groove; in the subsequent process of depositing the gate, the active area and STI are used as alignment references to ensure that the gate is prepared directly above the first bump 4031. This solution can improve the accuracy of the photolithography machine during exposure and development by arranging the second bump 407 on the first surface of the first substrate, avoiding the problem of inaccurate positioning during exposure.
[0091] The process of thinning the second surface of the first substrate 403 includes chemical mechanical polishing, and chemical mechanical polishing is a conventional technical means in the art and will not be described in detail here.
[0092] The preset thickness of the top silicon layer is between 50 nm and 100 nm. Of course, the preset thickness of the top silicon layer can be adjusted according to demand and is not limited here.
[0093] S6: forming a device structure on the top silicon layer; the device structure comprises: a shallow trench isolation structure, a source region, a drain region and a gate structure; the shallow trench isolation structure, the source region and the drain region are formed in the top silicon layer; the gate structure is formed on the surface of the top silicon layer and is located directly above a first bump; the source region and the drain region are respectively located directly above a first bump.
[0094] As an example, if the top silicon is P-type silicon, a well region is formed in the top silicon, and a semiconductor device is formed in a heavily doped region in the well region, wherein the semiconductor device specifically includes a gate 4041, a source region 4042, and a drain region 4043, wherein the gate 4041 is located directly above a first boss; and the gate 4041, the source region 4042, and the drain region 4043 are respectively led out through corresponding contact holes (not shown in the figure).
[0095] Wherein, in step S6, a device structure is formed on the top silicon layer, specifically the following steps:
[0096] S611: forming a shallow trench isolation structure 4044 in the top silicon layer 403, such as Fig.12 Show.
[0097] The preparation process of the shallow trench isolation structure 4044 is a conventional technical means in the art and will not be elaborated here.
[0098] S612: forming a well region (not shown in the figure) in the top silicon layer 403 in the region where the device structure is located, and forming a gate structure 4041 on the surface of the top silicon layer 403 in the region where the device structure is located. Fig.13 shown.
[0099] The gate structure 4041 in the device structure corresponds to a first bump 4031 and is located directly below the corresponding first bump 4031. The preparation process of the gate structure 4041 is a conventional technical means in the art and will not be described in detail here.
[0100] S613: forming a source region 4042 and a drain region 4043 in the well region of the top silicon layer 403 in the region where each device structure is located, such as Fig.14 shown.
[0101] Among them, the source region 4042 and the drain region 4043 are respectively located directly above a first bump 4031, and combined with the first bump 4031 located directly below the gate structure, the uniform distribution of the first bump 4031 can not only improve the uniformity of the film deposited by the buried oxide layer, but also improve the symmetry of the device structure.
[0102] The preparation process of the source region 4042 and the drain region 4043 is a conventional technical means in this field and will not be described in detail here.
[0103] S7: forming a body contact region 501 in a preset position of the top silicon layer, such as Fig.14 shown.
[0104] The body contact region 501 is a doped region formed at a preset position in the top silicon 150. The preset position is located at the periphery of the device structure, and the body contact region 501 is connected to the first bump 4031 and is externally connected to a fixed potential through a contact hole (not shown in the figure) to suppress the floating body effect of the device. As an example, the top silicon 403 is P-type silicon, and a P-type heavily doped body contact region 501 is formed at the periphery of the shallow trench isolation structure 4044.
[0105] In summary, the preparation method of the PD-SOI device provided in the embodiment of the present invention forms a plurality of first bumps in the first preset area of the first surface of the first substrate, and thins the second surface of the first substrate to form a top silicon layer of a preset thickness. Therefore, the thickness of the top silicon layer at the first bump is greater than the thickness of the top silicon layer in other areas. When the device structure and the body contact area are subsequently formed on the top silicon layer, the gate structure of the device structure is located directly above the first bump, and the first bump is in contact with the body contact area, so that the carriers accumulated in the well region of the PD-SOI device during operation can be released through the body contact area, thereby effectively suppressing the floating body effect of the PD-SOI device. While forming the first bump, at least three second bumps are also formed on the second preset area of the first surface of the first substrate, and after the second substrate is thinned, the buried oxide layer located between the second bumps and exposed is used as an alignment mark to ensure that the gate structure is located directly above the first bump. At the same time, the plurality of first bumps are in contact with the buried oxide layer, thereby enhancing the overall heat dissipation capacity of the PD-SOI device.
[0106] Furthermore, after forming the plurality of first bumps and at least three third bumps, the second hard mask layer is deposited and etched to form the at least three second bumps, thereby saving one photomask and thus reducing the manufacturing cost of the device.
[0107] Furthermore, since the plurality of first bumps are evenly distributed, not only can the buried oxide layer be formed more evenly and flatly, but the symmetry of the device structure can also be improved.
[0108] in, Fig.15 It is a simplified cross-sectional schematic diagram of the PD-SOI device provided in an embodiment of the present invention.
[0109] Please refer to Fig.15 The embodiment of the present invention further provides a PD-SOI device, including:
[0110] Substrate 401;
[0111] A buried oxide layer 402, located on the surface of the first substrate 401;
[0112] A top silicon layer 403 is located on the surface of the buried oxide layer 402; a side of the top silicon layer 403 facing the buried oxide layer 402 includes a plurality of first bumps 4031;
[0113] A device structure is located on a side of the top silicon layer 403 facing away from the buried oxide layer 402, a gate structure 4041 of the device structure is located on the surface of the top silicon layer 403, and the gate structure 4041 is located directly above a first bump 4031, a source region 4042 and a drain region 4043 of the device structure are located in the top silicon layer 403, and a shallow trench isolation structure 4044 of the device structure is located in the top silicon layer 403 and isolates the source region 4042 and the drain region 4043 from the periphery;
[0114] The body contact region 501 is located at a preset position in the top silicon layer 403, and the preset position is located at the periphery of the device structure.
[0115] Since the PD-SOI device of the above-mentioned embodiment is formed based on the preparation method of the above-mentioned PD-SOI device, for the detailed description of the various features of the PD-SOI device of the above-mentioned embodiment, please refer to the relevant explanations and descriptions in the preparation method of the above-mentioned PD-SOI device, which will not be repeated here.
[0116] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for preparing a PD-SOI device, characterized in that: include: providing a first substrate; Forming a plurality of first bumps in a first preset area of the first surface of the first substrate, and forming at least three second bumps in a second preset area of the first surface of the first substrate; wherein the thickness of the first bump is less than the thickness of the second bump; depositing a buried oxide layer on the first surface of the first substrate; Providing a second substrate, and bonding the first surface of the second substrate to the buried oxide layer; Thinning the second surface of the first substrate to form a top silicon layer of a preset thickness in the first preset area and expose the buried oxide layer; forming a device structure on the top silicon layer, wherein a gate structure of the device structure is formed on a surface of the top silicon layer, and the gate structure is located directly above one of the first bumps; A body contact region is formed in a preset position of the top silicon layer, and the preset position is located at the periphery of the device structure, and the body contact region is connected to the first bump.
2. The method for preparing a PD-SOI device according to claim 1, characterized in that: Forming a plurality of first bumps in a first preset area on the first surface of the first substrate specifically includes: depositing a first hard mask layer on the first surface of the first substrate; Forming a patterned first mask on the surface of the first hard mask layer, wherein the first mask includes a plurality of first bump blocking regions, at least three third bump blocking regions, and a window region; Using the patterned first mask as a mask, the first hard mask layer and the first substrate in the window area are etched in sequence, with the etching endpoint staying in the first substrate, so as to form the plurality of first bumps and at least three third bumps.
3. The method for preparing a PD-SOI device according to claim 2, characterized in that: Forming at least three second bumps on the second preset area specifically includes: After forming the first bump, depositing a second hard mask layer on the first surface of the first substrate; The second hard mask layer and the first substrate in the third bump spacing region are sequentially etched, with the etching endpoint staying within the first substrate, to form at least three second bumps, wherein the thickness of the second bumps is greater than that of the third bumps.
4. The method for preparing a PD-SOI device according to claim 1, characterized in that: The plurality of first bumps are evenly distributed, and the width of the first bumps is less than or equal to the width of the gate structure.
5. The method for preparing a PD-SOI device according to claim 1, characterized in that: The thickness of the buried oxide layer is between 100 nm and 200 nm, and the thickness of the second bump is between 80 nm and 180 nm.
6. The method for preparing a PD-SOI device according to claim 5, characterized in that: The preset thickness is between 50nm and 100nm.
7. The method for preparing a PD-SOI device according to claim 1, characterized in that: Depositing a buried oxide layer on the first surface of the first substrate specifically includes: depositing an oxide on the first surface of the first substrate; The surface of the oxide is subjected to chemical mechanical polishing to form the buried oxide layer.
8. A PD-SOI device, characterized in that: include: substrate; A buried oxide layer, located on the surface of the substrate; A top silicon layer is located on the surface of the buried oxide layer; a side of the top silicon layer facing the buried oxide layer includes a plurality of first bumps; A device structure is located on a side of the top silicon layer facing away from the buried oxide layer, a gate structure of the device structure is located on a surface of the top silicon layer, and the gate structure is located directly above one of the first bumps; A body contact region is located at a preset position of the top silicon layer, and the preset position is located at the periphery of the device structure.
9. The PD-SOI device according to claim 8, characterized in that: The width of the first bump is less than or equal to the width of the gate structure.
10. The PD-SOI device according to claim 8, characterized in that: The spacing between the plurality of first protrusions meets a preset minimum design dimension.