Preparation method of image sensor

Abstract

The invention provides a preparation method of an image sensor, and the method comprises the steps: firstly forming a deep well region in a substrate of a pixel region, then etching a hard mask layer of a logic region to form a plurality of openings, and then etching a part of thickness of the substrate at the bottom of each opening to form a groove, and then forming a second liner oxide layer on the side wall and the bottom wall of the trench and at the corner position of the top end of the trench, and finally executing a thermal annealing process to activate doped ions in the deep well region. The thermal annealing process is carried out after the second liner oxide layer of the logic region is formed, so that under the condition that the white dot performance is kept unchanged, the full well capacity is improved, meanwhile, the condition that the surface of the substrate is damaged due to direct high-temperature annealing after a deep well region ion implantation process in a traditional preparation process can be effectively avoided, and meanwhile, the quality of the substrate is improved. The second pad oxide layer at the corner position of the top end of the groove can be converted into a round corner, and the electric leakage performance of the device is effectively improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing an image sensor. Background Art

[0002] Silicon substrate damage can have a significant impact on the performance of CIS (CMOS image sensor) devices, including decreased quantum efficiency, increased dark current, uneven pixel performance, and reliability issues. Therefore, in the manufacturing process of CIS devices, the main methods used to reduce the occurrence of silicon substrate damage are to optimize process steps and control methods.

[0003] In order to improve the performance of CIS devices, the current CIS device tape-out (NTO) adopts an ion implantation (DDN) advance process in the deep well area of ​​the pixel area (forming the deep well area by high-energy ion implantation in the early step of the device preparation process) to increase the photodiode (Photo diode) in the pixel area. While the white pixel performance remains unchanged, the full well capacity (FWC) can be increased by 25%. However, current experimental results show that the DDN advance process requires high-temperature annealing after high-energy ion implantation, but high-temperature annealing will cause damage to the silicon substrate in the logic area of ​​the device, which will have a great impact on the performance of subsequent CIS devices. Summary of the invention

[0004] The present application provides a method for preparing an image sensor, which can solve the problem that high-temperature annealing after ion implantation in a deep well region of a pixel region causes damage to the silicon substrate in a logic region of the device, thereby greatly affecting the performance of the CIS device.

[0005] The present application provides a method for preparing an image sensor, comprising: Providing a substrate, the substrate comprising a pixel area and a logic area, and a first pad oxide layer formed on the substrate; Performing an ion implantation process on the substrate of the pixel region to form a deep well region in the substrate of the pixel region; removing the first pad oxide layer on the substrate of the pixel area and the logic area; forming a hard mask layer on the substrate in the pixel area and the logic area; etching the hard mask layer of the logic region to form a plurality of openings in the hard mask layer; Etching the first liner oxide layer and a portion of the thickness of the substrate at the bottom of each of the openings to form a trench, wherein the lateral dimension of the top of the trench is smaller than the lateral dimension of the opening; forming a second liner oxide layer, wherein the second liner oxide layer covers the sidewalls and bottom wall of the trench in the logic area and covers the top corner of the trench; A thermal annealing process is performed on the semiconductor structure after the second pad oxide layer is formed to activate doping ions in the deep well region.

[0006] Optionally, in the method for preparing the image sensor, during the thermal annealing process performed on the semiconductor structure after forming the second pad oxide layer, a certain flow rate of oxygen is introduced, the annealing temperature is 1100° C. to 1200° C., and the annealing time lasts at least 120 minutes.

[0007] Optionally, in the method for preparing the image sensor, the flow rate of oxygen introduced in the thermal annealing process is 0.1 slm~0.2 slm.

[0008] Optionally, in the method for preparing the image sensor, the second pad oxide layer is formed by a CVD process.

[0009] Optionally, in the method for preparing the image sensor, the thickness of the second pad oxide layer is 60 angstroms to 70 angstroms.

[0010] Optionally, in the method for preparing the image sensor, the material of the hard mask layer is silicon dioxide.

[0011] Optionally, in the method for preparing the image sensor, the hard mask layer of the logic area is etched using a dry etching process.

[0012] Optionally, in the method for preparing the image sensor, a dry etching process is used to etch a portion of the thickness of the substrate at the bottom of each opening to form a groove.

[0013] Optionally, in the method for manufacturing the image sensor, after performing a thermal annealing process on the semiconductor structure after forming the second pad oxide layer, the method for manufacturing the image sensor further includes: An isolation material layer is formed by adopting a high aspect ratio process, and the isolation material layer fills the trench and the opening at the top of the trench.

[0014] Optionally, in the method for preparing the image sensor, the isolation material layer is made of silicon dioxide.

[0015] The technical solution of this application has at least the following advantages: In the present application, a deep well region is first formed in the substrate of the pixel region through an ion implantation process, and then the hard mask layer of the logic region is etched to form a plurality of openings, and then a portion of the thickness of the substrate at the bottom of each opening is etched to form a groove, and then a second liner oxide layer is formed on the sidewalls and bottom walls of the groove and at the top corner of the groove, and finally a thermal annealing process is performed to activate the doped ions in the deep well region. The present application places the thermal annealing process after the second liner oxide layer of the logic region is formed, so that the full well capacity can be improved while the white pixel performance remains unchanged, and the substrate surface damage caused by direct high temperature annealing after the deep well region ion implantation process of the traditional preparation process can be effectively avoided. At the same time, the second liner oxide layer at the top corner of the groove can also be transformed into a rounded corner, which effectively improves the leakage performance of the CIS device, thereby avoiding the situation of device performance loss and improving the device yield and electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 is a flow chart of a method for preparing an image sensor according to an embodiment of the present invention; Figure 2-Figure 10 is a schematic diagram of a semiconductor structure in each process step of manufacturing an image sensor according to an embodiment of the present invention; The reference numerals are described as follows: 10 - substrate, 11 - deep well region, 20 - first liner oxide layer, 30 - first photoresist layer, 40 - hard mask layer, 50 - second photoresist layer, 61 - opening, 62 - trench, 70 - second liner oxide layer, 80 - isolation material layer. DETAILED DESCRIPTION

[0018] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0020] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0021] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0022] The present application provides a method for preparing an image sensor, referring to Figure 1 , Figure 1 is a flow chart of a method for preparing an image sensor according to an embodiment of the present invention, wherein the method for preparing the image sensor comprises: First, perform step S1: refer to Figure 2 , Figure 2 It is a schematic diagram of a semiconductor structure after a first liner oxide layer is formed according to an embodiment of the present application. A substrate 10 is provided. The substrate 10 includes a pixel region and a logic region. A first liner oxide layer 20 is formed on the substrate 10 .

[0023] Then, execute step S2: refer to Figure 3 , Figure 3 It is a schematic diagram of the semiconductor structure after the deep well region is formed in an embodiment of the present application. A first photoresist layer 30 is coated on the first pad oxide layer 20, and an ion implantation window is formed on the first photoresist layer 30 through a photolithography process. Subsequently, an ion implantation process is performed on the substrate 10 of the pixel region using the patterned first photoresist layer 30 as a mask to form a deep well region 11 in the substrate 10 of the pixel region.

[0024] In this embodiment, an N-type ion implantation process is performed on the substrate 10 of the pixel region to form an N-type deep well region 11 in the substrate 10 of the pixel region.

[0025] Next, execute step S3: refer to Figure 4 , Figure 4 It is a schematic diagram of the semiconductor structure after the first liner oxide layer on the substrate of the pixel area and the logic area is removed according to an embodiment of the present application, wherein the first liner oxide layer 20 on the substrate 10 of the pixel area and the logic area is removed.

[0026] Preferably, a wet cleaning process is used to remove the first pad oxide layer 20 on the substrate 10 in the pixel area and the logic area.

[0027] Further, step S4 is performed: refer to Figure 5 , Figure 5 1 is a schematic diagram of a semiconductor structure after a hard mask layer is formed according to an embodiment of the present application. A hard mask layer 40 is formed on the substrate of the pixel area and on the substrate 10 of the logic area.

[0028] In the embodiment, the material of the hard mask layer 40 is silicon dioxide.

[0029] In other embodiments, the hard mask layer 40 is a combined stacked layer, and the hard mask layer 40 includes: a silicon dioxide layer and a silicon nitride layer located on the silicon dioxide layer.

[0030] Next, execute step S5: refer to Figure 6 and Figure 7 , Figure 6 is a schematic diagram of a semiconductor structure after a patterned second photoresist layer is formed in an embodiment of the present application, Figure 7 This is a schematic diagram of the semiconductor structure after the opening is formed in an embodiment of the present application. First, a second photoresist layer 50 is coated on the hard mask layer 40, and an opening pattern is formed on the second photoresist layer 50 through a photolithography process to obtain a patterned second photoresist layer 50. Subsequently, the patterned second photoresist layer 50 is used as a mask to etch the hard mask layer 40 of the logic area to form a plurality of openings 61 in the hard mask layer 40 of the logic area.

[0031] Preferably, the hard mask layer 40 of the logic area is etched using a dry etching process.

[0032] Further, step S6 is performed: refer to Figure 8 , Figure 8 It is a schematic diagram of the semiconductor structure after the grooves are formed in an embodiment of the present application, where a portion of the thickness of the substrate 10 at the bottom of each opening 61 is etched to form a groove 62 , wherein the lateral dimension of the top of the groove 62 is smaller than the lateral dimension of the opening 61 .

[0033] Preferably, the lateral dimension of the top of the groove 62 is 60% to 80% of the lateral dimension of the opening 61 .

[0034] Preferably, a dry etching process is used to etch a portion of the thickness of the substrate 10 at the bottom of each opening 61 to form the trench 62 .

[0035] Next, execute step S7: refer to Fig. 9 , Fig. 9 It is a schematic diagram of the semiconductor structure after forming the second liner oxide layer in an embodiment of the present application, forming the second liner oxide layer 70, which covers the side walls and bottom walls of the trench 62 in the logic area and covers the top corner of the trench 62.

[0036] Preferably, the second pad oxide layer 70 is formed by a CVD process.

[0037] Preferably, the thickness of the second liner oxide layer 70 is 60 angstroms to 70 angstroms.

[0038] Finally, step S8 is performed: performing a thermal annealing process on the semiconductor structure after the second liner oxide layer 70 is formed, so as to activate the doped ions in the deep well region.

[0039] Preferably, during the thermal annealing process performed on the semiconductor structure after the second liner oxide layer 70 is formed, a certain flow of oxygen is introduced, the annealing temperature is 1100° C.-1200° C., and the annealing time lasts at least 120 minutes.

[0040] Preferably, the annealing time lasts for 120 min to 240 min.

[0041] In this embodiment, the annealing temperature is 1150°C.

[0042] Preferably, the flow rate of oxygen introduced during the thermal annealing process is 0.1slm~0.2slm.

[0043] It is worth noting that after the thermal annealing process is performed, the second liner oxide layer 70 deposited at the top corner of the trench 62 has a rounded shape, that is, the thermal annealing process can transform the second liner oxide layer at the top corner of the trench into a rounded shape.

[0044] For further reference, Fig.10 , Fig.10It is a schematic diagram of the semiconductor structure after the shallow trench isolation structure is formed in an embodiment of the present application. After performing a thermal annealing process on the semiconductor structure after the second liner oxide layer 70 is formed, the method for preparing the image sensor may further include: forming an isolation material layer 80 using a high aspect ratio process, the isolation material layer 80 filling the trench 62 and the opening at the top of the trench 62 to form a shallow trench isolation structure.

[0045] In this embodiment, the isolation material layer 80 is made of silicon dioxide.

[0046] It is worth noting that the steps for preparing the image sensor after forming the shallow trench isolation structure may refer to the conventional steps for preparing the traditional image sensor, and the present application does not impose any limitation on the steps for preparing the image sensor after forming the shallow trench isolation structure.

[0047] In the present application, the thermal annealing process is placed after the second pad oxide layer of the logic area is formed. In this way, the full well capacity can be improved while the white pixel performance remains unchanged, and the substrate surface damage caused by direct high-temperature annealing after the deep well area ion implantation process in the traditional preparation process can be effectively avoided. At the same time, the second pad oxide layer at the top corner of the trench can be transformed into a rounded corner, which effectively improves the leakage performance of the CIS device, thereby avoiding the loss of device performance and improving the yield and electrical performance of the device.

[0048] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for preparing an image sensor, characterized in that: include: Providing a substrate, the substrate comprising a pixel area and a logic area, and a first pad oxide layer formed on the substrate; Performing an ion implantation process on the substrate of the pixel region to form a deep well region in the substrate of the pixel region; removing the first pad oxide layer on the substrate of the pixel area and the logic area; forming a hard mask layer on the substrate in the pixel area and the logic area; etching the hard mask layer of the logic region to form a plurality of openings in the hard mask layer; Etching a portion of the thickness of the substrate at the bottom of each opening to form a groove, wherein the lateral dimension of the top of the groove is smaller than the lateral dimension of the opening; forming a second liner oxide layer, wherein the second liner oxide layer covers the sidewalls and bottom wall of the trench in the logic area and covers the top corner of the trench; A thermal annealing process is performed on the semiconductor structure after the second pad oxide layer is formed to activate doping ions in the deep well region.

2. The method for preparing an image sensor according to claim 1, characterized in that: During the thermal annealing process performed on the semiconductor structure after the second liner oxide layer is formed, a certain flow of oxygen is introduced, the annealing temperature is 1100° C. to 1200° C., and the annealing time lasts at least 120 minutes.

3. The method for preparing an image sensor according to claim 2, characterized in that: The flow rate of oxygen introduced during the thermal annealing process is 0.1slm~0.2slm.

4. The method for preparing an image sensor according to claim 1, characterized in that: The second pad oxide layer is formed by a CVD process.

5. The method for preparing an image sensor according to claim 1, characterized in that: The thickness of the second pad oxide layer is 60 angstroms to 70 angstroms.

6. The method for preparing an image sensor according to claim 1, characterized in that: The material of the hard mask layer is silicon dioxide.

7. The method for preparing an image sensor according to claim 1, characterized in that: The hard mask layer of the logic area is etched using a dry etching process.

8. The method for preparing an image sensor according to claim 1, characterized in that: A dry etching process is used to etch a portion of the thickness of the substrate at the bottom of each opening to form a groove.

9. The method for preparing an image sensor according to claim 1, characterized in that: After performing a thermal annealing process on the semiconductor structure after forming the second pad oxide layer, the method for manufacturing the image sensor further includes: An isolation material layer is formed by adopting a high aspect ratio process, and the isolation material layer fills the trench and the opening at the top of the trench.

10. The method for preparing an image sensor according to claim 9, characterized in that: The material of the isolation material layer is silicon dioxide.

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