Method for manufacturing TOPCon solar cell

Abstract

The invention relates to a method for manufacturing a TOPCon solar cell. The method comprises the following steps: preparing a TOPCon passivation structure on the surface of a silicon substrate; performing laser windowing on the surface of the TOPCon passivation structure to obtain a finger structure pattern; etching is carried out on the finger structure pattern area; wherein the laser overlapping rate adopted in the laser windowing process is not larger than 40%, and the area is not smaller than 40000 square micrometers. According to the method, laser windowing is carried out on the surface of the TOPCon passivation structure through low-overlapping large light spots. By means of the method, uniform large and small tower footing morphology and controllable corrosion depth can be obtained, opening pressure and FF are considered while short-flow lifting is met, FF lowering is avoided, efficiency is improved, and the product yield is increased. In addition, the CT value of laser marking can be reduced through application of low-overlapping large light spots, and the production efficiency is further improved.

Description

Technical Field

[0001] The invention relates to the technical field of solar cells, and in particular to a method for manufacturing a TOPCon solar cell. Background Art

[0002] In crystalline silicon solar cells, serious recombination occurs in the metal-semiconductor contact area, which has become an important factor restricting the development of crystalline silicon solar cell efficiency. In 2013, the Fraunhofer Institute for Solar Energy Research in Germany proposed the TOPCon solar cell technology. One of the biggest advantages of TOPCon solar cells is that the tunneling oxide layer and the doped polysilicon layer on the back constitute a tunneling oxide layer passivation contact structure, which can significantly reduce the recombination of the metal contact area, while having good contact performance, which can greatly improve the efficiency of solar cells.

[0003] According to the forecasts of InfoLink Consulting and other institutions, the market share of TOPCon solar cell technology has continued to rise in recent years and is expected to occupy a major share of the market in the next few years. For example, it is predicted that the market share of TOPCon solar cell technology will reach 65% or even higher in 2024, becoming the absolute mainstream in the market.

[0004] With the continuous innovation of TOPCon solar cell technology, especially after the promotion of laser-assisted sintering technology, the improvement of the front contact of TOPCon solar cells is very significant, and the efficiency of the cell end is increased by 0.2%+. Therefore, the demand for efficiency improvement solutions for the back of TOPCon solar cells is increasing. Among them, poly-finger technology is a technology with obvious benefits and rapid mass production. However, the uneven energy of the laser spot in mass production is inevitable, resulting in the efficiency yield of the product not meeting expectations. Summary of the invention

[0005] The present invention provides a method for manufacturing a TOPCon solar cell. By adding and optimizing the steps of laser window opening, a uniform large and small tower base morphology is further obtained. While satisfying the short-circuit improvement, the opening voltage and FF are taken into account to avoid the decrease of FF, thereby achieving efficiency improvement and improving product yield.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] A method for manufacturing a TOPCon solar cell, comprising:

[0008] The disclosed TOPCon solar cell manufacturing method of the present invention performs laser windowing on the surface of the TOPCon passivation structure to obtain a finger structure pattern. The laser overlap rate used in the laser windowing process is not greater than 40% and the area is not less than 40,000 square microns.

[0009] In one embodiment, the laser overlap rate is 40%.

[0010] In one embodiment, the laser overlap rate is 30%.

[0011] In one embodiment, the laser overlap rate is 20%.

[0012] In one embodiment, the laser overlap rate is 10%.

[0013] In one embodiment, the laser overlap rate is 0.

[0014] In one embodiment, the laser overlap ratio is less than 0.

[0015] In one embodiment, the laser window area is 45,000 square microns.

[0016] In one embodiment, the shape of the laser window is a rectangle of 450 microns*100 microns.

[0017] In one embodiment, the finger structure pattern area is etched using a wet etching process.

[0018] The disclosed TOPCon solar cell manufacturing method of the present invention performs laser windowing on the surface of the TOPCon passivation structure to obtain a finger structure pattern. And the laser overlap rate used in the laser windowing process is not greater than 40% and the area is not less than 40,000 square microns. It can be seen that the TOPCon solar cell manufacturing method disclosed in the present invention uses a large light spot with low overlap to perform laser windowing on the surface of the TOPCon passivation structure. The application of a large light spot with low overlap can obtain uniform large and small tower base morphologies and controllable corrosion depth. While satisfying the short-flow improvement, it takes into account the opening voltage and FF, avoids the decrease of FF, achieves efficiency improvement, and improves product yield.

[0019] In addition, the application of low-overlap large spot can also reduce the CT value of laser marking and further improve production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a morphology diagram after laser windowing and RCA cleaning in a TOPCon solar cell manufacturing method disclosed in an embodiment of the present invention;

[0021] Figure 2 This is a morphology diagram after laser windowing and RCA cleaning in another TOPCon solar cell manufacturing method disclosed in an embodiment of the present invention;

[0022] Figure 3 This is a morphology diagram after laser windowing and RCA cleaning in another TOPCon solar cell manufacturing method disclosed in an embodiment of the present invention;

[0023] Figure 4 This is a morphology diagram after laser windowing and RCA cleaning in another TOPCon solar cell manufacturing method disclosed in an embodiment of the present invention;

[0024] Figure 5 This is a morphology diagram after laser windowing and RCA cleaning in another TOPCon solar cell manufacturing method disclosed in an embodiment of the present invention;

[0025] Figure 6 This is a morphology diagram after laser windowing and RCA cleaning in another TOPCon solar cell manufacturing method disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] For ease of understanding of the present invention, the present invention will be described in more detail below. However, it should be understood that the present invention can be implemented in many different forms and is not limited to the embodiments or examples described herein. On the contrary, the purpose of providing these embodiments or examples is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific implementation methods or embodiments, and are not intended to limit the present invention. The optional scope of the term "and / or" used herein includes any one of two or more related listed items, and also includes any and all combinations of related listed items, and the combinations include any two related listed items, any more related listed items, or all related listed items.

[0028] One embodiment of the present invention discloses a method for manufacturing a TOPCon solar cell, comprising:

[0029] Prepare TOPCon passivation structure on the surface of silicon substrate;

[0030] Performing laser windowing on the surface of the TOPCon passivation structure to obtain a finger structure pattern;

[0031] The laser overlap rate used in the laser window opening process is no more than 40% and the area is no less than 40,000 square microns.

[0032] The researchers found that if a small spot is used for laser windowing, it will cause CT waste and prolong the windowing time. If the CT value is to be reduced, the overlap needs to be reduced, which will lead to poor energy consistency, and the depth of wet etching will be uncontrollable, resulting in corrosion structures of large and small tower bases, and the final efficiency improvement will be reduced. Moreover, the long-term simultaneous production of oxide layers in an oxygen-rich environment will increase the wet etching time. Therefore, in the TOPCon solar cell manufacturing method disclosed in the present invention, the laser overlap rate used in the laser windowing process is not more than 40% and the area is not less than 40,000 square microns. That is, the present invention uses a large spot with low overlap to laser window the surface of the TOPCon passivation structure. The application of a large spot with low overlap can obtain uniform large and small tower base morphology and controllable corrosion depth. While meeting the short flow improvement, it takes into account the opening pressure and FF, avoids the decline of FF, achieves efficiency improvement, and improves product yield.

[0033] In addition, the application of low-overlap large spot can also reduce the CT value of laser marking and further improve production efficiency.

[0034] Another embodiment discloses another method for manufacturing a TOPCon solar cell, comprising:

[0035] Texturing. The reaction time is 300s-470s, the reaction temperature is 60℃-80℃, and the solution contains alkaline solution, such as NaOH, KOH, etc., texturing additives, H 2 O are alkaline solutions of 0.9%-4%, 0.09%-1.2%, and 94.8%-99.01% respectively.

[0036] Boron diffusion + oxidation. The deposition temperature is 810℃-870℃, the deposition time is 300s-600s, the boron source flow rate is 100sccm-350sccm, the oxygen flow rate is 500sccm-1000sccm, the nitrogen flow rate is 2000sccm-4000sccm, the advancement temperature is 910℃-940℃, the time is 800s-1000s, the oxidation temperature is 1035℃-1050℃, the oxygen flow rate is 18000sccm-40000sccm, the time is 3000s-4500s, the suede area concentration is 1e18-6e18, and the doping depth is 0.6μm-1.1μm.

[0037] Remove BSG. Use HF solution with a mass fraction of 25% to 40% to chain clean the back of the silicon wafer for 50s to 150s to remove the BSG layer on the back and edge of the silicon wafer.

[0038] Alkali polishing. The reaction time is 200s-300s, the reaction temperature is 60℃-75℃, and the solution contains alkaline solution, such as NaOH, KOH, etc., polishing additives, H 2 O are alkaline solutions of 1.74%-2.81%, 1.16%-1.69%, and 95.5%-97.1% respectively.

[0039] LPCVD+phosphorus diffusion to form a TOPCon passivation structure. This process includes but is not limited to LPCVD ex-situ and PECVD in-situ. This embodiment uses LPCVD for ex-situ growth. Tunneling oxide layer growth, deposition temperature 600℃-620℃, reaction time 400s-600s, oxygen simmering time 400s-800s, grow a 1.1nm-1.4nm tunneling oxide layer, intrinsic amorphous silicon layer 590℃-620℃, reaction time 1500s-2300s, phosphorus doping, deposition temperature 800℃-830℃, time 900s-1100s, phosphorus source flow 1400sccm-1800sccm, oxidation flow 500sccm-1000sccm, advancement temperature 900℃-940℃, time 1000s-1400s, oxidation temperature 860℃-900℃, time 1300s-1600s, surface concentration is 1e20-4e20.

[0040] Laser windowing is used to obtain the finger structure pattern. Depending on the number of sub-grids on the screen, different widths of poly blanking can be achieved on the sub-grid. The poly blanking width is 200μm-600μm. According to the poly blanking width, the laser spot width is determined to achieve large spot windowing. Specifically, the laser overlap rate used in the laser windowing process is not greater than 40% and the area is not less than 40,000 square microns.

[0041] Remove PSG. Use HF solution with a mass fraction of 5% to 20% to chain clean the front of the silicon wafer for 100s to 400s to remove the PSG layer on the front and edge of the silicon wafer.

[0042] RCA cleaning. In this process, the first layer of Poly and SiO below the laser irradiated area is removed. 2 The PSG layer on the outermost side of the non-laser area, the oxide layer in the middle of the laser irradiation area, and the BSG layer in the front velvet area are removed in the subsequent tank. RCA is prepared in a proportion containing alkaline solution, such as NaOH, KOH, etc., RCA additives, H 2 O are alkaline solutions of 3.5%-4.5%, 0.8%-1.5%, and 94%-95.7% respectively.

[0043] Double-sided ALD. Trimethylaluminum and water are introduced cyclically to grow a 3nm-8nm aluminum oxide passivation layer.

[0044] Positive film + back film. Plasma chemical vapor deposition is used on the front of the silicon wafer to grow a 65nm-90nm silicon nitride composite layer; plasma chemical vapor deposition is used on the back of the silicon wafer to grow a 75nm-105nm silicon oxynitride and silicon nitride composite layer.

[0045] Screen printing. Electrodes are made on the front and back of the battery using silver-aluminum paste / silver paste, and laser-assisted sintering is performed.

[0046] In this embodiment, the RCA cleaning process can achieve etching of the finger structure pattern area. Specifically, in this embodiment, a wet etching process is used to etch the finger structure pattern area.

[0047] The TOPCon solar cell manufacturing method disclosed in the present invention uses a large spot with low overlap to perform laser windowing on the surface of the TOPCon passivation structure. The application of a large spot with low overlap can obtain uniform large and small tower base morphology, controllable corrosion depth, and while meeting the short current improvement, take into account the opening voltage and FF, avoid the decrease of FF, achieve efficiency improvement, and improve product yield.

[0048] Another embodiment discloses another method for manufacturing a TOPCon solar cell, wherein the laser overlap ratio is 30%.

[0049] Another embodiment discloses another method for manufacturing a TOPCon solar cell, wherein the laser overlap rate is 20%.

[0050] Another embodiment discloses another method for manufacturing a TOPCon solar cell, wherein the laser overlap ratio is 10%.

[0051] Another embodiment discloses another method for manufacturing a TOPCon solar cell, wherein the laser overlap ratio is 0.

[0052] Another embodiment discloses another method for manufacturing a TOPCon solar cell, wherein the laser overlap ratio is less than 0.

[0053] Another embodiment discloses another method for manufacturing a TOPCon solar cell, wherein the laser window area is 45,000 square micrometers.

[0054] Another embodiment discloses another method for manufacturing a TOPCon solar cell, wherein the shape of the laser window is a rectangle of 450 microns*100 microns.

[0055] The manufacturing method of TOPCon solar cells disclosed in the present invention has a large spot design with a low overlap rate, which can also reduce the CT value of laser marking. It can shorten the time for synchronous production of the oxide layer in an oxygen-rich environment, thereby reducing the wet etching time. Moreover, in order to control the overlap to be zero or even negative as much as possible, the energy epitaxial layer between the two spots is used to achieve the effect of spot overlap. On this basis, a uniform large and small tower base morphology and a controllable corrosion depth can be obtained, while satisfying the short-flow improvement, taking into account the opening pressure and FF, avoiding the decrease of FF, and achieving efficiency improvement.

[0056] The TOPCon solar cell manufactured by the manufacturing method of the TOPCon solar cell disclosed in the present invention will be described below by comparing with some specific embodiments.

[0057] Embodiment 1:

[0058] S1. The original silicon wafer is textured. The reaction time is 420s, the reaction temperature is 83°C, and the alkaline solution is prepared, containing NaOH, a texturing additive, and H 2 O are 1.2%, 0.3%, and 98.50% alkaline solutions respectively.

[0059] S2, after step S1, the silicon wafer is subjected to boron diffusion + oxidation. The deposition temperature is 840°C, the deposition time is 4100s, the boron source flow rate is 240sccm, the oxidation flow rate is 620sccm, the nitrogen flow rate is 2800sccm, the advancement temperature is 890°C, the time is 930s, the oxidation temperature is 1050°C, the time is 3600s, the texture area concentration is 5e18, and the junction depth is 0.68μm.

[0060] S3, remove BSG from the back of the silicon wafer after step S2, and use 31% HF solution to chain clean the back of the silicon wafer for 80 seconds.

[0061] S4. Polish the silicon wafer after step S3. The reaction time is 220s, the reaction temperature is 62°C, and the alkaline solution is prepared, containing NaOH, polishing additive, H 2 O are 3.5%, 0.4%, and 96.1% alkaline solutions respectively.

[0062] S5. Perform passivation structure growth and phosphorus diffusion on the silicon wafer after step S4. Tunneling oxide layer growth, deposition temperature 600℃, oxygen flow time 350s, oxygen simmering time 600s, intrinsic amorphous silicon layer 605℃, reaction time 1870s. Phosphorus doping, deposition temperature 815℃, time 1020s, phosphorus source flow 1420sccm, oxidation flow 620sccm, push temperature 885℃, time 1330s, oxidation temperature 880℃, time 1180s, surface concentration 4e20.

[0063] S6. According to the screen pattern, confirm that the poly blank is 300μm, use a large rectangular spot with a spot width of 450μm*100μm, and perform negative overlap in the 100μm direction. At this time, the energy extension of the two spots is 5μm.

[0064] S7, remove PSG from the front side of the silicon wafer after step S6, and use a 12% by mass HF solution to chain clean the front side of the silicon wafer for 240 seconds.

[0065] S8, remove poly from the silicon wafer after step S7. The reaction time is 110s, the reaction temperature is 65°C, and the proportion of the alkaline solution NaOH, RCA additive, H 2 O are 4.0%, 1.0%, and 95% alkaline solutions respectively.

[0066] S9. After step S8, the silicon wafer is double-sidedly coated with aluminum oxide, and the thickness of the aluminum oxide is 4 nm.

[0067] S10, coating the silicon wafer after step S9 with a 77nm silicon nitride composite layer on the front side and a 90nm silicon nitride oxide and silicon nitride composite layer on the back side.

[0068] S11, screen printing the silicon wafer after step S10, forming a positive electrode on the front side of the battery with silver-aluminum paste, forming a negative electrode on the back side with silver paste, and then performing laser-assisted sintering.

[0069] In this embodiment, the appearance after laser windowing and the appearance after RCA cleaning are as follows: Figure 1 shown.

[0070] Embodiment 2:

[0071] S1. The original silicon wafer is textured. The reaction time is 420s, the reaction temperature is 83°C, and the alkaline solution is prepared, containing NaOH, a texturing additive, and H 2 O are 1.2%, 0.3%, and 98.50% alkaline solutions respectively.

[0072] S2, after step S1, the silicon wafer is subjected to boron diffusion + oxidation. The deposition temperature is 840°C, the deposition time is 4100s, the boron source flow rate is 240sccm, the oxidation flow rate is 620sccm, the nitrogen flow rate is 2800sccm, the advancement temperature is 890°C, the time is 930s, the oxidation temperature is 1050°C, the time is 3600s, the texture area concentration is 5e18, and the junction depth is 0.68μm.

[0073] S3, remove BSG from the back of the silicon wafer after step S2, and use 31% HF solution to chain clean the back of the silicon wafer for 80 seconds.

[0074] S4. Polish the silicon wafer after step S3. The reaction time is 220s, the reaction temperature is 62°C, and the alkaline solution is prepared, containing NaOH, polishing additive, H 2 O are 3.5%, 0.4%, and 96.1% alkaline solutions respectively.

[0075] S5. Perform passivation structure growth and phosphorus diffusion on the silicon wafer after step S4. Tunneling oxide layer growth, deposition temperature 600℃, oxygen flow time 350s, oxygen simmering time 600s, intrinsic amorphous silicon layer 605℃, reaction time 1870s. Phosphorus doping, deposition temperature 815℃, time 1020s, phosphorus source flow 1420sccm, oxidation flow 620sccm, push temperature 885℃, time 1330s, oxidation temperature 880℃, time 1180s, surface concentration 4e20.

[0076] S6. According to the screen pattern, confirm that the poly blank is 300μm, use a large rectangular spot with a spot width of 450μm*100μm, and perform zero overlap in the 100μm direction. At this time, the distance between the two spots is 110μm, and their energy extension overlaps by 5μm.

[0077] S7, remove PSG from the front side of the silicon wafer after step S6, and use a 12% by mass HF solution to chain clean the front side of the silicon wafer for 240 seconds.

[0078] S8, remove poly from the silicon wafer after step S7. The reaction time is 110s, the reaction temperature is 65°C, and the proportion of the alkaline solution NaOH, RCA additive, H 2 O are 4.0%, 1.0%, and 95% alkaline solutions respectively.

[0079] S9. After step S8, the silicon wafer is double-sidedly coated with aluminum oxide, and the thickness of the aluminum oxide is 4 nm.

[0080] S10, coating the silicon wafer after step S9 with a 77nm silicon nitride composite layer on the front side and a 90nm silicon nitride oxide and silicon nitride composite layer on the back side.

[0081] S11, screen printing the silicon wafer after step S10, forming a positive electrode on the front side of the battery with silver-aluminum paste, forming a negative electrode on the back side with silver paste, and then performing laser-assisted sintering.

[0082] In this embodiment, the appearance after laser windowing and the appearance after RCA cleaning are as follows: Figure 2 shown.

[0083] Embodiment three:

[0084] S1. The original silicon wafer is textured. The reaction time is 420s, the reaction temperature is 83°C, and the alkaline solution is prepared, containing NaOH, a texturing additive, and H 2O are 1.2%, 0.3%, and 98.50% alkaline solutions respectively.

[0085] S2, after step S1, the silicon wafer is subjected to boron diffusion + oxidation. The deposition temperature is 840°C, the deposition time is 4100s, the boron source flow rate is 240sccm, the oxidation flow rate is 620sccm, the nitrogen flow rate is 2800sccm, the advancement temperature is 890°C, the time is 930s, the oxidation temperature is 1050°C, the time is 3600s, the texture area concentration is 5e18, and the junction depth is 0.68μm.

[0086] S3, remove BSG from the back of the silicon wafer after step S2, and use 31% HF solution to chain clean the back of the silicon wafer for 80 seconds.

[0087] S4. Polish the silicon wafer after step S3. The reaction time is 220s, the reaction temperature is 62°C, and the alkaline solution is prepared, containing NaOH, polishing additive, H 2 O are 3.5%, 0.4%, and 96.1% alkaline solutions respectively.

[0088] S5. Perform passivation structure growth and phosphorus diffusion on the silicon wafer after step S4. Tunneling oxide layer growth, deposition temperature 600℃, oxygen flow time 350s, oxygen simmering time 600s, intrinsic amorphous silicon layer 605℃, reaction time 1870s. Phosphorus doping, deposition temperature 815℃, time 1020s, phosphorus source flow 1420sccm, oxidation flow 620sccm, push temperature 885℃, time 1330s, oxidation temperature 880℃, time 1180s, surface concentration 4e20.

[0089] S6. Confirm that the poly blank is 300μm according to the screen pattern, use a large rectangular spot with a spot width of 450μm*100μm, and overlap 10% in the 100μm direction.

[0090] S7, remove PSG from the front side of the silicon wafer after step S6, and use a 12% by mass HF solution to chain clean the front side of the silicon wafer for 240 seconds.

[0091] S8, remove poly from the silicon wafer after step S7. The reaction time is 110s, the reaction temperature is 65°C, and the proportion of the alkaline solution NaOH, RCA additive, H 2 O are 4.0%, 1.0%, and 95% alkaline solutions respectively.

[0092] S9. After step S8, the silicon wafer is double-sidedly coated with aluminum oxide, and the thickness of the aluminum oxide is 4 nm.

[0093] S10, coating the silicon wafer after step S9 with a 77nm silicon nitride composite layer on the front side and a 90nm silicon nitride oxide and silicon nitride composite layer on the back side.

[0094] S11, screen printing the silicon wafer after step S10, forming a positive electrode on the front side of the battery with silver-aluminum paste, forming a negative electrode on the back side with silver paste, and then performing laser-assisted sintering.

[0095] In this embodiment, the appearance after laser windowing and the appearance after RCA cleaning are as follows: Figure 3 shown.

[0096] Embodiment 4:

[0097] S1. The original silicon wafer is textured. The reaction time is 420s, the reaction temperature is 83°C, and the alkaline solution is prepared, containing NaOH, a texturing additive, and H 2 O are 1.2%, 0.3%, and 98.50% alkaline solutions respectively.

[0098] S2, after step S1, the silicon wafer is subjected to boron diffusion + oxidation. The deposition temperature is 840°C, the deposition time is 4100s, the boron source flow rate is 240sccm, the oxidation flow rate is 620sccm, the nitrogen flow rate is 2800sccm, the advancement temperature is 890°C, the time is 930s, the oxidation temperature is 1050°C, the time is 3600s, the texture area concentration is 5e18, and the junction depth is 0.68μm.

[0099] S3, remove BSG from the back of the silicon wafer after step S2, and use 31% HF solution to chain clean the back of the silicon wafer for 80 seconds.

[0100] S4. Polish the silicon wafer after step S3. The reaction time is 220s, the reaction temperature is 62°C, and the alkaline solution is prepared, containing NaOH, polishing additive, H 2 O are 3.5%, 0.4%, and 96.1% alkaline solutions respectively.

[0101] S5. Perform passivation structure growth and phosphorus diffusion on the silicon wafer after step S4. Tunneling oxide layer growth, deposition temperature 600℃, oxygen flow time 350s, oxygen simmering time 600s, intrinsic amorphous silicon layer 605℃, reaction time 1870s. Phosphorus doping, deposition temperature 815℃, time 1020s, phosphorus source flow 1420sccm, oxidation flow 620sccm, push temperature 885℃, time 1330s, oxidation temperature 880℃, time 1180s, surface concentration 4e20.

[0102] S6. Confirm that the poly blank is 300μm according to the screen pattern, use a large rectangular spot with a spot width of 450μm*100μm, and overlap 20% in the 100μm direction.

[0103] S7, remove PSG from the front side of the silicon wafer after step S6, and use a 12% by mass HF solution to chain clean the front side of the silicon wafer for 240 seconds.

[0104] S8, remove poly from the silicon wafer after step S7. The reaction time is 110s, the reaction temperature is 65°C, and the proportion of the alkaline solution NaOH, RCA additive, H 2 O are 4.0%, 1.0%, and 95% alkaline solutions respectively.

[0105] S9. After step S8, the silicon wafer is double-sidedly coated with aluminum oxide, and the thickness of the aluminum oxide is 4 nm.

[0106] S10, coating the silicon wafer after step S9 with a 77nm silicon nitride composite layer on the front side and a 90nm silicon nitride oxide and silicon nitride composite layer on the back side.

[0107] S11, screen printing the silicon wafer after step S10, forming a positive electrode on the front side of the battery with silver-aluminum paste, forming a negative electrode on the back side with silver paste, and then performing laser-assisted sintering.

[0108] In this embodiment, the appearance after laser windowing and the appearance after RCA cleaning are as follows: Figure 4 shown.

[0109] Embodiment five:

[0110] S1. The original silicon wafer is textured. The reaction time is 420s, the reaction temperature is 83°C, and the alkaline solution is prepared, containing NaOH, a texturing additive, and H 2 O are 1.2%, 0.3%, and 98.50% alkaline solutions respectively.

[0111] S2, after step S1, the silicon wafer is subjected to boron diffusion + oxidation. The deposition temperature is 840°C, the deposition time is 4100s, the boron source flow rate is 240sccm, the oxidation flow rate is 620sccm, the nitrogen flow rate is 2800sccm, the advancement temperature is 890°C, the time is 930s, the oxidation temperature is 1050°C, the time is 3600s, the texture area concentration is 5e18, and the junction depth is 0.68μm.

[0112] S3, remove BSG from the back of the silicon wafer after step S2, and use 31% HF solution to chain clean the back of the silicon wafer for 80 seconds.

[0113] S4. Polish the silicon wafer after step S3. The reaction time is 220s, the reaction temperature is 62°C, and the alkaline solution is prepared, containing NaOH, polishing additive, H 2 O are 3.5%, 0.4%, and 96.1% alkaline solutions respectively.

[0114] S5. Perform passivation structure growth and phosphorus diffusion on the silicon wafer after step S4. Tunneling oxide layer growth, deposition temperature 600℃, oxygen flow time 350s, oxygen simmering time 600s, intrinsic amorphous silicon layer 605℃, reaction time 1870s. Phosphorus doping, deposition temperature 815℃, time 1020s, phosphorus source flow 1420sccm, oxidation flow 620sccm, push temperature 885℃, time 1330s, oxidation temperature 880℃, time 1180s, surface concentration 4e20.

[0115] S6. Confirm that the poly blank is 300μm according to the screen pattern, use a large rectangular spot with a spot width of 450μm*100μm, and overlap 30% in the 100μm direction.

[0116] S7, remove PSG from the front side of the silicon wafer after step S6, and use a 12% by mass HF solution to chain clean the front side of the silicon wafer for 240 seconds.

[0117] S8, remove poly from the silicon wafer after step S7. The reaction time is 110s, the reaction temperature is 65°C, and the proportion of the alkaline solution NaOH, RCA additive, H 2 O are 4.0%, 1.0%, and 95% alkaline solutions respectively.

[0118] S9. After step S8, the silicon wafer is double-sidedly coated with aluminum oxide, and the thickness of the aluminum oxide is 4 nm.

[0119] S10, coating the silicon wafer after step S9 with a 77nm silicon nitride composite layer on the front side and a 90nm silicon nitride oxide and silicon nitride composite layer on the back side.

[0120] S11, screen printing the silicon wafer after step S10, forming a positive electrode on the front side of the battery with silver-aluminum paste, forming a negative electrode on the back side with silver paste, and then performing laser-assisted sintering.

[0121] In this embodiment, the appearance after laser windowing and the appearance after RCA cleaning are as follows: Figure 5 shown.

[0122] Comparative Example 1:

[0123] S1. The original silicon wafer is textured. The reaction time is 420s, the reaction temperature is 83°C, and the alkaline solution is prepared, containing NaOH, a texturing additive, and H 2 O are 1.2%, 0.3%, and 98.50% alkaline solutions respectively.

[0124] S2, after step S1, the silicon wafer is subjected to boron diffusion + oxidation. The deposition temperature is 840°C, the deposition time is 4100s, the boron source flow rate is 240sccm, the oxidation flow rate is 620sccm, the nitrogen flow rate is 2800sccm, the advancement temperature is 890°C, the time is 930s, the oxidation temperature is 1050°C, the time is 3600s, the texture area concentration is 5e18, and the junction depth is 0.68μm.

[0125] S3, remove BSG from the back of the silicon wafer after step S2, and use 31% HF solution to chain clean the back of the silicon wafer for 80 seconds.

[0126] S4. Polish the silicon wafer after step S3. The reaction time is 220s, the reaction temperature is 62°C, and the alkaline solution is prepared, containing NaOH, polishing additive, H 2 O are 3.5%, 0.4%, and 96.1% alkaline solutions respectively.

[0127] S5. Perform passivation structure growth and phosphorus diffusion on the silicon wafer after step S4. Tunneling oxide layer growth, deposition temperature 600℃, oxygen flow time 350s, oxygen simmering time 600s, intrinsic amorphous silicon layer 605℃, reaction time 1870s. Phosphorus doping, deposition temperature 815℃, time 1020s, phosphorus source flow 1420sccm, oxidation flow 620sccm, push temperature 885℃, time 1330s, oxidation temperature 880℃, time 1180s, surface concentration 4e20.

[0128] S6. Do not perform laser window opening, skip this step, and simulate the existing process flow of the production line.

[0129] S7, remove PSG from the front side of the silicon wafer after step S5, and use a 12% by mass HF solution to chain clean the front side of the silicon wafer for 240 seconds.

[0130] S8, remove poly from the silicon wafer after step S7. The reaction time is 110s, the reaction temperature is 65°C, and the proportion of the alkaline solution NaOH, RCA additive, H 2 O are 4.0%, 1.0%, and 95% alkaline solutions respectively.

[0131] S9. After step S8, the silicon wafer is double-sidedly coated with aluminum oxide, and the thickness of the aluminum oxide is 4 nm.

[0132] S10, coating the silicon wafer after step S9 with a 77nm silicon nitride composite layer on the front side and a 90nm silicon nitride oxide and silicon nitride composite layer on the back side.

[0133] S11, screen printing the silicon wafer after step S10, forming a positive electrode on the front side of the battery with silver-aluminum paste, forming a negative electrode on the back side with silver paste, and then performing laser-assisted sintering.

[0134] Comparative Example 2:

[0135] S1. The original silicon wafer is textured. The reaction time is 420s, the reaction temperature is 83°C, and the alkaline solution is prepared, containing NaOH, a texturing additive, and H 2 O are 1.2%, 0.3%, and 98.50% alkaline solutions respectively.

[0136] S2, after step S1, the silicon wafer is subjected to boron diffusion + oxidation. The deposition temperature is 840°C, the deposition time is 4100s, the boron source flow rate is 240sccm, the oxidation flow rate is 620sccm, the nitrogen flow rate is 2800sccm, the advancement temperature is 890°C, the time is 930s, the oxidation temperature is 1050°C, the time is 3600s, the texture area concentration is 5e18, and the junction depth is 0.68μm.

[0137] S3, remove BSG from the back of the silicon wafer after step S2, and use 31% HF solution to chain clean the back of the silicon wafer for 80 seconds.

[0138] S4. Polish the silicon wafer after step S3. The reaction time is 220s, the reaction temperature is 62°C, and the alkaline solution is prepared, containing NaOH, polishing additive, H 2 O are 3.5%, 0.4%, and 96.1% alkaline solutions respectively.

[0139] S5. Perform passivation structure growth and phosphorus diffusion on the silicon wafer after step S4. Tunneling oxide layer growth, deposition temperature 600℃, oxygen flow time 350s, oxygen simmering time 600s, intrinsic amorphous silicon layer 605℃, reaction time 1870s. Phosphorus doping, deposition temperature 815℃, time 1020s, phosphorus source flow 1420sccm, oxidation flow 620sccm, push temperature 885℃, time 1330s, oxidation temperature 880℃, time 1180s, surface concentration 4e20.

[0140] S6. According to the screen pattern, confirm that the poly blank is 300μm, use a small square spot with a spot width of 150μm*150, overlap 50% on the X axis, and no overlap on the Y axis.

[0141] S7, remove PSG from the front side of the silicon wafer after step S6, and use a 12% by mass HF solution to chain clean the front side of the silicon wafer for 240 seconds.

[0142] S8, remove poly from the silicon wafer after step S7. The reaction time is 110s, the reaction temperature is 65°C, and the proportion of the alkaline solution NaOH, RCA additive, H 2 O are 4.0%, 1.0%, and 95% alkaline solutions respectively.

[0143] S9. After step S8, the silicon wafer is double-sidedly coated with aluminum oxide, and the thickness of the aluminum oxide is 4 nm.

[0144] S10, coating the silicon wafer after step S9 with a 77nm silicon nitride composite layer on the front side and a 90nm silicon nitride oxide and silicon nitride composite layer on the back side.

[0145] S11, screen printing the silicon wafer after step S10, forming a positive electrode on the front side of the battery with silver-aluminum paste, forming a negative electrode on the back side with silver paste, and then performing laser-assisted sintering.

[0146] In this embodiment, the appearance after laser windowing and the appearance after RCA cleaning are as follows: Figure 6 shown.

[0147] Experimental example:

[0148] After three batch experiments, the efficiency (Eta), short circuit current (Isc), open circuit voltage (Uoc) and fill factor (FF) of the final silicon wafer product cells were tracked, see Table 1.

[0149] Table 1:

[0150] Eta Uoc(V) Isc(A) FF Embodiment 1 26.63 0.7463 14.362 84.68 Embodiment 2 26.61 0.7461 14.357 84.67 Embodiment 3 26.46 0.7449 14.306 84.65 Embodiment 4 26.62 0.7464 14.351 84.72 Embodiment 5 26.55 0.7464 14.336 84.68 Comparative Example 1 26.41 0.7455 14.243 84.79 Comparative Example 2 26.56 0.7461 14.329 84.69

[0151] As shown in Table 1, compared with the comparative example, the efficiency Eta of the embodiment is improved by 0.05-0.21, the main gain is brought by Isc and Uoc, and the filling factor FF is slightly lost. Moreover, from the appearance after laser windowing and RCA cleaning of each embodiment, it can be seen that the tower base morphology after RCA cleaning of the method disclosed in the embodiment of the present invention is more uniform.

[0152] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0153] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for manufacturing a TOPCon solar cell, characterized in that: include: Prepare TOPCon passivation structure on the surface of silicon substrate; Performing laser windowing on the surface of the TOPCon passivation structure to obtain a finger structure pattern; Etching the finger structure pattern area; The laser overlap rate used in the laser window opening process is no more than 40% and the area is no less than 40,000 square microns.

2. The method according to claim 1, characterized in that: The laser overlap ratio is 40%.

3. The method according to claim 1, characterized in that: The laser overlap ratio is 30%.

4. The method according to claim 1, characterized in that: The laser overlap ratio is 20%.

5. The method according to claim 1, characterized in that: The laser overlap ratio is 10%.

6. The method according to claim 1, characterized in that: The laser overlap ratio is 0.

7. The method according to claim 1, characterized in that: The laser overlap ratio is less than 0.

8. The method according to claim 1, characterized in that: The laser window area is 45,000 square microns.

9. The method according to claim 1, characterized in that: The shape of the laser window is a rectangle of 450 microns*100 microns.

10. The manufacturing method according to claim 1, characterized in that: The finger structure pattern area is etched using a wet etching process.

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