Full-color micro LED display device and preparation method thereof

Abstract

The application discloses a full-color Micro LED display device and a preparation method thereof. The device comprises a plurality of display units, and each display unit comprises a first N-GaN layer, a blue light LED light-emitting layer, a first P-GaN layer, a first heavily doped PN junction layer, a second N-GaN layer, a green light LED light-emitting layer, a second P-GaN layer, a second heavily doped PN junction layer, a third N-GaN layer, a red light LED light-emitting layer, a third P-GaN layer, a third heavily doped PN junction layer, a fourth N-GaN layer and a metal reflection layer. A passivation layer covers the sidewalls of the first N-GaN layer, the blue light LED light-emitting layer, the first P-GaN layer, the first heavily doped PN junction layer, the second N-GaN layer, the green light LED light-emitting layer, the second P-GaN layer, the second heavily doped PN junction layer, the third N-GaN layer, the red light LED light-emitting layer, the third P-GaN layer, the third heavily doped PN junction layer, the fourth N-GaN layer and the metal reflection layer. The upper surfaces of a first electrode, a second electrode, a third electrode and a fourth electrode are flush. A CMOS driver covers the upper surface of a bonding layer and is electrically connected to the first electrode, the second electrode, the third electrode and the fourth electrode.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a full-color Micro LED display device and a preparation method thereof. BACKGROUND

[0002] Gallium nitride is a semiconductor material with excellent electrical properties and thermal stability, which is very suitable for manufacturing high-brightness and high-efficiency Micro LED. The light-emitting efficiency of gallium nitride Micro LED is high, which can significantly reduce energy consumption and provide high enough brightness to meet the needs of full-color display. Gallium nitride Micro LED has high stability and can operate stably for a long time without failure, which is particularly important for full-color display devices that need to operate for a long time.

[0003] In the prior art, in order to realize full-color Micro LED display, three wafers with different light-emitting colors are often used for device manufacturing, and then different light-emitting wavelength wafers are bonded to realize three-color integration. This method is complex, high in cost, low in yield, and long in manufacturing cycle. Alternatively, by changing the size of the current to change the light-emitting wavelength, full-color display can be realized. The wavelength change range of this method is limited, only covering the green to red or cyan to red range, and the color gamut of the display is insufficient. SUMMARY

[0004] The purpose of the present application is to overcome the shortcomings of the prior art, and the purpose of the present application is to provide a full-color Micro LED display device, and the purpose of the present application is to provide a preparation method of a full-color Micro LED display device.

[0005] To solve the above technical problems, the present application provides a full-color Micro LED display device, which comprises a plurality of display units, wherein the display unit comprises:

[0006] A first N-GaN layer, the side of the first N-GaN layer has a first step;

[0007] A blue light LED light-emitting layer covers the upper surface of the non-step region of the first N-GaN layer;

[0008] A first P-GaN layer covers the upper surface of the blue light LED light-emitting layer;

[0009] A first heavily doped PN junction layer covers the upper surface of the first P-GaN layer;

[0010] A second N-GaN layer covers the upper surface of the first heavily doped PN junction layer, and the side of the second N-GaN layer has a second step;

[0011] a green LED light emitting layer covering the upper surface of the non-step region of the second N-GaN layer;

[0012] a second P-GaN layer covering the upper surface of the green LED light emitting layer;

[0013] a second heavily doped PN junction layer covering the upper surface of the second P-GaN layer;

[0014] a third N-GaN layer covering the upper surface of the second heavily doped PN junction layer, the side edge of the third N-GaN layer having a third step;

[0015] a red LED light emitting layer covering the upper surface of the non-step region of the third N-GaN layer;

[0016] a third P-GaN layer covering the upper surface of the red LED light emitting layer;

[0017] a third heavily doped PN junction layer covering the upper surface of the third P-GaN layer;

[0018] a fourth N-GaN layer covering the upper surface of the third heavily doped PN junction layer;

[0019] a metal reflective layer covering the upper surface of the fourth N-GaN layer;

[0020] a passivation layer covering the sidewall of the first N-GaN layer, blue LED light emitting layer, first P-GaN layer, first heavily doped PN junction layer, second N-GaN layer, green LED light emitting layer, second P-GaN layer, second heavily doped PN junction layer, third N-GaN layer, red LED light emitting layer, third P-GaN layer, third heavily doped PN junction layer, fourth N-GaN layer, and metal reflective layer;

[0021] a first electrode located on the first step and extending away from the first N-GaN layer;

[0022] a second electrode located on the second step and extending away from the first N-GaN layer;

[0023] a third electrode located on the metal reflective layer and extending away from the first N-GaN layer;

[0024] a fourth electrode located on the third step and extending away from the first N-GaN layer;

[0025] the upper surfaces of the first electrode, second electrode, third electrode, and fourth electrode are flush;

[0026] A bonding layer fills the gaps between the first electrode, the second electrode, the third electrode, the fourth electrode, and the passivation layer, and covers the first electrode, the second electrode, the third electrode, the fourth electrode, and the passivation layer.

[0027] A CMOS driver covers the upper surface of the bonding layer and is electrically connected to the first electrode, the second electrode, the third electrode, and the fourth electrode.

[0028] Preferably, the bonding layer includes a first bonding layer and a second bonding layer stacked from bottom to top; the portions of the first electrode, the second electrode, the third electrode, and the fourth electrode located within the second bonding layer are respectively the first contact electrode, the second contact electrode, the third contact electrode, and the fourth contact electrode.

[0029] Preferably, the first heavily doped PN junction layer comprises a first P+-InGaN layer and a first N+-InGaN layer stacked from bottom to top, wherein the In content of the first P+-InGaN layer is 0-10%, the dopant is Mg, and the doping concentration is >5E19cm. -3 The first N+-InGaN layer has an In content of 0-10%, and the dopant is Si with a doping concentration >2E19cm⁻¹. -3 .

[0030] Preferably, the second heavily doped PN junction layer comprises a second P+-InGaN layer and a second N+-InGaN layer stacked from bottom to top, wherein the In content of the second P+-InGaN layer is 0-10%, the dopant is Mg, and the doping concentration is >5E19cm. -3 The second N+-InGaN layer has an In content of 0-10%, and the dopant is Si, with a doping concentration >2E19cm⁻¹. -3 .

[0031] Preferably, the third doped PN junction layer comprises a third P+-InGaN layer and a third N+-InGaN layer stacked from bottom to top, wherein the In content of the third P+-InGaN layer is 0-10%, the dopant is Mg, and the doping concentration is >5E19cm⁻¹. -3 The third N+-InGaN layer has an In content of 0-10%, and the dopant is Si with a doping concentration >2E19cm⁻¹. -3 .

[0032] Preferably, the thickness of the first P+-InGaN layer is 5-20 nm, the thickness of the first N+-InGaN layer is 5-20 nm, and the thickness ratio of the first P+-InGaN layer to the first N+-InGaN layer is 1:1.

[0033] Preferably, the second P+-InGaN layer has a thickness of 5-20 nm, the second N+-InGaN layer has a thickness of 5-20 nm, and the thickness ratio of the second N+-InGaN layer is 1:1.

[0034] Preferably, the third P+-InGaN layer has a thickness of 5-20 nm, the third N+-InGaN layer has a thickness of 5-20 nm, and the thickness ratio of the third P+-InGaN layer and the third N+-InGaN layer is 1:1.

[0035] Based on the same inventive concept, the application further provides a preparation method of a full-color Micro LED display device, comprising:

[0036] forming a first component, comprising the following steps:

[0037] Step 11, providing a silicon substrate, and epitaxially growing a nucleation layer, a buffer layer, a first N-GaN layer, a blue light LED light-emitting layer, a first P-GaN layer, a first heavily doped PN junction layer, a second N-GaN layer, a green light LED light-emitting layer, a second P-GaN layer, a second heavily doped PN junction layer, a third N-GaN layer, a red light LED light-emitting layer, a third P-GaN layer, a third heavily doped PN junction layer, and a fourth N-GaN layer on the surface of the silicon substrate in sequence;

[0038] Step 12, first etching, etching a part of each layer on the first N-GaN layer and a part of the first N-GaN layer along the thickness direction of the first component, and forming a first step on the side of the first N-GaN layer;

[0039] Step 13, second etching, etching a part of each layer on the second N-GaN layer and a part of the second N-GaN layer along the thickness direction of the first component, and forming a second step on the side of the second N-GaN layer;

[0040] Step 14, third etching, etching a part of each layer on the third N-GaN layer and a part of the third N-GaN layer along the thickness direction of the first component, and forming a third step on the side of the third N-GaN layer;

[0041] Step 15, forming a metal reflection layer on the upper surface of the fourth N-GaN layer;

[0042] Step 16, forming a passivation layer covering the first N-GaN layer, the blue LED light emitting layer, the first P-GaN layer, the first heavily doped PN junction layer, the second N-GaN layer, the green LED light emitting layer, the second P-GaN layer, the second heavily doped PN junction layer, the third N-GaN layer, the red LED light emitting layer, the third P-GaN layer, the third heavily doped PN junction layer, the fourth N-GaN layer, and the sidewall of the metal reflective layer;

[0043] Step 17, disposing a first sub-electrode, a second sub-electrode, a third sub-electrode, and a fourth sub-electrode above the first step, the second step, the metal reflective layer, and the third step, respectively;

[0044] Step 18, forming a first bonding layer, which fills the gaps between the first sub-electrode, the second sub-electrode, the third sub-electrode, the fourth sub-electrode, and the passivation layer, and covers the metal reflective layer;

[0045] Step 19, planarizing the first bonding layer;

[0046] forming a second component, comprising the following steps:

[0047] Step 21, providing a CMOS driver, and forming a second bonding layer above the CMOS driver;

[0048] Step 22, etching the second bonding layer along the thickness direction of the second bonding layer to form four through holes penetrating through the second bonding layer;

[0049] Step 23, placing a first contact electrode, a second contact electrode, a third contact electrode, and a fourth contact electrode in the through holes, respectively;

[0050] bonding the first component and the second component, comprising the following steps:

[0051] Step 31, horizontally transposing the second component to align and bond the first sub-electrode with the first contact electrode, the second sub-electrode with the second contact electrode, the third sub-electrode with the third contact electrode, and the fourth sub-electrode with the fourth contact electrode, and forming a first electrode, a second electrode, a third electrode, and a fourth electrode, respectively;

[0052] Step 32, removing the silicon substrate, the nucleation layer, and the buffer layer to obtain the full-color Micro LED display device.

[0053] Preferably, after the step 14, the first component is further subjected to P-type Mg doping activation, and the doping concentration is >5E18cm -3 .

[0054] Working principle: In the process of preparing full-color Micro LED display devices, three groups of P+-InGaN / N+-InGaN heavily doped PN junction materials are ingeniously introduced, laying a solid foundation for constructing high-performance electrode structures. The special feature of these PN junctions is their high doping concentration, which directly leads to a significant reduction in the junction width. Generally, the junction width of a PN junction is a key factor determining the probability of electron tunneling. The greater the width, the higher the energy required for electron tunneling, and the more difficult it is. However, in heavily doped PN junctions, due to the increase in doping concentration, the junction width is greatly compressed, allowing electrons to easily pass through this narrow region by tunneling effect. Quantum tunneling effect is a quantum mechanical phenomenon that allows electrons to pass through a potential barrier with a certain probability even if the energy is not sufficient to overcome the barrier. In heavily doped PN junctions, this effect is fully utilized, and electrons can easily achieve reverse conduction, thereby greatly enhancing the conductivity of the electrode. More importantly, this feature brings unprecedented flexibility to electrode fabrication. Since electrons can easily pass through the junction region, the etching depth requirement of the material during electrode fabrication becomes less stringent. This means that even if there is a certain deviation in the etching depth, it will not significantly affect the conductivity of the electrode, thereby reducing the difficulty and cost of the fabrication process.

[0055] Advantages: Compared with the prior art, the present application has the following significant features:

[0056] 1. Three kinds of light emitting wavelengths are integrated in one epitaxial wafer, which can be grown by epitaxial growth at one time, without the need for multiple re-growth in epitaxial machines (MOCVD / MBE) or the need for bonding and integration between three different light emitting wavelength (RGB three-color) wafers to achieve multiple light emitting materials. The device fabrication process is greatly simplified.

[0057] 2. The etching depth of the material does not need to be accurately controlled during the fabrication process of the electrode, the device fabrication process is highly simplified, and the yield of device fabrication is improved. By adding a heavily doped PN junction layer, the heavily doped PN junction has a small junction width due to its high doping, and electrons can tunnel through the heavily doped PN junction to form a reverse conduction current. Therefore, each electrode can be placed on the thicker N-type material layer behind the heavily doped PN junction by material etching. Since the N-type material layer has a relatively thick thickness, the control of the material etching depth does not need to be very strict.

[0058] 3. The three kinds of light emitting wavelengths in one wafer can be controlled individually, the control of light emitting wavelength is more accurate, the color adjustment range is wider, and a larger color gamut is achieved. Moreover, the shape of each electrode is relatively vertical, and the process steps are simple. BRIEF DESCRIPTION OF DRAWINGS

[0059] In the drawings, like reference numerals are used to refer to like elements throughout the several views. Not all elements of each drawing are necessarily labeled. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the technology and devices described herein.

[0060] Figure 1 A structural schematic of the product of step 11 of the present application is shown;

[0061] Figure 2 A structural schematic of the product of step 14 of the present application is shown;

[0062] Figure 3 A structural schematic of the product of step 15 of the present application is shown;

[0063] Figure 4 A structural schematic of the product of step 16 of the present application is shown;

[0064] Figure 5 A structural schematic of the product of step 17 of the present application is shown;

[0065] Figure 6 A top view of the product of step 17 of the present application is shown;

[0066] Figure 7 A structural schematic of the product of step 18 of the present application is shown;

[0067] Figures 8-9 A structural schematic of the product of step 21 of the present application is shown;

[0068] Figure 10 A structural schematic of the product of step 22 of the present application is shown;

[0069] Figure 11 A structural schematic of the product of step 23 of the present application is shown;

[0070] Figure 12 A structural schematic of the product of step 32 of the present application is shown.

[0071] Wherein the reference numerals are explained as follows:

[0072] 10-substrate, 20-nucleation layer, 30-buffer layer, 40-first N-GaN layer, 50-blue LED light emitting layer, 60-first P-GaN layer, 70-first heavily doped PN junction layer, 71-first P+-InGaN layer, 72-first N+-InGaN layer, 80-second N-GaN layer, 90-green LED light emitting layer, 100-second P-GaN layer, 110-second heavily doped PN junction layer, 111-second P+-InGaN layer, 112-second N+-InGaN layer, 120-third N-GaN layer, 130-red LED light emitting layer, 140-third P-GaN layer, 150-third heavily doped PN junction layer, 151-third P+-InGaN layer, 152-third N+-InGaN layer, 160-fourth N-GaN layer, 170-metallic reflection layer, 180-passivation layer, 191-first sub-electrode, 192-second sub-electrode, 193-third sub-electrode, 194-fourth sub-electrode, 201-first bonding layer, 202-second bonding layer, 210-CMOS driver, 220-via hole, 231-first contact electrode, 232-second contact electrode, 233-third contact electrode, 234-fourth contact electrode. DETAILED DESCRIPTION

[0073] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, the example embodiments can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the several views.

[0074] The expressions of position and direction described in the present application are described with reference to the drawings, but changes can be made as needed, and the changes are included in the scope of the present application.

[0075] The present application provides a preparation method of a full-color Micro LED display device, including preparing a first component, preparing a second component, and bonding the first component and the second component.

[0076] Specifically, the first component is prepared, and the preparation of the epitaxial structure can be completed by using a MOCVD epitaxial growth device, and the steps are as follows:

[0077] Step 11, a silicon substrate 10 is provided, and a nucleation layer 20, a buffer layer 30, a first N-GaN layer 40, a blue LED light emitting layer 50, a first P-GaN layer 60, a first heavily doped PN junction layer 70, a second N-GaN layer 80, a green LED light emitting layer 90, a second P-GaN layer 100, a second heavily doped PN junction layer 110, a third N-GaN layer 120, a red LED light emitting layer 130, a third P-GaN layer 140, a third heavily doped PN junction layer 150, and a fourth N-GaN layer 160 are epitaxially grown on the surface of the silicon substrate 10 in sequence, as shown in Figure 1 .

[0078] Specifically, the AlN nucleation layer 20 of 200 nm is grown on the substrate 10 at a temperature of 950-1150°C and a pressure of 50-100 torr.

[0079] The AlGaN buffer layer 30 of 0.2-1 μm is grown on the nucleation layer 20 at a temperature of 980-1180°C and a pressure of 50-100 torr.

[0080] The first N-GaN layer 40 of 0.5-2.0 μm is grown on the buffer layer 30 at a temperature of 1100-1200°C and a pressure of 200-300 torr.

[0081] The blue LED light emitting layer 50 of 90-150 nm is grown on the first N-GaN layer 40 at a temperature of 760-800°C and a pressure of 400-500 torr, and the blue LED light emitting layer 50 is a multi-quantum well structure.

[0082] The first P-GaN layer 60 of 50-100 nm is grown on the blue LED light emitting layer 50 at a temperature of 900-1000°C and a pressure of 200-300 torr.

[0083] The first heavily doped PN junction layer 70 is grown on the first P-GaN layer 60, and the first heavily doped PN junction layer 70 includes the first P+-InGaN layer 71 and the first N+-InGaN layer 72 stacked from bottom to top, wherein the In content is 0-10%, and when the In content is 0, the first heavily doped PN junction layer 70 includes the first P+-GaN layer 71 and the first N+-GaN layer 72 stacked from bottom to top.

[0084] The first P+-InGaN layer 71 of 5-20 nm is grown on the first P-GaN layer 60 at a temperature of 850-950°C and a pressure of 400-500 torr, the In content is 0-10%, the dopant is Mg, and the doping concentration is >5E19 cm -3 , and the preferred value is 1E20 cm -3 .

[0085] A first N+-InGaN layer 72 of 5-20 nm, with In content of 0-10%, doped with Si, and a doping concentration > 2E19cm -3 , preferably 3E19cm -3 , is grown on the first P+-InGaN layer 71 under temperature conditions of 850-950°C and pressure conditions of 400-500 torr.

[0086] A second N-GaN layer 80 of 0.5-2.0 μm is grown on the first N+-InGaN layer 72 under temperature conditions of 1000-1200°C and pressure conditions of 200-300 torr.

[0087] A green LED light emitting layer 90 of 90-150 nm is grown on the second N-GaN layer 80 under temperature conditions of 742-782°C and pressure conditions of 400-500 torr, the green LED light emitting layer 90 being a multi-quantum well structure.

[0088] A second P-GaN layer 100 of 50-100 nm is grown on the green LED light emitting layer 90 under temperature conditions of 900-1000°C and pressure conditions of 200-300 torr.

[0089] A second heavily doped PN junction layer 110 is grown on the second P-GaN layer 100, the second heavily doped PN junction layer 110 including a second P+-InGaN layer 111 and a second N+-InGaN layer 112 stacked from bottom to top, wherein the In content is 0-10%, and when the In content is 0, the second heavily doped PN junction layer 110 includes a second P+-GaN layer 111 and a second N+-GaN layer 112 stacked from bottom to top.

[0090] A second P+-InGaN layer 111 of 5-20 nm, with In content of 0-10%, doped with Mg, and a doping concentration > 5E19cm -3 , preferably 1E20cm -3 , is grown on the second P-GaN layer 100 under temperature conditions of 850-950°C and pressure conditions of 400-500 torr.

[0091] A second N+-InGaN layer 112 of 5-20 nm, with In content of 0-10%, doped with Si, and a doping concentration > 2E19cm -3 , preferably 3E19cm -3, the thickness ratio of the third P+-InGaN layer and the third N+-InGaN layer is 1:1.

[0092] A third N-GaN layer 120 of 0.5-2.0 μm is grown on the second N+-InGaN layer 112 at a temperature of 1000-1200 °C and a pressure of 200-300 torr.

[0093] A red LED light-emitting layer 130 of 90-150 nm is grown on the third N-GaN layer 120 at a temperature of 702-742 °C and a pressure of 400-500 torr, the red LED light-emitting layer 130 being a multi-quantum well structure.

[0094] A third P-GaN layer 140 of 50-100 nm is grown on the red LED light-emitting layer 130 at a temperature of 900-1000 °C and a pressure of 200-300 torr.

[0095] A third heavily doped PN junction layer 150 is grown on the third P-GaN layer 140, the third heavily doped PN junction layer 150 comprising a third P+-InGaN layer 151 and a third N+-InGaN layer 152 stacked from bottom to top, wherein the In content is 0-10%, and when the In content is 0, the third heavily doped PN junction layer 150 comprises a third P+-GaN layer 151 and a third N+-GaN layer 152 stacked from bottom to top.

[0096] The third P+-InGaN layer 151 of 5-20 nm is grown on the third P-GaN layer 140 at a temperature of 850-950 °C and a pressure of 400-500 torr, the In content being 0-10%, the dopant being Mg, and the doping concentration being >5E19 cm -3 , and the preferred value is 1E20 cm -3 .

[0097] The third N+-InGaN layer 152 of 5-20 nm is grown on the third P+-InGaN layer 151 at a temperature of 850-950 °C and a pressure of 400-500 torr, the In content being 0-10%, the dopant being Si, and the doping concentration being >2E19 cm -3 , and the preferred value is 3E19 cm -3 , the thickness ratio of the third P+-InGaN layer and the third N+-InGaN layer being 1:1.

[0098] The first heavily doped PN junction layer 70, the second heavily doped PN junction layer 110, and the third heavily doped PN junction layer 150 using InGaN material can reduce the forward voltage.

[0099] A fourth N-GaN layer 160 of 0.5-2.0 μm is grown on the third N+-InGaN layer 152 at a temperature of 1000-1200 °C and a pressure of 200-300 torr.

[0100] The three light emitting wavelengths are integrated in the epitaxial wafer, and are grown by one-time epitaxial growth without the need for multiple times of being put into a MOCVD machine for regrowth, without the need for bonding and integration among three wafers with different light emitting wavelengths (RGB three colors), and the related light emitting material and device manufacturing process is greatly simplified.

[0101] Step 12, first etching, etching a portion of each layer on the first N-GaN layer 40 and a portion of the first N-GaN layer 40 along the thickness direction of the first component, to form a first step on the side of the first N-GaN layer 40.

[0102] Photoresist is coated on the product obtained in step 11, and exposure and development are performed using a mask plate to form a pattern to be etched, and ion etching technology is used to etch the epitaxial layer according to the photoetching pattern to remove the unnecessary part, to etch to the first N-GaN layer 40, to form a first step on the side of the first N-GaN layer 40. The thickness of the first N-GaN layer 40 etched is less than the thickness of the first N-GaN layer 40.

[0103] Step 13, second etching, etching a portion of each layer on the second N-GaN layer 80 and a portion of the second N-GaN layer 80 along the thickness direction of the first component, to form a second step on the side of the second N-GaN layer 80.

[0104] Photoresist is coated on the product obtained in step 12, and exposure and development are performed using a mask plate to form a pattern to be etched, and ion etching technology is used to etch the epitaxial layer according to the photoetching pattern to remove the unnecessary part, to etch to the second N-GaN layer 80, to form a second step on the side of the second N-GaN layer 80. The thickness of the second N-GaN layer 80 etched is less than the thickness of the second N-GaN layer 80.

[0105] Step 14, third etching, etching a portion of each layer on the third N-GaN layer 120 and a portion of the third N-GaN layer 120 along the thickness direction of the first component, to form a third step on the side of the third N-GaN layer 120.

[0106] A photoresist is coated on the product obtained in step 13, and exposure and development are performed using a mask plate to form a pattern to be etched. The epitaxial layer is etched according to the photoetching pattern using an ion etching technique to remove unnecessary portions, and etching is performed to the third N-GaN layer 120 to form a third step on the side of the third N-GaN layer 120. The thickness of the third N-GaN layer 120 etched is less than the thickness of the third N-GaN layer 120.

[0107] The three etching steps are completed as shown in Figure 2 . The order of steps 12-14 can be changed.

[0108] After the side wall is etched, P-type activation can be performed at a high temperature of 600-700°C in a N2 atmosphere. The formation of the side wall is beneficial to the diffusion of H atoms from the side wall, thereby activating Mg doping, and the doping concentration is >5E18cm -3 .

[0109] Step 15, a metal reflection layer 170 is formed on the upper surface of the fourth N-GaN layer 160.

[0110] A photoresist is coated on the product obtained in step 14, and exposure and development are performed using a mask plate to expose the fourth N-GaN layer 160.

[0111] A vacuum electron beam evaporation device is used to form a 100nm metal reflection layer 170 on the surface of the fourth N-GaN layer 160, as shown in Figure 3 .

[0112] The material of the metal reflection layer 170 can be silver (Ag), aluminum (Al), or gold (Au), which has high reflectivity and can form good adhesion with the fourth N-GaN layer 160.

[0113] Step 16, a passivation layer 180 is formed, which covers the first N-GaN layer 40, the blue LED light emitting layer 50, the first P-GaN layer 60, the first heavily doped PN junction layer 70, the second N-GaN layer 80, the green LED light emitting layer 90, the second P-GaN layer 100, the second heavily doped PN junction layer 110, the third N-GaN layer 120, the red LED light emitting layer 130, the third P-GaN layer 140, the third heavily doped PN junction layer 150, the fourth N-GaN layer 160, and the side wall of the metal reflection layer 170.

[0114] A passivation layer 180 is deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD) method. Taking CVD method as an example, aluminum source (TMAl), nitrogen (N2) and ammonia (NH3) are used as reaction gases, the deposition temperature is 900-1000℃, the aluminum source gas flow is 100-150sccm, the nitrogen (N2) gas flow is 15000-25000sccm, the ammonia (NH3) gas flow is 250-350sccm, and the reaction time is 4-6min, etc. to obtain a uniform and dense passivation layer 180 of 5-50nm.

[0115] After forming the AlN passivation layer 180, photolithography and etching processes are required to form the desired patterns and windows, as shown in Figure 4 .

[0116] The main function of the passivation layer 180 is to protect the Micro LED device from damage from the external environment, such as oxidation, moisture, dust, etc., while improving the light extraction efficiency and performance of the Micro LED.

[0117] Step 17, a first sub-electrode 191, a second sub-electrode 192, a third sub-electrode 193, and a fourth sub-electrode 194 are respectively disposed above the first step, the second step, the metal reflection layer 170, and the third step.

[0118] Among them, the first sub-electrode 191 is perpendicular to the first step and is the negative electrode of the blue light LED. The second sub-electrode 192 is perpendicular to the second step and is the positive electrode of the blue light LED and the negative electrode of the green light LED. The third sub-electrode 193 is perpendicular to the metal reflection layer 170 and is the positive electrode of the red light LED. The fourth sub-electrode 194 is perpendicular to the third step and is the negative electrode of the red light LED and the positive electrode of the green light LED, as shown in Figure 5 . The electrode material can be gold (Au), platinum (Pt), titanium (Ti), etc.

[0119] As shown in Figure 6 , the top view of the product obtained in step 17, the first N-GaN layer 40 can be seen around the first sub-electrode 191, the second N-GaN layer 80 can be seen around the second sub-electrode 192, the third N-GaN layer 120 can be seen around the fourth sub-electrode 194, and the other areas and around the third sub-electrode 193 are the upper surface of the reflection metal layer 170.

[0120] Step 18, a first bonding layer 201 is formed, which fills the gaps between the first sub-electrode 191, the second sub-electrode 192, the third sub-electrode 193, the fourth sub-electrode 194, and the passivation layer 180, and covers the metal reflection layer 170.

[0121] A first bonding layer 201 of SiO2 is deposited by a plasma enhanced chemical vapor deposition (PECVD) process at a deposition temperature of 300-500°C in the gaps between the first sub-electrode 191, the second sub-electrode 192, the third sub-electrode 193, the fourth sub-electrode 194 and the passivation layer 180, and covers the metal reflective layer 170, as shown in Figure 7 .

[0122] Step 19, planarizing the first bonding layer 201.

[0123] The surface quality of the first bonding layer 201 is improved by using chemical mechanical polishing (CMP) or other planarization techniques.

[0124] Specifically, a second component is prepared to form a CMOS driving circuit, including the following steps:

[0125] Step 21, providing a CMOS driver 210, and forming a second bonding layer 202 above the CMOS driver 210.

[0126] The second bonding layer 202 is deposited by a PECVD process at a deposition temperature of 300-500°C to form a second bonding layer 202 of 0.1-1 μm of SiO2, as shown in Figures 8-9 .

[0127] Step 22, etching the second bonding layer 202 along the thickness direction of the second bonding layer 202 to form four through holes 220 penetrating the second bonding layer.

[0128] A photoresist is coated on the upper surface of the second bonding layer 202, and exposed and developed using a mask to form a pattern to be etched. The second bonding layer 202 is etched according to the photoetching pattern using ion etching technology to form four through holes 220 penetrating the second bonding layer 202, as shown in Figure 10 .

[0129] Step 23, placing a first contact electrode 231, a second contact electrode 232, a third contact electrode 233 and a fourth contact electrode 234 in the through holes 220, respectively, as shown in Figure 11 .

[0130] Specifically, the first component and the second component are bonded, including the following steps:

[0131] Step 31, horizontally transposing the second component, aligning and bonding the first sub-electrode 191 with the first contact electrode 231, the second sub-electrode 192 with the second contact electrode 232, the third sub-electrode 193 with the third contact electrode 233, and the fourth sub-electrode 194 with the fourth contact electrode 234, and forming a first electrode, a second electrode, a third electrode, and a fourth electrode, respectively.

[0132] The first sub-electrode 191 and the first contact electrode 231, the second sub-electrode 192 and the second contact electrode 232, the third sub-electrode 193 and the third contact electrode 233, and the fourth sub-electrode 194 and the fourth contact electrode 234 on the first bonding layer 201 and the second bonding layer 202 are aligned using an alignment device such as a microscope, a laser alignment system, etc. The first component and the second component are low-temperature bonded at a temperature below 350°C.

[0133] Step 32, removing the silicon substrate 10, the nucleation layer 20, and the buffer layer 30 to obtain the full-color Micro LED display device.

[0134] The silicon substrate 10 is removed by using a chemical solution or a physical method such as laser ablation, mechanical ablation, etc. The nucleation layer 20 and the buffer layer 30 are also removed together when the silicon substrate 10 is removed, and a full-color Micro LED display device is obtained, as shown in Figure 12 .

[0135] The devices with three light-emitting wavelengths of blue light, green light, and red light can be controlled individually, and a display with a larger color gamut can be achieved. The emitted light of three wavelengths goes out from the first N-GaN layer 40. The emitted red light is not absorbed by the green light and blue light emitting layers, and the emitted green light is not absorbed by the blue light emitting layer, so a higher light extraction efficiency can be achieved. Embodiment 1

[0136] A preparation method of a full-color Micro LED display device includes the following steps:

[0137] A first component is prepared. The preparation of an epitaxial structure can be completed by using an MOCVD epitaxial growth device, and the steps are as follows:

[0138] Step 11, providing a silicon substrate 10, and epitaxially growing a nucleation layer 20, a buffer layer 30, a first N-GaN layer 40, a blue light LED light-emitting layer 50, a first P-GaN layer 60, a first heavily doped PN junction layer 70, a second N-GaN layer 80, a green light LED light-emitting layer 90, a second P-GaN layer 100, a second heavily doped PN junction layer 110, a third N-GaN layer 120, a red light LED light-emitting layer 130, a third P-GaN layer 140, a third heavily doped PN junction layer 150, and a fourth N-GaN layer 160 on the surface of the silicon substrate 10 in sequence, as shown in Figure 1shown.

[0139] Specifically, a 200 nm AlN nucleation layer 20 is grown on the substrate 10 at a temperature of 1100 °C and a pressure of 50 torr.

[0140] A 1 μm AlGaN buffer layer 30 is grown on the nucleation layer 20 at a temperature of 1180 °C and a pressure of 75 torr.

[0141] A 0.5 μm first N-GaN layer 40 is grown on the buffer layer 30 at a temperature of 1150 °C and a pressure of 200 torr.

[0142] A 90 nm blue LED multi-quantum well light emitting layer 50 is grown on the first N-GaN layer 40 at a temperature of 780 °C and a pressure of 400 torr.

[0143] A 50 nm first P-GaN layer 60 is grown on the blue LED light emitting layer 50 at a temperature of 950 °C and a pressure of 200 torr.

[0144] A 10 nm first P+-InGaN layer 71 is grown on the first P-GaN layer 60 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 4%, a dopant of Mg, and a doping concentration of 1E20 cm -3 .

[0145] A 10 nm first N+-InGaN layer 72 is grown on the first P+-InGaN layer 71 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 4%, a dopant of Si, and a doping concentration of 3E19 cm -3 .

[0146] A 0.5 μm second N-GaN layer 80 is grown on the first N+-InGaN layer 72 at a temperature of 1150 °C and a pressure of 200 torr.

[0147] A 90 nm green LED light emitting layer 90 is grown on the second N-GaN layer 80 at a temperature of 762 °C and a pressure of 400 torr.

[0148] A 50 nm second P-GaN layer 100 is grown on the green LED light emitting layer 90 at a temperature of 950 °C and a pressure of 200 torr.

[0149] A 10 nm second P+-InGaN layer 111 is grown on the second P-GaN layer 100 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 4%, a dopant of Mg, and a doping concentration of 1E20 cm -3.

[0150] A second N+-InGaN layer 112 with 10nm thickness, 4% In content, Si dopant and 3E19cm-3 doping concentration is grown on the second P+-InGaN layer 111 at 900℃ and 400torr. -3 .

[0151] A third N-GaN layer 120 with 0.5μm thickness is grown on the second N+-InGaN layer 112 at 1150℃ and 200torr.

[0152] A red LED light emitting layer 130 with 90nm thickness is grown on the third N-GaN layer 120 at 722℃ and 400torr.

[0153] A third P-GaN layer 140 with 50nm thickness is grown on the red LED light emitting layer 130 at 950℃ and 200torr.

[0154] A third P+-InGaN layer 151 with 10nm thickness, 4% In content, Mg dopant and 1E20cm-3 doping concentration is grown on the third P-GaN layer 140 at 900℃ and 400torr. -3 .

[0155] A third N+-InGaN layer 152 with 10nm thickness, 4% In content, Si dopant and 3E19cm-3 doping concentration is grown on the third P+-InGaN layer 151 at 900℃ and 400torr. -3 .

[0156] The first, second and third heavily doped PN junction layers 70, 110 and 150 using InGaN material can reduce the forward voltage.

[0157] A fourth N-GaN layer 160 with 0.5μm thickness is grown on the third N+-InGaN layer 152 at 1150℃ and 200torr.

[0158] Step 12, first etching, etching a portion of layers on the first N-GaN layer 40 and a portion of the first N-GaN layer 40 along the thickness direction of the first component, forming a first step on the side of the first N-GaN layer 40.

[0159] A photoresist is coated on the product obtained in step 11, and exposure and development are performed using a mask to form a pattern to be etched. The epitaxial layer is etched according to the photoetching pattern using an ion etching technique to remove unnecessary portions, and etching is performed to the first N-GaN layer 40 to form a first step on the side of the first N-GaN layer 40. The thickness of the first N-GaN layer 40 etched is less than the thickness of the first N-GaN layer 40.

[0160] Step 13: Second etching. A portion of each layer on the second N-GaN layer 80 and a portion of the second N-GaN layer 80 are etched in the thickness direction of the first component to form a second step on the side of the second N-GaN layer 80.

[0161] A photoresist is coated on the product obtained in step 12, and exposure and development are performed using a mask to form a pattern to be etched. The epitaxial layer is etched according to the photoetching pattern using an ion etching technique to remove unnecessary portions, and etching is performed to the second N-GaN layer 80 to form a second step on the side of the second N-GaN layer 80. The thickness of the second N-GaN layer 80 etched is less than the thickness of the second N-GaN layer 80.

[0162] Step 14: Third etching. A portion of each layer on the third N-GaN layer 120 and a portion of the third N-GaN layer 120 are etched in the thickness direction of the first component to form a third step on the side of the third N-GaN layer 120.

[0163] A photoresist is coated on the product obtained in step 13, and exposure and development are performed using a mask to form a pattern to be etched. The epitaxial layer is etched according to the photoetching pattern using an ion etching technique to remove unnecessary portions, and etching is performed to the third N-GaN layer 120 to form a third step on the side of the third N-GaN layer 120. The thickness of the third N-GaN layer 120 etched is less than the thickness of the third N-GaN layer 120.

[0164] The three etching steps are completed, as shown in Figure 2 .

[0165] After the etching to form the side wall, P-type activation can be performed at a high temperature of 650°C in an N2 atmosphere. The formation of the side wall is beneficial to the diffusion of H atoms from the side wall, thereby activating Mg doping, and the doping concentration is > 5E18 cm -3 .

[0166] Step 15: A metal reflection layer 170 is formed on the upper surface of the fourth N-GaN layer 160.

[0167] A photoresist is coated on the product obtained in step 14, and exposure and development are performed using a mask to expose the fourth N-GaN layer 160.

[0168] A 100nm metal reflective layer 170 is formed on the surface of the fourth N-GaN layer 160 using a vacuum electron beam evaporation device, as shown in Figure 3 .

[0169] The material of the metal reflective layer 170 is aluminum (Al), which has high reflectivity and can form good adhesion with the fourth N-GaN layer 160.

[0170] Step 16, forming a passivation layer 180 covering the sidewalls of the first N-GaN layer 40, blue light LED light emitting layer 50, first P-GaN layer 60, first heavily doped PN junction layer 70, second N-GaN layer 80, green light LED light emitting layer 90, second P-GaN layer 100, second heavily doped PN junction layer 110, third N-GaN layer 120, red light LED light emitting layer 130, third P-GaN layer 140, third heavily doped PN junction layer 150, fourth N-GaN layer 160, and metal reflective layer 170.

[0171] The CVD method uses aluminum source (TMAl), nitrogen (N2) and ammonia (NH3) as reaction gas, deposition temperature 950℃, aluminum source gas flow 120sccm, nitrogen (N2) gas flow 20000sccm, ammonia (NH3) gas flow 300sccm, reaction time 5min, etc. to obtain uniform and dense 50nm passivation layer 180.

[0172] After forming the AlN passivation layer 180, photolithography and etching treatment are needed to form the required pattern and window, as shown in Figure 4 .

[0173] Step 17, arranging first sub-electrode 191, second sub-electrode 192, third sub-electrode 193 and fourth sub-electrode 194 above the first step, second step, metal reflective layer 170 and third step respectively.

[0174] Among them, the first sub-electrode 191 is perpendicular to the first step, which is the negative electrode of the blue light LED. The second sub-electrode 192 is perpendicular to the second step, which is the positive electrode of the blue light LED and the negative electrode of the green light LED. The third sub-electrode 193 is perpendicular to the metal reflective layer 170, which is the positive electrode of the red light LED. The fourth sub-electrode 194 is perpendicular to the third step, which is the negative electrode of the red light LED and the positive electrode of the green light LED, as shown in Figure 5 . Among them, the material of the electrode is titanium (Ti).

[0175] As shown in Figure 6As shown in the top view of the product of step 17, the first N-GaN layer 40 can be seen around the first sub-electrode 191, the second N-GaN layer 80 can be seen around the second sub-electrode 192, the third N-GaN layer 120 can be seen around the fourth sub-electrode 194, and the rest of the area is the upper surface of the reflective metal layer 170 as around the third sub-electrode 193.

[0176] Step 18, a first bonding layer 201 is formed, which fills the gaps among the first sub-electrode 191, the second sub-electrode 192, the third sub-electrode 193, the fourth sub-electrode 194, and the passivation layer 180, and covers the metal reflective layer 170.

[0177] The first bonding layer 201 with a material of SiO2 is deposited by a plasma enhanced chemical vapor deposition (PECVD) process at a deposition temperature of 350°C to fill the gaps among the first sub-electrode 191, the second sub-electrode 192, the third sub-electrode 193, the fourth sub-electrode 194, and the passivation layer 180, and to cover the metal reflective layer 170, as shown in Figure 7 .

[0178] Step 19, the first bonding layer is planarized.

[0179] The chemical mechanical polishing (CMP) planarization technique is used to improve the surface quality of the first bonding layer 201.

[0180] A second component is prepared to form a CMOS driving circuit, including the following steps:

[0181] Step 21, a CMOS driver 210 is provided, and a second bonding layer 202 is formed above the CMOS driver 210.

[0182] As shown in Figures 8-9 , the second bonding layer 202 is deposited by a PECVD process at a deposition temperature of 350°C to form a second bonding layer 202 with a thickness of 0.5 μm.

[0183] Step 22, the second bonding layer 202 is etched along the thickness direction of the second bonding layer 202 to form four through holes 220 penetrating through the second bonding layer.

[0184] A photoresist is coated on the upper surface of the second bonding layer 202, and exposure and development are performed using a mask to form a pattern to be etched. The second bonding layer 202 is etched according to the photoetching pattern using an ion etching technique to form four through holes 220 penetrating through the second bonding layer 202, as shown in Figure 10 .

[0185] Step 23, placing a first contact electrode 231, a second contact electrode 232, a third contact electrode 233, a fourth contact electrode 234 in the through hole 220 respectively, as shown in Figure 11 .

[0186] Bonding the first component and the second component, comprising the following steps:

[0187] Step 31, horizontally transposing the second component, aligning and bonding the first sub-electrode 191 with the first contact electrode 231, the second sub-electrode 192 with the second contact electrode 232, the third sub-electrode 193 with the third contact electrode 233, the fourth sub-electrode 194 with the fourth contact electrode 234, and forming a first electrode, a second electrode, a third electrode, a fourth electrode respectively.

[0188] Using a microscope to align the first sub-electrode 191 with the first contact electrode 231, the second sub-electrode 192 with the second contact electrode 232, the third sub-electrode 193 with the third contact electrode 233, the fourth sub-electrode 194 with the fourth contact electrode 234 on the first bonding layer 201 and the second bonding layer 202. Low-temperature bonding the first component and the second component at a temperature below 350℃.

[0189] Step 32, removing the silicon substrate 10, the nucleation layer 20, the buffer layer 30, to obtain the full-color Micro LED display device.

[0190] Using a chemical solution to remove the silicon substrate 10, the nucleation layer 20 and the buffer layer 30 will also be removed at the same time, to obtain the full-color Micro LED display device, as shown in Figure 12 . Embodiment 2

[0191] The other steps of this embodiment are the same as those of Embodiment 1, except that the growth of the first heavily doped PN junction layer 70, a 10nm first P+-GaN layer 71 is grown on the first P-GaN layer 60 under the condition of a temperature of 900℃ and a pressure of 400torr, the In content is 0%, the dopant is Mg, and the doping concentration is 1E20cm -3 .

[0192] A 10nm first N+-GaN layer 72 is grown on the first P+-GaN layer 71 under the condition of a temperature of 900℃ and a pressure of 400torr, the In content is 0%, the dopant is Si, and the doping concentration is 3E19cm -3 .

[0193] Growth of the second heavily doped PN junction layer 110, a 10 nm second P+-GaN layer 111 is grown on the second P-GaN layer 100 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 0%, a dopant of Mg, and a doping concentration of 1E20 cm -3 .

[0194] Growth of the second heavily doped PN junction layer 110, a 10 nm second P+-GaN layer 111 is grown on the second P-GaN layer 100 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 0%, a dopant of Mg, and a doping concentration of 1E20 cm -3 .

[0195] Growth of the second heavily doped PN junction layer 110, a 10 nm second P+-GaN layer 111 is grown on the second P-GaN layer 100 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 0%, a dopant of Mg, and a doping concentration of 1E20 cm -3 .

[0196] Growth of the second heavily doped PN junction layer 110, a 10 nm second P+-GaN layer 111 is grown on the second P-GaN layer 100 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 0%, a dopant of Mg, and a doping concentration of 1E20 cm -3 . Example 3

[0197] Growth of the second heavily doped PN junction layer 110, a 10 nm second P+-GaN layer 111 is grown on the second P-GaN layer 100 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 0%, a dopant of Mg, and a doping concentration of 1E20 cm -3 .

[0198] Growth of the second heavily doped PN junction layer 110, a 10 nm second P+-GaN layer 111 is grown on the second P-GaN layer 100 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 0%, a dopant of Mg, and a doping concentration of 1E20 cm -3 .

[0199] Growth of the second heavily doped PN junction layer 110, a 10 nm second P+-GaN layer 111 is grown on the second P-GaN layer 100 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 0%, a dopant of Mg, and a doping concentration of 1E20 cm -3 .

[0200] A second P+-InGaN layer 111 of 10 nm thickness is grown on the second P-GaN layer 100 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 10%, a dopant of Mg, and a doping concentration of 1 E20 cm -3 .

[0201] A third P+-InGaN layer 151 of 10 nm thickness is grown on the third P-GaN layer 140 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 10%, a dopant of Mg, and a doping concentration of 1 E20 cm -3 .

[0202] A third N+-InGaN layer 152 of 10 nm thickness is grown on the third P+-InGaN layer 151 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 10%, a dopant of Si, and a doping concentration of 3 E19 cm -3 .

[0203] Comparative Example 1

[0204] The first P+-InGaN layer 71 of 10 nm thickness is grown on the first P-GaN layer 60 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 15%, a dopant of Mg, and a doping concentration of 1 E20 cm -3 .

[0205] A first N+-InGaN layer 72 of 10 nm thickness is grown on the first P+-InGaN layer 71 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 15%, a dopant of Si, and a doping concentration of 3 E19 cm -3 .

[0206] A second P+-InGaN layer 111 of 10 nm thickness is grown on the second P-GaN layer 100 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 15%, a dopant of Mg, and a doping concentration of 1 E20 cm -3 .

[0207] A second N+-InGaN layer 112 of 10 nm thickness is grown on the second P+-InGaN layer 111 at a temperature of 900 °C and a pressure of 400 torr, with an In content of 15%, a dopant of Si, and a doping concentration of 3 E19 cm -3 .

[0208] Growth of the third heavily doped PN junction layer 150, a third P+-InGaN layer 151 of 10 nm is grown on the third P-GaN layer 140 at a temperature of 900 °C and a pressure of 400 torr, with In content of 15%, dopant of Mg, and doping concentration of 1E20 cm -3 .

[0209] Growth of the third heavily doped PN junction layer 150, a third P+-InGaN layer 151 of 10 nm is grown on the third P-GaN layer 140 at a temperature of 900 °C and a pressure of 400 torr, with In content of 15%, dopant of Mg, and doping concentration of 1E20 cm -3 .

[0210] Comparative Example 2

[0211] The present comparative example is the same as other steps of Example 1, except that the growth of the first heavily doped PN junction layer 70, a first P+-InGaN layer 71 of 10 nm is grown on the first P-GaN layer 60 at a temperature of 900 °C and a pressure of 400 torr, with In content of 20%, dopant of Mg, and doping concentration of 1E20 cm -3 .

[0212] Growth of the third heavily doped PN junction layer 150, a third P+-InGaN layer 151 of 10 nm is grown on the third P-GaN layer 140 at a temperature of 900 °C and a pressure of 400 torr, with In content of 15%, dopant of Mg, and doping concentration of 1E20 cm -3 .

[0213] Growth of the third heavily doped PN junction layer 150, a third P+-InGaN layer 151 of 10 nm is grown on the third P-GaN layer 140 at a temperature of 900 °C and a pressure of 400 torr, with In content of 15%, dopant of Mg, and doping concentration of 1E20 cm -3 .

[0214] Growth of the third heavily doped PN junction layer 150, a third P+-InGaN layer 151 of 10 nm is grown on the third P-GaN layer 140 at a temperature of 900 °C and a pressure of 400 torr, with In content of 15%, dopant of Mg, and doping concentration of 1E20 cm -3 .

[0215] Growth of the third heavily doped PN junction layer 150, a third P+-InGaN layer 151 of 10 nm is grown on the third P-GaN layer 140 at a temperature of 900 °C and a pressure of 400 torr, with In content of 15%, dopant of Mg, and doping concentration of 1E20 cm -3 .

[0216] A third N+-InGaN layer 152 with a thickness of 10 nm, an In content of 20%, a dopant of Si, and a doping concentration of 3E19 cm-3 is grown on the third P+-InGaN layer 151 at a temperature of 900 DEG C and a pressure of 400 torr. -3 .

[0217] The display unit operating voltage test and the light emitting efficiency test of the full-color Micro LED display device of Examples 1-3 and Comparative Examples 1-2 are performed, and the results are shown in Table 1.

[0218] Table 1

[0219]

[0220] From the data in Table 1, it can be seen that: 1. When the In content of the P+-InGaN layer is 0-4% and the In content of the N+-InGaN layer is 0-4%, the energy band structure of the P+-InGaN layer and the N+-InGaN layer is relatively stable when the In content is low, and the voltage of the full-color Micro LED display unit is slightly reduced. The increase of the In content will increase the light emitting efficiency of the display unit to a certain extent. The light emitting efficiency of the display unit is the highest when the In content in the heavily doped PN junction is about 4%. 2. With the increase of the In content (4-10%), the energy band structure of the P+-InGaN layer and the N+-InGaN layer starts to change significantly. The introduction of In makes the band gap of the display unit smaller, and the increase of the ionization ratio of the Mg dopant and the Si dopant makes the voltage of the display unit decrease, and the light emitting efficiency is slightly lower than that of Example 1. 3. When the In content is too high (more than 15%), the P+-InGaN layer and the N+-InGaN layer will absorb the light emitted by the display unit, and the light emitting efficiency will decrease, and the decrease of the blue light and the green light is more obvious.

[0221] Although the embodiments of the present application have been shown and described above, it should be understood that the above embodiments are exemplary and should not be construed as limiting the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments without departing from the principles and spirit of the present application within the scope of the present application, and all these changes should be within the protection scope of the claims of the present application.

Claims

1. A method for preparing a full-color Micro LED display device, characterized in that, The preparation method comprises the following steps: forming a first component comprising the following steps: Step 11, providing a silicon substrate, and epitaxially growing, on the surface of the silicon substrate, a nucleation layer, a buffer layer, a first N-GaN layer, a blue light LED light-emitting layer, a first P-GaN layer, a first heavily doped PN junction layer, a second N-GaN layer, a green light LED light-emitting layer, a second P-GaN layer, a second heavily doped PN junction layer, a third N-GaN layer, a red light LED light-emitting layer, a third P-GaN layer, a third heavily doped PN junction layer, and a fourth N-GaN layer; Step 12, first etching, etching a portion of each layer on the first N-GaN layer and a portion of the first N-GaN layer along the thickness direction of the first component, and forming a first step on the side of the first N-GaN layer; Step 13, second etching, etching a portion of each layer on the second N-GaN layer and a portion of the second N-GaN layer along the thickness direction of the first component, and forming a second step on the side of the second N-GaN layer; Step 14, third etching, etching a portion of each layer on the third N-GaN layer and a portion of the third N-GaN layer along the thickness direction of the first component, and forming a third step on the side of the third N-GaN layer; Step 15, forming a metal reflection layer on the upper surface of the fourth N-GaN layer; Step 16, forming a passivation layer covering the side walls of the first N-GaN layer, the blue light LED light-emitting layer, the first P-GaN layer, the first heavily doped PN junction layer, the second N-GaN layer, the green light LED light-emitting layer, the second P-GaN layer, the second heavily doped PN junction layer, the third N-GaN layer, the red light LED light-emitting layer, the third P-GaN layer, the third heavily doped PN junction layer, the fourth N-GaN layer, and the metal reflection layer; Step 17, disposing a first sub-electrode, a second sub-electrode, a third sub-electrode, and a fourth sub-electrode above the first step, the second step, the metal reflection layer, and the third step, respectively; Step 18, forming a first bonding layer, which fills the gaps between the first sub-electrode, the second sub-electrode, the third sub-electrode, the fourth sub-electrode, and the passivation layer, and covers the metal reflection layer; Step 19, planarizing the first bonding layer; forming a second component comprising the following steps: Step 21, providing a CMOS driver, and forming a second bonding layer above the CMOS driver; Step 22, etching the second bonding layer along the thickness direction of the second bonding layer to form four through holes penetrating through the second bonding layer; Step 23, placing a first contact electrode, a second contact electrode, a third contact electrode, and a fourth contact electrode in the through holes, respectively; bonding the first component and the second component comprising the following steps: Step 31, horizontally transposing the second component, aligning and bonding the first sub-electrode with the first contact electrode, the second sub-electrode with the second contact electrode, the third sub-electrode with the third contact electrode, and the fourth sub-electrode with the fourth contact electrode, and forming a first electrode, a second electrode, a third electrode, and a fourth electrode, respectively; Step 32, removing the silicon substrate, the nucleation layer, and the buffer layer to obtain the full-color Micro LED display device. 2.The method of claim 1, wherein, The step 14 is followed by a step 15 of P-type Mg-doping activation of the first component, with a doping concentration > 5E18 cm -3 . 3.The method of claim 1, wherein the method further comprises: forming a first color conversion layer on the first color conversion layer; and forming a second color conversion layer on the second color conversion layer. The first heavily doped PN junction layer comprises a first P+-InGaN layer and a first N+-InGaN layer stacked from bottom to top, the first P+-InGaN layer has an In content of 0-10%, a dopant of Mg, and a doping concentration >5E19 cm -3 ; the first N+-InGaN layer has an In content of 0-10%, a dopant of Si, and a doping concentration >2E19 cm -3 . 4.The method of claim 1, wherein The second heavily doped PN junction layer comprises a second P+-InGaN layer and a second N+-InGaN layer stacked from bottom to top, the second P+-InGaN layer has an In content of 0-10%, a dopant of Mg, and a doping concentration >5E19 cm -3 ; the second N+-InGaN layer has an In content of 0-10%, a dopant of Si, and a doping concentration >2E19 cm -3 . 5.The method of claim 1, wherein The third heavily doped PN junction layer comprises a third P+-InGaN layer and a third N+-InGaN layer stacked from bottom to top, the third P+-InGaN layer has an In content of 0-10%, a dopant of Mg, and a doping concentration >5E19 cm -3 ; the third N+-InGaN layer has an In content of 0-10%, a dopant of Si, and a doping concentration >2E19 cm -3 . 6.The method of claim 3, wherein the method further comprises forming a plurality of color conversion layers on the plurality of sub-pixels. The first P+-InGaN layer has a thickness of 5-20 nm, the first N+-InGaN layer has a thickness of 5-20 nm, and the thickness ratio of the first P+-InGaN layer to the first N+-InGaN layer is 1:

1. 7.The method of claim 4, wherein the method further comprises forming a plurality of color conversion layers on the plurality of sub-pixels. The second P+-InGaN layer has a thickness of 5-20 nm, the second N+-InGaN layer has a thickness of 5-20 nm, and the thickness ratio of the second P+-InGaN layer to the second N+-InGaN layer is 1:

1. 8.The method of claim 5, wherein the method further comprises: forming a plurality of color conversion layers on the plurality of sub-pixels. The third P+-InGaN layer has a thickness of 5-20 nm, the third N+-InGaN layer has a thickness of 5-20 nm, and the thickness ratio of the third P+-InGaN layer to the third N+-InGaN layer is 1:1.

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